CD54AC139 TI | Alldatasheet

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CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068 AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage /C0068 Buffered Inputs /C0068 Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception /C0068 Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption /C0068 Balanced Propagation Delays /C0068 ±24-mA Output Drive Current – Fanout to 15 F Devices /C0068 SCR-Latchup-Resistant CMOS Process and Circuit Design /C0068 Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015 description/ordering information The ’AC139 devices are dual 2-line to 4-line decoders/demultiplexers designed for 1.5-V to 5.5-V VCC operation. These devices are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When used with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible. The active-low enable (G ) input can be used as a data line in demultiplexing applications. These decoders/demultiplexers feature fully buffered inputs, each of which represents only one normalized load to its driving circuit.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING PDIP – E Tube CD74AC139E CD74AC139E 55°Ct o1 2 5°C SOIC M Tube CD74AC139M AC139M–55°C to 125°C SOIC – M Tape and reel CD74AC139M96 AC139M CDIP – F Tube CD54AC139F3A CD54AC139F3A † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Copyright  2003, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. CD54AC139 ...F PACKAGE CD74AC139 ...E O R M PACKAGE (TOP VIEW) 1Y0 1Y1 1Y2 1Y3 GND VCC 2Y0 2Y1 2Y2 2Y3 On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters.

CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

(each decoder/demultiplexer) INPUTS OUTPUTS G SELECT OUTPUTS G B A Y0 Y1 Y2 Y3 H X X H H H H L L LL HHH L L HH LHH L H LH HLH L H H H H H L logic diagram (positive logic) Select Inputs Select Inputs Data Outputs 2Y3 2Y2 2Y1 2Y0 1Y3 1Y2 1Y1 1Y0 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) TA = 25°C –55°C to 125°C –40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX VCC = 1.5 V 1.2 1.2 1.2 VIH High-level input voltage VCC = 3 V 2.1 2.1 2.1 V VCC = 5.5 V 3.85 3.85 3.85 VCC = 1.5 V 0.3 0.3 0.3 VIL Low-level input voltage VCC = 3 V 0.9 0.9 0.9 V VCC = 5.5 V 1.65 1.65 1.65 VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current VCC = 4.5 V to 5.5 V –24 –24 –24 mA IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA ∆t/∆v Input transition rise or fall rate VCC = 1.5 V to 3 V 50 50 50 ns/V∆t/∆v Input transition rise or fall rate VCC = 3.6 V to 5.5 V 20 20 20 ns/V NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C –55°C to 125°C –40°C to 85°C UNITCC MIN MAX MIN MAX MIN MAX 1.5 V 1.4 1.4 1.4 IOH = –50 µA 3 V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 VOH VI = VIH or VIL IOH = –4 mA 3 V 2.58 2.4 2.48 V IOH = –24 mA 4.5 V 3.94 3.7 3.8 IOH = –50 mA† 5.5 V 3.85 IOH = –75 mA† 5.5 V 3.85 1.5 V 0.1 0.1 0.1 IOL = 50 µA 3 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 VOL VI = VIH or VIL IOL = 12 mA 3 V 0.36 0.5 0.44 V IOL = 24 mA 4.5 V 0.36 0.5 0.44 IOL = 50 mA† 5.5 V 1.65 – IOL = 75 mA† 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 µA ICC VI = VCC or GND, IO = 0 5.5 V 8 160 80 µA C i 10 10 10 pF † Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

CD54AC139, CD74AC139 DUAL 2-LINE TO 4-LINE DECODERS/DEMULTIPLEXERS SCHS332 – MARCH 2003

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) CAPACITANCE MIN MAX MIN MAX tPLH Ao rB Any Y C L =5 0pF 131 119 nstPHL A or B Any Y C L = 50 pF 131 119 ns tPLH G Any Y C L =5 0pF 131 119 ns tPHL G Any Y C L = 50 pF 131 119 ns switching characteristics over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) CAPACITANCE MIN MAX MIN MAX tPLH Ao rB Any Y C L =5 0pF 3.7 14.7 3.9 13.4 nstPHL A or B Any Y C L = 50 pF 3.7 14.7 3.9 13.4 ns tPLH G Any Y C L =5 0pF 3.7 14.7 3.9 13.4 ns tPHL G Any Y C L = 50 pF 3.7 14.7 3.9 13.4 ns switching characteristics over recommended operating free-air temperature range, VCC = 5 V± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE –55°C to 125°C –40°C to 85°C UNIT(INPUT) (OUTPUT) CAPACITANCE MIN MAX MIN MAX tPLH Ao rB Any Y C L =5 0pF 2.6 10.5 2.8 9.5 nstPHL A or B Any Y C L = 50 pF 2.6 10.5 2.8 9.5 ns tPLH G Any Y C L =5 0pF 2.6 10.5 2.8 9.5 ns tPHL G Any Y C L = 50 pF 2.6 10.5 2.8 9.5 ns operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TYP UNIT C pd Power dissipation capacitance 83 pF

NOTES: A. C L includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω , tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms

/C0077/C0069/C0067/C0072/C0065/C0078/C0073/C0067/C0065/C0076 MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 N (R-PDIP-T) PLASTIC DUAL-IN-LINE PACKAGE BB AC AD 0.325 (8,26) 0.300 (7,62) 0.010 (0,25) NOM Gauge Plane 0.015 (0,38) 0.430 (10,92) MAX 1.060 (26,92) 0.940 (23,88) 0.920 0.850 0.775 0.745 (19,69) (18,92) 0.775 (19,69) (18,92) 0.745A MIN DIM A MAX PINS (23,37) (21,59) Seating Plane 14/18 PIN ONLY 20 pin vendor option 4040049/E 12/2002 0.070 (1,78) A 0.015 (0,38) 0.021 (0,53) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.240 (6,10) 0.260 (6,60) M0.010 (0,25) 0.100 (2,54)

16 PINS SHOWN

D D D0.030 (0,76) 0.045 (1,14) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.197 (5,00)A MAX A MIN (4,80) 0.189 0.337 (8,55) (8,75) 0.344 0.386 (9,80) (10,00) 0.394 16DIM PINS ** 4040047/E 09/01 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.044 (1,12) 0.244 (6,20) 0.228 (5,80) 0.020 (0,51) 0.014 (0,35) 1 4 8 5 0.150 (3,81) 0.157 (4,00) 0.008 (0,20) NOM 0°– 8° Gage Plane A 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

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