CD54AC138 TI | Alldatasheet

Document overview

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Technical content

Features

  • Buffered Inputs
  • Typical Propagation Delay - 5ns at V CC = 5V, TA = 25oC, CL = 50pF
  • Exceeds 2kV ESD Protection MIL-STD-883, Method 3015
  • SCR-Latchup-Resistant CMOS Process and Circuit Design
  • Speed of Bipolar FAST™/AS/S with Significantly Reduced Power Consumption
  • Balanced Propagation Delays
  • AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply
  • –24mA Output Drive Current - Fanout to 15 FAST™ ICs - Drives 50W Transmission Lines Pinout CD54AC138, CD54ACT138 (CERDIP) CD74AC138, CD74ACT138, CD74AC238, CD74ACT238 (PDIP, SOIC) TOP VIEW

Description

The ’AC138, ’ACT138, CD74AC238, and CD74ACT238 are 3-to-8-line decoders/demultiplexers that utilize Advanced CMOS Logic technology. Both circuits have three binary select inputs (A0, A1, and A2). If the device is enabled, these inputs determine which one of the eight normally HIGH out- puts of the AC/ACT138 will go LOW or which on of the nor- mally LOW outputs of the AC/ACT238 will go HIGH. Two active LOW and one active HIGH enables ( E1, E2 and E3) are provided to simplify the cascading of these devices. GND AC/ACT138 Y7 VCC Y1 AC/ACT138 Y2 AC/ACT138 Y3 AC/ACT138 Y4 AC/ACT138 Y5 AC/ACT138 Y6 AC/ACT138 Y0 AC/ACT138 AC/ACT238 Y7 Y0 AC/ACT238 Y1 AC/ACT238 Y2 AC/ACT238 Y3 AC/ACT238 Y4 AC/ACT238 Y5 AC/ACT238 Y6 AC/ACT238

Ordering Information

TEMP. RANGE ( oC) PACKAGE CD54AC138F3A -55 to 125 16 Ld CERDIP CD74AC138E 0 to 70 oC, -40 to 85, -55 to 125

16 Ld PDIP

CD74AC138M 0 to 70 oC, -40 to 85, -55 to 125

16 Ld SOIC

CD54ACT138F3A -55 to 125 16 Ld CERDIP CD74ACT138E 0 to 70 oC, -40 to 85, -55 to 125 CD74ACT138M 0 to 70 oC, -40 to 85, -55 to 125 CD74AC238E 0 to 70 oC, -40 to 85, -55 to 125 CD74AC238M 0 to 70 oC, -40 to 85, -55 to 125 CD74ACT238E 0 to 70 oC, -40 to 85, -55 to 125 CD74ACT238M 0 to 70 oC, -40 to 85, -55 to 125 NOTES: 1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel. 2. Wafer and die for this part number is available which meets all elec- trical specifications. Please contact your local TI sales office or cus- tomer service for ordering information. September 1998 - Revised May 2000 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. FAST™ is a Trademark of Fairchild Semiconductor. Copyright © 2000, Texas Instruments Incorporated. CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238 3-to-8-Line Decoders/Demultiplexers [ /Title (CD74 AC138 CD74 ACT13 CD74 AC238 CD74 ACT23 /Sub- ject (3- to-8- Line Decod- ers/De multi- plex- ers) /Autho r () /Key- words (Har- ris Semi- con- ductor, Advan ced

(NOTE 4) E0 A 2 A 1 A 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 XH XXXHHHHHHHH LX XXXHHHHHHHH HL L L L LHHHHHHH HL LLHHLHHHHHH HL LHLHHLHHHHH HL LHHHHHLHHHH HL HL LHHHHLHHH HL HLLHHHHHLHH HL HHLHHHHHHLH HL HHHHHHHHHHL CD74AC/ACT238 TRUTH TABLE INPUTS OUTPUTSENABLE ADDRESS (NOTE 4) E0 A 2 A 1 A 0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 X HXXXLLLLLLLL LX XXXLLLLLLLL HL LLLHLLLLLLL HL LLHLHLLLLLL HL LHLLLHLLLLL HL LHHLLLHLLLL HL HLLLLLLHLLL HL HLHLLLLLHLL HL H HLLLLLLLHL HL H H HLLLLLLLH NOTES: 3. H = High Level, L = Low Level, X = Don’t Care E0 = E1 +E2 CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC (Note 6) DC Input or Output Voltage, V Input Rise and Fall Slew Rate, dt/dv Thermal Resistance (Typical, Note 7) q JA (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 5. For up to 4 outputs per device, add–25mA for each additional output. 6. Unless otherwise specified, all voltages are referenced to ground. 7. q JA is measured with the component mounted on an evaluation PC board in free air. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI(V) I O (mA) MIN MAX MIN MAX MIN MAX AC TYPES High Level Input Voltage V Low Level Input Voltage V IL - - 1.5 - 0.3 - 0.3 - 0.3 V -75 (Note 8, 9) -50 (Note 8, 9) CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238

12 3 - 0.36 - 0.44 - 0.5 V 24 4.5 - 0.36 - 0.44 - 0.5 V (Note 8, 9) (Note 8, 9) 5 . 5 ----- 1.65 V Input Leakage Current I I VCC or GND Quiescent Supply Current MSI ICC VCC or GND 0 5.5 - 8 - 80 - 160 mA ACT TYPES High Level Input Voltage V IH - - 4.5 to 5.5 2-2-2-V Low Level Input Voltage V IL - - 4.5 to 5.5 -75 (Note 8, 9) -50 (Note 8, 9) 24 4.5 - 0.36 - 0.44 - 0.5 V (Note 8, 9) (Note 8, 9) 5 . 5 ----- 1.65 V Input Leakage Current I I VCC or GND Quiescent Supply Current MSI ICC VCC or GND 0 5.5 - 8 - 80 - 160 mA Additional Supply Current per Input Pin TTL Inputs High

1 Unit Load

-2.1 - 4.5 to 5.5 - 2.4 - 2.8 - 3 mA NOTES: 8. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize power dissipation. 9. Test verifies a minimum 50W transmission-line-drive capability at 85oC, 75W at 125oC. ACT Input Load Table INPUT UNIT LOAD A0-A2 0.83 E1,E2 1 E3 0.42 NOTE: Unit load isDICC limit specified in DC Electrical Specifications Table, e.g., 2.4mA max at 25oC. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSVI(V) I O (mA) MIN MAX MIN MAX MIN MAX CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238

Switching SpecificationsInput tr, tf = 3ns, CL = 50pF (Worst Case) PARAMETER SYMBOL V CC (V) -40oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN TYP MAX AC TYPES Propagation Delay, An to Output (CD54/74AC/ACT138) t PLH , tPHL 1.5 - - 125 - - 138 ns 3.3 (Note 11) 4 - 14 3.9 - 15.4 ns (Note 12) 2.8 - 10 2.8 - 11 ns Propagation Delay, E1,E2 to Output (CD54/74AC/ACT138) tPLH , tPHL 1.5 - - 114 - - 125 ns 3.3 3.6 - 12.7 3.5 - 14 ns 5 2.6 - 9.1 2.5 - 10 ns Propagation Delay, E3 to Output (CD54/74AC/ACT138) t PLH , tPHL 1.5 - - 125 - - 138 ns 3.3 4 - 14 3.9 - 15.4 ns 5 2.8 - 10 2.8 - 11 ns Propagation Delay, An to Output (CD74AC/ACT238) t PLH , tPHL 1.5 - - 170 - - 187 ns 3.3 5.4 - 19.1 5.3 - 21 ns 5 3.9 - 13.6 3.8 - 15 ns Propagation Delay, E1,E2 to Output (CD74AC/ACT238) tPLH , tPHL 1.5 - - 135 - - 149 ns 5 3.1 - 10.7 3 - 11.9 ns Propagation Delay, E3 to Output (CD74AC/ACT238) t PLH , tPHL 1.5 - - 189 - - 208 ns 3.3 6 - 21.1 5.8 - 23.2 ns 5 4.3 - 15.1 4.2 - 16.6 ns Input Capacitance C I - - -1 0- -1 0 p F Power Dissipation Capacitance C PD (Note 13) - - 110 - - 110 - pF ACT TYPES Propagation Delay, An to Output (CD54/74AC/ACT138) t PLH , tPHL 5 (Note 12) 3.1 - 10.9 3 - 12 ns Propagation Delay, E1,E2 to Output (CD54/74AC/ACT138) tPLH , tPHL 5 2.7 - 9.5 2.6 - 10.5 ns Propagation Delay, E3 to Output (CD54/74AC/ACT138) t PLH , tPHL 5 2.8 - 10 2.8 - 11 ns Propagation Delay, An to Output (CD74AC/ACT238) t PLH , tPHL 5 4 - 14.2 3.9 - 15.6 ns Propagation Delay, E1,E2 to Output (CD74AC/ACT238) tPLH , tPHL 5 3.7 - 12.9 3.6 - 14.2 ns CD54/74AC138, CD54/74ACT138, CD74AC238, CD74ACT238

PD is used to determine the dynamic power consumption per package. ACT: PD = VCC 2 fi(CPD + CL) + VCC DICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage. FIGURE 1. PROPAGATION DELAY TIMES FIGURE 2. PROPAGATION DELAY TIMES

138 OUTPUT

238 OUTPUT

238 OUTPUT tPLH tPHL

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kW. FIGURE 3. PROPAGATION DELAY TIMES

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