CD74AC109 TI | Alldatasheet

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Technical content

CDx4AC109 Dual J-K Positive-Edge-Triggered Flip-flops with Clear and Preset

1 Features

  • AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
  • Speed of bipolar F, AS, and S, with significantly reduced power consumption
  • Balanced propagation delays
  • ±24mA output drive current – Fanout to 15 F devices
  • SCR-latchup-resistant CMOS process and circuit design
  • Exceeds 2kV ESD protection per MIL-STD-883, method 3015

2 Description

The CD74AC109-Q1 device contains two independent J-K positive edge triggered flip-flops. A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs that meets the setup-time requirements is transferred to the outputs on the positive-going edge of the clock (CLK) pulse. The device is qualified for automotive applications. Device Information PART NUMBER PACKAGE(1) BODY SIZE(2) CDx4AC109 D (SOIC, 16) 9.90mm x 3.90mm N (PDIP, 16) 19.3mm x 6.35mm J (CDIP, 16) 19.56mm x 6.92mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The body size (length × width) is a nominal value and does not include pins. PRE CLK J CLR Q Q C C C C K TG TG TG TG C C C C C C Copyright © 2016, Texas Instruments Incorporated Logic Diagram CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

10 Mechanical, Packaging, and Orderable

CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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3 Pin Configuration and Functions

Figure 3-1. CD54AC109 J Package; CD74AC109 D or N Package; 16-Pin CDIP, SOIC or PDIP (Top View) Table 3-1. Pin Functions PIN I/O(1) DESCRIPTION NAME NO. 1CLR 1 I Active low clear for first channel 1J 2 I J input for first channel 1K 3 I Active low K input for first channel 1CLK 4 I CLK input for first channel 1PRE 5 I Active low Preset input for first channel 1Q 6 O True Q output for first channel 1Q 7 O Inverted Q output for first channel GND 8 - Ground 2Q 9 O True Q output for second channel 2Q 10 O Inverted Q output for second channel 2PRE 11 I Active low preset for second channel 2CLK 12 I Clock input for second channel 2K 13 I Active low K input for second channel 2J 14 I J input for second channel 2CLR 15 I Active low clear for second channel VCC 16 - Power pin (1) I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CD54AC109 CD74AC109

4 Specifications

4.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 6 V IIK (2) Input clamp current (VI < 0 V or VI > VCC) ±20 mA IOK (2) Output clamp current (VO < 0 V or VO > VCC) ±50 mA IO Continuous output current (VO > 0 V or VO < VCC) ±50 mA Continuous current through VCC or GND ±100 mA Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

4.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), Level H0(1) ±2000 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.

4.3 Recommended Operating Conditions

(over operating free-air temperature range (unless otherwise noted)(1) TA = 25°C -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX VIH High-level input voltage VCC = 1.5 V 1.2 1.2 1.2 VVCC = 3 V 2.1 2.1 2.1 VCC = 5.5 V 3.85 3.85 3.85 VIL VCC = 1.5 V 0.3 0.3 0.3 VLow-level input voltage VCC = 3 V 0.9 0.9 0.9 VCC = 5.5 V 1.65 1.65 1.65 VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current VCC = 4.5 V to 5.5 V -24 -24 -24 mA IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA Δt/Δv Input transition rise or fall rate VCC = 1.5 V to 3 V 50 50 50 ns/V VCC = 3.6 V to 5.5 V 20 20 20 (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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4.4 Thermal Information

THERMAL METRIC(1) CD74AC109 UNITD (SOIC) N (PDIP)

16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 73 67 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

4.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25 °C -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX MIN MAX VOH VI = VIH or VIL IOH = -50 μΑ 1.5 V 1.4 1.4 1.4 V 3 V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 IOH = -4 mA 3 V 2.58 2.4 2.48 IOH = -24 mA 4.5 V 3.94 3.7 3.8 IOH = -50 mA(1) 5.5 V 3.85 IOH = -75 mA(1) 5.5 V 3.85 VOL VI = VIH or VIL IOL = 50 μA 1.5 V 0.1 0.1 0.1 V 3 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA 3 V 0.36 0.5 0.44 IOL = 24 mA 4.5 V 0.36 0.5 0.44 IOL = 50 mA(1) 5.5 V 1.65 IOL = 75 mA(1) 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 80 40 μA Ci 10 10 10 pF (1) Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C.

4.6 Timing Requirements

over recommended operating free-air temperature range, VCC = 1.5 V (unless otherwise noted) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 8 9 MHz tw Pulse duration CLK high or low 63 55 ns CLR or PRE low 56 49 tsu Setup time, before CLK↑ J or K 69 61 ns th Hold time, after CLK↑ J or K 0 0 ns trec Recovery time, before CLK↑ CLR ↑ or PRE↑ 31 27 ns www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CD54AC109 CD74AC109

4.7 Timing Requirements

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 71 81 MHz tW Pulse duration CLK high or low 7 6 ns CLR or PRE low 6.3 5.5 tsu Setup time, before CLK↑ J or K 7.7 6.8 ns th Hold time, after CLK↑ J or K 0 0 ns trec Recovery time, before CLK↑ CLR ↑ or PRE↑ 3.5 3.1 ns

4.8 Timing Requirements

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fclock Clock frequency 100 114 MHz tW Pulse duration CLK high or low 5 4.4 ns CLR or PRE low 4.5 3.9 tsu Setup time, before CLK↑ J or K 5.5 4.8 ns th Hold time, after CLK↑ J or K 0 0 ns trec Recovery time, before CLK↑ CLR ↑ or PRE↑ 2.5 2.2 ns

4.9 Switching Characteristics

over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fmax 8 9 MHz tPLH CLK Q or Q 129 117 ns CLR or PRE 153 139 tPHL CLK Q or Q 129 117 ns CLR or PRE 153 139

4.10 Switching Characteristics

over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fmax 71 81 MHz tPLH CLK Q or Q 3.6 14.4 3.7 13.1 ns CLR or PRE 4.3 17.1 4.4 15.5 tPHL CLK Q or Q 3.6 14.4 3.7 13.1 ns CLR or PRE 4.3 17.1 4.4 15.5 CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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4.11 Switching Characteristics

over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) -55°C to 125°C -40°C to 85°C UNIT MIN MAX MIN MAX fmax 100 114 MHz tPLH CLK Q or Q 2.6 10.3 2.7 9.4 ns CLR or PRE 3.1 12.2 3.2 11.1 tPHL CLK Q or Q 2.6 10.3 2.7 9.4 ns CLR or PRE 3.1 12.2 3.2 11.1

4.12 Operating Characteristics

VCC = 5 V, TA = 25°C PARAMETER TYP UNIT Cpd Power dissipation capacitance 56 pF www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CD54AC109 CD74AC109

5 Parameter Measurement Information

A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. I. All parameters and waveforms are not applicable to all devices. Figure 5-1. Load Circuit and Voltage Waveforms CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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tPLZ/tPZL 2 × VCC tPHZ/tPZH GND www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CD54AC109 CD74AC109

6 Detailed Description

6.1 Overview

A low level at the preset ( PRE) or clear ( CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

6.2 Functional Block Diagram

Figure 6-1. Logic Diagram, Each Flip-flop (Positive Logic)

6.3 Device Functional Modes

Table 6-1. Function Table (Each Flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H(1) H(1) H H ↑ L L L H H H ↑ H L Toggle H H ↑ L H Q0 Q0 H H ↑ H H H L H H L X X Q0 Q0 (1) Unpredictable and unstable condition if both PRE and CLR go low simultaneously CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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7 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

7.1 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1 μF and 1μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.

7.2 Layout

7.2.1 Layout Guidelines

  • Bypass capacitor placement – Place near the positive supply terminal of the device – Provide an electrically short ground return path – Use wide traces to minimize impedance – Keep the device, capacitors, and traces on the same side of the board whenever possible
  • Signal trace geometry – 8mil to 12mil trace width – Lengths less than 12cm to minimize transmission line effects – Avoid 90° corners for signal traces – Use an unbroken ground plane below signal traces – Flood fill areas around signal traces with ground – For traces longer than 12cm
  • Use impedance controlled traces
  • Source-terminate using a series damping resistor near the output
  • Avoid branches; buffer signals that must branch separately

7.2.2 Layout Example

≥ W W W ≥ 5W WORST BETTER BEST Figure 7-1. Example Trace Corners for Improved Signal Integrity www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CD54AC109 CD74AC109

0.1 F Figure 7-2. Example Bypass Capacitor Placement for TSSOP and Similar Packages 0.1 F VCC GND 1 20 10 11 9 12 GNDVCC GND Figure 7-3. Example Bypass Capacitor Placement for WQFN and Similar Packages GND GND VCC 0.1 F VCC Figure 7-4. Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages Long controlled-impedance trace Receiving PortTransmitting Port Figure 7-5. Example Damping Resistor Placement for Improved Signal Integrity CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 www.ti.com

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8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

8.1 Documentation Support

8.1.1 Related Documentation

For related documentation, see the following:

  • Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
  • Texas Instruments, Designing With Logic application report
  • Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application report

8.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

8.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

8.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

9 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision * (January 2003) to Revision A (December 2024) Page

  • Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Device Functional Modes, Application and Implementation section, Device and Documentation Support section, and

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com CD54AC109, CD74AC109 SCHS326A – JANUARY 2003 – REVISED DECEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: CD54AC109 CD74AC109

www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CD54AC109F3A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC109F3A CD54AC109F3A.A Active Production CDIP (J) | 16 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC109F3A CD74AC109E Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC109E CD74AC109E.A Active Production PDIP (N) | 16 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC109E CD74AC109M96 Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC109M CD74AC109M96.A Active Production SOIC (D) | 16 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC109M (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 29-May-2025 OTHER QUALIFIED VERSIONS OF CD54AC109, CD74AC109 :

  • Catalog : CD74AC109
  • Military : CD54AC109 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product
  • Military - QML certified for Military and Defense Applications Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC109M96 SOIC D 16 2500 353.0 353.0 32.0 Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CD74AC109E N PDIP 16 25 506 13.97 11230 4.32 CD74AC109E N PDIP 16 25 506 13.97 11230 4.32 CD74AC109E.A N PDIP 16 25 506 13.97 11230 4.32 CD74AC109E.A N PDIP 16 25 506 13.97 11230 4.32 Pack Materials-Page 3

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