CD54AC05_V01 TI | Alldatasheet
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Technical content
CDx4AC05 Hex Inverters With Open-Drain Outputs
1 Features
- AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
- Speed of bipolar F, AS, and S, with significantly reduced power consumption
- Fanout to 15 F devices
- SCR-latchup-resistant CMOS process and circuit design
- Exceeds 2kV ESD protection per MIL-STD-883, method 3015
2 Description
The 'AC05 devices contain six independent inverters. These devices perform the Boolean function Y = A. The open-drain outputs require pullup resistors to perform correctly, and can be connected to other open-drain outputs to implement active-low wired-OR or active-high wired-AND functions. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) CD54AC05 J (CDIP, 14) 19.56mm × 7.9mm 19.56mm × 6.67mm CD74AC05 BQA (WQFN, 14) 3mm × 2.5mm 3mm × 2.5mm D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.91mm N (PDIP, 14) 19.3mm × 9.4mm 19.3mm × 6.35mm PW (TSSOP, 14) 5mm × 6.4mm 5mm × 4.4mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. YA Logic Diagram, Each Inverter (Positive Logic) CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 www.ti.com
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Product Folder Links: CD54AC05 CD74AC05
3 Pin Configuration and Functions
Figure 3-1. CD54AC05 J Package, 14-Pin CDIP; CD74AC05 D, N, or PW Packages; 14-Pin SOIC, PDIP , or TSSOP (Top View) GND PAD 1A V CC 1 14 Figure 3-2. CD74AC05 BQA Package, 14-Pin WQFN Table 3-1. Pin Functions PIN I/O(1) DESCRIPTION NAME CD74AC05 CD54AC05 BQA, D, N, PW J 1A 1 1 I 1A Input 1Y 2 2 O 1Y Output 2A 3 3 I 2A Input 2Y 4 4 O 2Y Output 3A 5 5 I 3A Input 3Y 6 6 O 3Y Output GND 7 7 — Ground Pin 4Y 8 8 O 4Y Output 4A 9 9 I 4A Input 5Y 10 10 I 5Y Output 5A 11 11 I 5A Input 6Y 12 12 O 6Y Output 6A 13 13 I 6A Input VCC 14 14 — Power Pin NC — — — No Connection Thermal pad — Connect the GND pin to the exposed thermal pad for correct operation. Connect the thermal pad to any internal PCB ground plane using multiple vias for good thermal performance. (1) I = input, O = output, P = power, FB = feedback, GND = ground, N/A = not applicable www.ti.com CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CD54AC05 CD74AC05
4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 6 V IIK Input clamp current(2) VI < 0 or VI > VCC ±20 mA IOK Output clamp current(2) VO < 0 –50 mA IO Continuous current ±50 mA Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative voltage ratings may be exceeded if the input and output current ratings are observed.
4.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
4.3 Recommended Operating Conditions
over recommended operating free-air temperature range (unless otherwise noted)(1) TA = 25°C –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX MIN MAX VIH High-level input voltage VCC = 1.5 V 1.2 1.2 1.2 VVCC = 3 V 2.1 2.1 2.1 VCC = 5.5 V 3.85 3.85 3.85 VIL Low-level input voltage VCC = 1.5 V 0.3 0.3 0.3 VVCC = 3 V 0.9 0.9 0.9 VCC = 5.5 V 1.65 1.65 1.65 VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 5.5 0 5.5 0 5.5 V IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA Δt/Δv Input transition rise or fall rate VCC = 1.5 V to 3 V 50 50 50 ns/V VCC = 3.6 V to 5.5 V 20 20 20 (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4.4 Thermal Information
(WQFN) D (SOIC) N (PDIP) PW (TSSOP)
14 PINS
RθJA Junction-to-ambient thermal resistance 85.4 89.9 80 132.2 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, (SPRA953). CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 www.ti.com
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4.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX MIN MAX VOL VI = VIH or VIL IOL = 50 μA 1.5 V 0.1 0.1 0.1 V 3 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA 3 V 0.36 0.44 0.5 IOL = 24 mA 4.5 V 0.36 0.44 0.5 IOL = 50 mA(1) 5.5 V 1.65 IOL = 75 mA(1) 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 80 μA CI 10 10 10 pF (1) Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. 4.6 Switching Characteristics, VCC = 1.5 V over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLZ A Y 94 103 ns tPZL 74 81 4.7 Switching Characteristics, VCC = 3.3 V ± 0.3 V over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLZ A Y 3 10.4 2.9 11.5 ns tPZL 2.3 8.3 2.3 9.1 4.8 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLZ A Y 2.2 7.5 2.1 8.2 ns tPZL 1.7 5.9 1.6 6.5 www.ti.com CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CD54AC05 CD74AC05
4.9 Operating Characteristics
VCC = 5 V, TA = 25°C PARAMETER TYP UNIT Cpd Power dissipation capacitance 105 pF CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 www.ti.com
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5 Parameter Measurement Information
NOTES: A. C L includes probe and jig capacitance. B. All input pulses are supplied by generators having the following characteristics:PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤/charBnZrBnZrBnZrBnZrBnZrBnZrBnZrBnZr 3 ns, tf ≤ 3 ns. C. The outputs are measured one at a time, with one input transition per measurement. 50% VCC 50% VCC Output VOL ≈VCC 50% VCC 20% VCC From Output Under Test CL = 50 pF (see Note A) LOAD CIRCUIT 2 × VCC R1 = 500 Ω † R2 = 500 Ω † † When VCC = 1.5 V, R1 = R2 = 1 kΩ Figure 5-1. Load Circuit and Voltage Waveforms www.ti.com CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CD54AC05 CD74AC05
6 Detailed Description
6.1 Functional Block Diagram
Figure 6-1. Logic Diagram, Each Inverter (Positive Logic)
6.2 Device Functional Modes
(Each Inverter) INPUT A OUTPUT Y H L L Z CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 www.ti.com
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7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Power Supply Recommendations
The power supply can be any voltage between the MIN and MAX supply voltage rating located in the Recommended Operating Conditions table. Each V CC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, 0.1 μF is recommended. If there are multiple V CC pins, 0.01 μF or 0.022 μF is recommended for each power pin. It is acceptable to parallel multiple bypass caps to reject different frequencies of noise. A 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close to the power pin as possible for best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified in Figure 7-1 are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V CC; whichever makes more sense or is more convenient. It is generally acceptable to float outputs unless the part is a transceiver. If the transceiver has an output enable pin, it will disable the outputs section of the part when asserted. This will not disable the input section of the IOs, so they cannot float when disabled.
7.2.2 Layout Example
0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 7-1. Example Layout for the CD74AC05 www.ti.com CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CD54AC05 CD74AC05
8 Device and Documentation Support
8.1 Documentation Support (Analog)
8.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY CD54AC05 Click here Click here Click here Click here Click here CD74AC05 Click here Click here Click here Click here Click here
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (August 2024) to Revision E (November 2024) Page
- Added BQA and PW packages to Device Information table, Pin Configuration and Functions section, and Changes from Revision C (June 2002) to Revision D (August 2024) Page
- Added Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table, Device Functional Modes,Application and Implementation section, Device and Documentation Support section, and CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 www.ti.com
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com CD54AC05, CD74AC05 SCHS306E – JANUARY 2001 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CD54AC05 CD74AC05
www.ti.com 22-Nov-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CD54AC05F3A ACTIVE CDIP J 14 25 Non-RoHS & Green SNPB N / A for Pkg Type -55 to 125 CD54AC05F3A Samples CD74AC05BQAR ACTIVE WQFN BQA 14 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AC05 Samples CD74AC05E ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD74AC05E Samples CD74AC05M OBSOLETE SOIC D 14 TBD Call TI Call TI -55 to 125 AC05M CD74AC05M96 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 AC05M Samples CD74AC05PWR ACTIVE TSSOP PW 14 3000 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -55 to 125 AC05 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
www.ti.com 22-Nov-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54AC05, CD74AC05 :
- Catalog : CD74AC05
- Military : CD54AC05 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC05BQAR WQFN BQA 14 3000 210.0 185.0 35.0 CD74AC05M96 SOIC D 14 2500 353.0 353.0 32.0 CD74AC05M96 SOIC D 14 2500 356.0 356.0 35.0 CD74AC05PWR TSSOP PW 14 3000 366.0 364.0 50.0 CD74AC05PWR TSSOP PW 14 3000 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-Nov-2024 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CD74AC05E N PDIP 14 25 506 13.97 11230 4.32 CD74AC05E N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B
www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X
www.ti.com PACKAGE OUTLINE C 12X 0.65 3.9 14X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023
0.1 C A B
0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 7 8 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 14X (1.5) 14X (0.45) 12X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0014A SMALL OUTLINE PACKAGE 4220202/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 7 8
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQA 14 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3, 0.5 mm pitch 4227145/A
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max height PLASTIC QUAD FLAT PACK-NO LEAD BQA0014A A 0.08 C 0.05 C B SYMM SYMM 2.6 2.4 3.1 2.9PIN 1 INDEX AREA 0.8 0.7 0.05 0.00 SEATING PLANE C 1.1 0.9 1.6 1.4 2X 0.5 8X 0.5 14X 0.3 0.2 14X 0.5 0.3 (0.2) TYP 7 8 141 PIN 1 ID (OPTIONAL)
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (1.5)2X (0.5) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (Ø0.2) VIA TYP (R0.05) TYP 7 8 (PREFERRED) SOLDER MASK DEFINED
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224636/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQA0014A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 88% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.38) 8X (0.5) (2) 2X (0.5) 14X (0.25) 14X (0.6) (2.3) (2.8) (R0.05) TYP 7 8
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