CD74AC00 TI | Alldatasheet
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Technical content
CDx4AC00 Quadruple 2-Input Positive-nand Gates
1 Features
- AC types feature 1.5V to 5.5V operation and balanced noise immunity at 30% of the supply voltage
- Speed of bipolar F, AS, and S, with significantly reduced power consumption
- Balanced propagation delays
- ±24mA output drive current – Fanout to 15 F devices
- SCR-latchup-resistant CMOS process and circuit design
- Exceeds 2kV ESD protection per MIL-STD-883, method 3015
2 Description
The ‘AC00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function of Y = A • B or Y = A + B in positive logic. Device Information PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) CDx4AC00 D (SOIC, 14) 8.65mm × 6mm 8.65mm × 3.9mm N (PDIP, 14) 19.3mm × 9.4mm 19.3mm × 6.35mm J (CDIP, 14) 19.56mm × 7.9mm 19.56mm × 6.67mm (1) For more information, see Section 10. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. Logic Diagram, Each Gate (Positive Logic) CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
10 Mechanical, Packaging, and Orderable
CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 www.ti.com
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3 Pin Configuration and Functions
Figure 3-1. CD54AC00 J Package, 14-Pin CDIP; CD74AC00 D or N Packages, 14-Pin SOIC, or PDIP (Top View) PIN TYPE1 DESCRIPTION NO. NAME 1 1A I 1A Input 2 1B I 1B Input 3 1Y O 1Y Output 4 2A I 2A Input 5 2B I 2B Input 6 2Y O 2Y Output
7 GND – GND
14 VCC — Power Pin
(1) Signal Types: I = Input, O = Output, I/O = Input or Output. www.ti.com CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CD54AC00 CD74AC00
4 Specifications
4.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range –0.5 6 V IIK Input clamp current (VI < 0 or VI > VCC)(2) ±50 mA IOK Output clamp current (VO < 0 or VO > VCC)(2) ±50 mA IO Continuous output current (VO = 0 to VCC) ±50 mA VCC or GND Continuous current ±100 mA Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
4.2 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) TA = 25 °C -40°C TO 85°C -55°C TO 125°C UNIT MIN MAX MIN MAX MIN MAX VIH High-level input voltage VCC = 1.5 V 1.2 1.2 1.2 V VCC = 3 V 2.1 2.1 2.1 VCC = 4.5 V 3.15 3.15 VCC = 5.5 V 3.85 3.85 3.85 VIL Low-level input voltage VCC = 1.5 V 0.3 0.3 0.3 V VCC = 3 V 0.9 0.9 0.9 VCC = 4.5 V 1.35 1.35 VCC = 5.5 V 1.65 1.65 1.65 VI Input voltage 0 VCC 0 VCC 0 VCC V VO Output voltage 0 VCC 0 VCC 0 VCC V IOH High-level output current VCC = 4.5 V to 5.5 V -24 -24 -24 mA IOL Low-level output current VCC = 4.5 V to 5.5 V 24 24 24 mA Δt/Δv Input transition rise or fall rate VCC = 1.5 V to 3 V 50 50 50 ns/VVCC = 3.6 V to 5.5 V 20 20 20 (1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4.3 Thermal Information
UNITD (SOIC) N (PDIP)
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 119.9 80 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 www.ti.com
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4.4 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C -40°C TO 85 °C -55 °C TO 125°C UNIT MIN MAX MIN MAX MIN MAX VOH VI = VIH or VIL IOH = -50 μΑ 1.5 V 1.4 1.4 1.4 V 3 V 2.9 2.9 2.9 4.5 V 4.4 4.4 4.4 IOH = -4 mA 3 V 2.58 2.48 2.4 IOH = -24 mA 4.5 V 3.94 3.8 3.7 IOH = -50 mA(1) 5.5 V 3.85 IOH = -75 mA(1) 5.5 V 3.85 VOL VI = VIH or VIL IOL = 50 μA 1.5 V 0.1 0.1 0.1 V 3 V 0.1 0.1 0.1 4.5 V 0.1 0.1 0.1 IOL = 12 mA 3 V 0.36 0.44 0.5 IOL = 24 mA 4.5 V 0.36 0.44 0.5 IOL = 50 mA(1) 5.5 V 1.65 IOL = 75 mA(1) 5.5 V 1.65 II VI = VCC or GND 5.5 V ±0.1 ±1 ±1 μA ICC VI = VCC or GND, IO = 0 5.5 V 4 40 80 μA Ci 10 10 10 PF (1) Test one output at a time, not exceeding 1-second duration. Measurement is made by forcing indicated current and measuring voltage to minimize power dissipation. Test verifies a minimum 50-Ω transmission-line drive capability at 85°C and 75-Ω transmission-line drive capability at 125°C. 4.5 Switching Characteristics, VCC = 1.5V over recommended operating free-air temperature range, VCC = 1.5V, CL = 50pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLH A or B Y 83 91 ns tPHL 83 91 4.6 Switching Characteristics, VCC = 3.3V ± 0.3V over recommended operating free-air temperature range, VCC = 3.3V ± 0.3V, CL = 50pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLH A or B Y 2.7 9.3 2.6 10.2 ns tPHL 2.7 9.3 2.6 10.2 www.ti.com CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CD54AC00 CD74AC00
4.7 Switching Characteristics, VCC = 5V ± 0.5V over recommended operating free-air temperature range, VCC = 5V ± 0.5V, CL = 50pF (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) –40°C TO 85°C –55°C TO 125°C UNIT MIN MAX MIN MAX tPLH A or B Y 1.9 6.6 1.8 7.3 ns tPHL 1.9 6.6 1.8 7.3
4.8 Operating Characteristics
VCC = 5 V, TA = 25°C PARAMETER TYP UNIT Cpd Power dissipation capacitance 45 pF CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 www.ti.com
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5 Parameter Measurement Information
A. CL includes probe and test-fixture capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 3 ns, tf = 3 ns. Phase relationships between waveforms are arbitrary. D. For clock inputs, fmax is measured with the input duty cycle at 50%. E. The outputs are measured one at a time with one input transition per measurement. F. tPLH and tPHL are the same as tpd. G. tPZL and tPZH are the same as ten. H. tPLZ and tPHZ are the same as tdis. Figure 5-1. Load Circuit and Voltage Waveforms www.ti.com CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CD54AC00 CD74AC00
6 Detailed Description
6.1 Functional Block Diagram
Figure 6-1. Logic Diagram, Each Gate (Positive Logic)
6.2 Device Functional Modes
Table 6-1. Function Table (Each Gate) INPUTS OUTPUT Y A B H H L L X H X L H CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 www.ti.com
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7 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
7.1 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Section 4.2. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor and if there are multiple VCC terminals then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are commonly used in parallel. The bypass capacitor should be installed as close as possible to the power terminal for best results.
7.2 Layout
7.2.1 Layout Guidelines
When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions of digital logic devices are unused, for example, when only two inputs of a triple-input AND gate are used or only three of the four buffer gates are used. Such input pins should not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. Specified below are the rules that must be observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low bias to prevent them from floating. The logic level that should be applied to any particular unused input depends on the function of the device. Generally they will be tied to GND or V CC whichever make more sense or is more convenient. Floating outputs is generally acceptable, unless the part is a transceiver. If the transceiver has an output enable pin it will disable the outputs section of the part when asserted. This will not disable the input section of the I.O’s so they also cannot float when disabled.
7.2.2 Layout Example
0.1 F Unused inputs tied to VCC Bypass capacitor placed close to the device Avoid 90° corners for signal lines Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation Unused output left floating Figure 7-1. Layout Example for the CDx4AC00 www.ti.com CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CD54AC00 CD74AC00
8 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.
8.1 Documentation Support (Analog)
8.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 8-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY CD54AC00 Click here Click here Click here Click here Click here CD74AC00 Click here Click here Click here Click here Click here
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
8.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
8.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
8.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
9 Revision History
Changes from Revision C (June 2002) to Revision D (July 2024) Page
- Added Device Information table, Pin Functions table, Thermal Information table, Device Functional Modes,Application and Implementation section, Device and Documentation Support section, and Mechanical, CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 www.ti.com
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10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com CD54AC00, CD74AC00 SCHS303D – JANUARY 2001 – REVISED JULY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CD54AC00 CD74AC00
www.ti.com 29-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CD54AC00F3A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC00F3A CD54AC00F3A.A Active Production CDIP (J) | 14 25 | TUBE No SNPB N/A for Pkg Type -55 to 125 CD54AC00F3A CD74AC00E Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC00E CD74AC00E.A Active Production PDIP (N) | 14 25 | TUBE Yes NIPDAU N/A for Pkg Type -55 to 125 CD74AC00E CD74AC00M Obsolete Production SOIC (D) | 14 - - Call TI Call TI -55 to 125 AC00M CD74AC00M96 Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU | NIPDAU Level-1-260C-UNLIM -55 to 125 AC00M CD74AC00M96.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC00M CD74AC00M96G4.A Active Production SOIC (D) | 14 2500 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -55 to 125 AC00M (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1
www.ti.com 29-May-2025 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF CD54AC00, CD74AC00 :
- Catalog : CD74AC00
- Military : CD54AC00 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Military - QML certified for Military and Defense Applications Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC00M96 SOIC D 14 2500 356.0 356.0 35.0 CD74AC00M96 SOIC D 14 2500 353.0 353.0 32.0 Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 23-May-2025 TUBE L - Tube length T - Tube height W - Tube width B - Alignment groove width *All dimensions are nominal Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm) CD74AC00E N PDIP 14 25 506 13.97 11230 4.32 CD74AC00E N PDIP 14 25 506 13.97 11230 4.32 CD74AC00E.A N PDIP 14 25 506 13.97 11230 4.32 CD74AC00E.A N PDIP 14 25 506 13.97 11230 4.32 Pack Materials-Page 3
www.ti.com PACKAGE OUTLINE C TYP6.2 5.8
1.75 MAX
12X 1.27 14X 0.51 0.31 7.62 TYP0.25 0.13 0 - 8 0.25 0.10 0.25 GAGE PLANE 1.27 0.40 A NOTE 3 8.75 8.55 B NOTE 4 4.0 3.8 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: 1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm, per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side. 5. Reference JEDEC registration MS-012, variation AB. 1 14
0.25 C A B
0.1 C SEE DETAIL A DETAIL A TYPICAL SCALE 1.800
www.ti.com EXAMPLE BOARD LAYOUT (5.4)
0.07 MAX
0.07 MIN
14X (1.55) 14X (0.6) 12X (1.27) (R0.05) TYP 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT SYMM SYMM LAND PATTERN EXAMPLE SCALE:8X 7 8 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. METALSOLDER MASK OPENING NON SOLDER MASK DEFINED SOLDER MASK DETAILS SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN (5.4) 12X (1.27) 14X (0.6) 14X (1.55) 4220718/A 09/2016 SOIC - 1.75 mm max heightD0014A SMALL OUTLINE INTEGRATED CIRCUIT NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SYMM SYMM 7 8 SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:8X
www.ti.com PACKAGE OUTLINE C 14X .008-.014 [0.2-0.36]TYP -150 AT GAGE PLANE -.314 .308 -7.97 7.83 [ ] 14X -.026 .014 -1.65 1.15 [ ] .2 MAX TYP [5.08] .13 MIN TYP [3.3] TYP-.060 .015 -1.52 0.38 [ ] 4X .005 MIN [0.13] 12X .100 [2.54] .015 GAGE PLANE [0.38] A -.785 .754 -19.9419.15 [ ] B -.283 .245 -7.19 6.22 [ ] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 NOTES: 1. All controlling linear dimensions are in inches. Dimensions in brackets are in millimeters. Any dimension in brackets or parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is hermitically sealed with a ceramic lid using glass frit. 4. Index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. Falls within MIL-STD-1835 and GDIP1-T14. 7 8 PIN 1 ID (OPTIONAL) SCALE 0.900 SEATING PLANE .010 [0.25] C A B
www.ti.com EXAMPLE BOARD LAYOUT ALL AROUND [0.05] MAX .002 .002 MAX [0.05] ALL AROUND SOLDER MASK OPENING METAL (.063) [1.6] (R.002 ) TYP [0.05] 14X ( .039) [1] ( .063) [1.6] 12X (.100 ) [2.54] (.300 ) TYP [7.62] CDIP - 5.08 mm max heightJ0014A CERAMIC DUAL IN LINE PACKAGE 4214771/A 05/2017 LAND PATTERN EXAMPLE NON-SOLDER MASK DEFINED SCALE: 5X SEE DETAIL A SEE DETAIL B SYMM SYMM 7 8 DETAIL A SCALE: 15X SOLDER MASK OPENING METAL DETAIL B 13X, SCALE: 15X
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