CD54/74HC374

CD54HC374 TI | Alldatasheet

Document overview

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Technical content

Features

• Buffered Inputs
• Common Three-State Output Enable Control
• Three-State Outputs
• Bus Line Driving Capability
• Typical Propagation Delay (Clock to Q) = 15ns at V CC = 5V, CL = 15pF, TA = 25oC
• Fanout (Over Temperature Range)
• Wide Operating Temperature Range . . . -55 oC to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types - 2-V to 6-V Operation - High Noise Immunity: N IL = 30%, NIH = 30% of VCC at VCC = 5V
• HCT Types - 4.5-V to 5.5-V Operation - Direct LSTTL Input Logic Compatibility, V IL= 0.8V (Max), VIH = 2V (Min) - CMOS Input Compatibility, Il≤ 1µA at VOL , VOH

Description

The ’HC374, ’HCT374, ’HC574, and ’HCT574 are octal D-type flip-flops with 3-state outputs and the capability to drive 15 LSTTL loads. The eight edge-triggered flip-flops enter data into their registers on the LOW to HIGH transition of clock (CP). The output enable ( OE) controls the 3-state outputs and is independent of the register operation. WhenOE is HIGH, the outputs are in the high-impedance state. The 374 and 574 are identical in function and differ only in their pinout arrangements.

Ordering Information

TEMP. RANGE (oC) PACKAGE CD54HC374F3A -55 to 125 20 Ld CERDIP CD54HC574F3A -55 to 125 20 Ld CERDIP CD54HCT374F3A -55 to 125 20 Ld CERDIP CD54HCT574F3A -55 to 125 20 Ld CERDIP CD74HC374E -55 to 125 20 Ld PDIP CD74HC374M -55 to 125 20 Ld SOIC CD74HC374M96 -55 to 125 20 Ld SOIC CD74HC574E -55 to 125 20 Ld PDIP CD74HC574M -55 to 125 20 Ld SOIC CD74HC574M96 -55 to 125 20 Ld SOIC CD74HCT374E -55 to 125 20 Ld PDIP CD74HCT374M -55 to 125 20 Ld SOIC CD74HCT374M96 -55 to 125 20 Ld SOIC CD74HCT574E -55 to 125 20 Ld PDIP CD74HCT574M -55 to 125 20 Ld SOIC CD74HCT574M96 -55 to 125 20 Ld SOIC CD74HCT574PWR -55 to 125 20 Ld TSSOP NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. February 1998 - Revised May 2004 CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © 2004, Texas Instruments Incorporated CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574 High-Speed CMOS Logic Octal D-Type Flip-Flop, 3-State Positive-Edge Triggered [ /Title (CD74 H C374 C D74 H CT37 C D74 H C574 C D74 H CT57

CD54HC374, CD54HCT374 (CERDIP) CD74HC374, CD74HCT374 (PDIP, SOIC) TOP VIEW CD54HC574, CD54HCT574 (CERDIP) CD74HC574 (PDIP, SOIC) CD74HCT574 (PDIP, SOIC, TSSOP) TOP VIEW TRUTH TABLE INPUTS OUTPUT OE CP Dn Qn L ↑ HH L ↑ LL LLX Q 0 HXXZ H = High Level (Steady State) L = Low Level (Steady State) X= Don’t Care ↑ = Transition from Low to High Level Q0= The level of Q before the indicated steady-state input conditions were established Z = High Impedance State 1OE GND V CC CP 11 1OE GND V CC CP Q 0 D 0 CP OE Q 1 D 1 Q 2 D 2 Q 3 D 3 Q 4 D 4 Q 5 D 5 Q 6 D 6 Q 7 D 7 D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q D CP Q CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

Absolute Maximum Ratings Thermal Information DC Input Diode Current, IIK DC Output Diode Current, IOK DC Drain Current, per Output, IO DC Output Source or Sink Current per Output Pin, IO Operating Conditions Supply Voltage Range, VCC DC Input or Output Voltage, V Input Rise and Fall Time JA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating, and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. The package thermal impedance is calculated in accordance with JESD 51-7. PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HC TYPES High Level Input Voltage V Low Level Input Voltage High Level Output Voltage CMOS Loads V OH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V High Level Output Voltage TTL Loads - - --- - - - - V Low Level Output Voltage CMOS Loads V OL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V Low Level Output Voltage TTL Loads - - --- - - - - V Input Leakage Current I I VCC or GND CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

0 6 - - 8 - 80 - 160 µA Three- State Leakage Current VIL or VIH VO =V CC or GND HCT TYPES High Level Input Voltage VIH - - 4.5 to 5.5 2-- 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 High Level Output Voltage CMOS Loads V High Level Output Voltage TTL Loads Low Level Output Voltage CMOS Loads V Low Level Output Voltage TTL Loads Input Leakage Current I I VCC and GND Quiescent Device Current ICC VCC or GND 0 5.5 - - 8 - 80 - 160 µA Three- State Leakage Current VIL or VIH VO =V CC or GND Additional Quiescent Device Current Per Input Pin: 1 Unit Load CC (Note 2) VCC -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 µA NOTE: PARAMETER SYMBOL TEST CONDITIONS VCC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSVI(V) I O (mA) MIN TYP MAX MIN MAX MIN MAX HCT Input Loading Table INPUT UNIT LOADS HCT374 HCT574 D0 - D7 0.3 0.4 CP 0.9 0.75 OE 1.3 0.6 NOTE: Unit Load is∆ICC limit specific in DC Electrical Specifications Table, e.g., 360µA max. at 25oC. CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

Prerequisite for Switching Specifications PARAMETER SYMBOL V CC (V) 25oC -40 oC TO 85oC -55 oC TO 125oC UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX HC TYPES Maximum Clock Frequency fMAX 2 6 - - 5 - - 4 - - MHz 4.5 30 - - 25 - - 20 - - MHz 6 35 - - 29 - - 23 - - MHz Clock Pulse Width t W 2 80 - - 100 - - 120 - - ns 61 4 - -1 7- -2 0- - n s Setup Time Data to Clock tSU 26 0 - -7 5- -9 0- - n s 61 0 - -1 3- -1 5- - n s Hold Time Data to Clock 65 --5- -5-- n s HCT TYPES Maximum Clock Frequency fMAX 4.5 30 - - 25 - - 20 - - MHz Clock Pulse Width t W 4.5 16 - - 20 - - 24 - - ns Setup Time Data to Clock tSU 4.5 12 - - 15 - - 18 - - ns Hold Time Data to Clock Switching SpecificationsC L = 50pF, Input tr, tf= 6ns PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX HC TYPES Propagation Delay t PLH , tPHL C L = 50pF Clock to Output 2 - - 165 - 205 - 250 ns 4.5 - - 33 - 41 - 50 ns C L = 15pF 5 - 15 - - - - - ns C L = 50pF 6 - - 28 - 35 - 43 ns Output Disable to Q t PLZ ,tPHZ C L = 50pF 2 - - 135 - 170 - 205 ns 4.5 - - 27 - 34 - 41 ns C L = 15pF 5 - 11 - - - - - ns C L = 50pF 6 - - 23 - 29 - 35 ns CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

Output Enable to Q t PZL ,tPZH C L = 50pF 2 - - 150 - 190 - 225 ns 4.5 - - 30 - 38 - 45 ns C L = 15pF 5 - 12 - - - - - ns C L = 50pF 6 - - 26 - 33 - 38 ns Maximum Clock Frequency f MAX C L = 15pF 5 - 60 - - - - - MHz Output Transition Time t THL , tTLH C L = 50pF 2 - - 60 - 75 - 90 ns 4.5 - - 12 - 15 - 18 ns 6 - - 10 - 13 - 15 ns Input Capacitance C I C L = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance C O - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 3, 4) C PD C L = 15pF 5 - 39 - - - - - pF HCT TYPES Propagation Delay t PHL, tPLH Clock to Output C L = 50pF 4.5 - - 33 - 41 - 50 ns C L = 15pF 5 - 15 - - - - - ns Output Disable to Q t PLZ ,tPHZ C L = 50pF 4.5 - - 28 - 35 - 42 ns C L = 15pF 5 - 11 - - - - - ns Output Enable to Q t PZL ,tPZH C L = 50pF 4.5 - - 30 - 38 - 45 ns C L = 15pF 5 - 12 - - - - - ns Maximum Clock Frequency f MAX C L = 15pF 5 - 60 - - - - - MHz Output Transition Time t TLH , tTHL C L = 50pF 4.5 - - 12 - 15 - 18 ns Input Capacitance C I C L = 50pF - 10 - 10 - 10 - 10 pF Three-State Output Capacitance C O - - 20 - 20 - 20 - 20 pF Power Dissipation Capacitance (Notes 3, 4) C PD C L = 15pF 5 - 47 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package. 4. PD =C PD VCC 2 fi+ ∑ VCC 2 fO C L where fi= Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage. Switching SpecificationsC L = 50pF, Input tr, tf= 6ns (Continued) PARAMETER SYMBOL TEST CONDITIONS V CC (V) 25oC -40oC TO 85oC -55oC TO 125oC UNITSMIN TYP MAX MIN MAX MIN MAX CD54/74HC374, CD54/74HCT374, CD54/74HC574, CD54/74HCT574

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) 5962-8974201RA ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HC574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT374F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT574F ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD54HCT574F3A ACTIVE CDIP J 20 1 None Call TI Level-NC-NC-NC CD74HC374E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC374M ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HC374M96 ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HC574E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HC574M ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HC574M96 ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HCT374E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT374M ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HCT374M96 ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HCT574E ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-NC-NC-NC CD74HCT574M ACTIVE SOIC DW 20 25 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HCT574M96 ACTIVE SOIC DW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1 YEAR/ Level-1-235C-UNLIM CD74HCT574PWR ACTIVE TSSOP PW 20 2000 Pb-Free (RoHS) CU NIPDAU Level-1-250C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - May not be currently available - please checkhttp://www.ti.com/productcontentfor the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br):TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 1

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 28-Feb-2005 Addendum-Page 2

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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