TPS6735_08 TI1 | Alldatasheet
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Technical content
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 /C0068Negative 5-V 200-mA Output (VCC ≥ 4.5 V) /C00684-V to 6.2-V Input Operating Range /C006878% Typical Efficiency /C0068160-kHz Fixed-Frequency Current-Mode PWM Controller /C0068EN Input Inhibits Operation and Reduces Supply Current to 1 µA /C0068Soft Start /C00688-Pin SOIC and DIP Packages /C0068−40°C to 85°C Free-Air Temperature Range /C0068Pin-for-Pin Compatible with MAX735
description
The TPS6735 is a fixed negative 5-V output inverting dc/dc converter capable of delivering 200 mA from inputs as low as 4.5 V. The only external components required are an inductor, an output filter capacitor, an input filter capacitor, a reference filter capacitor, and a Schottky rectifier. An enable input is provided to shut down the inverter when a −5-V output is not needed. The typical supply current is 1.9 mA at no-load and is further reduced to 1-µA when the enable input is low. The TPS6735 is a 160-kHz current-mode pulse-width-modulation (PWM) controller with a p-channel MOSFET power switch. The gate drive uses the −5-V output to reduce the die area needed to realize the 0.4-Ω MOSFET. Soft start is accomplished with the addition of one small capacitor at SS. A 1.22-V reference is available for external loads up to 125 µA. The TPS6735 is attractive for board-level dc/dc conversion in computer peripherals and in battery-powered equipment requiring high efficiency and low supply current. The TPS6735 is available in 8-pin DIP and SOIC packages and operates over a free-air temperature range of −40°C to 85°C. EN REF SS COMP VCC OUT GND FB TPS6735 1 µF 47 µF 82 pF† 10 µF 10 µH 1N5817 100 µF − 5 V VI 4 V to 6.2 V ENABLE † Not required for loads of 100 mA or less Figure 1. Typical Circuit Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 AVAILABLE OPTIONS PACKAGED DEVICES CHIP FORMTA SMALL OUTLINE (D) PLASTIC DIP (P) CHIP FORM (Y) −40°C to 85°C TPS6735ID TPS6735IP TPS6735Y The D package is also available taped and reeled (TPS6735IDR). functional block diagram EN EN1EN Error Amplifier Voltage Reference SS Clamp 1.2 MΩ R S Q 160-kHz Oscillator PWM Comparator Σ Driver FB Power Switch PMOS UVLO VCC REF Overcurrent Comparator VCC OUT FB COMP GND REF 3SS Current- Sense Amplifier Drive Latch
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 chip information These chips, when properly assembled, display characteristics similar to the TPS6735. Thermal compression or ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with conductive epoxy or a gold-silicon preform. 88 81 45 5 TPS6735Y (1) (2) (3) (8) (7) (6) EN REF SS OUT FB VCC GND BONDING PAD ASSIGNMENTS CHIP THICKNESS: 15 TYPICAL BONDING PADS: 4 × 4 MINIMUM TJ max = 150°C TOLERANCES ARE ±10%. ALL DIMENSIONS ARE IN MILS. (4) (5) COMP Terminal Functions TERMINAL DESCRIPTIONNAME NO. DESCRIPTION EN 1 Enable. EN > 2 V turns on the TPS6735. EN ≤ 0.4 V turns it off. REF 2 1.22-V reference voltage output. REF can source 125 µA for external loads. SS 3 Soft start. A capacitor between SS and GND brings the output voltage up slowly. COMP 4 Compensation. A capacitor to ground stabilizes the feedback loop. FB 5 Feedback. FB connects to the dc/dc converter output. GND 6 Ground OUT 7 Power MOSFET drain connection VCC 8 Supply-voltage input
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 detailed description The following descriptions refer to the functional block diagram. current-sense amplifier The current-sense amplifier, which has a fixed gain of 3, amplifies the slope-compensated current-sense voltage (a summation of the voltage on the current-sense resistor and the oscillator ramp) and feeds it to the PWM comparator. driver latch The latch, which consists of a set/reset flip-flop and associated logic, controls the state of the power switch by turning the driver on and off. A high output from the latch turns the switch on; a low output turns it off. In normal operation the flip-flop is set high during the clock pulse, but gating keeps the latch output low until the clock pulse is over. The latch is reset when the PWM comparator output goes high. enable (EN) A logic low on EN puts the TPS6735 in shutdown mode. In shutdown, the output power switch, voltage reference, and other functions shut off and the supply current is reduced to 1-µA maximum. The soft-start capacitor is discharged through a 1.2-MΩ resistance and the output falls to zero volts. error amplifier The error amplifier is a high-gain differential amplifier used to regulate the converter output voltage. The amplifier generates an error signal, which is fed to the PWM comparator, by comparing a sample of the output voltage to the reference and amplifying the difference. The output sample is obtained from a resistive divider connected between FB and REF. FB is connected externally to the converter output, and the divider output is connected to the error-amplifier input. An 82-pF capacitor connected between COMP and GND is required to stabilize the control loop for loads greater than 100 mA. oscillator and ramp generator The oscillator circuit provides a 160-kHz clock to set the converter operating frequency, and a timing ramp for slope compensation. The clock waveform is a pulse, a few hundred nanoseconds in duration, that is used to limit the maximum power switch duty cycle to 95%. The timing ramp is summed with the current-sense signal at the input to the current-sense amplifier. overcurrent comparator The overcurrent comparator monitors the current in the power switch. The comparator trips and initiates a soft-start cycle if the power-switch current exceeds 2 A peak. power switch The power switch is a 0.4-Ω p-channel MOSFET with current sensing. The drain is connected to OUT and the current sense is connected to a resistor. The voltage across the resistor is proportional to current in the power switch and is tied to the overcurrent comparator and the current-sense amplifier. In normal operation, the power switch is turned on at the start of each clock cycle and turned off when the PWM comparator resets the drive latch. PWM comparator The comparator resets the drive latch and turns off the power switch whenever the slope-compensated current-sense signal from the current-sense amplifier exceeds the error signal. reference The 1.22-V reference is brought out on REF and can source 125-µA maximum to external loads. A 10-µF capacitor connected between REF and GND is recommended to minimize noise pickup.
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 5POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 SS clamp The SS clamp circuit limits the signal level on error-amplifier output during start-up. The voltage on SS is amplified and used to override the error-amplifier output until it rises above that output, at which point the error amplifier takes over. This prevents the input to the PWM comparator from exceeding its common-mode range (i.e., error amplifier output too high to be reached by the current ramp) by limiting the maximum voltage on the error-amplifier output during start-up. Soft start causes the output voltage to increase to the regulation point at the controlled rate. The voltage on the charging soft-start capacitor gradually raises the clamp on the error amplifier output voltage, limiting surge currents at power up by increasing the current limit threshold on a cycle-by-cycle basis. A soft-start cycle is initiated when either the enable (EN) signal is switched high or an overcurrent fault condition triggers the discharge of the soft-start capacitor. undervoltage lockout (UVLO) The supply voltage is fed through a voltage divider to the input of the UVLO and compared to a reference. The undervoltage-lockout logic prevents the MOSFET from turning on while the supply voltage is below the undervoltage-lockout voltage threshold, and once the supply voltage on V CC is above the threshold, an SS cycle is initiated. DISSIPATION RATING TABLE PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR ABOVE T A = 25°C TA = 70°C POWER RATING TA = 85°C POWER RATING D 725 mW 5.8 mW/°C 464 mW 377 mW P 1175 mW 9.4 mW/°C 752 mW 611 mW absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All voltage values are with respect to network terminal ground. recommended operating conditions MIN NOM MAX UNIT Supply voltage 4 6.2 V Decoupling capacitor 1 µF Input capacitor 47 µF Reference capacitor 10 µF Output capacitor 100 µF Compensation capacitor 82 pF Inductor 10 µH
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 electrical characteristics over recommended operating free-air temperature range, VCC = 5 V, IO = 0, EN = 5 V, typical values are at TA = 25°C (unless otherwise noted) (refer to Figure 15) PARAMETER TEST CONDITION MIN TYP MAX UNIT Supply current 1.9 mA Standby current EN = 0.4 V 1 10 µA High-level input threshold voltage, EN 2 V Low-level input threshold voltage, EN 0.4 V Input current, EN −1 1 µA Compensation pin impedance 7.5 kΩ Oscillator frequency 160 kHz Reference voltage IO(ref) ≤ 125 µA 1.22 V Reference drift 50 ppm/°C Undervoltage lockout 3.7 V On resistance, OUT 0.4 Ω Leakage current, OUT 20 nA performance characteristics over recommended operating free-air temperature range, typical values at TA = 25°C (unless otherwise noted) (refer to Figure 15) PARAMETER TEST CONDITION MIN TYP MAX UNIT Output voltage VCC = 4.5 V to 6.2 V IO = 0 mA to 200 mA −4.75 −5 −5.25 V Load current VCC = 4.5 V to 6.2 V 200 270 mA Line regulation VCC = 4.5 V to 6.2 V 0.2% Load regulation IO = 25 mA to 200 mA 0.2% Efficiency IO =100 mA 78%
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
APPLICATION INFORMATION
− Load Current − mAIL 200 Output Voltage Ripple − mV −50 t − Time − s 100 VI = 5 V VO = − 5 V IO = 0 mA to 200 mA 2 ms/div Figure 4. Load Transient Response Figure 5. Line Transient Response
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 system typical characteristics (continued) Figure 9 0.6 0.4 0.5 1 1.5 2 2.5 3 4 No-Load Supply Current − mA 1.4 1.8 Supply Voltage − V NO-LOAD SUPPLY CURRENT vs SUPPLY VOLTAGE 4.5 5 6 6.53.5 5.5 1.6 1.2 0.8 0.2 IO = 0 A (see Figure 15) Figure 11 162 160 156 154 − 40 − 20 0 − Oscillator Frequency − kHz 166 170 OSCILLATOR FREQUENCY vs TEMPERATURE 172 20 40 168 164 158 T − Temperature − °C fosc 60 80 100 120 140 VI = 5 V VI = 6 V VI = 4 V Figure 10 200 150 Maximum Load Current − mA 250 350 Supply Voltage − V MAXIMUM LOAD CURRENT vs SUPPLY VOLTAGE 400 5.75 6 6.25 6.5 300 100 5.5 (see Figure 15) Figure 12 0.6 0.4 200 400 600 800 Switch Current Limit − A 1.4 1.8 Soft-Start Voltage − mV SWITCH CURRENT LIMIT vs SOFT-START VOLTAGE 1000 1200 1.6 1.2 0.8 0.2 VI = 6 V VI = 5 V VI = 4 V R1 and R2 Varied (see Figure 15)
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 A low equivalent series resistance (ESR) output filter capacitor is necessary to minimize the output-ripple voltage. An ESR of 100 mΩ limits the output ripple to 90 mV or less for output loads up to 200 mA. rectifier A Schottky diode or high-speed silicon rectifier should be used with a maximum continuous current rating of 1 A for operation up to full load (200 mA). output ripple filtering A low-pass filter may be added to the converter output to reduce the output voltage ripple (see Figure 15). The LC filter has a cutoff frequency of 7.2 kHz. The inductor filter must have a low resistance to avoid large output voltage drops. The output voltage ripple is reduced to 5 mV when the LC output filter is used. FB must be connected to the output node before the connection for the low-pass filter. printed circuit board layout A ground plane is recommended in a printed circuit board (PCB) layout to ensure quiet operation. Attention should be given to minimizing the lengths of the switching loops. Bypass capacitors should be placed as close to the TPS6735 as possible to prevent instability and noise pickup. V CC and GND should be bypassed directly with a 1-µF ceramic capacitor and a large bypass capacitor (e.g. 47 µF) to maximize noise immunity. The TPS6735 should not be used with IC sockets, wire-wrap prototype boards, or other constructions that are susceptible to noise pick-up. Optional Low-Pass Output Filter 22 µH 22 µF EN REF SS COMP VCC OUT GND FB TPS6735ID 82 pF 10 µF 130 kΩ 300 kΩ 47 µF 10 kΩ 1 µF 10 µH 1N5817
1 A, 20 V +
100 µF/10 V VO VI ENABLE 0.1 µF Figure 15. Application Circuit
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 13POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Table 1. Bill of Materials
1 IC Power supply −5 V U1 TPS6735ID Texas Instruments
1 Diode Schottky D1 1N5817GI General Instrument
1 Inductor 10 µH L1 DO1608C-103
1 Capacitor 47 µF tantalum 16 V 7343 C1 593D476X9016D2W
1 Capacitor 100 µF tantalum 10 V 7343 C2 593D107X9010D2W
1 Capacitor 10 µF tantalum 10 V 3528 C3 293D106X0010B2W
1 Capacitor 82 pF ceramic 50 V 0805 C4
1 Capacitor 1 µF ceramic 16 V 1206 C5
1 Resistor 130 kΩ 0805 R1
1 Resistor 300 kΩ 0805 R2
1 Resistor 10 kΩ 0805 R3
Figure 16. Component Placement
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Figure 17. Solder Paste Mask Figure 18. PC Component Side
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 15POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 Figure 19. PC Wiring Side (Viewed From Component Side)
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0.228 (5,80) 0.244 (6,20) 0.069 (1,75) MAX 0.010 (0,25) 0.004 (0,10) 0.014 (0,35) 0.020 (0,51) A 0.157 (4,00) 0.150 (3,81) 0.044 (1,12) 0.016 (0,40) Seating Plane 0.010 (0,25) PINS ** 0.008 (0,20) NOM A MIN A MAX DIM Gage Plane 0.189 (4,80) (5,00) 0.197 (8,55) (8,75) 0.337 0.344 (9,80) 0.394 (10,00) 0.386 0.004 (0,10) M0.010 (0,25) 0.050 (1,27) 0°−/C0257 8° NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Four center pins are connected to die mount pad. E. Falls within JEDEC MS-012
/C0084/C0080/C0083/C0054/C0055/C0051/C0053 /C0070/C0073/C0088/C0069/C0068 /C0078/C0069/C0071/C0065/C0084/C0073/C0086/C0069 /C0053/C0262/C0086 /C0050/C0048/C0048/C0262/C0109/C0065 /C0073/C0078/C0086/C0069/C0082/C0084/C0073/C0078/C0071 /C0068/C0067/C0047/C0068/C0067 /C0067/C0079/C0078/C0086/C0069/C0082/C0084/C0069/C0082 SLVS141A − JULY 1996 − REVISED JANUARY 1997 17POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443 MECHANICAL DATA P (R-PDIP-T8) PLASTIC DUAL-IN-LINE PACKAGE 4040082/B 03/95 0.310 (7,87) 0.290 (7,37) 0.010 (0,25) NOM 0.400 (10,60) 0.355 (9,02) 0.020 (0,51) MIN 0.070 (1,78) MAX 0.240 (6,10) 0.260 (6,60) 0.200 (5,08) MAX 0.125 (3,18) MIN 0.015 (0,38) 0.021 (0,53) Seating Plane M0.010 (0,25) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Falls within JEDEC MS-001
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