CD4724BC FAIRCHILD | Alldatasheet

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Technical content

Features

■ Wide supply voltage range: 3.0V to 15V ■ High noise immunity: 0.45 VDD (typ.) ■ Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS ■ Serial to parallel capability ■ Storage register capability ■ Random (addressable) data entry ■ Active high demultiplexing capability ■ Common active high clear Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Pin Assignments for DIP and SOIC Top View Truth Table Order Number Package Number Package Description CD4724BCM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body CD4724BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Mode Selection E CL Addressed Unaddressed Mode Latch Latch L L Follows Data Holds Previous Data Addressable Latch H L Hold Previous Data Holds Previous Data Memory L H Follows Data Reset to “0” Demultiplexer H H Reset to “0” Reset to “0” Clear

www.fairchildsemi.com 2 CD4724BC Logic Diagram

3 www.fairchildsemi.com CD4724BC Absolute Maximum Ratings(Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of “Recom- mended Operating Conditions” and Electrical Characteristics” provide con- ditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. Note 3: IOL and IOH are tested one output at a time. DC Supply Voltage (VDD ) −0.5V to +18 VDC Input Voltage (VIN) −0.5V to VDD +0.5 VDC Storage Temperature (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (TL) (Soldering, 10 seconds) 260 °C DC Supply Voltage (VDD ) 3.0V to 15 V DC Input Voltage (VIN) 0V to V DD VDC Operating Temperature Range (TA) −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD = 5V 20 0.02 20 150 µA Current V DD = 10V 40 0.02 40 300 µA VDD = 15V 80 0.02 80 600 µA VOL LOW Level |I O | ≤ 1 µA Output Voltage V DD = 5V 0.05 0 0.05 0.05 V VDD = 10V 0.05 0 0.05 0.05 V VDD = 15V 0.05 0 0.05 0.05 V VOH HIGH Level |I O | ≤ 1 µA Output Voltage V DD = 5V 4.95 4.95 5.0 4.95 V VDD = 10V 9.95 9.95 10 9.95 V VDD = 15V 14.95 14.95 15 14.95 V Input Voltage V DD = 10V, VO = 1V or 9V 3.0 4.5 3.0 3.0 V Input Voltage V DD = 10V, VO = 1V or 9V 7.0 7.0 5.5 7.0 V IIN Input Current V DD = 15V, VIN = 0V −0.30 −10−5 −0.30 −1.0 µA VDD = 15V, VIN = 15V 0.30 10 −5 0.30 1.0 µA

www.fairchildsemi.com 4 CD4724BC TA = 25°C, CL = 50 pF , RL = 200k, Input tr = tf = 20 ns, unless otherwise noted Note 4: AC Parameters are guaranteed by DC correlated testing. Note 5: Dynamic power dissipation (PD ) is given by: PD = (CPD + CL) VCC 2f + PQ ; where CL = load capacitance; f = frequency of operation; for further details, see Application Note AN-90, “Family Characteristics”. Symbol Parameter Conditions Min Typ Max Units tPHL, tPLH Propagation Delay V DD = 5V 200 400 ns Data to Output V DD = 10V 75 150 ns VDD = 15V 50 100 ns tPLH , tPHL Propagation Delay V DD = 5V 200 400 ns Enable to Output V DD = 10V 80 160 ns VDD = 15V 60 120 ns tPHL Propagation Delay V DD = 5V 175 350 ns Clear to Output V DD = 10V 80 160 ns VDD = 15V 65 130 ns tPLH , tPHL Propagation Delay V DD = 5V 225 450 ns Address to Output V DD = 10V 100 200 ns VDD = 15V 75 150 ns tTHL , tTLH Transition Time V DD = 5V 100 200 ns (Any Output) V DD = 10V 50 100 ns VDD = 15V 40 80 ns TWH , TWL Minimum Data V DD = 5V 100 200 ns Pulse Width V DD = 10V 50 100 ns VDD = 15V 40 80 ns tWH , tWL Minimum Address V DD = 5V 200 400 ns Pulse Width V DD = 10V 100 200 ns VDD = 15V 65 125 ns tWH Minimum Clear V DD = 5V 75 150 ns Pulse Width V DD = 10V 40 75 ns VDD = 15V 25 50 ns tSU Minimum Setup Time V DD = 5V 40 80 ns Data to E V DD = 10V 20 40 ns VDD = 15V 15 30 ns tH Minimum Hold Time V DD = 5V 60 120 ns Data to E V DD = 10V 30 60 ns VDD = 15V 25 50 ns tSU Minimum Setup Time V DD = 5V −15 50 ns Address to E V DD = 10V 0 30 ns VDD = 15V 0 20 ns tH Minimum Hold Time V DD = 5V −50 15 ns Address to E V DD = 10V −20 10 ns VDD = 15V −15 5 ns C PD Power Dissipation Per Package 100 pF Capacitance (Note 5) C IN Input Capacitance Any Input 5.0 7.5 pF

5 www.fairchildsemi.com CD4724BC Switching Time Waveforms

www.fairchildsemi.com 6 CD4724BC Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body Package Number M16A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. CD4724BC 8-Bit Addressable Latch LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide Package Number N16E