CD4723

CD4723BM NSC | Alldatasheet

Document overview

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Technical content

Features

Y Wide supply voltage range 3.0V to 15V Y High noise immunity 0.45 V DD (typ.) Y Low power TTL fan out of 2 driving 74L compatibility or 1 driving 74LS Y Serial to parallel capability Y Storage register capability Y Random (addressable) data entry Y Active high demultiplexing capability Y Common active high clear Connection Diagrams CD4723B Dual-In-Line Package TL/F/6003–1 Top View CD4724B Dual-In-Line Package TL/F/6003–2 Top View Order Number CD4723B or CD4724B Truth Table Mode Selection E CL Addressed Unaddressed ModeLatch Latch L L Follows Data Holds Previous Data Addressable Latch H L Hold Previous Data Holds Previous Data Memory L H Follows Data Reset to ‘‘0’’ Demultiplexer H H Reset to ‘0’’ Reset to ‘‘0’’ Clear C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2 ) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. DC Supply Voltage (V DD) b0.5V to a18 V DC Input Voltage (V IN) b0.5V to V DD a0.5 V DC Storage Temperature (T S) b65§Ct o a150§C Power Dissipation (P D) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (T (Soldering, 10 seconds) 260 §C Recommended Operating Conditions (Note 2) DC Supply Voltage (V DD) 3.0V to 15 V DC Input Voltage (V IN) 0 Vt oV DD VDC Operating Temperature Range (T A) CD4723BM/CD4724BM b55§Ct o a125§C CD4723BC/CD4724BC b40§Ct o a85§C Symbol Parameter Conditions b55§C a25§C a125§C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD e 5V 5.0 0.02 5.0 150 mA Current V DD e 10V 10 0.02 10 300 mA VDD e 15V 20 0.02 20 600 mA VOL Low Level lIOl s 1 mA Output Voltage V DD e 5V 0.05 0 0.05 0.05 V VDD e 10V 0.05 0 0.05 0.05 V VDD e 15V 0.05 0 0.05 0.05 V VOH High Level lIOl s 1 mA Output Voltage V DD e 5V 4.95 4.95 5.0 4.95 V VDD e 10V 9.95 9.95 10 9.95 V VDD e 15V 14.95 14.95 15 14.95 V Input Voltage V DD e 10V, V O e 1V or 9V 3.0 4.5 3.0 3.0 V Input Voltage V DD e 10V, V O e 1V or 9V 7.0 7.0 5.5 7.0 V IIN Input Current V DD e 15V, V IN e 0V b0.1 b10b5 b0.1 b1.0 mA VDD e 15V, V IN e 15V 0.1 10 b5 0.1 1.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device operation. Note 2: V SS e 0V unless otherwise specified. Note 3: IOL and I OH are tested one output at a time.

Symbol Parameter Conditions b40§C a25§C a85§C Units Min Max Min Typ Max Min Max IDD Quiescent Device V DD e 5V 20 0.02 20 150 mA Current V DD e 10V 40 0.02 40 300 mA VDD e 15V 80 0.02 80 600 mA VOL Low Level lIOl s 1 mA Output Voltage V DD e 5V 0.05 0 0.05 0.05 V VDD e 10V 0.05 0 0.05 0.05 V VDD e 15V 0.05 0 0.05 0.05 V VOH High Level lIOl s 1 mA Output Voltage V DD e 5V 4.95 4.95 5.0 4.95 V VDD e 10V 9.95 9.95 10 9.95 V VDD e 15V 14.95 14.95 15 14.95 V Input Voltage V DD e 10V, V O e 1V or 9V 3.0 4.5 3.0 3.0 V Input Voltage V DD e 10V, V O e 1V or 9V 7.0 7.0 5.5 7.0 V IIN Input Current V DD e 15V, V IN e 0V b0.30 b10b5 b0.30 b1.0 mA VDD e 15V, V IN e 15V 0.30 10 b5 0.30 1.0 mA Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device operation. Note 2: V SS e 0V unless otherwise specified. Note 3: IOL and I OH are tested one output at a time.

TA e 25§C, C L e 50 pF, R L e 200k, Input t r e tf e 20 ns, unless otherwise noted Symbol Parameter Conditions Min Typ Max Units tPHL, tPLH Propagation Delay V DD e 5V 200 400 ns Data to Output V DD e 10V 75 150 ns VDD e 15V 50 100 ns tPLH,t PHL Propagation Delay V DD e 5V 200 400 ns Enable to Output V DD e 10V 80 160 ns VDD e 15V 60 120 ns tPHL Propagation Delay V DD e 5V 175 350 ns Clear to Output V DD e 10V 80 160 ns VDD e 15V 65 130 ns tPLH,t PHL Propagation Delay V DD e 5V 225 450 ns Address to Output V DD e 10V 100 200 ns VDD e 15V 75 150 ns tTHL,t TLH Transition Time V DD e 5V 100 200 ns (Any Output) V DD e 10V 50 100 ns VDD e 15V 40 80 ns TWH,T WL Minimum Data V DD e 5V 100 200 ns Pulse Width V DD e 10V 50 100 ns VDD e 15V 40 80 ns tWH,t WL Minimum Address V DD e 5V 200 400 ns Pulse Width V DD e 10V 100 200 ns VDD e 15V 65 125 ns tWH Minimum Clear V DD e 5V 75 150 ns Pulse Width V DD e 10V 40 75 ns VDD e 15V 25 50 ns tSU Minimum Setup Time V DD e 5V 40 80 ns Data to E V DD e 10V 20 40 ns VDD e 15V 15 30 ns tH Minimum Hold Time V DD e 5V 60 120 ns Data to E V DD e 10V 30 60 ns VDD e 15V 25 50 ns tSU Minimum Setup Time V DD e 5V b15 50 ns Address to E V DD e 10V 0 30 ns VDD e 15V 0 20 ns tH Minimum Hold Time V DD e 5V b50 15 ns Address to E V DD e 10V b20 10 ns VDD e 15V b15 5 ns CPD Power Dissipation Per Package 100 pFCapacitance (Note 4) CIN Input Capacitance Any Input 5.0 7.5 pF *AC Parameters are guaranteed by DC correlated testing. Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and Electrical Characteristics’’ provide conditions for actual device operation. Note 2: V SS e 0V unless otherwise specified. Note 3: IOL and I OH are tested one output at a time. Note 4: Dynamic power dissipation (P D) is given by: P D e (CPD a CL)V CC2f a PQ; where C L e load capacitance; f e frequency of operation; for further details, see Application Note AN-90, ‘‘54C/74C Family Characteristics’’.

TL/F/6003–3

Logic Diagrams (Continued) CD4724B TL/F/6003–4

TL/F/6003–5

CD4723BM/CD4723BC Dual 4-Bit Addressable Latch CD4724BM/CD4724BC 8-Bit Addressable Latch Physical Dimensions inches (millimeters) Ceramic Dual-In-Line Package (J) Order Number CD4723BMJ, CD4723BCJ, CD4724BMJ or CD4724BCJ Molded Dual-In-Line Package (N) Order Number CD4723BMN, CD4723BCN, CD4724BMN or CD4724BCN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.

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a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.