CD4504BMS INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 8

Technical content

Features

  • High Voltage Type (20V Rating)
  • Independence of Power Supply Sequence Consider- ations - VCC can Exceed VDD - Input Signals can Exceed Both VCC and VDD
  • Up and Down Level Shifting Capability
  • Shiftable Input Threshold for Either CMOS or TTL Compatibility
  • 100% Tested for Quiescent Current at 20V
  • 5V, 10V and 15V Parametric Ratings
  • Standardized Symmetrical Output Characteristics
  • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25 oC
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Description

CD4504BMS hex voltage level shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is at a LOW logic state, each circuit translates signals from one CMOS level to another. The CD4504BMS is supplied in these 16-lead outline packages: Frit Seal DIP H1F Ceramic Flatpack H6W December 1992 File Number 3336 Pinout CD4504BMS TOP VIEW Functional Diagram VCC AOUT AIN BOUT BIN COUT VSS CIN VDD FIN SELECT EOUT EIN DOUT DIN FOUT TTL/CMOS MODE SELECT LEVEL SHIFTER OUT * IN SELECT VCC = PIN 1 VDD = PIN 16 VSS = PIN 8 VDD VSS * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VCC VDD

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs.
  2. For accuracy, voltage is measured differentially to VDD. Limit

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25oC limit.

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 oC TABLE 6. APPLICABLE SUBGROUPS TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VCC, VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V
  2. Each pin except VCC, VDD and GND will have a series resistor of 47K± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,
  3. Oscillator output to be VDD/2.

TABLE 6. APPLICABLE SUBGROUPS (Continued)

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. FIGURE 7. HIGH LEVEL SUPPLY VOLTAGE vs LOW LEVEL SUPPLY VOLTAGE derived from the basic inch dimensions as indicated. METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.