CD4504BT INTERSIL | Alldatasheet
Document overview
- Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
- PDF pages: 3
Technical content
Features
- QML Class T, Per MIL-PRF-38535
- Radiation Performance - Gamma Dose (γ) 1 x 105 RAD(Si) - SEP Effective LET > 75 MEV/gm/cm2
- Independence of Power Supply Sequence Considerations -V CC Can Exceed VDD - Input Signals can Exceed Both VCC and VDD
- Up and Down Level Shifting Capability
- Shiftable Input Threshold for Either CMOS or TTL Compatibility
- 100% Tested for Quiescent Current at 20V
- 5V, 10V and 15V Parametric Ratings
- Standardized Symmetrical Output Characteristics Pinouts CD4504BT (SBDIP), CDIP2-T16 TOP VIEW CD4504BT (FLATPACK), CDFP4-16 TOP VIEW
Ordering Information
TEMP. RANGE (oC) 5962R9666501TEC CD4504BDTR -55 to 125 5962R9666501TXC CD4504BKTR -55 to 125 NOTE: Minimum order quantity for -T is 150 units through distribution, or 450 units direct. VCC AOUT A IN B OUT B IN C OUT VSS C IN VDD FIN SELECT EOUT EIN D OUT D IN FOUT VCC AOUT A IN B OUT B IN C OUT C IN VSS 11 6 VDD FOUT FIN SELECT EOUT EIN D OUT D IN Data Sheet July 1999 File Number 4623.1
† IN SELECT VCC = PIN 1 VDD = PIN 16 VSS = PIN 8 VDD VSS † ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VCC VDD CD4504BT
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 Die Characteristics DIE DIMENSIONS: (2540µm x 1753µm x 533µm ±25.4µm) 100 x 69 x 21mils±1mil METALLIZATION: Type: Al Thickness: 12.5kÅ ±1.5kÅ SUBSTRATE POTENTIAL: Leave Floating or Tie to VDD Bond Pad #16 (VDD ) First BACKSIDE FINISH: Silicon PASSIVATION: Type: Phosphorus Doped Silox (SiO 2) Thickness: 13.0kÅ ±2.6kÅ WORST CASE CURRENT DENSITY: < 2.0e5 A/cm2 TRANSISTOR COUNT: PROCESS: Bulk CMOS Metallization Mask Layout CD4504BT 69mils 100mils CD4504BT