CD4503BMS RENESAS | Alldatasheet

Document overview

  • Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 8

Technical content

Features

  • High Voltage Type (20V Rating)
  • 3 State Non-Inverting Type
  • 1 TTL Load Output Drive Capability
  • 2 Output Disable Controls
  • 3 State Outputs
  • Pin Compatible with Industry Types MM80C97, MC14503, and 340097
  • 5V, 10V and 15V Parametric Ratings
  • Maximum Input Current of 1 A at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25 oC
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

  • 3 State Hex Buffer for Interfacing ICs with Data Buses
  • COS/MOS to TTL Hex Buffer Pinout CD4503BMS TOP VIEW Functional Diagram Braze Seal DIP H4T Frit Seal DIP H1E Ceramic Flatpack H6W DIS A VSS VDD DQ6 DIS B Q13 VDD = 16 VSS = 8 DISABLE A D1 2 Q25D2 4 Q37D3 6 Q49D4 10 Q511D5 12 Q613D6 14 15DISABLE B

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs.
  2. For accuracy, voltage is measured differentially to VDD. Limit is

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. -55 oC and +125oC limits guaranteed, 100% testing being implemented.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial

design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25 oC limit.

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 6. APPLICABLE SUBGROUPS NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
  2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

FN3335 Rev 0.00 Page 8 of 8 December 1992 CD4503BMS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 1999. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Chip Dimensions and Pad Layout Dimensions in parenthesis are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10-3 inch). METALLIZATION: Thickness: 11kÅ 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches