CD4502BMS INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 8

Technical content

Features

  • High Voltage Type (20V Rating)
  • 2 TTL Load Output Drive Capability
  • 3 State Outputs
  • Common Output Disable Control
  • Inhibit Control
  • 100% Tested for Quiescent Current at 20V
  • 5V, 10V and 15V Parametric Ratings
  • Maximum Input Current of 1µA at 18V Over Full Pack- age Temperature Range; 100nA at 18V and +25 oC
  • Noise Margin (Over Full Package/Temperature Range) - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
  • Meets All Requirements of JEDEC Tentative Standard No. 13B, “Standard Specifications for Description of ‘B’ Series CMOS Devices”

Applications

  • 3 State Hex Inverter for Interfacing ICs with Data Buses
  • COS/MOS to TTL Hex Buffer

Description

CD4502BMS consists of six inverter/buffers with 3 state outputs. A logic “1” on the OUTPUT DISABLE input produces a high impedance state in all six outputs. This feature permits common busing of the outputs, thus simplifying system design. A Logic “1” on the INHIBIT input switches all six outputs to logic “0” if the OUTPUT DISABLE input is a logic “0”. This device is capable of driving two standard TTL loads, which is equivalent to six times the JEDEC “B” series IOL standard. The CD4502BMS is supplied in these 16-lead outline packages: Braze Seal DIP H4T Frit Seal DIP H1F Ceramic Flatpack H6W December 1992 File Number 3334 Pinout CD4502BMS TOP VIEW Functional Diagram

3 STATE

43 STATE

VDD = 16 VSS = 8 OUTPUT DISABLE INHIBIT 12 Q32 D3 1 Q49 D4 10 Q511 D5 13 Q614 D6 15

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs.
  2. For accuracy, voltage is measured differentially to VDD. Limit

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25oC limit.

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 oC TABLE 6. APPLICABLE SUBGROUPS NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION

FIGURE 2. DISABLE DELAY TIMES TEST CIRCUIT AND WAVEFORMS TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V
  2. Each pin except VDD and GND will have a series resistor of 47K± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures,

FIGURE 1. LOGIC DIAGRAM OF 1 OF 6 IDENTICAL INVERTER/BUFFERS

01 X 0