CD4000BMS INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • High-Voltage Types (20V Rating)
  • Propagation Delay Time = 60ns (typ.) at CL = 50pF, VDD = 10V
  • Buffered Inputs and Outputs
  • Standard Symmetrical Output Characteristics
  • 100% Tested for Maximum Quiescent Current at 20V
  • 5V, 10V and 15V Parametric Ratings
  • Maximum Input Current of 1µA at 18V Over Full Pack- age-Temperature Range; 100nA at 18V and +25 oC
  • Noise Margin (Over Full Package Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
  • Meets All Requirements of JEDEC Tentative Stan- dards No. 13B, “Standard Specifications for Descrip- tion of “B” Series CMOS Device’s

Description

CD4000BMS, CD4001BMS, CD4002BMS, and CD4025BMS NOR gates provide the system designer with direct implementation of the NOR function and supplement the existing family of CMOS gates. All inputs and outputs are buffered. The CD4000BMS, CD4001BMS, CD4002BMS and the CD4025BMS is supplied in these 14 lead outline packages: CD4000BMS - Dual 3 Plus Inverter CD4001BMS - Quad 2 Input CD4002BMS - Dual 4 Input CD4025BMS - Triple 3 Input CD4000B CD4001B CD4002B CD4025B Braze Seal DIP H4X H4Q H4Q H4Q Frit Seal DIP H1B H1B H1B H1B Ceramic Flatpack H3W H3W H3W H3W File Number 3289 November 1994

CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Functional Diagrams CD4000BMS CD4001BMS CD4002BMS CD4025BMS NC NC A B C H VSS VDD F E D K L G K = D + E + F H = A + B + C L =G A B J K C D VSS VDD H G M L F E J =A + B M = G + H K = C + D L =E + F J A B C D NC VSS VDD K H G F E NC 8K = E + F + G + H J =A + B + C + D A B D E F K VSS VDD G H I L J C L =G + H + I K = D + E + F J =A + B + C

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs
  2. For accuracy, voltage is measured differentially to VDD. Limit

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized

on initial design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25oC limit.

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25 O C TABLE 6. APPLICABLE SUBGROUPS NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. TABLE 7. TOTAL DOSE IRRADIATION TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VDD and GND will have a series resistor of 10K± 5%, VDD = 18V± 0.5V
  2. Each pin except VDD and GND will have a series resistor of 47K± 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD

Specifications CD4000BMS, CD4001BMS, CD4002BMS, CD4025BMS Schematic and Logic Diagrams CD4000BMS CD4001BMS CD4002BMS CD4025BMS 5(12) 4(13) (10) LOGIC DIAGRAM (12) (11) (13) p n p p p p nn n n n pn p 6(10) VDD14 VSS7 INVERTER AND 1 OF 2 GATES (NUMBERS IN PARENTHESES ARE p n p n p n TERMINAL NUMBERS FOR SECOND GATE) 3(11) p n p n pp p nn n (8, 6, 13) (9, 5, 12) VDD14 VSS7 (10, 4, 11) 1(8, 6,13) 2(9, 5, 12) (10, 4, 11) LOGIC DIAGRAM

1 OF 4 GATES (NUMBERS IN PARANTHESES

ARE TERMINAL NUMBERS FOR OTHER GATES) VDD VSS *ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK 2(12) 4(10) (13) 5(9) 3(11) (12) (11) (10) (9) p n p pp p p nn n n n n pn pn p (13) V DD14 VSS7 LOGIC DIAGRAM

1 OF 2 GATES (NUMBERS IN

NUMBERS FOR SECOND GATE) 3(1, 11) 5(8, 13) (9, 10) LOGIC DIAGRAM (1, 11) (2, 12) (8, 13) p n p p p p nn n n n pn p (9, 10) VDD14 VSS71 OF 3 GATES (NUMBERS IN PARENTHESES ARE TERMINAL NUMBERS FOR OTHER GATES) 4(2, 12)