CD3086 INTERSIL | Alldatasheet

Document overview

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Technical content

Applications

  • Three Isolated Transistors and One Differentially Connected Transistor Pair For Low-Power Applications from DC to 120MHz
  • General-Purpose Use in Signal Processing Systems Operating in the DC to 190MHz Range
  • Temperature Compensated Amplifiers
  • See Application Note, AN5296 “Application of the CA3018 Integrated-Circuit Transistor Array” for Suggested Applications

Description

The CA3086 consists of five general-purpose silicon NPN transistors on a common monolithic substrate. Two of the transistors are internally connected to form a differentially connected pair. The transistors of the CA3086 are well suited to a wide vari- ety of applications in low-power systems at frequencies from DC to 120MHz. They may be used as discrete transistors in conventional circuits. However, they also provide the very significant inherent advantages unique to integrated circuits, such as compactness, ease of physical handling and ther- mal matching Pinout CA3086 (PDIP, CERDIP, SOIC) TOP VIEW

Ordering Information

(BRAND) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA3086 -55 to 125 14 Ld PDIP E14.3 CA3086M (3086) -55 to 125 14 Ld SOIC M14.15 CA3086M96 (3086) -55 to 125 14 Ld SOIC Tape and Reel M14.15 CA3086F -55 to 125 14 Ld CERDIP F14.3 SUBSTRATE Q 1 Q 2 Q 5 Q 4 Q 3 File Number 483.3CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information The following ratings apply for each transistor in the device: Operating Conditions Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. The collector of each transistor in the CA3086 is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. To avoid undesirable coupling between transistors, the substrate (Terminal 13) should be maintained at either DC or signal (AC) ground. A suitable bypass capacitor can be used to establish a signal ground. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = 25oC, For Equipment Design PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Collector-to-Base Breakdown Voltage V (BR)CBO lC = 10µA, IE = 0 20 60 - V Collector-to-Emitter Breakdown Voltage V (BR)CEO IC = 1mA, IB = 0 15 24 - V Collector-to-Substrate Breakdown Voltage V (BR)ClO IC = 10µA, ICI = 0 20 60 - V Emitter-to-Base Breakdown Voltage V (BR)EBO IE = 10µA, IC = 0 5 7 - V Collector-Cutoff Current (Figure 1) I CBO VCB = 10V, IE = 0, - 0.002 100 nA Collector-Cutoff Current (Figure 2) I CEO VCE = 10V, IB = 0, - (Figure 2) 5 µA DC Forward-Current Transfer Ratio (Figure 3) hFE VCE = 3V, IC = 1mA 40 100 - Electrical SpecificationsTA = 25oC, Typical Values Intended Only for Design Guidance PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS DC Forward-Current Transfer Ratio (Figure 3) hFE VCE = 3V I C = 10mA 100 IC = 10µA5 4 Base-to-Emitter Voltage (Figure 4) V BE VCE = 3V I E = 1 mA 0.715 V IE = 10mA 0.800 V VBE Temperature Coefficient (Figure 5)∆VBE /∆TV CE = 3V, lC = 1 mA -1.9 mV/ oC Collector-to-Emitter Saturation Voltage VCE SAT IB = 1mA, IC = 10mA 0.23 V Noise Figure (Low Frequency) NF f = 1kHz, VCE = 3V, IC = 100µA, RS = 1kΩ 3.25 dB CA3086

FIGURE 1. ICBO vs TEMPERATURE FIGURE 2. I CEO vs TEMPERATURE

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FIGURE 9. yOE vs FREQUENCY FIGURE 10. y RE vs FREQUENCY FIGURE 11. fT vs IC