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Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 10

Technical content

Features

  • 128 Analog Switches
  • L o w rON
  • Guaranteed rON Matching
  • Analog Signal Input Voltage Equal to the Supply Voltage
  • Parallel Input Addressing
  • Very Low Crosstalk
  • Pin and Functionally Compatible with the Following Types: SGS M3494 and Mitel MT8816
  • Pb-Free (RoHS Compliant)

Applications

  • PBX Systems
  • Instrumentation
  • Analog and Digital Multiplexers
  • Video Switching Networks Block Diagram AX0 AX1 AX2 AX3 AY0 AY1 AY2 128 STROBE DATA RESET 128 X0 - X15 Y0 - Y7 LEVEL SHIFTERS 128

7 TO 128

FN2793 Rev 8.00 Page 2 of 10 May 29, 2014

Ordering Information

(Note 3) PART MARKING TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. CD22M3494EZ CD22M3494EZ -40 to 85 40 Ld PDIP (Note 2) E40.6 CD22M3494MQZ (Note 1) CD22M3494MQZ -40 to 85 44 Ld PLCC (Mitel Ld Compatible) N44.65 CD22M3494MQAZ (Note 1) CD22M3494MQAZ -40 to 85 44 Ld PLCC (Mitel Ld Compatible) N44.65 CD22M3494SQZ (Note 1) CD22M3494SQZ -40 to 85 44 Ld PLCC (SGS Ld Compatible) N44.65 NOTES: 1. Add “96” suffix for tape and reel. At one time the "QZ" and "QAZ" were different products, but since 1994 these parts have been exactly the same. 2. Pb-free PDIPs can be used for through-hole wave solder processing only. They are not intended for use in Reflow solder processing applications. 3. Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Pinouts CD22M3494E (PDIP) TOP VIEW CD22M3494MQ (PLCC) (MITEL LEAD COMPATIBLE) TOP VIEW CD22M3494SQ (PLCC) (SGS LEAD COMPATIBLE) TOP VIEW DATA NC AX2 AY0 AX1 AY1 X13 X12 CS VDD STROBE X11 X10 X15 X14 AX0 NC AY2 RESET AX3 VSS VEE 4065 321 4 4 4 3 4 2 4 14 18 19 20 21 22 23 24 25 26 27 28 8 38 NC X13 X12 NC AX2 AY0 AX1 AY1 STROBE V SS V EE NC DATA CS V DD AX0 AY2 RESET AX3 NC X11 X10 X15 X14 NC NC 8 38 NC X13 X12 NC CS STROBE V EE AX1 AX2 AY0 AY1 NC AX0 NC AX3 RESET AY2 V DD DATA X11 X10 X15 X14 NC NC VSS

FN2793 Rev 8.00 Page 3 of 10 May 29, 2014 Pin Descriptions SYMBOL

40 LD PDIP

PIN NO.

44 LD PLCC

PIN NO. DESCRIPTIONMQ SQ POWER SUPPLIES VDD 40 44 44 Positive Supply. VSS 16 18 17 Negative Supply (Digital). VEE 20 22 22 Negative Supply (Analog). ADDRESS AX0 - AX3 5, 22, 23 and 4 5, 24, 25 and 4 X Address Lines. These pins select one of the 16 rows of switches. See the Truth Table on page 7 for the valid addresses. AY0 - AY2 24, 25 and 2 26, 27 and 2 Y Address Lines. These pins select one of the 8 columns of switches. See the Truth Table on page 7 for the valid addresses. CONTROL DATA 38 42 DATA Input determines the state of the addressed switch. A high or one will close the switch. A low or zero will open the switch. STROBE 18 20 STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or zero results in no action. The ADDRESS Input must be stable before the STROBE Input goes to the active high level. The DATA Input must be stable on the failing edge of the STROBE. RESET 3 3 MASTER RESET. A high or one on this line opens all switches. CS 36 40 39 CHIP SELECT. Device is selected when CS is at a high level, allows the crosspoint array to be cascaded for matrix expansion. INPUTS/OUTPUTS X0 - X5 X6 - X11 X12 - X15 33-28, 8-13, 27, 26, 6, 7 37-32, 9-14, 31, 30, 7, 8 Analog or Digital Inputs/Outputs. These pins are the rows X0 - X15. Y0 - Y7 I/O 35, 37, 39, 1, 21, 19, 17, 15 39, 41, 43, 1, 23, 21, 19, 17 40, 41, 43, 1, 23, 21, 19, 18 Analog or Digital Inputs/Outputs. These pins are the columns Y0 - Y7.

FN2793 Rev 8.00 Page 4 of 10 May 29, 2014 Absolute Maximum Ratings Thermal Information DC Supply Voltage (VDD) DC Supply Voltage (VDD) DC Input Diode Current, IIN For VI, Digital < VSS -0.5V or VI,  DC Output Diode Current, IOK For VO, Digital < VSS -0.5V or VO,  Power Dissipation Per Package (Po) Thermal Resistance (Typical, Note 4) JA (°C/W) Maximum Storage Temperature Range (TSTG). . . .-65°C to +150°C *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing. applications. Operating Conditions Operating Temperature Range (TA) Supply Voltage Range For TA = Full Package Temperature Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 4. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications TA = -40°C to +85°C, VDD = 5V, VSS = 0V, VEE = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC CONTROLS Supply Current IDD VDD = 5V, Logic Inputs = VDD - - 2 mA VDD = 15V, Logic Inputs = VDD - - 5 mA High-Level Input Voltage VIH VDD = 5V 2.4 (Note 5) - - V Low-Level Input Voltage VIL - - 0.8 (Note 5) V Input Leakage Current, Digital IIN Reset = Low (Note 6) - - ±10 (Note 7) µA Electrical Specifications TA = -40°C to +85°C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC CROSSPOINTS ON Resistance rON VSS = VEE = 0V, TA = +25°C, VIN = VDD/2, VX - VY = 0.2V VDD = 10V - 40 75  VDD = 12V - 36 65  ON Resistance rON TA = -40°C to +85°C, VIN = VDD/2, VX -VY = 0.2V, VSS = VEE = 0V VDD = 10V - 50 75  VDD = 12V - 45 65  Difference in ON Resistance  Between Any Two Switches rON TA = +25°C, VIN = VDD/2, VX - VY = 0.2V,  VSS = VEE = 0V, VDD = 12V - 6 10 

FN2793 Rev 8.00 Page 5 of 10 May 29, 2014 Difference in ON Resistance  Between Any Two Switches rON TA = -40°C to +85°C, VIN = VDD/2, VX - VY = 0.2V, VDD = 12V VSS = VEE = 0V, VDD = 12V - - 10  OFF-State Leakage Current IL |VX - VY| = 12V - - ±10 (Note 7) µA Electrical Specifications TA = -40°C to +85°C, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Electrical Specifications TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, CL = 50pF, Unless Otherwise Specified. PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DYNAMIC CROSSPOINTS Switch I/O Capacitance VIN = VDD/2, f = 1MHz - - 20 pF Switch Feedthrough Capacitance VIN = VDD/2, f = 1MHz - 0.3 - pF Propagation Delay Time (Switch ON) Signal Input to Output, tPHL or tPLH - 5 30 ns Frequency Response Channel ON f = 20log (VX/VY) = -3dB CL = 3pF, RL = 75, VIN = 2VP-P - 50 - MHz Total Harmonic, THD VIN = 2VP-P, f = 1kHz - 0.01 - % Feedthrough Channel OFF Feedthrough = 20log (VX/VY) = FDT VIN = 2VP-P, f = 1kHz - -95 - dB Frequency for Signal Crosstalk, fCT Attenuation of: 40dB VIN = 2VP-P, RL = 75 - 10 - MHz 110dB VIN = 2VP-P, RL = 1k || 10pF - 5 - kHz Control Crosstalk  DATA-Input, ADDRESS, or STROBE to Output Control Input = 3VP-P Square Wave, tR = tF = 10ns RIN = 1K, ROUT = 10k || 10pF - 75 - mVPEAK Electrical Specifications TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DYNAMIC CONTROLS Digital Input Capacitance CIN VIN = 5V, f = 1MHz - 5 - pF Propagation Delay Time  STROBE to Output Switch Turn-ON tPSN - 50 100 ns Switch Turn-OFF tPSF - 50 100 ns DATA-IN to Output Turn-ON to High Level tPZH - 60 100 ns Turn-ON to Low Level tPZL - 70 100 ns ADDRESS to Output Turn-ON to High Level tPAN - 70 - ns Turn-OFF to Low Level tPAF - 70 - ns

FN2793 Rev 8.00 Page 6 of 10 May 29, 2014 Setup Time CS to STROBE tCS 10 - - ns DATA-IN to STROBE tDS 10 - - ns ADDRESS to STROBE tAS 10 - - ns Hold Time STROBE to CS tCH 10 - - ns ADDRESS to CS 10 - - ns STROBE to DATA-IN tDH 20 - - ns STROBE to ADDRESS tAH 10 - - ns DATA-IN to CS 20 - - ns Pulse Width STROBE tSPW 20 - - ns RESET tRPW 20 - - ns RESET Turn-OFF to Output Delay tPHZ - 70 100 ns NOTES: 5. Operation of VIH at 2.4V or VIL at 0.8V will result in much higher supply current (IDD) than for logic inputs equal to VDD or VSS respectively. 6. Reset IIH < 20µA, Reset = VIH. 7. At +25°C Limit is 100nA. Electrical Specifications TA = +25°C, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1k || 50pF, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

FN2793 Rev 8.00 Page 7 of 10 May 29, 2014 Timing Diagram ADDRESS STROBE DATA RESET 50% 50% tSPWtAS tAH 50% tDHtDS 50% 50% tRPW 50% 50% 90% tPAF tPZL SWITCH OUTPUT 90% 10% tPAN tPHZ tPZH tPSF tPSN 50% 50% tCS tCH CS 10% TRUTH TABLE X AXIS X ADDRESS AX3 AX2 AX1 AX0 X SWITCH 0 0 0 0 X0 0 0 0 1 X1 0 0 1 0 X2 0 0 1 1 X3 0 1 0 0 X4 0 1 0 1 X5 0 1 1 0 X12 0 1 1 1 X13 1 0 0 0 X6 1 0 0 1 X7 1 0 1 0 X8 1 0 1 1 X9 1 1 0 0 X10 1 1 0 1 X11 1 1 1 0 X14 1 1 1 1 X15 TRUTH TABLE Y AXIS Y ADDRESS AY2 AY1 AY0 Y SWITCH 0 0 0 Y0 0 0 1 Y1 0 1 0 Y2 0 1 1 Y3 1 0 0 Y4 1 0 1 Y5 1 1 0 Y6 1 1 1 Y7

FN2793 Rev 8.00 Page 8 of 10 May 29, 2014 CD22M3494 Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2000-2014. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. To make a connection (close switch) between any two points, spe cify an “X” address, a “Y” address, set “DATA” high, and switch “STROBE” from low to high. To break a connection, follow this same procedure with “DATA” low. Typical Performance Curve Example: DATA X ADDRESS Y ADDRESS AX3 AX2 AX1 AX0 AY2 AY1 AY0 To connect switch X3 to switch Y4: 1 0 0 1 1 1 0 0 To connect switch X6 to switch Y7: 1 1 0 0 0 1 1 1 To break connection from X3 to Y4: 0 0 0 1 1 1 0 0 ON RESISTANCE () -8 -6 -4 -2 0 2 4 6 8 VIN (V) +25°C -40°C +85°C rON vs VIN AT -55°C, +25°C AND +85°C VEE = -6V, VSS = 0V, VDD = 6V

FN2793 Rev 8.00 Page 9 of 10 May 29, 2014 Plastic Leaded Chip Carrier Packages (PLCC) NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane contact point. 5. Centerline to be determined where center leads exit plastic body. 6. “N” is the number of terminal positions. -C- A SEATING PLANE 0.020 (0.51) MIN VIEW “A” D2/E2 0.025 (0.64) 0.045 (1.14) R 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP EE1 0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER CL D 0.020 (0.51) MAX 3 PLCS 0.026 (0.66) 0.032 (0.81) 0.045 (1.14) MIN 0.013 (0.33) 0.021 (0.53) 0.025 (0.64) MIN VIEW “A” TYP. 0.004 (0.10) C -C- D2/E2 CL N44.65 (JEDEC MS-018AC ISSUE A)

44 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE

A 0.165 0.180 4.20 4.57 - A1 0.090 0.120 2.29 3.04 - D 0.685 0.695 17.40 17.65 - D1 0.650 0.656 16.51 16.66 3 D2 0.291 0.319 7.40 8.10 4, 5 E 0.685 0.695 17.40 17.65 - E1 0.650 0.656 16.51 16.66 3 E2 0.291 0.319 7.40 8.10 4, 5 N4 4 4 4 6 Rev. 2 11/97

FN2793 Rev 8.00 Page 10 of 10 May 29, 2014 Dual-In-Line Plastic Packages (PDIP) NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dam- bar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. eA -C- CL E eA C eB eC -B- INDEX 12 3 N / 2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L -A- 0.010 (0.25) C AM BS E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.250 - 6.35 4 A1 0.015 - 0.39 - 4 A2 0.125 0.195 3.18 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.030 0.070 0.77 1.77 8 C 0.008 0.015 0.204 0.381 - D 1.980 2.095 50.3 53.2 5 D1 0.005 - 0.13 - 5 E 0.600 0.625 15.24 15.87 6 E1 0.485 0.580 12.32 14.73 5 e 0.100 BSC 2.54 BSC - e A 0.600 BSC 15.24 BSC 6 eB - 0.700 - 17.78 7 L 0.115 0.200 2.93 5.08 4 N4 0 4 0 9 Rev. 0 12/93