CD22M3494 INTERSIL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
  • PDF pages: 7

Technical content

Features

  • 128 Analog Switches
  • L o w RON
  • Guaranteed RON Matching
  • Analog Signal Input Voltage Equal to the Supply Voltage
  • Parallel Input Addressing
  • Very Low Crosstalk
  • Pin and Functionally Compatible with the Following Types: SGS M3494 and Mitel MT8816

Applications

  • PBX Systems
  • Instrumentation
  • Analog and Digital Multiplexers
  • Video Switching Networks Block Diagram

Ordering Information

TEMP. RANGE ( oC) PACKAGE PKG. NO. CD22M3494E -40 to 85 40 Ld PDIP E40.6 CD22M3494MQ -40 to 85 44 Ld PLCC (Mitel Ld Compatible) N44.65 CD22M3494SQ -40 to 85 44 Ld PLCC (SGS Ld Compatible) N44.65 AX0 AX1 AX2 AX3 AY0 AY1 AY2 128 STROBE DATA RESET 128 X0 - X15 Y0 - Y7 LEVEL SHIFTERS 128

7 TO 128

Data Sheet January 1997 File Number 2793.5

Absolute Maximum Ratings Thermal Information DC Supply Voltage (VDD ) DC Supply Voltage (VDD ) DC Input Diode Current, IIN For VI, Digital < VSS -0.5V or VI, DC Output Diode Current, IOK For VO , Digital < VSS -0.5V or VO , Power Dissipation Per Package (Po) Thermal Resistance (Typical, Note 1) θJA (oC/W) Maximum Storage Temperature Range (TSTG ) . . . . -65oC to 150oC (PLCC - Lead Tips Only) Operating Conditions Operating Temperature Range (TA) Supply Voltage Range For TA = Full Package Temperature Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTA = -40oC to 85oC, VDD = 5V, VSS = 0V, VEE = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC CONTROLS Supply Current I DD VDD = 5V, Logic Inputs = VDD --2 m A VDD = 15V, Logic Inputs = VDD --5 m A High-Level Input Voltage V IH VDD = 5V 2.4 (Note 2) -- V Low-Level Input Voltage V IL - - 0.8 (Note 2) V Input Leakage Current, Digital I IN Reset = Low (Note 3) - - ±10 (Note 4) µA Electrical SpecificationsTA = -40oC to 85oC, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC CROSSPOINTS ON Resistance R ON VSS = VEE = 0V, TA =2 5oC, VIN=V DD /2, VX - VY = 0.2V VDD = 10V - 40 75 Ω VDD = 12V - 36 65 Ω ON Resistance R ON TA = -40oC to 85oC, VIN = VDD /2, VX -VY = 0.2V, VSS = VEE = 0V VDD = 10V - 50 75 Ω VDD = 12V - 45 65 Ω Difference in ON Resistance Between Any Two Switches ΔR ON TA = 25oC, VIN = VDD /2, VX - VY = 0.2V, VSS = VEE = 0V, VDD = 12V -6 1 0 Ω CD22M3494

Difference in ON Resistance Between Any Two Switches ΔR ON TA = -40oC to 85oC, VIN = VDD /2, VX - VY = 0.2V, VDD = 12V VSS = VEE = 0V, VDD = 12V -- 1 0 Ω OFF-State Leakage Current I L |VX - VY| = 12V - - ±10 (Note 4) µA Electrical SpecificationsTA = 25oC, VSS = 0V, VEE = 0V, VDD = 14V, CL = 50pF , Unless Otherwise Specified PARAMETER TEST CONDITIONS MIN TYP MAX UNITS DYNAMIC CROSSPOINTS Switch I/O Capacitance V IN = VDD /2, f = 1MHz - - 20 pF Switch Feedthrough Capacitance V IN = VDD /2, f = 1MHz - 0.3 - pF Propagation Delay Time (Switch ON) Signal Input to Output, tPHL or tPLH - 5 30 ns Frequency Response Channel ON f = 20log (VX/VY) = -3dB C L = 3pF, RL = 75Ω , VIN = 2VP-P -5 0- M H z Total Harmonic, THD V IN = 2VP-P, f = 1kHz - 0.01 - % Feedthrough Channel OFF Feedthrough = 20log (VX/VY) = FDT VIN = 2VP-P, f = 1kHz - -95 - dB Frequency for Signal Crosstalk, fCT Attenuation of: 40dB V IN = 2VP-P, RL = 75Ω -1 0- M H z 110dB V IN = 2VP-P, RL = 1kΩ || 10pF - 5 - kHz Control Crosstalk DATA-Input, ADDRESS, or STROBE to Output Control Input = 3V P-P Square Wave, tR = tF = 10ns R IN = 1K, ROUT = 10kΩ || 10pF -7 5- m V PEAK Electrical SpecificationsTA = 25oC, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1kΩ || 50pF , Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DYNAMIC CONTROLS Digital Input Capacitance C IN VIN = 5V, f = 1MHz - 5 - pF Propagation Delay Time STROBE to Output Switch Turn-ON t PSN - 50 100 ns Switch Turn-OFF t PSF - 50 100 ns DATA-IN to Output Turn-ON to High Level t PZH - 60 100 ns Turn-ON to Low Level t PZL - 70 100 ns ADDRESS to Output Turn-ON to High Level t PAN -7 0-n s Turn-OFF to Low Level t PAF -7 0-n s Electrical SpecificationsTA = -40oC to 85oC, VDD = 12V, VSS = 0V, VEE = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS CD22M3494

CS to STROBE t CS 10 - - ns DATA-IN to STROBE t DS 10 - - ns ADDRESS to STROBE t AS 10 - - ns Hold Time STROBE to CS t CH 10 - - ns ADDRESS to CS 10 - - ns STROBE to DATA-IN t DH 20 - - ns STROBE to ADDRESS t AH 10 - - ns DATA-IN to CS 20 - - ns Pulse Width STROBE t SPW 20 - - ns RESET t RPW 20 - - ns RESET Turn-OFF to Output Delay t PHZ - 70 100 ns NOTES: 2. Operation of VIH at 2.4V or VIL at 0.8V will result in much higher supply current (IDD ) than for logic inputs equal to VDD or VSS respectively. 3. Reset IIH < 20µA, Reset = VIH. 4. At 25oC Limit is±100nA. Electrical SpecificationsTA = 25oC, VSS = 0V, VEE = 0V, VDD = 14V, RL = 1kΩ || 50pF , Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS ADDRESS STROBE DATA RESET 50% 50% tSPWtAS tAH 50% tDHtDS 50% 50% tRPW 50% 50% 90% tPAF tPZL SWITCH OUTPUT 90% 10% tPAN tPHZ tPZH tPSF tPSN 50% 50% tCS tCH CS 10% CD22M3494

To make a connection (close switch) between any two points, specify an “X” address, a “Y” address, set “DATA” high, and switch “STROBE” from low to high. To break a connection, follow this same procedure with “DATA” low. Typical Performance Curve TRUTH TABLE X AXIS X ADDRESS AX3 AX2 AX1 AX0 X SWITCH

0000 X 0

0001 X 1

0010 X 2

0011 X 3

0100 X 4

0101 X 5

0110 X 1 2

0111 X 1 3

1000 X 6

1001 X 7

1010 X 8

1011 X 9

1100 X 1 0

1101 X 1 1

1110 X 1 4

1111 X 1 5

000 Y 0

001 Y 1

010 Y 2

011 Y 3

100 Y 4

101 Y 5

110 Y 6

111 Y 7

Example: DATA X ADDRESS Y ADDRESS AX3 AX2 AX1 AX0 AY2 AY1 AY0 To connect switch X3 to switch Y4: 1 0011100 To connect switch X6 to switch Y7: 1 1000111 To break connection from X3 to Y4: 0 0011100 ON RESISTANCE ( Ω ) -8 -6 -4 -2 0 2 4 6 8 VIN (V) 25oC -40oC 85oC R ON VS VIN AT -55oC, 25oC AND 85oC VEE = -6v, VSS = 0V, VDD = 6V CD22M3494

40 LEAD PDIP

PIN NO.

44 LEAD PLCC

PIN NO. DESCRIPTIONMQ SQ POWER SUPPLIES VDD 40 44 44 Positive Supply VSS 16 18 17 Negative Supply (Digital) VEE 20 22 22 Negative Supply (Analog) ADDRESS AX0 - AX3 5, 22, 23 and 4 5, 24, 25 and 4 X Address Lines. These pins select one of the 16 rows of switches. See the Truth Table for the valid addresses. AY0 - AY2 24, 25 and 2 26, 27 and 2 Y Address Lines. These pins select one of the 8 columns of switches. See the Truth Table for the valid addresses. CONTROL DATA 38 42 DATA Input determines the state of the addressed switch. A high or one will close the switch. A low or zero will open the switch. STROBE 18 20 STROBE Input enables the action defined by the DATA and ADDRESS Inputs. A low or zero results in no action. The ADDRESS Input must be stable before the STROBE Input goes to the active high level. The DATA Input must be stable on the failing edge of the STROBE. RESET 3 3 MASTER RESET. A high or one on this line opens all switches. CS 36 40 39 CHIP SELECT. Device is selected when CS is at a high level, allows the crosspoint array to be cascaded for matrix expansion. INPUTS/OUTPUTS X0 - X5 X6 - X11 X12 - X15 33 - 28, 8 - 13, 27, 26, 6, 7 37 - 32 9 - 14, 31, 30, 7, 8 Analog or Digital Inputs/Outputs. These pins are the rows X0 - X15. Y0 - Y7 I/O 35, 37, 39, 1, 21, 19, 17 and 15 40, 41, 43, 1, 23, 21, 19 and 18 Analog or Digital Inputs/Outputs. These pins are the columns Y0 - Y7. Pinouts CD22M3494E (PDIP) TOP VIEW CD22M3494MQ (PLCC) (MITEL LEAD COMPATIBLE) TOP VIEW CD22M3494SQ (PLCC) (SGS LEAD COMPATIBLE) TOP VIEW DATA NC AX2 AY0 AX1 AY1 X13 X12 CS VDD STROBE X11 X10 X15 X14 AX0 NC AY2 RESET AX3 VSS VEE 4065 321 4 4 4 3 4 2 4 14 18 19 20 21 22 23 24 25 26 27 28 8 38 NC X13 X12 NC AX2 AY0 AX1 AY1 STROBE V SS V EE NC DATA CS V DD AX0 AY2 RESET AX3 NC X11 X10 X15 X14 NC NC 8 38 NC X13 X12 NC CS STROBE V EE AX1 AX2 AY0 AY1 NC AX0 NC AX3 RESET AY2 V DD DATA X11 X10 X15 X14 NC NC V SS CD22M3494

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD22M3494