CD22301 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Automatic Line Buildout
  • Buffered Output

Applications

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. CD22301E -40 to 85 18 Ld PDIP E18.3 January 1997 Functional Diagram ALBO OUTPUT CIRCUIT 171 VCC FROM ALBO PEAK DETECTOR VEE 100Ω ALBO BIAS AO1 50K 18K 15K AO2 AO3 ALBO GND 100Ω 100Ω 100Ω100Ω 100Ω Pinout CD22301 (PDIP) TOP VIEW 1ALBO GROUND ALBO 1 OUTPUT ALBO 2 OUTPUT ALBO 3 OUTPUT PREAMP INPUT + PREAMP INPUT - PREAMP OUTPUT + PREAMP OUTPUT - SUBSTRATE ALBO BIAS OSC BIAS LC TANK INPUT CLOCK LIMITER OUTPUT TIMING PULSE INPUT OUTPUT PULSE 1 OUTPUT PULSE 2VEE VCC CD22301 Monolithic PCM Repeater File Number 1368.3CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207| Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information Power Dissipation For T For TA = 60oC to 85oC . . . . Derate Linearly 12mW/oC to 200mW Device Dissipation per Output Transistor Operating Conditions CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsTA = 25oC, VCC = 5.1V±5% (See Figure 4) PARAMETER MIN TYP MAX UNITS STATIC DC VOLTAGES ALBO Pins (Pins 2, 3, 4 and 17) - 0 0.1 V Pre Amp Inputs and Outputs (Pins 5, 6, 7 and 8) 2.4 2.9 3.4 V Output Pulse 1, 2 (Pins 10 and 11) - 5.1 - V Oscillator/Clock (Pins 12, 13, 15 and 16) 3.1 3.6 4.1 V STATIC DC CURRENTS I CC -2 2 3 0 m A Output Pulse 1, 2 (Pins 10 and 11) - 0 100 µA Electrical SpecificationsTA = 25oC, VCC = 5.1V±5% PARAMETER SYMBOL FIGURE NOTE MIN TYP MAX UNITS DYNAMIC SPECIFICATIONS Preamplifier Input Impedance Z IN 72 0 - - k Ω Preamplifier Output Impedance Z OUT 7- - 2 k Ω Preamplifier Gain at 2.37MHz A O 74 7 5 0 - d B Preamplifier Output Offset VoltageΔVOUT 7 1 -50 0 50 mV Clock Limiter Input Impedance Z IN(CL) 5 2 10 - - k Ω ALBO Off Impedance Z ALBO (off) 5 3 20 - - k Ω ALBO On Impedance Z ALBO (on) 5 4 - - 10 Ω DATA Threshold Voltage V TH (D) 6 5, 8 0.62 0.7 0.78 V CLOCK Threshold Voltage V TH (CL) 6 6, 8 0.92 1.1 1.28 V ALBO Threshold V TH (AL) 6 7, 8 1.4 1.5 1.6 V VTH (D) as % of VTH (AL) 44 47 49 % VTH (CL) as % of VTH (AL) 66 73 80 % Buffer Gate Voltage (low) V OL 4 9 0.65 0.8 0.95 V Differential Buffer Gate Voltage ΔVOL 4 9 -0.15 0 0.15 V Output Pulse Rise Time t R 4, 8 9, 10 - - 40 ns

  1. No signal input. Measure voltage between pins 7 and 8.
  2. Measure clock limiter input impedance at pin 15. See Figure 5.
  3. Adjust potentiometer for 0V (See Figure 5). Measure ALBO off impedances from pins 2, 3 and 4 to pin 1.
  4. Increase potentiometer until voltage at pin 17 = 2V (See Figure 5). Measure ALBO on impedances from pins 2, 3 and 4 to pin 1.
  5. Adjust potentiometer forΔV = 0V (See Figure 6). Then slowly increaseΔV in the positive direction until pulses are observed at the DATA
  6. Continue increasingΔV until the DC level at the clock terminal drops to 4V (See Figure 6).
  7. Continue increasingΔV until the ALBO terminal rises to 1V (See Figure 6).
  8. Turn potentiometer in the opposite direction and measure negative threshold voltages by repeating tests outlined in notes 5, 6 and 7.
  9. Adjust input signal amplitude until pulses just appear in outputs. Increase input amplitude by 3dB.

FIGURE 1. TYPICAL 1.544MHz T1 REPEATER SYSTEM

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD22301