CD22103A INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • HDB3 Coding and Decoding for Data Rates from 50Kb/s to 10Mb/s in a Manner Consistent with CCITT G703 Recommendations
  • HDB3/AMI Transmission Coding/Reception Decoding with Code Error Detection is Performed in Independent Coder and Decoder Sections
  • All Transmitter and Receiver Inputs/Outputs are TTL Compatible
  • Internal Loop Test Capability
  • Pin and Functionally Compatible with Type MJ1471 Pinout CD22103A (PDIP, SBDIP) TOP VIEW TRANSMITTER CODER RECEIVER DECODER AIS DETECT ERROR DETECT NRZ-IN CTX HDB3/AMI NRZ-OUT CRX AIS RAIS LTE CKR ERR +HDB3 OUT -HDB3 OUT +HDB3 IN -HDB3 IN ENCODER IN DECODER REQUIRES CLOCK RECOVERY CIRCUIT

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. CD22103AD -55 to 125 16 Ld SBDIP D16.3 CD22103AE -40 to 85 16 Ld PDIP E16.3 NRZ-IN CTX HDB3/AMI NRZ-OUT CRX AIS LTE CKR ERR VDD VSS +HDB3 OUT -HDB3 OUT +HDB3 IN -HDB3 INRAIS Data Sheet January 1997 File Number 1310.3

Absolute Maximum Ratings Thermal Information Supply Voltage (VDD ) Supply Voltage Range Power Dissipation For TA = 60oC to 85oC For TA = 100oC to 125oC Device Dissipation per Output Transistor Operating Conditions Temperature Range CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationo ft h e device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical SpecificationsVDD = 5V±10%, TA = 25oC PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS STATIC SPECIFICATIONS Quiescent Device Current I DD - - 100 µA Operating Device Current f CL = 10MHz - - 8 mA HDB3 Output Low (Sink) Current I OL1 VOL = 0.5V 1.6 - - mA HDB3 Output High (Source) Current I OH1 VOH = 2.8V -10 - - mA All Other Outputs Low (Sink) Current I OL2 VOL = 0.5V 1.6 - - mA All Other Outputs High (Source) Current IOH2 VOH = 2.8V -1.6 - - mA Input Low Current I IL -- - 1 µA Input High Current I IH --1 µA Input Low Voltage V IL - - 0.8 V Input High Voltage V IH 2--V Input Capacitance I IN --5 p F Electrical SpecificationsTA = -40oC to 85oC for Plastic Package; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V; C L = 15pF PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS DYNAMIC INPUT CTX, CRX Input Frequency f CTX , fCRX 0.05 - 10 MHz CTX, CRX Input Rise Time t RCL 3--1 µs Fall Time t FCL 3--1 µs NRZ-IN to CTX Data Setup Time t S 31 5- - n s Data Hold Time t H 31 5- - n s HDB3 IN to CRX Data Setup Time t S 41 5- - n s Data Hold Time t H 30- - n s CD22103A

The CD22103A is designed to code and decode HDB3 signals which are coded as binary digital signals (NRZ-lN) and (+HDB3 IN, -HDB3 IN), accompanied by sampling clocks (CTX) and (CRX). The two binary coded HDB3 out- puts, (+HDB3 OUT, -HDB3 OUT) may be externally mixed to create the ternary HDB3 signals (See Figure 1). The two binary HDB3 input signals have been split from the input ternary HDB3 in an external line receiver. The receiver decoder converts binary unipolar inputs (+HDB3 IN, -HDB3 IN), which were externally split from ternary bipolar HDB3 signals, and a synchronous clock signal (CRX) into binary unipolar NRZ signals (NRZ-OUT). Received signals not consistent with HDB3 coding rules are detected as errors. The receiver error output (ERR) is active high during one CRX period of each bit of received data that is inconsis- tent with HDB3 coding rules. An input string consisting of all ones (or marks) is detected and signaled by a high level at the Alarm Signal (AIS) output. The AIS output is set to a high level when less than three zeros are received during two consecutive periods of the Reset Alarm Inhibit Signal (RAIS). The AIS output is subsequently reset to a low level when three or more zeros are received during two periods of the reset signal ( RAIS). A diagnostic Loop-Test Mode may be entered by driving the Loop Test Enable Input (LTE) high. In this mode the HDB3 transmitter outputs (+HDB3 OUT, -HDB3 OUT) are internally connected to the HDB3 receiver inputs, and the external HDB3 receiver inputs, and the external HDB3 receiver inputs (+HDB3 IN, -HDB3 IN) are disabled. The NRZ binary output signal (NRZ - OUT) corresponds to the NRZ binary input signal (NRZ - IN) delayed by approxi- mately 8 clock periods. The Clock Receiver Output (CKR) is the product of the two HDB3 input signals or-ed together. The CRX clock signal may be derived from the CKR signal with external clock extraction circuitry. In the Loop Test Mode (LTE = 1) CKR is the product of the +HDB3 OUT and -HDB3 OUT signals or-ed together. The CD22103A may also be used to perform the AMI to NRZ coding/decoding function. To use the CD22103A in this mode, the HDB3/AMI control input is driven low. Error Detection Received HDB3/AMl binary input signals are checked for coding violations, and an error signal (ERR) is generated as described below.

  • HDB3 Signals HDB3/AMl = High The error signal (ERR) is flagged high for one CTX period if a violation pulse (±V) is received of the same polarity as the last received violation pulse. A violation pulse (±V) is considered a reception error and does not cause replacement of the last string of 4 bits to zeros, if: CRX to CKR (CRX = 8.448MHz) Pretrigger t P 5-- 2 0 n s Delay t D 5-- 2 0 n s DYNAMIC OUTPUT Transmitter Coder, CTX to HDB3 OUT: Data Propagation Delay Time t DD 3-- 9 0 n s Handling Delay Time t HD 1 - 4 - Clock Period HDB3 OUT Output Pulse Width (Clock duty cycle = 50%) fCL = 2.048MHz t W 3 238 - 260 ns fCL = 8.448MHz t W 35 3-6 5 Receiver Decoder CRX to NRZ OUT: Data Propagation Delay Times t DD 4-- 9 0 n s Handling Delay Time t HD 2 - 4 - Clock Period HDB3 IN to CKR HDB3 Propagation Delay Time LTE = 0 t IN CKR 4-- 6 5 n s LTE = 1 4 - - 30 ns Electrical SpecificationsTA = -40oC to 85oC for Plastic Package; -55oC to 125oC for Ceramic Package; VDD = 4.5V to 5.5V; C L = 15pF (Continued) PARAMETER SYMBOL FIGURE MIN TYP MAX UNITS CD22103A

care). The error signal (ERR) remains low.

  1. The data sequences B000V and BB00V are valid HDB3 codings

of the NRZ binary sequence 10000.

  1. The error signal (ERR) count, is the accurate number of all single
  • AMl Signals HDB3/AMl = Low - A coding error (ERR) is signaled when a violation pulse (+V) is received.
  • In Either the HDB3 or AMI Mode - When high levels appear simultaneously on both HDB3 inputs (+ HDB3 IN, -HDB3 IN) a logical one is assumed in the HDB3/AMl input stream and the error signal (ERR) goes high for the duration of the violation. Alarm Inhibit Signal - The alarm output (AIS) is set high if, in two successive periods of the external Reset Alarm Signal ( RAlS), less than three zeros are received. - The alarm output (AlS) is reset low when three or more zeros are received during two Reset Alarm Signal periods. Transcoder Operation Transmitter Coder (See Figure 1) The HDB3/AMI transmitter coder operates on 4-bit serial strings of NRZ binary data and a synchronous transmitter clock (CTX). NRZ binary data is serially clocked into the transmitter on the negative transition of the (CTX) clock. HDB3/AMI coding is performed on the 4-bit string, and HDB3/AMI binary output data is clocked out to the (+HDB3 OUT, -HDB3 OUT) outputs on the positive transition of the transmitter clock (CTX) 3 1/2 clock pulses after the data appeared at the (NRZ-IN) input. Receiver Decoder (See Figure 2) The HDB3/AMI receiver decoder operates on 4-bit serial strings of binary coded HDB3/AMI signals, and a synchro- nous receiver clock (CRX), HDB3/AMI binary data is serially clocked into the receiver on the positive transition of the (CRX) clock. HDB3/AMI decoding is performed on the 4-bit string, and NRZ binary output data is clocked out to the (NRZ-OUT) output on the positive transition of the receiver clock (CRX) 4 clock pulses after the data appeared at the (+HDB3 IN, -HDB3 IN) inputs. HANDLING DELAY NRZ - IN +HDB3 OUT HDB3 CODED -HDB3 OUT EXTERNAL GENERATED TERNERY HDB3 +HDB3 OUT AMI CODED -HDB3 OUT EXTERNAL GENERATED AMI CTX

FIGURE 1. TRANSMITTER CODER OPERATION TIMING WAVEFORMS - NRZ TO HDB3/AMI CODING

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitehttp://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CD22103A