CD14538BMS RENESAS | Alldatasheet

Document overview

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Technical content

Features

  • High-Voltage Type (20V Rating)
  • Retriggerable/Resettable Capability
  • Trigger and Reset Propagation Delays Independent of RX, CX
  • Triggering From Leading or Trailing Edge
  • Q and Q Buffered Outputs Available
  • Separate Resets
  • Wide Range of Output-Pulse Widths
  • Schmitt-Trigger Input Allow s Unlimited Rise and Fall Times On +TR and -TR Inputs
  • 100% Tested For Maximum Quiescent Current at 20V
  • Maximum Input Current of 1 A at 18V Over Full Pack- age-Temperature Range: - 100nA at 18V and +25 oC
  • Noise Margin (Full Package-Temperature Range): - 1V at VDD = 5V - 2V at VDD = 10V - 2.5V at VDD = 15V
  • 5V, 10V and 15V Parametric Ratings
  • Standardized Symmetrical Output Characteristics
  • Meets All Requirements of JEDEC Tentative Standards No. 13B, “Standard Specifications for Description of “B” Series CMOS Device’s

Applications

  • Pulse Delay and Timing
  • Pulse Shaping Functional Diagram

Description

CD14538BMS dual precision monostable multivibrator provides stable retriggerable/resettable one-shot operation for any fixed-voltage timing application. An external resistor (RX) and an external capacitor (CX) control the tim- ing and accuracy for the circuit. Adjustment of RX and CX provides a wide range of output pulse widths from the Q and Q terminals. The time delay from trigger input to output transition (trigger propagation delay) and the time delay from reset input to output transition (reset propagation delay) are independent of RX and CX. Precision control of output pulse widths is achieved through linear CMOS techniques. Leading-edge-triggering (+TR) and trailing-edge-triggering (-TR) inputs are provided for triggering from either edge of an input pulse. An unused +TR input should be tied to VSS. An unused -TR input should be tied to VDD. A RESET (on low level) is provided for immediate ter- mination of the output pulse or to prevent output pulses when power is turned on. An unused RESET input should be tied to VDD. However, if an entire section of the CD14538BMS is not used, its inputs must be tied to either VDD or VSS. See Table 1. In normal operation the circuit retriggers (extends the output pulse one period) on the application of each new trigger pulse. For operation in the non-retriggerable mode, Q is connected to -TR when leading-edge triggering (+TR) is used or Q is connected to +TR when trailing-edge triggering (-TR) is used. The time period (T) for this multivibrator can be calculated by: T = RXCX. The minimum value of external resistance, RX is 4K. The minimum and maximum values of external capacitance, CX, are 0pF and 100F, respectively. The CD14538BMS is interchangeable with type MC14538 and is simi- lar to and pin-compatible with the CD4098B* and CD4538B**. * T = 0.5 R XCX for CX  1000pF. *T = RXCX; CX min = 5000pF. The CD14538BMS is supplied in these 16-lead outline packages: PinoutMONO1 MONO2 CX1 RX1 VDD 21R X C X ( 1 ) 15 14 RXCX(2) VDD CX2 RX2 +TR -TR RESET +TR -TR RESET VDD = 16 VSS = 8 Braze Seal DIP H4X Frit Seal DIP H1L Ceramic Flatpack H6W CD14538BMS TOP VIEW CX1 RXCX (1) RESET (1) +TR (1) -TR (1) VSS VDD RXCX (2) RESET (2) +TR (2) -TR (2) CX2

TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. Go/No Go test with limits applied to inputs
  2. For accuracy, voltage is measured differentially to VDD. Limit is

TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS oC and +125oC limits guaranteed, 100% testing being implemented. TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS

  1. All voltages referenced to device GND.
  2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized on initial

design release and upon design changes which would affect these characteristics. TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS NOTES: 1. All voltages referenced to device GND.

  1. See Table 2 for +25 oC limit.

TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)

TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25OC TABLE 6. APPLICABLE SUBGROUPS NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2. TABLE 7. TOTAL DOSE IRRADIATION TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS

  1. Each pin except VDD and GND will have a series resistor of 10K  5%, VDD = 18V  0.5V
  2. Each pin except VDD and GND will have a series resistor of 47K 5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD = 10V

TABLE 9. FUNCTIONAL TERMINAL CONNECTIONS

  1. A triggerable one-shot multivibrator has an output pulse width
  2. A non-triggerable one-shot multivibrator has a time period (T) ref-

erenced from the application of the first trigger pulse. ply, the energy stored in CX could discharge into Pin 2 or 14. for CX should be provided as shown in Figure 1. 51-ohm current-limiting resistor is inserted in series with C X. FIGURE 1. RAPID POWER-DOWN PROTECTION CIRCUIT FIGURE 2. ALTERNATE RAPID POWER-DOWN PROTECTION

51 OHMS

FIGURE 3. 1/2 OF DEVICE SHOWN

8 VSS

FN3192 Rev 0.00 Page 10 of 10 November 1994 CD14538BMS Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. Chip Dimension and Pad Layout Dimensions in parentheses are in millimeters and are derived from the basic inch dimensions as indicated. Grid graduations are in mils (10 -3 inch) METALLIZATION: Thickness: 11kÅ 14kÅ, AL. PASSIVATION: 10.4kÅ - 15.6kÅ, Silane BOND PADS: 0.004 inches X 0.004 inches MIN DIE THICKNESS: 0.0198 inches - 0.0218 inches