CC430F5145IRGZT

Texas Instruments

MSP430 SoC With RF Core

Manufacturer: Texas Instruments

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Manufacturer or author: Texas Instruments, Incorporated [SLAS555,A]
PDF pages: 118

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 MSP430SoCWithRFCore 1FEATURES 23• True System-on-Chip (SoC) forLow-Power – SerialOnboard Programming, No External WirelessCommunication Applications Programming VoltageNeeded

Wide Supply VoltageRange: – Embedded EmulationModule (EEM) 3.6V Down to1.8V • High-PerformanceSub-1-GHz RF Transceiver
UltralowPower Consumption: Core – CPU ActiveMode (AM):160 µA/MHz – Same as inCC1101 – Standby Mode (LPM3 RTC Mode): 2.0µA – Wide Supply VoltageRange: 2.0V to3.6V – OffMode (LPM4 RAM Retention):1.0µA – Frequency Bands: 300 MHz to348 MHz, 389 MHz to464 MHz, and 779 MHz to– RTC Only Mode (LPM3.5):1.0µA 928 MHz– Shutdown Mode (LPM4.5):0.3µA – Programmable Data Rate From 0.6kBaud– Radio inRX: 15 mA, 250 kbps,915 MHz to500 kBaud• MSP430 ™ System and Peripherals – High Sensitivity(-117dBm at0.6kBaud,– 16-BitRISC Architecture,Extended ‑‑111 dBm at1.2kBaud, 315 MHz, 1% PacketMemory, up to20-MHz System Clock ErrorRate) – Wake-Up From Standby Mode inLess – ExcellentReceiverSelectivityand BlockingThan 6 µs Performance – FlexiblePower Management System With – Programmable Output Power Up toSVS and Brownout +12 dBm forAllSupported Frequencies – UnifiedClock System With FLL – 2-FSK,2-GFSK, and MSK Supported as well – 16-BitTimer TA0, Timer_A With Five as OOK and FlexibleASK Shaping Capture/Compare Registers – FlexibleSupport forPacket-Oriented – 16-BitTimer TA1, Timer_A With Three Systems: On-Chip Support forSync Word Capture/Compare Registers Detection,Address Check, FlexiblePacket – Hardware Real-TimeClock Length,and Automatic CRC Handling – Two UniversalSerialCommunication – Support forAutomatic ClearChannel Interfaces Assessment (CCA) BeforeTransmitting(for Listen-Before-TalkSystems)– USCI_A0 Supports UART, IrDA,SPI – DigitalRSSI Output– USCI_B0 Supports I2C ™ ,SPI – SuitedforSystems TargetingCompliance– 10-BitA/D ConverterWith Internal With EN 300 220 (Europe)andReference,Sample-and-Hold,and Autoscan FCC CFR Part15 (US)Features(OnlyCC430F614x and CC430F514x) – SuitedforSystems TargetingCompliance With WirelessM-Bus Standard– Comparator EN 13757‑‑4:2005– IntegratedLCD DriverWith Contrast – Support forAsynchronous andControlforup to96 Segments (Only Synchronous SerialReceive/TransmitModeCC430F614x) forBackward CompatibilityWith Existing– 128-BitAES SecurityEncryptionand Radio Communication ProtocolsDecryptionCoprocessor
FamilyMembers Summarized inTable1– 32-BitHardware Multiplier
For Complete Module Descriptions,See the– Three-ChannelInternalDMA CC430 FamilyUser'sGuide (SLAU259 ) Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsof Texas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. 2MSP430 isa trademarkofTexas Instruments. 3Allothertrademarksarethepropertyoftheirrespectiveowners. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2012–2013,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com

DESCRIPTION

The Texas InstrumentsCC430 familyof ultralow-powermicrocontrollersystem-on-chipwith integratedRF transceivercoresconsistsofseveraldevicesfeaturingdifferentsetsofperipheralstargetedfora wide range of applications.The architecture,combined with seven low-power modes (includingLPM3.5 and LMP4.5), is optimizedto achieve extended batterylifein portablemeasurement applications.The device featuresthe powerfulMSP430 ™ 16-bitRISC CPU, 16-bitregisters,and constantgeneratorsthatcontributetomaximum code efficiency. The CC430 familyprovidesa tightintegrationbetween themicrocontrollercore,itsperipherals,software,and the RF transceiver,making thesetruesystem-on-chipsolutionseasy touse as wellas improvingperformance. The CC430F614x seriesaremicrocontrollersystem-on-chipconfigurationscombiningtheexcellentperformance ofthestate-of-the-artCC1101 sub-1-GHz RF transceiverwiththeMSP430 CPUXV2, up to32 kB ofin-system programmableflashmemory, up to4 kB ofRAM, two 16-bittimers,a high-performance10-bitA/D converterwith eightexternalinputsplusinternaltemperatureand batterysensors,comparator,universalserialcommunication interfaces(USCIs),128-bitAES securityaccelerator,hardware multiplier,DMA, real-timeclockmodule with alarmcapabilities,LCD driver,and up to44 I/Opins. The CC430F514x and CC430F512x seriesare microcontrollersystem-on-chipconfigurationscombiningthe excellentperformanceofthestate-of-the-artCC1101 sub-1-GHz RF transceiverwiththeMSP430 CPUXV2, up to32 kB ofin-systemprogrammableflashmemory, up to4 kB ofRAM, two 16-bittimers,a highperformance10- bitA/D converterwithsixexternalinputsplusinternaltemperatureand batterysensorson CC430F514x devices, comparator,universalserialcommunicationinterfaces(USCI),128-bitAES securityaccelerator,hardware multiplier,DMA, real-timeclockmodule withalarmcapabilities,and up to30 I/Opins. Typicalapplicationsforthesedevicesincludewirelessanalogand digitalsensorsystems,heatcostallocators, thermostats,metering(AMR, AMI),smartgridwirelessnetworksetc. Familymembers availablearesummarized inTable1. Forcompletemodule descriptions,see theCC430 FamilyUser's Guide (SLAU259 ). Table1.FamilyMembers USCI Channel Channel Program SRAM A: B:Device Timer_A (1) LCD_B (2) ADC10_A (2) Comp_B I/O Package(KB) (KB) UART, SPI,I2C LIN,IrDA, SPI 8 ext,CC430F6147 32 4 5,3 96 seg 1 1 8 ch. 44 64 RGC4 intch. 8 ext,CC430F6145 16 2 5,3 96 seg 1 1 8 ch. 44 64 RGC4 intch. 8 ext,CC430F6143 8 2 5,3 96 seg 1 1 8 ch. 44 64 RGC4 intch. 6 ext,CC430F5147 32 4 5,3 n/a 1 1 6 ch. 30 48 RGZ4 intch. 6 ext,CC430F5145 16 2 5,3 n/a 1 1 6 ch. 30 48 RGZ4 intch. 6 ext,CC430F5143 8 2 5,3 n/a 1 1 6 ch. 30 48 RGZ4 intch. CC430F5125 16 2 5,3 n/a 1 1 n/a 6 ch. 30 48 RGZ CC430F5123 8 2 5,3 n/a 1 1 n/a 6 ch. 30 48 RGZ (1) Each number inthesequence representsan instantiationofTimer_A withitsassociatednumber ofcapturecompare registersand PWM outputgeneratorsavailable.Forexample,a number sequence of5,3 wouldrepresenttwo instantiationsofTimer_A,thefirst instantiationhaving5 and thesecond instantiationhaving3 capturecompare registersand PWM outputgenerators,respectively. (2) n/a= notavailable

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table2.OrderingInformation(1) PACKAGED DEVICES (2) TA PLASTIC 64-PINQFN (RGC) PLASTIC 48-PINQFN (RGZ) CC430F6147IRGC CC430F5147IRGZ CC430F6145IRGC CC430F5145IRGZ -40°C to85°C CC430F6143IRGC CC430F5143IRGZ CC430F5125IRGZ CC430F5123IRGZ (1) Forthemost currentpackage and orderinginformation,see thePackage OptionAddendum attheend ofthisdocument,orsee theTIweb siteatwww.ti.com. (2) Package drawings,thermaldata,and symbolizationareavailableatwww.ti.com/packaging. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3

(S: 3+1) Comp_B SMCLK ACLK MDB MAB XOUTXIN Spy-Bi- Wire CRC16 Bus Cntrl Logic MAB MDB MAB MDB MCLK USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) LCD_B Segments 1,2,3,4 Mux I/O Ports P1/P2 2x8 I/Os PA 1x16 I/Os P1.x/P2.x 2x8 I/O Ports P3/P4 2x8 I/Os PB 1x16 I/Os P3.x/P4.x 2x8 I/O Ports 1x8 I/Os P5.x 1x8 AES128 Security En-/De- cryption RF_XOUTRF_XIN RF_NRF_P TA1 3 CC Registers MODEM RF/ANALOG TX & RX Frequency Synthesizer CPU Interface Packet Handler Digital RSSI Carrier Sense PQI / LQI CCA Sub-1GHz Radio (CC1101) MPY32 ADC10 (32kHz) (26MHz) Unified Clock System CPUXV2 incl. 16 Registers JTAG Interface DMA Controller

3 Channel

(128B) incl. LPM3.5 Domain RTC_D (Calendar Counter Mode) REF Voltage Reference incl. REFOUT ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com CC430F614x FunctionalBlock Diagram NOTE: Edge-selectableinterruptand LPM3.5 and LPM4.5 wake-up inputcapabilityisavailableforportsP1 and P2.

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(TOP VIEW) CC430F614x P3.7/PM_SMCLK/S17 P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 P3.6/PM_RFGDO1/S16 P2.1/PM_TA1CCR0A/CB1/A1 P3.5/PM_TA0CCR4A/S15 P2.2/PM_TA1CCR1A/CB2/A2 P2.3/PM_TA1CCR2A/CB3/A3 P3.4/PM_TA0CCR3A/S14 P2.4/PM_RTCCLK/CB4/A4/VeREF- P3.3/PM_TA0CCR2A/S13 P2.5/ /CB5/A5 PM_SVMOUT /VREF+/VeREF+ P3.2/PM_TA0CCR1A/S12 DVCC P4.4/S6 RST/NMI/SBWTDIO P4.3/S5 TEST/SBWTCK P4.2/S4 PJ.3/TCK P4.1/S3 P2.6/PM_ACLK/CB6/A6 P3.1/PM_TA0CCR0A/S11 P2.7/ /CB7/A7 PM_ADC10CLK/PM_DMAE0 P3.0/PM_CBOUT0/PM_TA0CLK/S10 AVCC DVCC P5.0/XIN P4.7/S9 P5.1/XOUT P4.6/S8 AVSS P4.5/S7 P4.0/S2P1.0/PM_RFGDO0/S18 3316 P5.3/S1P1.1/PM_RFGDO2/S19 3415 P5.2/S0P1.2/PM_UCB0SOMI/PM_UCB0SCL/S20 3514 RF_XINP1.3/PM_UCB0SIMO/PM_UCB0SDA/S21 3613 RF_XOUTP1.4/PM_UCB0CLK/PM_UCA0STE/S22 3712 AVCC_RFDVCC 3811 GUARDLCDCAP/R33 454 PJ.0/TDOP1.5/PM_UCA0RXD/PM_UCA0SOMI/R23 463 PJ.1/TDI/TCLKP1.6/PM_UCA0TXD/PM_UCA0SIMO/R13/LCDREF 472 PJ.2/TMSP1.7/PM_UCA0CLK/PM_UCB0STE/R03 481 AVCC_RFVCORE 3910 RF_PP5.4/S23 409 RF_NP5.5/COM3/S24 418 AVCC_RFP5.6/COM2/S25 427 AVCC_RFP5.7/COM1/S26 436 R_BIASCOM0 445 VSS Exposed die attached pad ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 NOTE: The secondarydigitalfunctionson portsP1, P2, and P3 arefullymappable.Pinoutshows onlythedefaultmapping. See Table10 fordetails. CAUTION: LCDCAP/R33 must be connectedtoVSS ifnotused. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5

(128B) incl. LPM3.5 Domain Power Mgmt LDO SVM/SVS Brownout SYS TA0 5 CC Registers EEM (S: 3+1) Comp_B Flash 32kB 16kB 8kB SMCLK ACLK MDB MAB XOUTXIN Spy-Bi- Wire CRC16 Bus Cntrl Logic MAB MDB MAB MDB MCLK USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) I/O Ports P1/P2 2x8 I/Os PA 1x16 I/Os P1.x/P2.x 2x8 I/O Ports 1x8 I/Os P3.x 1x8 I/O Ports 1x2 I/Os P5.x 1x2 AES128 Security En-/De- cryption RF_XOUTRF_XIN RF_NRF_P TA1 3 CC Registers MODEM RF/ANALOG TX & RX Frequency Synthesizer CPU Interface Packet Handler Digital RSSI Carrier Sense PQI / LQI CCA Sub-1GHz Radio (CC1101) MPY32 ADC10 (32kHz) (26MHz) Unified Clock System CPUXV2 incl. 16 Registers JTAG Interface DMA Controller incl. REFOUT RTC_D (Calendar Counter Mode) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com CC430F514x FunctionalBlock Diagram NOTE: Edge-selectableinterruptand LPM3.5 and LPM4.5 wake-up inputcapabilityisavailableforportsP1 and P2.

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(TOP VIEW) 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 P1.1/PM_RFGDO2 P1.2/PM_UCB0SOMI/PM_UCB0SCL P1.7/PM_UCA0CLK/PM_UCB0STE P2.0/PM_CBOUT1/PM_TA1CLK/CB0/A0 P2.1/PM_TA1CCR0A/CB1/A1 P2.2/PM_TA1CCR1A/CB2/A2 P1.3/PM_UCB0SIMO/PM_UCB0SDA P1.4/PM_UCB0CLK/PM_UCA0STE DVCC VCORE P1.5/PM_UCA0RXD/PM_UCA0SOMI P1.6/PM_UCA0TXD/PM_UCA0SIMO RF_XIN RF_XOUT AVCC_RF GUARD PJ.0/TDO PJ.1/TDI/TCLK AVCC_RF RF_P RF_N AVCC_RF AVCC_RF R_BIAS P1.0/PM_RFGDO0P3.7/PM_SMCLKP3.6/PM_RFGDO1 P3.0/PM_CBOUT0/PM_TA0CLK DVCC P2.7/PM_ADC10CLK/PM_DMAE0 P2.6/PM_ACLK VSS Exposed die attached pad CC430F514x ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 NOTE: The secondarydigitalfunctionson portsP1, P2, and P3 arefullymappable.Pinoutshows onlythedefaultmapping. See Table10 fordetails. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7

(S: 3+1) Comp_B Flash 32kB 16kB 8kB SMCLK ACLK MDB MAB XOUTXIN Spy-Bi- Wire CRC16 Bus Cntrl Logic MAB MDB MAB MDB MCLK USCI_A0 (UART, IrDA, SPI) USCI_B0 (SPI, I2C) I/O Ports P1/P2 2x8 I/Os PA 1x16 I/Os P1.x/P2.x 2x8 I/O Ports 1x8 I/Os P3.x 1x8 I/O Ports 1x2 I/Os P5.x 1x2 AES128 Security En-/De- cryption RF_XOUTRF_XIN RF_NRF_P TA1 3 CC Registers MODEM RF/ANALOG TX & RX Frequency Synthesizer CPU Interface Packet Handler Digital RSSI Carrier Sense PQI / LQI CCA Sub-1GHz Radio (CC1101) MPY32 (32kHz) (26MHz) Unified Clock System CPUXV2 incl. 16 Registers JTAG Interface DMA Controller (128B) incl. LPM3.5 Domain RTC_D (Calendar Counter Mode) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com CC430F512x FunctionalBlock Diagram NOTE: Edge-selectableinterruptand LPM3.5 and LPM4.5 wake-up inputcapabilityisavailableforportsP1 and P2.

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(TOP VIEW) 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 P1.1/PM_RFGDO2 P1.2/PM_UCB0SOMI/PM_UCB0SCL P1.7/PM_UCA0CLK/PM_UCB0STE P2.0/PM_CBOUT1/PM_TA1CLK/CB0 P2.1/PM_TA1CCR0A/CB1 P2.2/PM_TA1CCR1A/CB2 P1.3/PM_UCB0SIMO/PM_UCB0SDA P1.4/PM_UCB0CLK/PM_UCA0STE DVCC VCORE P1.5/PM_UCA0RXD/PM_UCA0SOMI P1.6/PM_UCA0TXD/PM_UCA0SIMO RF_XIN RF_XOUT AVCC_RF GUARD PJ.0/TDO PJ.1/TDI/TCLK AVCC_RF RF_P RF_N AVCC_RF AVCC_RF R_BIAS P1.0/PM_RFGDO0P3.7/PM_SMCLKP3.6/PM_RFGDO1 P3.0/PM_CBOUT0/PM_TA0CLK DVCC P2.7/PM_DMAE0 P2.6/PM_ACLK VSS Exposed die attached pad CC430F512x ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 NOTE: The secondarydigitalfunctionson portsP1, P2, and P3 arefullymappable.Pinoutshows onlythedefaultmapping. See Table10 fordetails. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 9

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table3.CC430F614x TerminalFunctions TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.7/PM_UCA0CLK/ 1 I/O Defaultmapping:USCI_A0 clockinput/output;USCI_B0 SPI slavetransmitenablePM_UCB0STE/ R03 Input/outputportoflowestanalogLCD voltage(V5) General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P1.6/PM_UCA0TXD/ Defaultmapping:USCI_A0 UART transmitdata;USCI_A0 SPI slaveinmasterout2 I/OPM_UCA0SIMO/ R13/ LCDREF Input/outputportofthirdmost positiveanalogLCD voltage(V3 orV4) ExternalreferencevoltageinputforregulatedLCD voltage General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.5/PM_UCA0RXD/ 3 I/O Defaultmapping:USCI_A0 UART receivedata;USCI_A0 SPI slaveoutmasterinPM_UCA0SOMI/ R23 Input/outputportofsecond most positiveanalogLCD voltage(V2) LCD capacitorconnection LCDCAP/ R33 4 I/O Input/outputportofmost positiveanalogLCD voltage(V1) CAUTION: Must be connectedtoVSS ifnotused. COM0 5 O LCD common outputCOM0 forLCD backplane General-purposedigitalI/O P5.7/COM1/ S26 6 I/O LCD common outputCOM1 forLCD backplane LCD segment outputS26 General-purposedigitalI/O P5.6/COM2/ S25 7 I/O LCD common outputCOM2 forLCD backplane LCD segment outputS25 General-purposedigitalI/O P5.5/COM3/ S24 8 I/O LCD common outputCOM3 forLCD backplane LCD segment outputS24 General-purposedigitalI/OP5.4/S23 9 I/O LCD segment outputS23 VCORE 10 Regulatedcorepower supply DVCC 11 Digitalpower supply General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.4/PM_UCB0CLK/ 12 I/O Defaultmapping:USCI_B0 clockinput/output;USCI_A0 SPI slavetransmitenablePM_UCA0STE/ S22 LCD segment outputS22 General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.3/PM_UCB0SIMO/ 13 I/O Defaultmapping:USCI_B0 SPI slaveinmasterout;USCI_B0 I2C dataPM_UCB0SDA/ S21 LCD segment outputS21 General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.2/PM_UCB0SOMI/ 14 I/O Defaultmapping:USCI_B0 SPI slaveoutmasterin;UCSI_B0 I2C clockPM_UCB0SCL/ S20 LCD segment outputS20 General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P1.1/PM_RFGDO2/ S19 15 I/O Defaultmapping:RadioGDO2 output LCD segment outputS19 General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P1.0/PM_RFGDO0/ S18 16 I/O Defaultmapping:RadioGDO0 output LCD segment outputS18 General-purposedigitalI/Owithmappable secondaryfunction P3.7/PM_SMCLK/ S17 17 I/O Defaultmapping:SMCLK output LCD segment outputS17 General-purposedigitalI/Owithmappable secondaryfunction P3.6/PM_RFGDO1/ S16 18 I/O Defaultmapping:RadioGDO1 output LCD segment outputS16 General-purposedigitalI/Owithmappable secondaryfunction P3.5/PM_TA0CCR4A/ S15 19 I/O Defaultmapping:TA0 CCR4 compare outputorcaptureinput LCD segment outputS15 General-purposedigitalI/Owithmappable secondaryfunction P3.4/PM_TA0CCR3A/ S14 20 I/O Defaultmapping:TA0 CCR3 compare outputorcaptureinput LCD segment outputS14 General-purposedigitalI/Owithmappable secondaryfunction P3.3/PM_TA0CCR2A/ S13 21 I/O Defaultmapping:TA0 CCR2 compare outputorcaptureinput LCD segment outputS13 (1) I= input,O = output

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table3.CC430F614x TerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithmappable secondaryfunction P3.2/PM_TA0CCR1A/ S12 22 I/O Defaultmapping:TA0 CCR1 compare outputorcaptureinput LCD segment outputS12 General-purposedigitalI/Owithmappable secondaryfunction P3.1/PM_TA0CCR0A/ S11 23 I/O Defaultmapping:TA0 CCR0 compare outputorcaptureinput LCD segment outputS11 General-purposedigitalI/Owithmappable secondaryfunctionP3.0/PM_CBOUT0/ PM_TA0CLK/ 24 I/O Defaultmapping:Comparator_Boutput;TA0 clockinputS10 LCD segment outputS10 DVCC 25 Digitalpower supply General-purposedigitalI/OP4.7/S9 26 I/O LCD segment outputS9 General-purposedigitalI/OP4.6/S8 27 I/O LCD segment outputS8 General-purposedigitalI/OP4.5/S7 28 I/O LCD segment outputS7 General-purposedigitalI/OP4.4/S6 29 I/O LCD segment outputS6 General-purposedigitalI/OP4.3/S5 30 I/O LCD segment outputS5 General-purposedigitalI/OP4.2/S4 31 I/O LCD segment outputS4 General-purposedigitalI/OP4.1/S3 32 I/O LCD segment outputS3 General-purposedigitalI/OP4.0/S2 33 I/O LCD segment outputS2 General-purposedigitalI/OP5.3/S1 34 I/O LCD segment outputS1 General-purposedigitalI/OP5.2/S0 35 I/O LCD segment outputS0 RF_XIN 36 I InputterminalforRF crystaloscillatororexternalclockinput RF_XOUT 37 O OutputterminalforRF crystaloscillator AVCC_RF 38 Radioanalogpower supply AVCC_RF 39 Radioanalogpower supply RF PositiveRF inputtoLNA inreceivemodeRF_P 40 I/O PositiveRF outputfromPA intransmitmode RF NegativeRF inputtoLNA inreceivemodeRF_N 41 I/O NegativeRF outputfromPA intransmitmode AVCC_RF 42 Radioanalogpower supply AVCC_RF 43 Radioanalogpower supply RBIAS 44 Externalbiasresistorforradioreferencecurrent GUARD 45 Power supplyconnectionfordigitalnoiseisolation General-purposedigitalI/OPJ.0/TDO 46 I/O Testdataoutputport General-purposedigitalI/OPJ.1/TDI/TCLK 47 I/O Testdatainputortestclockinput General-purposedigitalI/OPJ.2/TMS 48 I/O Testmode select General-purposedigitalI/OPJ.3/TCK 49 I/O Testclock Testmode pin-selectdigitalI/Oon JTAG pinsTEST/ SBWTCK 50 I Spy-bi-wireinputclock Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 11

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table3.CC430F614x TerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. Resetinputactivelow RST/NMI/ SBWTDIO 51 I/O Non-maskableinterruptinput Spy-bi-wiredatainput/output DVCC 52 Digitalpower supply AVSS 53 AnaloggroundsupplyforADC10 General-purposedigitalI/OP5.1/XOUT 54 I/O OutputterminalofcrystaloscillatorXT1 General-purposedigitalI/OP5.0/XIN 55 I/O InputterminalforcrystaloscillatorXT1 AVCC 56 Analogpower supply General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P2.7/PM_ADC10CLK/ Defaultmapping:ADC10CLK output;DMA externaltriggerinput57 I/OPM_DMAE0/ CB7 (/A7) Comparator_BinputCB7 AnaloginputA7 -10-bitADC General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:ACLK outputP2.6/PM_ACLK/ CB6 (/A6) 58 I/O Comparator_BinputCB6 AnaloginputA6 -10-bitADC General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:SVM output Comparator_BinputCB5P2.5/PM_SVMOUT/ CB5 59 I/O AnaloginputA5 -10-bitADC(/A5/VREF+/ VeREF+) OutputofreferencevoltagetotheADC PositiveterminalfortheADC referencevoltageforbothsources,theinternalreference voltage,oran externalappliedreferencevoltage General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:RTCCLK output P2.4/PM_RTCCLK/ CB4 Comparator_BinputCB460 I/O(/A4/VeREF-) AnaloginputA4 -10-bitADC NegativeterminalfortheADC referencevoltageforan externalappliedreference voltage General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR2 compare outputorcaptureinputP2.3/PM_TA1CCR2A/ CB3 (/A3) 61 I/O Comparator_BinputCB3 AnaloginputA3 -10-bitADC General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR1 compare outputorcaptureinputP2.2/PM_TA1CCR1A/ CB2 (/A2) 62 I/O Comparator_BinputCB2 AnaloginputA2 -10-bitADC General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR0 compare outputorcaptureinputP2.1/PM_TA1CCR0A/CB1(/A1) 63 I/O Comparator_BinputCB1 AnaloginputA1 -10-bitADC General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P2.0/PM_CBOUT1/ PM_TA1CLK/ Defaultmapping:Comparator_Boutput;TA1 clockinput64 I/OCB0 (/A0) Comparator_BinputCB0 AnaloginputA0 -10-bitADC Ground supply VSS -Exposed dieattachpad The exposed dieattachpad must be connected toa solidground planeas thisis theground connectionforthechip.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table4.CC430F514x and CC430F512x TerminalFunctions TERMINAL I/O(1) DESCRIPTION NAME NO. General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR1 compare outputorcaptureinputP2.2/PM_TA1CCR1A/ CB2/ (A2) 1 I/O Comparator_BinputCB2 AnaloginputA2 -10-bitADC (onlyCC430F514x) General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR0 compare outputorcaptureinputP2.1/PM_TA1CCR0A/ CB1/ (A1) 2 I/O Comparator_BinputCB1 AnaloginputA1 -10-bitADC (onlyCC430F514x) General-purposedigitalI/Owithportinterruptand mappable secondaryfunction P2.0/PM_CBOUT1/ PM_TA1CLK/ Defaultmapping:Comparator_Boutput;TA1 clockinput3 I/OCB0/ (A0) Comparator_BinputCB0 AnaloginputA0 -10-bitADC (onlyCC430F514x) P1.7/PM_UCA0CLK/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction4 I/OPM_UCA0STE Defaultmapping:USCI_A0 clockinput/output;USCI_B0 SPI slavetransmitenable P1.6/PM_UCA0TXD/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction5 I/OPM_UCA0SIMO Defaultmapping:USCI_A0 UART transmitdata;USCI_A0 SPI slaveinmasterout P1.5/PM_UCA0RXD/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction6 I/OPM_UCA0SOMI Defaultmapping:USCI_A0 UART receivedata;USCI_A0 SPI slaveoutmasterin VCORE 7 Regulatedcorepower supply DVCC 8 Digitalpower supply P1.4/PM_UCB0CLK/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction9 I/OPM_UCA0STE Defaultmapping:USCI_B0 clockinput/output;USCI_A0 SPI slavetransmitenable P1.3/PM_UCB0SIMO/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction10 I/OPM_UCB0SDA Defaultmapping:USCI_B0 SPI slaveinmasterout;USCI_B0 I2C data P1.2/PM_UCB0SOMI/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction11 I/OPM_UCB0SCL Defaultmapping:USCI_B0 SPI slaveoutmasterin;UCSI_B0 I2C clock General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.1/PM_RFGDO2 12 I/O Defaultmapping:RadioGDO2 output General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP1.0/PM_RFGDO0 13 I/O Defaultmapping:RadioGDO0 output General-purposedigitalI/Owithmappable secondaryfunctionP3.7/PM_SMCLK 14 I/O Defaultmapping:SMCLK output General-purposedigitalI/Owithmappable secondaryfunctionP3.6/PM_RFGDO1 15 I/O Defaultmapping:RadioGDO1 output General-purposedigitalI/Owithmappable secondaryfunctionP3.5/PM_TA0CCR4A 16 I/O Defaultmapping:TA0 CCR4 compare outputorcaptureinput General-purposedigitalI/Owithmappable secondaryfunctionP3.4/PM_TA0CCR3A 17 I/O Defaultmapping:TA0 CCR3 compare outputorcaptureinput General-purposedigitalI/Owithmappable secondaryfunctionP3.3/PM_TA0CCR2A 18 I/O Defaultmapping:TA0 CCR2 compare outputorcaptureinput General-purposedigitalI/Owithmappable secondaryfunctionP3.2/PM_TA0CCR1A 19 I/O Defaultmapping:TA0 CCR1 compare outputorcaptureinput General-purposedigitalI/Owithmappable secondaryfunctionP3.1/PM_TA0CCR0A 20 I/O Defaultmapping:TA0 CCR0 compare outputorcaptureinput General-purposedigitalI/Owithmappable secondaryfunctionP3.0/PM_CBOUT0/ PM_TA0CLK 21 I/O Defaultmapping:Comparator_Boutput;TA0 clockinput DVCC 22 Digitalpower supply P2.7/PM_ADC10CLK/ General-purposedigitalI/Owithportinterruptand mappable secondaryfunction23 I/OPM_DMAE0 Defaultmapping:ADC10CLK output;DMA externaltriggerinput General-purposedigitalI/Owithportinterruptand mappable secondaryfunctionP2.6/PM_ACLK 24 I/O Defaultmapping:ACLK output RF_XIN 25 I InputterminalforRF crystaloscillator,orexternalclockinput RF_XOUT 26 O OutputterminalforRF crystaloscillator AVCC_RF 27 Radioanalogpower supply (1) I= input,O = output Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 13

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table4.CC430F514x and CC430F512x TerminalFunctions(continued) TERMINAL I/O(1) DESCRIPTION NAME NO. AVCC_RF 28 Radioanalogpower supply RF PositiveRF inputtoLNA inreceivemodeRF_P 29 I/O PositiveRF outputfromPA intransmitmode RF NegativeRF inputtoLNA inreceivemodeRF_N 30 I/O NegativeRF outputfromPA intransmitmode AVCC_RF 31 Radioanalogpower supply AVCC_RF 32 Radioanalogpower supply RBIAS 33 Externalbiasresistorforradioreferencecurrent GUARD 34 Power supplyconnectionfordigitalnoiseisolation General-purposedigitalI/OPJ.0/TDO 35 I/O Testdataoutputport General-purposedigitalI/OPJ.1/TDI/TCLK 36 I/O Testdatainputortestclockinput General-purposedigitalI/OPJ.2/TMS 37 I/O Testmode select General-purposedigitalI/OPJ.3/TCK 38 I/O Testclock Testmode pin-selectdigitalI/Oon JTAG pinsTEST/ SBWTCK 39 I Spy-bi-wireinputclock Resetinputactivelow RST/NMI/ SBWTDIO 40 I/O Non-maskableinterruptinput Spy-bi-wiredatainput/output DVCC 41 Digitalpower supply AVSS 42 AnaloggroundsupplyforADC10 General-purposedigitalI/OP5.1/XOUT 43 I/O OutputterminalofcrystaloscillatorXT1 General-purposedigitalI/OP5.0/XIN 44 I/O InputterminalforcrystaloscillatorXT1 AVCC 45 Analogpower supply General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:SVM output P2.5/PM_SVMOUT/ CB5/ Comparator_BinputCB546 I/O(A5/VREF+/VeREF+) AnaloginputA5 -10-bitADC (onlyCC430F514x) PositiveterminalfortheADC referencevoltageforbothsources,theinternalreference voltage,oran externalappliedreferencevoltage(onlyCC430F514x) General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:RTCCLK output P2.4/PM_RTCCLK/ CB4/ Comparator_BinputCB447 I/O(A4/VeREF-) AnaloginputA4 -10-bitADC (onlyCC430F514x) NegativeterminalfortheADC referencevoltageforan externalappliedreference voltage(onlyCC430F514x) General-purposedigitalI/Owithportinterruptand mappable secondaryfunction Defaultmapping:TA1 CCR2 compare outputorcaptureinputP2.3/PM_TA1CCR2A/ CB3/ (A3) 48 I/O Comparator_BinputCB3 AnaloginputA3 -10-bitADC (onlyCC430F514x) Ground supply VSS -Exposed dieattachpad The exposed dieattachpad must be connected toa solidground planeas thisis theground connectionforthechip.

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RBIAS RF_XIN RF_XOUT XOSC LNA FREQ SYNTH ADC DEMODULATOR PACKET HANDLER RXFIFOTXFIFO INTERFACE TO MCU RADIO□CONTROL RF_P RF_N RC□OSC ADC MODULATOR ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 SHORT-FORM DESCRIPTION Sub-1-GHz Radio The implementedsub-1-GHz radiomodule isbased on theindustry-leadingCC1101, requiringveryfew external components.Figure1 shows a high-levelblockdiagramoftheimplementedradio. Figure1. Sub-1 GHz Radio Block Diagram The radiofeaturesa low-IFreceiver.The receivedRF signalisamplifiedby a low-noiseamplifier(LNA) and down-convertedinquadraturetotheintermediatefrequency(IF).At IF,theI/Qsignalsare digitized.Automatic gaincontrol(AGC),finechannelfiltering,demodulationbitand packetsynchronizationareperformeddigitally. The transmitterpartisbased on directsynthesisof the RF frequency.The frequencysynthesizerincludesa completelyon-chipLC VCO and a 90° phase shifterforgeneratingthe I and Q LO signalsto the down- conversionmixersinreceivemode. The 26-MHz crystaloscillatorgeneratesthe referencefrequencyforthe synthesizer,as wellas clocksforthe ADC and thedigitalpart. A memory mapped registerinterfaceisused fordataaccess,configurationand statusrequestby theCPU. The digitalbaseband includessupportforchannelconfiguration,packethandling,and databuffering. Forcompletemodule descriptions,see theCC430 FamilyUser'sGuide (SLAU259 ). Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 15

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com CPU The MSP430 CPU has a 16-bitRISC architecturethatishighlytransparentto the application.Alloperations, otherthanprogram-flowinstructions,areperformedas registeroperationsinconjunctionwithseven addressing modes forsourceoperandand fouraddressingmodes fordestinationoperand. The CPU isintegratedwith16 registersthatprovidereducedinstructionexecutiontime.The register-to-register operationexecutiontimeisone cycleoftheCPU clock. Four oftheregisters,R0 toR3, are dedicatedas program counter,stackpointer,statusregister,and constant generator,respectively.The remainingregistersaregeneral-purposeregisters. Peripheralsare connectedto the CPU usingdata,address,and controlbuses and can be handled withall instructions. The instructionsetconsistsof the original51 instructionswiththreeformatsand seven addressmodes and additionalinstructionsfortheexpanded addressrange.Each instructioncan operateon word and bytedata. OperatingModes The CC430 has one activemode and seven softwareselectablelow-powermodes of operation.An interrupt eventcan wake up thedevicefrom any ofthelow-powermodes, servicetherequest,and restoreback tothe low-powermode on returnfromtheinterruptprogram. The followingeightoperatingmodes can be configuredby software:

Low-power mode 4 (LPM4)• Activemode (AM) – CPU isdisabled– Allclocksareactive – ACLK isdisabled• Low-power mode 0 (LPM0) – MCLK, FLL loop control,and DCOCLK are– CPU isdisabled disabled – ACLK and SMCLK remain active,MCLK is – DCO's dc-generatorisdisableddisabled – Crystaloscillatorisstopped– FLL loopcontrolremainsactive – Completedataretention• Low-power mode 1 (LPM1) • Low-power mode 3.5(LPM3.5)– CPU isdisabled – Internalregulatordisabled– FLL loopcontrolisdisabled – No data retentionexcept Backup RAM and– ACLK and SMCLK remain active,MCLK is RTCdisabled – RTC enabled and clockedby low-frequency• Low-power mode 2 (LPM2) crystaloscillatorXT1 – CPU isdisabled – Wake up fromRST/NMI, RTC, P1,P2 – MCLK and FLL loopcontroland DCOCLK are • Low-power mode 4.5(LPM4.5)disabled – Internalregulatordisabled– DCO's dc-generatorremainsenabled – No dataretentionexceptBackup RAM– ACLK remainsactive – Wake up fromRST/NMI, P1,P2• Low-power mode 3 (LPM3) – CPU isdisabled – MCLK, FLL loop control,and DCOCLK are disabled – DCO's dc-generatorisdisabled – ACLK remainsactive

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 InterruptVectorAddresses The interruptvectorsand thepower-upstartaddressarelocatedintheaddressrange0FFFFh to0FF80h. The vectorcontainsthe16-bitaddressoftheappropriateinterrupt-handlerinstructionsequence. Table5.InterruptSources,Flags,and Vectors SYSTEM WORDINTERRUPT SOURCE INTERRUPT FLAG PRIORITYINTERRUPT ADDRESS System Reset Power-Up ExternalReset WDTIFG, KEYV (SYSRSTIV) (1)(2) Reset 0FFFEh 63,highestWatchdog Timeout,Password Violation FlashMemory Password Violation System NMI SVMLIFG, SVMHIFG, DLYLIFG, DLYHIFG,PMM VLRLIFG, VLRHIFG, VMAIFG, JMBNIFG, (Non)maskable 0FFFCh 62VacantMemory Access JMBOUTIFG (SYSSNIV)(1)(3) JTAG Mailbox User NMI NMI NMIIFG, OFIFG, ACCVIFG (SYSUNIV)(1)(3) (Non)maskable 0FFFAh 61OscillatorFault FlashMemory Access Violation Comparator_B Comparator_BInterruptFlags(CBIV)(1) Maskable 0FFF8h 60 Watchdog IntervalTimerMode WDTIFG Maskable 0FFF6h 59 USCI_A0 ReceiveorTransmit UCA0RXIFG, UCA0TXIFG (UCA0IV)(1) Maskable 0FFF4h 58 UCB0RXIFG, UCB0TXIFG, I2C StatusInterruptUSCI_B0 ReceiveorTransmit Maskable 0FFF2h 57Flags(UCB0IV)(1) ADC10IFG0, ADC10INIFG, ADC10LOIFG,ADC10_A ADC10HIIFG, ADC10TOVIFG, ADC10OVIFG Maskable 0FFF0h 56(Reservedon CC430F512x) (ADC10IV)(1) TA0 TA0CCR0 CCIFG0 Maskable 0FFEEh 55 TA0CCR1 CCIFG1 ...TA0CCR4 CCIFG4,TA0 Maskable 0FFECh 54TA0IFG (TA0IV)(1) RadioInterfaceInterruptFlags(RF1AIFIV)RF1A CC1101-based Radio Maskable 0FFEAh 53RadioCore InterruptFlags(RF1AIV) DMA DMA0IFG, DMA1IFG, DMA2IFG (DMAIV)(1) Maskable 0FFE8h 52 TA1 TA1CCR0 CCIFG0 Maskable 0FFE6h 51 TA1CCR1 CCIFG1 ...TA1CCR2 CCIFG2,TA1 Maskable 0FFE4h 50TA1IFG (TA1IV)(1) I/OPortP1 P1IFG.0toP1IFG.7(P1IV)(1) Maskable 0FFE2h 49 I/OPortP2 P2IFG.0toP2IFG.7(P2IV)(1) Maskable 0FFE0h 48 LCD_B (Reservedon CC430F514x and LCD_B InterruptFlags(LCDBIV)(1) Maskable 0FFDEh 47 CC430F512x) RTCRDYIFG, RTCTEVIFG, RTCAIFG,RTC_D Maskable 0FFDCh 46RT0PSIFG, RT1PSIFG, RTCOFIFG (RTCIV)(1) AES AESRDYIFG Maskable 0FFDAh 45 0FFD8h 44 Reserved Reserved(4) ⋮ ⋮ 0FF80h 0,lowest (1) Multiplesourceflags (2) A resetisgeneratediftheCPU triestofetchinstructionsfromwithinperipheralspace. (3) (Non)maskable:theindividualinterruptenablebitcan disablean interruptevent,butthegeneralinterruptenablecannotdisableit. (4) Reservedinterruptvectorsataddressesarenotused inthisdeviceand can be used forregularprogramcode ifnecessary.To maintain compatibilitywithotherdevices,itisrecommended toreservetheselocations. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 17

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Memory Organization Table6.Memory Organization(1) CC430F6145 CC430F6143CC430F6147 CC430F5145 CC430F5143CC430F5147 CC430F5125 CC430F5123 Total 32kB 16kB 8kBMain Memory (flash) Size Main:Interruptvector 00FFFFh-00FF80h 00FFFFh-00FF80h 00FFFFh-00FF80h Bank 0 32kB 16kB 8kBMain:code memory 00FFFFh-008000h 00FFFFh-00C000h 00FFFFh-00E000h Total 4kB 2kB 2kBRAM Size Sect1 2kB notavailable notavailable 002BFFh-002400h Sect0 1.875kB 1.875kB 1.875kB 0023FFh-001C80h 0023FFh-001C80h 0023FFh-001C80h 128B 128B 128BBackup RAM (2) 001C7Fh-001C00h 001C7Fh-001C00h 001C7Fh-001C00h

128 B 128 B 128 B

001AFFh to001A80h 001AFFh to001A80h 001AFFh to001A80h DeviceDescriptor 001A7Fh to001A00h 001A7Fh to001A00h 001A7Fh to001A00h InfoA 128 B 128 B 128 B 0019FFh to001980h 0019FFh to001980h 0019FFh to001980h InfoB 128 B 128 B 128 B 00197Fh to001900h 00197Fh to001900h 00197Fh to001900hInformationmemory (flash) InfoC 128 B 128 B 128 B 0018FFh to001880h 0018FFh to001880h 0018FFh to001880h InfoD 128 B 128 B 128 B 00187Fh to001800h 00187Fh to001800h 00187Fh to001800h BSL 3 512 B 512 B 512 B 0017FFh to001600h 0017FFh to001600h 0017FFh to001600h BSL 2 512 B 512 B 512 B 0015FFh to001400h 0015FFh to001400h 0015FFh to001400hBootstraploader (BSL)memory (flash) BSL 1 512 B 512 B 512 B 0013FFh to001200h 0013FFh to001200h 0013FFh to001200h BSL 0 512 B 512 B 512 B 0011FFh to001000h 0011FFh to001000h 0011FFh to001000h

4 KB 4 KB 4 KBPeripherals 000FFFh to0h 000FFFh to0h 000FFFh to0h

(1) Allmemory regionsnotspecifiedherearevacantmemory and any accesstothem causesa VacantMemory Interrupt. (2) ContentretainedinLPM3.5 and LPM4.5.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 BootstrapLoader (BSL) The BSL enablesusersto program the flashmemory or RAM usingvariousserialinterfaces.Access to the devicememory viathe BSL isprotectedby an user-definedpassword.BSL entryrequiresa specificentry sequence on theRST/NMI/SBWTDIO and TEST/SBWTCK pins.Fora completedescriptionofthefeaturesofthe BSL and itsimplementation,see theMSP430 Programming ViatheBootstrapLoaderUser'sGuide (SLAU319 ). Table7.UART BSL Pin Requirements and Functions DEVICE SIGNAL BSL FUNCTION RST/NMI/SBWTDIO Entrysequence signal TEST/SBWTCK Entrysequence signal P1.6 Data transmit P1.5 Data receive VCC Power supply VSS Ground supply JTAG Operation JTAG Standard Interface The CC430 familysupportsthestandardJTAG interfacewhich requiresfoursignalsforsendingand receiving data.The JTAG signalsare shared withgeneral-purposeI/O.The TEST/SBWTCK pinisused to enablethe JTAG signals.In additionto these signals,the RST/NMI/SBWTDIO is requiredto interfacewith MSP430 developmenttoolsand deviceprogrammers.The JTAG pin requirementsare shown in Table 8. For further detailson interfacingto developmenttoolsand deviceprogrammers,see theMSP430 Hardware ToolsUser's Guide (SLAU278 ).For a completedescriptionofthefeaturesoftheJTAG interfaceand itsimplementation,see MSP430 Programming ViatheJTAG Interface(SLAU320 ). Table8.JTAG Pin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION PJ.3/TCK IN JTAG clockinput PJ.2/TMS IN JTAG statecontrol PJ.1/TDI/TCLK IN JTAG datainput,TCLK input PJ.0/TDO OUT JTAG dataoutput TEST/SBWTCK IN EnableJTAG pins RST/NMI/SBWTDIO IN Externalreset VCC Power supply VSS Ground supply Spy-Bi-WireInterface InadditiontothestandardJTAG interface,theCC430 familysupportsthetwo wireSpy-Bi-Wireinterface.Spy-Bi- Wire can be used to interfacewithMSP430 development toolsand deviceprogrammers.The Spy-Bi-Wire interfacepinrequirementsare shown inTable 9. For furtherdetailson interfacingto developmenttoolsand deviceprogrammers,see theMSP430 Hardware ToolsUser'sGuide (SLAU278 ).For a completedescriptionof the featuresof the JTAG interfaceand itsimplementation,see MSP430 Programming Via the JTAG Interface (SLAU320 ). Table9.Spy-Bi-WirePin Requirements and Functions DEVICE SIGNAL DIRECTION FUNCTION TEST/SBWTCK IN Spy-Bi-Wireclockinput RST/NMI/SBWTDIO IN,OUT Spy-Bi-Wiredatainput/output VCC Power supply VSS Ground supply Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 19

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com FlashMemory The flashmemory can be programmed viatheJTAG port,Spy-Bi-Wire(SBW), or in-systemby theCPU. The CPU can performsingle-byte,single-word,and long-wordwritesto the flashmemory. Featuresof the flash memory include:

Flashmemory has n segments ofmain memory and foursegments ofinformationmemory (InfoA toInfoD) of128 byteseach.Each segment inmain memory is512 bytesinsize.
Segments 0 ton may be erasedinone step,oreach segment may be individuallyerased.
Segments InfoA to InfoD can be erased individually,or as a group withthe main memory segments. Segments InfoA toInfoD arealsocalledinformationmemory .
Segment A can be lockedseparately. RAM Memory The RAM memory ismade up of n sectors.Each sectorcan be completelypowered down to save leakage, however alldataislost.FeaturesoftheRAM memory include:
RAM memory has n sectorsof2k byteseach.
Each sector0 ton can be completedisabled;however,dataretentionislost.
Each sector0 ton automaticallyenterslow-powerretentionmode when possible. Backup RAM The backup RAM provides128 bytesofmemory thatareretainedeven inLPM3.5 and LPM4.5 when thecoreis powered down. Peripherals Peripheralsare connectedtotheCPU throughdata,address,and controlbuses and can be handledusingall instructions.Forcompletemodule descriptions,see theCC430 FamilyUser'sGuide (SLAU259 ). Oscillatorand System Clock The UnifiedClock System (UCS) module includessupportfora 32768-Hz watch crystaloscillator,an internal very-low-powerlow-frequencyoscillator(VLO), an internaltrimmed low-frequencyoscillator(REFO), an integratedinternaldigitally-controlledoscillator(DCO), and a high-frequencycrystaloscillator.The UCS module isdesignedto meet the requirementsof both low system costand low-powerconsumption.The UCS module featuresdigitalfrequencylockedloop(FLL)hardwarethat,inconjunctionwitha digitalmodulator,stabilizesthe DCO frequencyto a programmable multipleof the watch crystalfrequency.The internalDCO providesa fast turn-onclocksourceand stabilizesinlessthan5 µs.The UCS module providesthefollowingclocksignals:
Auxiliaryclock(ACLK),sourcedfrom a 32768-Hz watch crystal,a high-frequencycrystal,the internallow- frequencyoscillator(VLO),orthetrimmedlow-frequencyoscillator(REFO).
Main clock(MCLK), the system clockused by the CPU. MCLK can be sourced by same sourcesmade availabletoACLK.
Sub-Main clock(SMCLK), thesubsystem clockused by theperipheralmodules.SMCLK can be sourcedby same sourcesmade availabletoACLK.
ACLK/n,thebufferedoutputofACLK, ACLK/2,ACLK/4,ACLK/8,ACLK/16,ACLK/32. Power Management Module (PMM) The PMM includesan integratedvoltageregulatorthatsuppliesthe core voltageto the deviceand contains programmableoutputlevelstoprovideforpower optimization.The PMM alsoincludessupplyvoltagesupervisor (SVS) and supplyvoltagemonitoring(SVM) circuitry,as wellas brownoutprotection.The brownoutcircuitis implemented to providethe properinternalresetsignalto the deviceduringpower-on and power-off.The SVS/SVM circuitrydetectsifthe supplyvoltagedrops below a user-selectableleveland supportsboth supply voltagesupervision(thedeviceisautomaticallyreset)and supplyvoltagemonitoring(SVM, the deviceisnot automaticallyreset).SVS and SVM circuitryisavailableon theprimarysupplyand coresupply.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 DigitalI/O Thereareup tofive8-bitI/Oportsimplemented:portsP1 throughP5.

AllindividualI/Obitsareindependentlyprogrammable.
Any combinationofinput,output,and interruptconditionsispossible.
Programmable pulluporpulldownon allports.
Programmable drivestrengthon allports.
Edge-selectableinterruptand LPM3.5 and LPM4.5 wake-up inputcapabilityisavailableforalltheeightbitsof portsP1 and P2.
Read and writeaccesstoport-controlregistersissupportedby allinstructions.
Portscan be accessedbyte-wise(P1 throughP5) orword-wiseinpairs(PA and PB). PortMapping Controller The portmapping controllerallowsthe flexibleand re-configurablemapping of digitalfunctionsto portpinsof portsP1 throughP3. Table10.PortMapping Mnemonics and Functions INPUT PIN FUNCTION OUTPUT PIN FUNCTIONVALUE PxMAPy MNEMONIC (PxDIR.y= 0) (PxDIR.y= 1)

0 PM_NONE None DVSS

PM_CBOUT0 Comparator_Boutput(onTA0 clockinput) 1(1) PM_TA0CLK TA0 clockinput - PM_CBOUT1 - Comparator_Boutput(onTA1 clockinput) 2(1) PM_TA1CLK TA1 clockinput -

3 PM_ACLK None ACLK output

4 PM_MCLK None MCLK output

5 PM_SMCLK None SMCLK output

6 PM_RTCCLK None RTCCLK output

PM_ADC10CLK - ADC10CLK output 7(1) PM_DMAE0 DMA externaltriggerinput -

8 PM_SVMOUT None SVM output

9 PM_TA0CCR0A TA0 CCR0 captureinputCCI0A TA0 CCR0 compare outputOut0

10 PM_TA0CCR1A TA0 CCR1 captureinputCCI1A TA0 CCR1 compare outputOut1

11 PM_TA0CCR2A TA0 CCR2 captureinputCCI2A TA0 CCR2 compare outputOut2

12 PM_TA0CCR3A TA0 CCR3 captureinputCCI3A TA0 CCR3 compare outputOut3

13 PM_TA0CCR4A TA0 CCR4 captureinputCCI4A TA0 CCR4 compare outputOut4

14 PM_TA1CCR0A TA1 CCR0 captureinputCCI0A TA1 CCR0 compare outputOut0

15 PM_TA1CCR1A TA1 CCR1 captureinputCCI1A TA1 CCR1 compare outputOut1

16 PM_TA1CCR2A TA1 CCR2 captureinputCCI2A TA1 CCR2 compare outputOut2

PM_UCA0RXD USCI_A0 UART RXD (Directioncontrolledby USCI -input) 17(2) PM_UCA0SOMI USCI_A0 SPI slaveoutmasterin(directioncontrolledby USCI) PM_UCA0TXD USCI_A0 UART TXD (Directioncontrolledby USCI -output) 18(2) PM_UCA0SIMO USCI_A0 SPI slaveinmasterout(directioncontrolledby USCI) PM_UCA0CLK USCI_A0 clockinput/output(directioncontrolledby USCI) 19(3) PM_UCB0STE USCI_B0 SPI slavetransmitenable(directioncontrolledby USCI -input) PM_UCB0SOMI USCI_B0 SPI slaveoutmasterin(directioncontrolledby USCI) 20(4) PM_UCB0SCL USCI_B0 I2C clock(opendrainand directioncontrolledby USCI) (1) Inputoroutputfunctionisselectedby thecorrespondingsettingintheportdirectionregisterPxDIR. (2) UART orSPI functionalityisdeterminedby theselectedUSCI mode. (3) UCA0CLK functiontakesprecedenceoverUCB0STE function.Ifthemapped pinisrequiredas UCA0CLK inputoroutput,USCI_B0 is forcedto3-wireSPI mode even if4-wiremode isselected. (4) SPI orI2C functionalityisdeterminedby theselectedUSCI mode. IfI2C functionalityisselected,theoutputofthemapped pindrives onlythelogical0 toVSS level. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 21

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table10.PortMapping Mnemonics and Functions(continued) INPUT PIN FUNCTION OUTPUT PIN FUNCTIONVALUE PxMAPy MNEMONIC (PxDIR.y= 0) (PxDIR.y= 1) PM_UCB0SIMO USCI_B0 SPI slaveinmasterout(directioncontrolledby USCI) 21(4) PM_UCB0SDA USCI_B0 I2C data(opendrainand directioncontrolledby USCI) PM_UCB0CLK USCI_B0 clockinput/output(directioncontrolledby USCI) 22(5) PM_UCA0STE USCI_A0 SPI slavetransmitenable(directioncontrolledby USCI -input)

23 PM_RFGDO0 RadioGDO0 (directioncontrolledby Radio)

24 PM_RFGDO1 RadioGDO1 (directioncontrolledby Radio)

25 PM_RFGDO2 RadioGDO2 (directioncontrolledby Radio)

26 Reserved None DVSS

27 Reserved None DVSS

28 Reserved None DVSS

29 Reserved None DVSS

30 Reserved None DVSS

Disablestheoutputdriverand theinputSchmitttriggertopreventparasiticcrosscurrents31 (0FFh)(6) PM_ANALOG when applyinganalogsignals. (5) UCB0CLK functiontakesprecedenceoverUCA0STE function.Ifthemapped pinisrequiredas UCB0CLK inputoroutput,USCI_A0 is forcedto3-wireSPI mode even if4-wiremode isselected. (6) The valueofthePM_ANALOG mnemonic issetto0FFh.The portmapping registersareonly5 bitswideand theupperbitsareignored resultingina readoutvalueof31. Table11.DefaultMapping INPUT PIN FUNCTION OUTPUT PIN FUNCTIONPIN PxMAPy MNEMONIC (PxDIR.y= 0) (PxDIR.y= 1) P1.0/P1MAP0 PM_RFGDO0 None RadioGDO0 P1.1/P1MAP1 PM_RFGDO2 None RadioGDO2 USCI_B0 SPI slaveoutmasterin(directioncontrolledby USCI)P1.2/P1MAP2 PM_UCB0SOMI/PM_UCB0SCL USCI_B0 I2C clock(opendrainand directioncontrolledby USCI) USCI_B0 SPI slaveinmasterout(directioncontrolledby USCI)P1.3/P1MAP3 PM_UCB0SIMO/PM_UCB0SDA USCI_B0 I2C data(opendrainand directioncontrolledby USCI) USCI_B0 clockinput/output(directioncontrolledby USCI)P1.4/P1MAP4 PM_UCB0CLK/PM_UCA0STE USCI_A0 SPI slavetransmitenable(directioncontrolledby USCI -input) USCI_A0 UART RXD (Directioncontrolledby USCI -input)P1.5/P1MAP5 PM_UCA0RXD/PM_UCA0SOMI USCI_A0 SPI slaveoutmasterin(directioncontrolledby USCI) USCI_A0 UART TXD (Directioncontrolledby USCI -output)P1.6/P1MAP6 PM_UCA0TXD/PM_UCA0SIMO USCI_A0 SPI slaveinmasterout(directioncontrolledby USCI) USCI_A0 clockinput/output(directioncontrolledby USCI)P1.7/P1MAP7 PM_UCA0CLK/PM_UCB0STE USCI_B0 SPI slavetransmitenable(directioncontrolledby USCI -input) P2.0/P2MAP0 PM_CBOUT1/PM_TA1CLK TA1 clockinput Comparator_Boutput P2.1/P2MAP1 PM_TA1CCR0A TA1 CCR0 captureinputCCI0A TA1 CCR0 compare outputOut0 P2.2/P2MAP2 PM_TA1CCR1A TA1 CCR1 captureinputCCI1A TA1 CCR1 compare outputOut1 P2.3/P2MAP3 PM_TA1CCR2A TA1 CCR2 captureinputCCI2A TA1 CCR2 compare outputOut2 P2.4/P2MAP4 PM_RTCCLK None RTCCLK output P2.5/P2MAP5 PM_SVMOUT None SVM output P2.6/P2MAP6 PM_ACLK None ACLK output P2.7/P2MAP7 PM_ADC10CLK/PM_DMAE0 DMA externaltriggerinput ADC10CLK output P3.0/P3MAP0 PM_CBOUT0/PM_TA0CLK TA0 clockinput Comparator_Boutput P3.1/P3MAP1 PM_TA0CCR0A TA0 CCR0 captureinputCCI0A TA0 CCR0 compare outputOut0 P3.2/P3MAP2 PM_TA0CCR1A TA0 CCR1 captureinputCCI1A TA0 CCR1 compare outputOut1 P3.3/P3MAP3 PM_TA0CCR2A TA0 CCR2 captureinputCCI2A TA0 CCR2 compare outputOut2 P3.4/P3MAP4 PM_TA0CCR3A TA0 CCR3 captureinputCCI3A TA0 CCR3 compare outputOut3 P3.5/P3MAP5 PM_TA0CCR4A TA0 CCR4 captureinputCCI4A TA0 CCR4 compare outputOut4

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table11.DefaultMapping (continued) INPUT PIN FUNCTION OUTPUT PIN FUNCTIONPIN PxMAPy MNEMONIC (PxDIR.y= 0) (PxDIR.y= 1) P3.6/P3MAP6 PM_RFGDO1 None RadioGDO1 P3.7/P3MAP7 PM_SMCLK None SMCLK output System Module (SYS) The SYS module handlesmany of the system functionswithinthe device.These includepower on resetand power up clearhandling,NMI sourceselectionand management, resetinterruptvectorgenerators,boot strap loaderentrymechanisms, as wellas,configurationmanagement (devicedescriptors).Italsoincludesa data exchange mechanism viaJTAG calleda JTAG mailboxthatcan be used intheapplication. Table12.System Module InterruptVectorRegisters INTERRUPT VECTOR REGISTER ADDRESS INTERRUPT EVENT VALUE PRIORITY SYSRSTIV, System Reset 019Eh No interruptpending 00h Brownout(BOR) 02h Highest RST/NMI (POR) 04h DoBOR (BOR) 06h Reserved 08h Securityviolation(BOR) 0Ah SVSL (POR) 0Ch SVSH (POR) 0Eh SVML_OVP (POR) 10h SVMH_OVP (POR) 12h DoPOR (POR) 14h WDT timeout(PUC) 16h WDT passwordviolation(PUC) 18h KEYV flashpasswordviolation(PUC) 1Ah Reserved 1Ch Peripheralareafetch(PUC) 1Eh PMM passwordviolation(PUC) 20h Reserved 22h to3Eh Lowest SYSSNIV, System NMI 019Ch No interruptpending 00h SVMLIFG 02h Highest SVMHIFG 04h DLYLIFG 06h DLYHIFG 08h VMAIFG 0Ah JMBINIFG 0Ch JMBOUTIFG 0Eh VLRLIFG 10h VLRHIFG 12h Reserved 14h to1Eh Lowest SYSUNIV, User NMI 019Ah No interruptpending 00h NMIFG 02h Highest OFIFG 04h ACCVIFG 06h Reserved 08h to1Eh Lowest Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 23

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com DMA Controller The DMA controllerallowsmovement of data from one memory addressto anotherwithoutCPU intervention. Using the DMA controllercan increasethe throughputof peripheralmodules. The DMA controllerreduces system power consumptionby allowingthe CPU to remain insleepmode, withouthavingto awaken to move datatoorfroma peripheral. Table13.DMA TriggerAssignments (1) CHANNEL TRIGGER 0 1 2

0 DMAREQ DMAREQ DMAREQ

1 TA0CCR0 CCIFG TA0CCR0 CCIFG TA0CCR0 CCIFG

2 TA0CCR2 CCIFG TA0CCR2 CCIFG TA0CCR2 CCIFG

3 TA1CCR0 CCIFG TA1CCR0 CCIFG TA1CCR0 CCIFG

4 TA1CCR2 CCIFG TA1CCR2 CCIFG TA1CCR2 CCIFG

5 Reserved Reserved Reserved

6 Reserved Reserved Reserved

7 Reserved Reserved Reserved

8 Reserved Reserved Reserved

9 Reserved Reserved Reserved

10 Reserved Reserved Reserved

11 Reserved Reserved Reserved

12 Reserved Reserved Reserved

13 Reserved Reserved Reserved

14 RFRXIFG RFRXIFG RFRXIFG

15 RFTXIFG RFTXIFG RFTXIFG

16 UCA0RXIFG UCA0RXIFG UCA0RXIFG

17 UCA0TXIFG UCA0TXIFG UCA0TXIFG

18 UCB0RXIFG UCB0RXIFG UCB0RXIFG

19 UCB0TXIFG UCB0TXIFG UCB0TXIFG

20 Reserved Reserved Reserved

21 Reserved Reserved Reserved

22 Reserved Reserved Reserved

23 Reserved Reserved Reserved

24 ADC10IFG0 (2) ADC10IFG0 (2) ADC10IFG0 (2)

25 Reserved Reserved Reserved

26 Reserved Reserved Reserved

27 Reserved Reserved Reserved

28 Reserved Reserved Reserved

29 MPY ready MPY ready MPY ready

30 DMA2IFG DMA0IFG DMA1IFG

31 DMAE0 DMAE0 DMAE0

(1) ReservedDMA triggersmay be used by otherdevicesinthefamily.ReservedDMA triggerswillnot cause any DMA triggereventwhen selected. (2) Onlyon CC430F614x and CC430F514x. Reservedon CC430F512x. Watchdog Timer (WDT_A) The primaryfunctionof the watchdog timeristo performa controlledsystem restartaftera softwareproblem occurs.Iftheselectedtimeintervalexpires,a system resetisgenerated.Ifthewatchdog functionisnotneeded inan application,thetimercan be configuredas an intervaltimerand can generateinterruptsatselectedtime intervals.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 CRC16 The CRC16 module producesa signaturebased on a sequence ofentereddatavaluesand can be used fordata checkingpurposes.The CRC16 module signatureisbased on theCRC-CCITT standard. Hardware Multiplier The multiplicationoperationissupportedby a dedicatedperipheralmodule.The module performsoperationswith 32-bit,24-bit,16-bit,and 8-bitoperands.The module iscapableofsupportingsignedand unsignedmultiplication as wellas signedand unsignedmultiplyand accumulateoperations. AES128 Accelerator The AES acceleratormodule performsencryptionand decryptionof128-bitdatawith128-bitkeys accordingto theAdvanced EncryptionStandard(AES) (FIPSPUB 197)inhardware. UniversalSerialCommunication Interface(USCI) The USCI module is used for serialdata communication.The USCI module supports synchronous communicationprotocolssuch as SPI (3or4 pin)and I2C, and asynchronouscommunicationprotocolssuch as UART, enhanced UART withautomaticbaudratedetection,and IrDA. The USCI_An module providessupportforSPI (3or4 pin),UART, enhanced UART, and IrDA. The USCI_Bn module providessupportforSPI (3or4 pin)and I2C. A USCI_A0 and USCI_B0 module areimplemented. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 25

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com TA0 TA0 is a 16-bittimer/counter(Timer_A type)withfivecapture/compareregisters.TA0 can supportmultiple capture/compares,PWM outputs,and intervaltiming.TA0 alsohas extensiveinterruptcapabilities.Interrupts may be generatedfromthecounteron overflowconditionsand fromeach ofthecapture/compareregisters. Table14.TA0 SignalConnections MODULE OUTPUT DEVICE OUTPUTDEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK SIGNAL SIGNAL PM_TA0CLK TACLK ACLK (internal) ACLK Timer NA SMCLK (internal) SMCLK RFCLK/192 (1) INCLK PM_TA0CCR0A CCI0A PM_TA0CCR0A DVSS CCI0B CCR0 TA0 DVSS GND DVCC VCC PM_TA0CCR1A CCI1A PM_TA0CCR1A ADC10 (internal)(2) CBOUT (internal) CCI1B ADC10SHSx = {1}CCR1 TA1 DVSS GND DVCC VCC PM_TA0CCR2A CCI2A PM_TA0CCR2A ACLK (internal) CCI2B CCR2 TA2 DVSS GND DVCC VCC PM_TA0CCR3A CCI3A PM_TA0CCR3A GDO1 fromradio CCI3B(internal) CCR3 TA3 DVSS GND DVCC VCC PM_TA0CCR4A CCI4A PM_TA0CCR4A GDO2 fromradio CCI4B(internal) CCR4 TA4 DVSS GND DVCC VCC (1) Ifa differentRFCLK dividersettingisselectedfora radioGDO output,thisdividersettingisalsoused fortheTimer_A INCLK. (2) Onlyon CC430F614x and CC430F514x.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 TA1 TA1 isa 16-bittimer/counter(Timer_A type)withthreecapture/compareregisters.TA1 can supportmultiple capture/compares,PWM outputs,and intervaltiming.TA1 alsohas extensiveinterruptcapabilities.Interrupts may be generatedfromthecounteron overflowconditionsand fromeach ofthecapture/compareregisters. Table15.TA1 SignalConnections DEVICE OUTPUT MODULE OUTPUT SIGNALDEVICE INPUT SIGNAL MODULE INPUT NAME MODULE BLOCK SIGNAL PZ PM_TA1CLK TACLK ACLK (internal) ACLK Timer NA SMCLK (internal) SMCLK RFCLK/192 (1) INCLK PM_TA1CCR0A CCI0A PM_TA1CCR0A RF Async.Output CCI0B RF Async.Input(internal)(internal) CCR0 TA0 DVSS GND DVCC VCC PM_TA1CCR1A CCI1A PM_TA1CCR1A CBOUT (internal) CCI1B CCR1 TA1 DVSS GND DVCC VCC PM_TA1CCR2A CCI2A PM_TA1CCR2A ACLK (internal) CCI2B CCR2 TA2 DVSS GND DVCC VCC (1) Ifa differentRFCLK dividersettingisselectedfora radioGDO output,thisdividersettingisalsoused fortheTimer_A INCLK. Real-TimeClock (RTC_D) The RTC_D module can be used as a general-purpose32-bitcounter(countermode) or as an integratedreal- timeclock(RTC) (calendarmode).Incountermode, theRTC_D alsoincludestwo independent8-bittimersthat can be cascaded toforma 16-bittimer/counter.Both timerscan be readand writtenby software.Calendarmode integratesan internalcalendarwhich compensates formonths withlessthan 31 days and includesleapyear correction.The RTC_D alsosupportsflexiblealarmfunctionsand offset-calibrationhardware. REF VoltageReference(IncludingOutput) The referencemodule (REF) isresponsibleforgenerationofallcriticalreferencevoltagesthatcan be used by thevariousanalogperipheralsinthedevice.These includetheADC10_A, LCD_B, and COMP_B modules. Itcan alsoprovidetheADC referencevoltagestotheVREF+ pin(seethepinschematics). LCD_B (OnlyCC430F614x) The LCD_B drivergeneratesthesegment and common signalsrequiredtodrivea LiquidCrystalDisplay(LCD). The LCD_B controllerhas dedicateddatamemories toholdsegment driveinformation.Common and segment signalsare generatedas definedby the mode. Static,2-mux, 3-mux, and 4-mux LCDs are supported.The module can providea LCD voltageindependentof the supplyvoltagewithitsintegratedcharge pump. Itis possibleto controlthe levelof the LCD voltageand thuscontrastby software.The module alsoprovidesan automaticblinkingcapabilityforindividualsegments. Comparator_B The primaryfunctionof the Comparator_B module isto supportprecisionslopeanalog-to-digitalconversions, batteryvoltagesupervision,and monitoringofexternalanalogsignals. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 27

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com ADC10_A (OnlyCC430F614x and CC430F514x) The ADC10_A module supportsfast,10-bitanalog-to-digitalconversions.The module implementsa 10-bitSAR core,sample selectcontrol,referencegeneratorand a conversionresultbuffer.A window comparatorwitha lowerand upperlimitallowsCPU independentresultmonitoringwiththreewindow comparatorinterruptflags. Embedded EmulationModule (EEM) (S Version) The Embedded EmulationModule (EEM) supportsreal-timein-systemdebugging.The S versionof the EEM implementedon alldeviceshas thefollowingfeatures:

Threehardwaretriggersorbreakpointson memory access
One hardwaretriggerorbreakpointon CPU registerwriteaccess
Up tofourhardwaretriggerscan be combined toformcomplextriggersorbreakpoints
One cyclecounter
Clockcontrolon module level

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PeripheralFileMap Table16.Peripherals OFFSET ADDRESSMODULE NAME BASE ADDRESS RANGE SpecialFunctions(seeTable17) 0100h 000h-01Fh PMM (seeTable18) 0120h 000h-00Fh FlashControl(seeTable19) 0140h 000h-00Fh CRC16 (seeTable20) 0150h 000h-007h RAM Control(seeTable21) 0158h 000h-001h Watchdog (seeTable22) 015Ch 000h-001h UCS (seeTable23) 0160h 000h-01Fh SYS (seeTable24) 0180h 000h-01Fh Shared Reference(seeTable25) 01B0h 000h-001h PortMapping Control(seeTable26) 01C0h 000h-007h PortMapping PortP1 (seeTable27) 01C8h 000h-007h PortMapping PortP2 (seeTable28) 01D0h 000h-007h PortMapping PortP3 (seeTable29) 01D8h 000h-007h PortP1,P2 (seeTable30) 0200h 000h-01Fh PortP3,P4 (seeTable31) (P4 notavailableon CC430F514x and 0220h 000h-01Fh CC430F512x) PortP5 (seeTable32) 0240h 000h-01Fh PortPJ (seeTable33) 0320h 000h-01Fh TA0 (seeTable34) 0340h 000h-03Fh TA1 (seeTable35) 0380h 000h-03Fh RTC_D (seeTable36) 04A0h 000h-01Fh 32-BitHardware Multiplier(seeTable37) 04C0h 000h-02Fh DMA Module Control(seeTable38) 0500h 000h-00Fh DMA Channel0 (seeTable39) 0510h 000h-00Fh DMA Channel1 (seeTable40) 0520h 000h-00Fh DMA Channel2 (seeTable41) 0530h 000h-00Fh USCI_A0 (seeTable42) 05C0h 000h-01Fh USCI_B0 (seeTable43) 05E0h 000h-01Fh ADC10 (seeTable44) 0740h 000h-01Fh(onlyCC430F614x and CC430F514x) Comparator_B(seeTable45) 08C0h 000h-00Fh AES Accelerator(seeTable46) 09C0h 000h-00Fh LCD_B (seeTable47 (onlyCC430F614x) 0A00h 000h-05Fh RadioInterface(seeTable48) 0F00h 000h-03Fh Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 29

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table17.SpecialFunctionRegisters(Base Address: 0100h) REGISTER DESCRIPTION REGISTER OFFSET SFR interruptenable SFRIE1 00h SFR interruptflag SFRIFG1 02h SFR resetpincontrol SFRRPCR 04h Table18.PMM Registers(Base Address: 0120h) REGISTER DESCRIPTION REGISTER OFFSET PMM Control0 PMMCTL0 00h PMM control1 PMMCTL1 02h SVS highsidecontrol SVSMHCTL 04h SVS lowsidecontrol SVSMLCTL 06h PMM interruptflags PMMIFG 0Ch PMM interruptenable PMMIE 0Eh PMM power mode 5 control PM5CTL0 10h Table19.FlashControlRegisters(Base Address: 0140h) REGISTER DESCRIPTION REGISTER OFFSET Flashcontrol1 FCTL1 00h Flashcontrol3 FCTL3 04h Flashcontrol4 FCTL4 06h Table20.CRC16 Registers(Base Address: 0150h) REGISTER DESCRIPTION REGISTER OFFSET CRC datainput CRC16DI 00h CRC datainputreversebyte CRCDIRB 02h CRC initializationand result CRCINIRES 04h CRC resultreversebyte CRCRESR 06h Table21.RAM ControlRegisters(Base Address: 0158h) REGISTER DESCRIPTION REGISTER OFFSET RAM control0 RCCTL0 00h Table22.Watchdog Registers(Base Address: 015Ch) REGISTER DESCRIPTION REGISTER OFFSET Watchdog timercontrol WDTCTL 00h Table23.UCS Registers(Base Address: 0160h) REGISTER DESCRIPTION REGISTER OFFSET UCS control0 UCSCTL0 00h UCS control1 UCSCTL1 02h UCS control2 UCSCTL2 04h UCS control3 UCSCTL3 06h UCS control4 UCSCTL4 08h UCS control5 UCSCTL5 0Ah UCS control6 UCSCTL6 0Ch UCS control7 UCSCTL7 0Eh UCS control8 UCSCTL8 10h

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table24.SYS Registers(Base Address: 0180h) REGISTER DESCRIPTION REGISTER OFFSET System control SYSCTL 00h Bootstraploaderconfigurationarea SYSBSLC 02h JTAG mailboxcontrol SYSJMBC 06h JTAG mailboxinput0 SYSJMBI0 08h JTAG mailboxinput1 SYSJMBI1 0Ah JTAG mailboxoutput0 SYSJMBO0 0Ch JTAG mailboxoutput1 SYSJMBO1 0Eh Bus Errorvectorgenerator SYSBERRIV 18h User NMI vectorgenerator SYSUNIV 1Ah System NMI vectorgenerator SYSSNIV 1Ch Resetvectorgenerator SYSRSTIV 1Eh Table25.Shared ReferenceRegisters(Base Address: 01B0h) REGISTER DESCRIPTION REGISTER OFFSET Shared referencecontrol REFCTL 00h Table26.PortMapping ControlRegisters(Base Address: 01C0h) REGISTER DESCRIPTION REGISTER OFFSET Portmapping key register PMAPKEYID 00h Portmapping controlregister PMAPCTL 02h Table27.PortMapping PortP1 Registers(Base Address: 01C8h) REGISTER DESCRIPTION REGISTER OFFSET PortP1.0mapping register P1MAP0 00h PortP1.1mapping register P1MAP1 01h PortP1.2mapping register P1MAP2 02h PortP1.3mapping register P1MAP3 03h PortP1.4mapping register P1MAP4 04h PortP1.5mapping register P1MAP5 05h PortP1.6mapping register P1MAP6 06h PortP1.7mapping register P1MAP7 07h Table28.PortMapping PortP2 Registers(Base Address: 01D0h) REGISTER DESCRIPTION REGISTER OFFSET PortP2.0mapping register P2MAP0 00h PortP2.1mapping register P2MAP1 01h PortP2.2mapping register P2MAP2 02h PortP2.3mapping register P2MAP3 03h PortP2.4mapping register P2MAP4 04h PortP2.5mapping register P2MAP5 05h PortP2.6mapping register P2MAP6 06h PortP2.7mapping register P2MAP7 07h Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 31

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table29.PortMapping PortP3 Registers(Base Address: 01D8h) REGISTER DESCRIPTION REGISTER OFFSET PortP3.0mapping register P3MAP0 00h PortP3.1mapping register P3MAP1 01h PortP3.2mapping register P3MAP2 02h PortP3.3mapping register P3MAP3 03h PortP3.4mapping register P3MAP4 04h PortP3.5mapping register P3MAP5 05h PortP3.6mapping register P3MAP6 06h PortP3.7mapping register P3MAP7 07h Table30.PortP1,P2 Registers(Base Address: 0200h) REGISTER DESCRIPTION REGISTER OFFSET PortP1 input P1IN 00h PortP1 output P1OUT 02h PortP1 direction P1DIR 04h PortP1 pullup/pulldownenable P1REN 06h PortP1 drivestrength P1DS 08h PortP1 selection P1SEL 0Ah PortP1 interruptvectorword P1IV 0Eh PortP1 interruptedge select P1IES 18h PortP1 interruptenable P1IE 1Ah PortP1 interruptflag P1IFG 1Ch PortP2 input P2IN 01h PortP2 output P2OUT 03h PortP2 direction P2DIR 05h PortP2 pullup/pulldownenable P2REN 07h PortP2 drivestrength P2DS 09h PortP2 selection P2SEL 0Bh PortP2 interruptvectorword P2IV 1Eh PortP2 interruptedge select P2IES 19h PortP2 interruptenable P2IE 1Bh PortP2 interruptflag P2IFG 1Dh Table31.PortP3,P4 Registers(Base Address: 0220h) REGISTER DESCRIPTION REGISTER OFFSET PortP3 input P3IN 00h PortP3 output P3OUT 02h PortP3 direction P3DIR 04h PortP3 pullup/pulldownenable P3REN 06h PortP3 drivestrength P3DS 08h PortP3 selection P3SEL 0Ah PortP4 input P4IN 01h PortP4 output P4OUT 03h PortP4 direction P4DIR 05h PortP4 pullup/pulldownenable P4REN 07h PortP4 drivestrength P4DS 09h PortP4 selection P4SEL 0Bh

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table32.PortP5 Registers(Base Address: 0240h) REGISTER DESCRIPTION REGISTER OFFSET PortP5 input P5IN 00h PortP5 output P5OUT 02h PortP5 direction P5DIR 04h PortP5 pullup/pulldownenable P5REN 06h PortP5 drivestrength P5DS 08h PortP5 selection P5SEL 0Ah Table33.PortJ Registers(Base Address: 0320h) REGISTER DESCRIPTION REGISTER OFFSET PortPJ input PJIN 00h PortPJ output PJOUT 02h PortPJ direction PJDIR 04h PortPJ pullup/pulldownenable PJREN 06h PortPJ drivestrength PJDS 08h Table34.TA0 Registers(Base Address: 0340h) REGISTER DESCRIPTION REGISTER OFFSET TA0 control TA0CTL 00h Capture/comparecontrol0 TA0CCTL0 02h Capture/comparecontrol1 TA0CCTL1 04h Capture/comparecontrol2 TA0CCTL2 06h Capture/comparecontrol3 TA0CCTL3 08h Capture/comparecontrol4 TA0CCTL4 0Ah TA0 counterregister TA0R 10h Capture/compareregister0 TA0CCR0 12h Capture/compareregister1 TA0CCR1 14h Capture/compareregister2 TA0CCR2 16h Capture/compareregister3 TA0CCR3 18h Capture/compareregister4 TA0CCR4 1Ah TA0 expansionregister0 TA0EX0 20h TA0 interruptvector TA0IV 2Eh Table35.TA1 Registers(Base Address: 0380h) REGISTER DESCRIPTION REGISTER OFFSET TA1 control TA1CTL 00h Capture/comparecontrol0 TA1CCTL0 02h Capture/comparecontrol1 TA1CCTL1 04h Capture/comparecontrol2 TA1CCTL2 06h TA1 counterregister TA1R 10h Capture/compareregister0 TA1CCR0 12h Capture/compareregister1 TA1CCR1 14h Capture/compareregister2 TA1CCR2 16h TA1 expansionregister0 TA1EX0 20h TA1 interruptvector TA1IV 2Eh Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 33

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table36.Real Time Clock Registers(Base Address: 04A0h) REGISTER DESCRIPTION REGISTER OFFSET RTC control0 RTCCTL0 00h RTC control1 RTCCTL1 01h RTC control2 RTCCTL2 02h RTC control3 RTCCTL3 03h RTC prescaler0 control RTCPS0CTL 08h RTC prescaler1 control RTCPS1CTL 0Ah RTC prescaler0 RTCPS0 0Ch RTC prescaler1 RTCPS1 0Dh RTC interruptvectorword RTCIV 0Eh RTC seconds/counterregister1 RTCSEC/RTCNT1 10h RTC minutes/counterregister2 RTCMIN/RTCNT2 11h RTC hours/counterregister3 RTCHOUR/RTCNT3 12h RTC day ofweek/counterregister4 RTCDOW/RTCNT4 13h RTC days RTCDAY 14h RTC month RTCMON 15h RTC yearlow RTCYEARL 16h RTC yearhigh RTCYEARH 17h RTC alarmminutes RTCAMIN 18h RTC alarmhours RTCAHOUR 19h RTC alarmday ofweek RTCADOW 1Ah RTC alarmdays RTCADAY 1Bh Table37.32-BitHardware MultiplierRegisters(Base Address: 04C0h) REGISTER DESCRIPTION REGISTER OFFSET 16-bitoperand1 -multiply MPY 00h 16-bitoperand1 -signedmultiply MPYS 02h 16-bitoperand1 -multiplyaccumulate MAC 04h 16-bitoperand1 -signedmultiplyaccumulate MACS 06h 16-bitoperand2 OP2 08h 16 × 16 resultlowword RESLO 0Ah 16 × 16 resulthighword RESHI 0Ch 16 × 16 sum extensionregister SUMEXT 0Eh 32-bitoperand1 -multiplylowword MPY32L 10h 32-bitoperand1 -multiplyhighword MPY32H 12h 32-bitoperand1 -signedmultiplylowword MPYS32L 14h 32-bitoperand1 -signedmultiplyhighword MPYS32H 16h 32-bitoperand1 -multiplyaccumulatelowword MAC32L 18h 32-bitoperand1 -multiplyaccumulatehighword MAC32H 1Ah 32-bitoperand1 -signedmultiplyaccumulatelowword MACS32L 1Ch 32-bitoperand1 -signedmultiplyaccumulatehighword MACS32H 1Eh 32-bitoperand2 -lowword OP2L 20h 32-bitoperand2 -highword OP2H 22h 32 × 32 result0 -leastsignificantword RES0 24h 32 × 32 result1 RES1 26h 32 × 32 result2 RES2 28h 32 × 32 result3 -most significantword RES3 2Ah MPY32 controlregister0 MPY32CTL0 2Ch

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table38.DMA Module ControlRegisters(Base Address: 0500h) REGISTER DESCRIPTION REGISTER OFFSET DMA module control0 DMACTL0 00h DMA module control1 DMACTL1 02h DMA module control2 DMACTL2 04h DMA module control3 DMACTL3 06h DMA module control4 DMACTL4 08h DMA interruptvector DMAIV 0Ah Table39.DMA Channel 0 Registers(Base Address: 0510h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel0 control DMA0CTL 00h DMA channel0 sourceaddresslow DMA0SAL 02h DMA channel0 sourceaddresshigh DMA0SAH 04h DMA channel0 destinationaddresslow DMA0DAL 06h DMA channel0 destinationaddresshigh DMA0DAH 08h DMA channel0 transfersize DMA0SZ 0Ah Table40.DMA Channel 1 Registers(Base Address: 0520h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel1 control DMA1CTL 00h DMA channel1 sourceaddresslow DMA1SAL 02h DMA channel1 sourceaddresshigh DMA1SAH 04h DMA channel1 destinationaddresslow DMA1DAL 06h DMA channel1 destinationaddresshigh DMA1DAH 08h DMA channel1 transfersize DMA1SZ 0Ah Table41.DMA Channel 2 Registers(Base Address: 0530h) REGISTER DESCRIPTION REGISTER OFFSET DMA channel2 control DMA2CTL 00h DMA channel2 sourceaddresslow DMA2SAL 02h DMA channel2 sourceaddresshigh DMA2SAH 04h DMA channel2 destinationaddresslow DMA2DAL 06h DMA channel2 destinationaddresshigh DMA2DAH 08h DMA channel2 transfersize DMA2SZ 0Ah Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 35

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table42.USCI_A0 Registers(Base Address: 05C0h) REGISTER DESCRIPTION REGISTER OFFSET USCI control1 UCA0CTL1 00h USCI control0 UCA0CTL0 01h USCI baud rate0 UCA0BR0 06h USCI baud rate1 UCA0BR1 07h USCI modulationcontrol UCA0MCTL 08h USCI status UCA0STAT 0Ah USCI receivebuffer UCA0RXBUF 0Ch USCI transmitbuffer UCA0TXBUF 0Eh USCI LIN control UCA0ABCTL 10h USCI IrDAtransmitcontrol UCA0IRTCTL 12h USCI IrDAreceivecontrol UCA0IRRCTL 13h USCI interruptenable UCA0IE 1Ch USCI interruptflags UCA0IFG 1Dh USCI interruptvectorword UCA0IV 1Eh Table43.USCI_B0 Registers(Base Address: 05E0h) REGISTER DESCRIPTION REGISTER OFFSET USCI synchronouscontrol1 UCB0CTL1 00h USCI synchronouscontrol0 UCB0CTL0 01h USCI synchronousbitrate0 UCB0BR0 06h USCI synchronousbitrate1 UCB0BR1 07h USCI synchronousstatus UCB0STAT 0Ah USCI synchronousreceivebuffer UCB0RXBUF 0Ch USCI synchronoustransmitbuffer UCB0TXBUF 0Eh USCI I2C own address UCB0I2COA 10h USCI I2C slaveaddress UCB0I2CSA 12h USCI interruptenable UCB0IE 1Ch USCI interruptflags UCB0IFG 1Dh USCI interruptvectorword UCB0IV 1Eh Table44.ADC10_A Registers(Base Address: 0740h) REGISTER DESCRIPTION REGISTER OFFSET ADC10_A Controlregister0 ADC10CTL0 00h ADC10_A Controlregister1 ADC10CTL1 02h ADC10_A Controlregister2 ADC10CTL2 04h ADC10_A Window ComparatorLow Threshold ADC10LO 06h ADC10_A Window ComparatorHighThreshold ADC10HI 08h ADC10_A Memory ControlRegister0 ADC10MCTL0 0Ah ADC10_A ConversionMemory Register ADC10MEM0 12h ADC10_A InterruptEnable ADC10IE 1Ah ADC10_A InterruptFlags ADC10IGH 1Ch ADC10_A InterruptVectorWord ADC10IV 1Eh

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table45.Comparator_B Registers(Base Address: 08C0h) REGISTER DESCRIPTION REGISTER OFFSET Comp_B controlregister0 CBCTL0 00h Comp_B controlregister1 CBCTL1 02h Comp_B controlregister2 CBCTL2 04h Comp_B controlregister3 CBCTL3 06h Comp_B interruptregister CBINT 0Ch Comp_B interruptvectorword CBIV 0Eh Table46.AES AcceleratorRegisters(Base Address: 09C0h) REGISTER DESCRIPTION REGISTER OFFSET AES acceleratorcontrolregister0 AESACTL0 00h Reserved 02h AES acceleratorstatusregister AESASTAT 04h AES acceleratorkey register AESAKEY 06h AES acceleratordatainregister AESADIN 008h AES acceleratordataoutregister AESADOUT 00Ah Table47.LCD_B Registers(Base Address: 0A00h) REGISTER DESCRIPTION REGISTER OFFSET LCD_B controlregister0 LCDBCTL0 000h LCD_B controlregister1 LCDBCTL1 002h LCD_B blinkingcontrolregister LCDBBLKCTL 004h LCD_B memory controlregister LCDBMEMCTL 006h LCD_B voltagecontrolregister LCDBVCTL 008h LCD_B portcontrolregister0 LCDBPCTL0 00Ah LCD_B portcontrolregister1 LCDBPCTL1 00Ch LCD_B chargepump controlregister LCDBCTL0 012h LCD_B interruptvectorword LCDBIV 01Eh LCD_B memory 1 LCDM1 020h LCD_B memory 2 LCDM2 021h ... LCD_B memory 14 LCDM14 02Dh LCD_B blinkingmemory 1 LCDBM1 040h LCD_B blinkingmemory 2 LCDBM2 041h ... LCD_B blinkingmemory 14 LCDBM14 04Dh Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 37

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table48.Radio InterfaceRegisters(Base Address: 0F00h) REGISTER DESCRIPTION REGISTER OFFSET Radiointerfacecontrolregister0 RF1AIFCTL0 00h Radiointerfacecontrolregister1 RF1AIFCTL1 02h Radiointerfaceerrorflagregister RF1AIFERR 06h Radiointerfaceerrorvectorword RF1AIFERRV 0Ch Radiointerfaceinterruptvectorword RF1AIFIV 0Eh Radioinstructionword register RF1AINSTRW 10h Radioinstructionword register,1-byteauto-read RF1AINSTR1W 12h Radioinstructionword register,2-byteauto-read RF1AINSTR2W 14h Radiodatainregister RF1ADINW 16h Radiostatusword register RF1ASTATW 20h Radiostatusword register,1-byteauto-read RF1ASTAT1W 22h Radiostatusword register,2-byteauto-read RF1AISTAT2W 24h Radiodataoutregister RF1ADOUTW 28h Radiodataoutregister,1-byteauto-read RF1ADOUT1W 2Ah Radiodataoutregister,2-byteauto-read RF1ADOUT2W 2Ch Radiocoresignalinputregister RF1AIN 30h Radiocoreinterruptflagregister RF1AIFG 32h Radiocoreinterruptedge selectregister RF1AIES 34h Radiocoreinterruptenableregister RF1AIE 36h Radiocoreinterruptvectorword RF1AIV 38h

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 AbsoluteMaximum Ratings(1) overoperatingfree-airtemperaturerange(unlessotherwisenoted) VoltageappliedatDVCC and AVCC pinstoVSS -0.3V to4.1V -0.3V to(VCC + 0.3V),Voltageappliedtoany pin(excludingVCORE, RF_P, RF_N, and R_BIAS)(2) 4.1V Maximum VoltageappliedtoVCORE, RF_P, RF_N, and R_BIAS (2) -0.3V to2.0V InputRF levelatpinsRF_P and RF_N 10 dBm Diodecurrentatany deviceterminal ±2 mA Storagetemperaturerange(3),Tstg -55°C to150°C Maximum junctiontemperature,TJ 95°C (1) Stressesbeyond thoselistedunder"absolutemaximum ratings"may cause permanentdamage tothedevice.These arestressratings only,and functionaloperationofthedeviceattheseorany otherconditionsbeyond thoseindicatedunder"recommended operating conditions"isnotimplied.Exposuretoabsolute-maximum-ratedconditionsforextendedperiodsmay affectdevicereliability. (2) AllvoltagesreferencedtoVSS . (3) Highertemperaturemay be appliedduringboardsolderingaccordingtothecurrentJEDEC J-STD-020specificationwithpeak reflow temperaturesnothigherthanclassifiedon thedevicelabelon theshippingboxes orreels. Thermal Packaging CharacteristicsCC430F51xx Low-K board 48 QFN (RGZ) 98°C/W θJA Junction-to-ambientthermalresistance,stillair High-Kboard 48 QFN (RGZ) 28°C/W Thermal Packaging CharacteristicsCC430F61xx Low-K board 64 QFN (RGC) 83°C/W θJA Junction-to-ambientthermalresistance,stillair High-Kboard 64 QFN (RGC) 26°C/W Recommended OperatingConditions TypicalvaluesarespecifiedatVCC = 3.3V and TA = 25°C (unlessotherwisenoted) MIN NOM MAX UNIT SupplyvoltagerangeappliedatallDVCC and AVCC PMMCOREVx = 0 1.8 3.6 Vpins(1)(2)duringprogramexecutionand flash (defaultafterPOR)VCC programmingwithPMM defaultsettings.Radioisnot PMMCOREVx = 1 2.0 3.6 VoperationalwithPMMCOREVx = 0,1.(3) SupplyvoltagerangeappliedatallDVCC and AVCC PMMCOREVx = 2 2.2 3.6 V VCC pins(1)(2)duringprogramexecution,flashprogramming PMMCOREVx = 3 2.4 3.6 Vand radiooperationwithPMM defaultsettings.(3) SupplyvoltagerangeappliedatallDVCC and AVCC pins(1)(2)duringprogramexecution,flashprogramming PMMCOREVx = 2, VCC and radiooperationwithPMMCOREVx = 2,high-side SVSHRVLx = SVSHRRRLx = 1 2.0 3.6 V SVS levellowered(SVSHRVLx = SVSHRRRLx = 1)or orSVSHE = 0 high-sideSVS disabled(SVSHE = 0).(4)(3) Supplyvoltageappliedattheexposed dieattachVSSVSS 0 Vand AVSS pin TA Operatingfree-airtemperature -40 85 °C TJ Operatingjunctiontemperature -40 85 °C C VCORE Recommended capacitoratVCORE 470 nF fSYSTEM ≤ 16 MHz,C VCORE Reduced capacitoratVCORE 100 nFPMMCOREVx ≤ 2,VCC ≥ 2.2V C DVCC Recommended capacitoratDVCC 4.7 µF (1) Itisrecommended topower AVCC and DVCC fromthesame source.A maximum differenceof0.3V between AVCC and DVCC can be toleratedduringpower up and operation. (2) The minimum supplyvoltageisdefinedby thesupervisorSVS levelswhen itisenabled.See thePMM, SVS HighSidethreshold parametersfortheexactvaluesand furtherdetails. (3) Modules may have a differentsupplyvoltagerangespecification.See thespecificationoftherespectivemodule inthisdatasheet. (4) Loweringthehigh-sideSVS levelordisablingthehigh-sideSVS mightcause theLDO tooperateoutofregulationbutthecorevoltage stillstayswithinitslimitsand isstillsupervisedby thelow-sideSVS toensurereliableoperation. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 39

2.01.8 System Frequency - MHz Supply Voltage - V The numbers within the fields denote the supported PMMCOREVx settings. 2.2 2.4 3.6 1, 2, 31, 21 2, 3 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Recommended OperatingConditions(continued) TypicalvaluesarespecifiedatVCC = 3.3V and TA = 25°C (unlessotherwisenoted) MIN NOM MAX UNIT PMMCOREVx = 0 0 8 MHz(defaultcondition) PMMCOREVx = 1 0 12 MHzfSYSTEM Processor(MCLK) frequency(5)(seeFigure2) PMMCOREVx = 2 0 16 MHz PMMCOREVx = 3 0 20 MHz PINT Internalpower dissipation VCC × IDVCC W (VCC -VIOH)× IIOH +PIO I/Opower dissipationofI/Opinspowered by DVCC WVIOL × IIOL PMAX Maximum allowedpower dissipation,PMAX > PIO + PINT (TJ -TA)/θJA W (5) Modules may have a differentmaximum inputclockspecification.See thespecificationoftherespectivemodule inthisdatasheet. Figure2. Maximum System Frequency

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IAM - Active Mode Supply Current - mA VCC = 3.0 V PM M VCOR E x=2 PM M VCOR E x=0 PM M VCOR E x=1 PM M VCOR E x=3 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 ElectricalCharacteristics ActiveMode Supply CurrentIntoVCC ExcludingExternalCurrent overrecommended operatingfree-airtemperature(unlessotherwisenoted)(1)(2)(3) FREQUENCY (fDCO = fMCLK = fSMCLK ) EXECUTIONPARAMETER VCC PMMCOREVx 1 MHz 8 MHz 12 MHz 16 MHz 20 MHz UNITMEMORY TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX 0 0.23 0.26 1.35 1.60 IAM, Flash(4) Flash 3.0V mA 0 0.18 0.20 0.95 1.10 IAM, RAM (5) RAM 3.0V mA (1) Allinputsaretiedto0 V ortoVCC .Outputsdo notsourceorsinkany current. (2) The currentsarecharacterizedwitha MicroCrystalMS1V-T1K crystalwitha loadcapacitanceof12.5pF.The internaland externalload capacitancearechosen tocloselymatch therequired12.5pF. (3) Characterizedwithprogramexecutingtypicaldataprocessing. fACLK = 32786 Hz,fDCO = fMCLK = fSMCLK atspecifiedfrequency. XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0. (4) Activemode supplycurrentwhen programexecutesinflashata nominalsupplyvoltageof3.0V. (5) Activemode supplycurrentwhen programexecutesinRAM ata nominalsupplyvoltageof3.0V. TypicalCharacteristics-ActiveMode Supply Currents ActiveMode Supply Current vs MCLK Frequency Figure3. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 41

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Low-Power Mode Supply Currents(IntoVCC )ExcludingExternalCurrent overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1)(2) Temperature (TA ) PARAMETER VCC PMMCOREVx -40°C 25°C 60°C 85°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX 2.2V 0 80 100 80 100 80 100 80 100 ILPM0,1MHz Low-power mode 0(3)(4) µA 3.0V 3 90 110 90 110 90 110 90 110 ILPM2 Low-power mode 2(5)(4) µA 2 2.0 2.2 3.4 5.1 Low-power mode 3, 1 1.0 1.2 2.3 3.9 ILPM3,VLO,WDT VLO mode, onlyWDT 3.0V µA 1 0.9 1.1 2.2 3.8 ILPM4 Low-power mode 4(8)(4) 3.0V µA 2 1.0 1.2 2.4 4.1 ILPM3.5 Low-power mode 3.5(9) ILPM4.5 Low-power mode 4.5(10) (1) Allinputsaretiedto0 V ortoVCC .Outputsdo notsourceorsinkany current. (2) The currentsarecharacterizedwitha MicroCrystalMS1V-T1K crystalwitha loadcapacitanceof12.5pF.The internaland externalload capacitancearechosen tocloselymatch therequired12.5pF. (3) Currentforwatchdogtimerclockedby SMCLK included.ACLK = lowfrequencycrystaloperation(XTS = 0,XT1DRIVEx = 0). CPUOFF = 1,SCG0 = 0,SCG1 = 0,OSCOFF = 0 (LPM0);fACLK = 32768 Hz,fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz (4) Currentforbrownoutand high-sidesupervisor(SVSH )normalmode included.Low-sidesupervisor(SVSL)and low-sidemonitor(SVM L) disabled.High-sidemonitordisabled(SVM H ).RAM retentionenabled. (5) Currentforwatchdogtimerclockedby ACLK and RTC clockedby LFXT1 (32768Hz) included.ACLK = lowfrequencycrystaloperation (XTS = 0,XT1DRIVEx = 0). CPUOFF = 1,SCG0 = 0,SCG1 = 1,OSCOFF = 0 (LPM2);fACLK = 32768 Hz,fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting= 1 MHz operation,DCO biasgeneratorenabled. (6) Currentforwatchdogtimerclockedby ACLK and RTC clockedby LFXT1 (32768Hz) included.ACLK = lowfrequencycrystaloperation (XTS = 0,XT1DRIVEx = 0). CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 0 (LPM3);fACLK = 32768 Hz,fMCLK = fSMCLK = fDCO = 0 MHz (7) Currentforwatchdogtimerclockedby VLO included. CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 0 (LPM3);fACLK = fVLO ,fMCLK = fSMCLK = fDCO = 0 MHz (8) CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 1 (LPM4);fDCO = fACLK = fMCLK = fSMCLK = 0 MHz (9) Internalregulatordisabled.No dataretentionexceptBackup RAM. CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 1,PMMREGOFF = 1 (LPMx.5),RTC active(Calendarmode) withRTCHOLD = 0 (LPM3.5)and fXT1 = 32768 Hz,fDCO = fACLK = fMCLK = fSMCLK = 0 MHz. (10)Internalregulatordisabled.No dataretentionexceptbBackup RAM. CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 1,PMMREGOFF = 1 (LPMx.5),RTC disabledwithRTCHOLD = 1 (LPM4.5),fDCO = fACLK = fMCLK = fSMCLK = 0 MHz.

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0.5 1.5 -40 -20 0 20 40 60 80 ILPM3.5 - LPM3.5 Supply Current - uA TA - Free-Air Temperature - °C VCC = 3.0 V 0.5 1.5 -40 -20 0 20 40 60 80 ILPM4.5 - LPM4.5 Supply Current - uA TA - Free-Air Temperature - ˚C VCC = 3.0 V -40 -20 0 20 40 60 80 TA - Fre e -Air Te m pe rature - °C ILPM3,XT1LF - LPM3 Supply Current - uA VCC = 3.0 V PM M COR E Vx = 3 PM M COR E Vx = 0 -40 -20 0 20 40 60 80 TA - Fre e -Air Te m pe rature - °C ILPM4 - LPM4 Supply Current - uA VDD = 3.0 V PM M COR E Vx = 3 PM M COR E Vx = 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 TypicalCharacteristics-Low-Power Mode Supply Currents LPM3 Supply Current LPM4 Supply Current vs vs Temperature Temperature Figure4. Figure5. LPM3.5 Supply Current LPM4.5 Supply Current vs vs Temperature Temperature Figure6. Figure7. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 43

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Low-Power Mode With LCD Supply Currents(IntoVCC )ExcludingExternalCurrent overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1)(2) Temperature (TA ) PARAMETER VCC PMMCOREVx -40°C 25°C 60°C 85°C UNIT TYP MAX TYP MAX TYP MAX TYP MAX ILPM3 (LPM3) current,LCD 4- 1 3.2 3.4 4.5 6.2 LCD, mux mode, internal 3.0V µA disabled(3)(4) 0 4.0 2.2V 1 4.1 Low-power mode 3 2 4.2(LPM3) current,LCD 4-ILPM3 mux mode, internal 0 4.2 µALCD,CP biasing,chargepump 1 4.3enabled(3)(5) 3.0V 2 4.5 3 4.5 (1) Allinputsaretiedto0 V ortoVCC .Outputsdo notsourceorsinkany current. (2) The currentsarecharacterizedwitha MicroCrystalMS1V-T1K crystalwitha loadcapacitanceof12.5pF.The internaland externalload capacitancearechosen tocloselymatch therequired12.5pF. (3) Currentforwatchdogtimerand RTC clockedby ACLK included.ACLK = lowfrequencycrystaloperation(XTS = 0,XT1DRIVEx = 0). CPUOFF = 1,SCG0 = 1,SCG1 = 1,OSCOFF = 0 (LPM3);fACLK = 32768 Hz,fMCLK = fSMCLK = fDCO = 0 MHz Currentforbrownout,high-sidesupervisor(SVSH )normalmode included.Low-sidesupervisorand monitorsdisabled(SVSL,SVM L). Highsidemonitordisabled(SVM H ).RAM retentionenabled. (4) LCDMx = 11 (4-muxmode),LCDREXT=0, LCDEXTBIAS=0 (internalbiasing),LCD2B=0 (1/3bias),LCDCPEN=0 (chargepump disabled),LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4= 256 Hz) (5) LCDMx = 11 (4-muxmode),LCDREXT=0, LCDEXTBIAS=0 (internalbiasing),LCD2B=0 (1/3bias),LCDCPEN = 1 (chargepump enabled),VLCDx = 1000 (VLCD = 3 V typ.),LCDSSEL=0, LCDPREx=101, LCDDIVx=00011 (fLCD = 32768 Hz/32/4= 256 Hz)

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 DigitalInputs overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.8V 0.80 1.40 VIT+ Positive-goinginputthresholdvoltage V 3 V 1.50 2.10 1.8V 0.45 1.00 VIT- Negative-goinginputthresholdvoltage V 3 V 0.75 1.65 1.8V 0.3 0.8 Vhys Inputvoltagehysteresis(VIT+ -VIT-) V 3 V 0.4 1.0 Forpullup:VIN = VSS ,R Pull Pullup/pulldownresistor 20 35 50 kΩForpulldown:VIN = VCC C I Inputcapacitance VIN = VSS orVCC 5 pF Ilkg(Px.x) High-impedanceleakagecurrent (1)(2) ±50 nA PortswithinterruptcapabilityExternalinterrupttiming(externaltriggerpulset(int) (seeblockdiagramand 1.8V,3 V 20 nsdurationtosetinterruptflag)(3) terminalfunctiondescriptions) (1) The leakagecurrentismeasured withVSS orVCC appliedtothecorrespondingpin(s),unlessotherwisenoted. (2) The leakageofthedigitalportpinsismeasured individually.The portpinisselectedforinputand thepullup/pulldownresistoris disabled. (3) An externalsignalsetstheinterruptflageverytimetheminimum interruptpulsedurationt(int)ismet.Itmay be setby triggersignals shorterthant(int). Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 45

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com DigitalOutputs overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN MAX UNIT High-leveloutputvoltage,VOH I(OHmax) = -1mA, PxDS.y = 0(2) 1.8V VCC -0.25 VCC VReduced DriveStrength(1) High-leveloutputvoltage,VOH I(OHmax) = -3mA, PxDS.y = 0(3) 1.8V VCC -0.60 VCC VReduced DriveStrength(1) High-leveloutputvoltage,VOH I(OHmax) = -2mA, PxDS.y = 0(2) 3.0V VCC -0.25 VCC VReduced DriveStrength(1) High-leveloutputvoltage,VOH I(OHmax) = -6mA, PxDS.y = 0(3) 3.0V VCC -0.60 VCC VReduced DriveStrength(1) Low-leveloutputvoltage,VOL I(OLmax) = 1 mA, PxDS.y = 0(2) 1.8V VSS VSS + 0.25 VReduced DriveStrength(1) Low-leveloutputvoltage,VOL I(OLmax) = 3 mA, PxDS.y = 0(3) 1.8V VSS VSS + 0.60 VReduced DriveStrength(1) Low-leveloutputvoltage,VOL I(OLmax) = 2 mA, PxDS.y = 0(2) 3.0V VSS VSS + 0.25 VReduced DriveStrength(1) Low-leveloutputvoltage,VOL I(OLmax) = 6 mA, PxDS.y = 0(3) 3.0V VSS VSS + 0.60 VReduced DriveStrength(1) High-leveloutputvoltage,VOH I(OHmax) = -3mA, PxDS.y = 1(2) 1.8V VCC -0.25 VCC VFullDriveStrength High-leveloutputvoltage,VOH I(OHmax) = -10mA, PxDS.y = 1(3) 1.8V VCC -0.60 VCC VFullDriveStrength High-leveloutputvoltage,VOH I(OHmax) = -5mA, PxDS.y = 1(2) 3 V VCC -0.25 VCC VFullDriveStrength High-leveloutputvoltage,VOH I(OHmax) = -15mA, PxDS.y = 1(3) 3 V VCC -0.60 VCC VFullDriveStrength Low-leveloutputvoltage,VOL I(OLmax) = 3 mA, PxDS.y = 1(2) 1.8V VSS VSS + 0.25 VFullDriveStrength Low-leveloutputvoltage,VOL I(OLmax) = 10 mA, PxDS.y = 1(3) 1.8V VSS VSS + 0.60 VFullDriveStrength Low-leveloutputvoltage,VOL I(OLmax) = 5 mA, PxDS.y = 1(2) 3 V VSS VSS + 0.25 VFullDriveStrength Low-leveloutputvoltage,VOL I(OLmax) = 15 mA, PxDS.y = 1(3) 3 V VSS VSS + 0.60 VFullDriveStrength VCC = 1.8V, 16PMMCOREVx = 0PortoutputfrequencyfPx.y C L = 20 pF,R L (4)(5) MHz(withload) VCC = 3 V, 25PMMCOREVx = 2 VCC = 1.8V, 16PMMCOREVx = 0 fPort_CLK Clockoutputfrequency C L = 20 pF (5) MHz VCC = 3 V, 25PMMCOREVx = 2 (1) Selectingreduceddrivestrengthmay reduceEMI. (2) The maximum totalcurrent,I(OHmax) and I(OLmax),foralloutputscombined shouldnotexceed ±48 mA toholdthemaximum voltagedrop specified. (3) The maximum totalcurrent,I(OHmax) and I(OLmax),foralloutputscombined shouldnotexceed ±100 mA toholdthemaximum voltage dropspecified. (4) A resistivedividerwith2 × R1 between VCC and VSS isused as load.The outputisconnectedtothecentertapofthedivider.Forfull drivestrength,R1 = 550 Ω.Forreduceddrivestrength,R1 = 1.6kΩ.C L = 20 pF isconnectedtotheoutputtoVSS . (5) The outputvoltagereachesatleast10% and 90% VCC atthespecifiedtogglefrequency.

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-25 -20 -15 -10 0 0.5 1 1.5 2 2.5 3 3.5 VOH - H igh-Le ve l Output Voltage - V IOH - Typical High-Level Output Current - mA VCC = 3.0 V VCC = 3.0 V P4.3 TA = 25°C TA = 85°C 0 0.5 1 1.5 2 VOH - H igh-Le ve l Output Voltage - V IOH - Typical High-Level Output Current - mA VDD = 5.5 VVDD = 5.5 V VCC = 1.8 V P4.3 TA = 25°C TA = 85°C 0 0.5 1 1.5 2 2.5 3 3.5 VOL - Low -Le ve l Output Voltage - V IOL - Typical Low-Level Output Current - mA VCC = 3.0 V P4.3 TA = 25/c176C TA = 85°C 0 0.5 1 1.5 2 VOL - Low -Le ve l Output Voltage - V IOL - Typical Low-Level Output Current - mA VDD = 5.5 V VCC = 1.8 V P4.3 TA = 25°C TA = 85°C ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 TypicalCharacteristics-Outputs,Reduced DriveStrength(PxDS.y = 0) TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE Figure8. Figure9. TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Figure10. Figure11. TypicalCharacteristics-Outputs,FullDriveStrength(PxDS.y = 1) Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 47

-60 -50 -40 -30 -20 -10 0 0.5 1 1.5 2 2.5 3 3.5 VOH - H igh-Le ve l Output Voltage - V IOH - Typical High-Level Output Current - mA VCC = 3.0 V VCC = 3.0 V P4.3 TA = 25°C TA = 85°C -25 -20 -15 -10 0 0.5 1 1.5 2 VOH - H igh-Le ve l Output Voltage - V IOH - Typical High-Level Output Current - mA VDD = 5.5 VVDD = 5.5 V VCC = 1.8 V P4.3 TA = 25°C TA = 85°C 0 0.5 1 1.5 2 2.5 3 3.5 VOL - Low -Le ve l Output Voltage - V IOL - Typical Low-Level Output Current - mA VCC = 3.0 V P4.3 TA = 25°C TA = 85°C 0 0.5 1 1.5 2 VOL - Low -Le ve l Output Voltage - V IOL - Typical Low-Level Output Current - mA VDD = 5.5 V VCC = 1.8 V P4.3 TA = 25°C TA = 85°C ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT vs vs LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE Figure12. Figure13. TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT vs vs HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE Figure14. Figure15.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 CrystalOscillator,XT1, Low-Frequency Mode (1) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fOSC = 32768 Hz,XTS = 0, 0.075XT1BYPASS = 0,XT1DRIVEx = 1,TA = 25°C DifferentialXT1 oscillatorcrystal fOSC = 32768 Hz,XTS = 0,ΔIDVCC.LF currentconsumptionfromlowest 3 V 0.170 µAXT1BYPASS = 0,XT1DRIVEx = 2,TA = 25°Cdrivesetting,LF mode fOSC = 32768 Hz,XTS = 0, 0.290XT1BYPASS = 0,XT1DRIVEx = 3,TA = 25°C XT1 oscillatorcrystalfrequency,fXT1,LF0 XTS = 0,XT1BYPASS = 0 32768 HzLF mode XT1 oscillatorlogic-levelsquare-fXT1,LF,SW XTS = 0,XT1BYPASS = 1(2)(3) 10 32.768 50 kHzwave inputfrequency,LF mode XTS = 0,XT1BYPASS = 0,XT1DRIVEx = 0, 210fXT1,LF = 32768 Hz,C L,eff= 6 pFOscillationallowanceforOA LF kΩLF crystals(4) XTS = 0,XT1BYPASS = 0,XT1DRIVEx = 1, 300fXT1,LF = 32768 Hz,C L,eff= 12 pF XTS = 0,XCAPx = 0(6) 2 XTS = 0,XCAPx = 1 5.5IntegratedeffectiveloadC L,eff pFcapacitance,LF mode (5) XTS = 0,XCAPx = 2 8.5 XTS = 0,XCAPx = 3 12.0 XTS = 0,Measured atACLK,Dutycycle,LF mode 30 70 %fXT1,LF = 32768 Hz Oscillatorfaultfrequency,fFault,LF XTS = 0(8) 10 10000 HzLF mode (7) fOSC = 32768 Hz,XTS = 0, XT1BYPASS = 0,XT1DRIVEx = 0, 1000 TA = 25°C, C L,eff= 6 pF tSTART,LF Startuptime,LF mode 3 V ms fOSC = 32768 Hz,XTS = 0, XT1BYPASS = 0,XT1DRIVEx = 3, 500 TA = 25°C, C L,eff= 12 pF (1) To improveEMI on theXT1 oscillator,thefollowingguidelinesshouldbe observed. (a) Keep thetracebetween thedeviceand thecrystalas shortas possible. (b) Designa good groundplanearoundtheoscillatorpins. (c)PreventcrosstalkfromotherclockordatalinesintooscillatorpinsXIN and XOUT. (d) AvoidrunningPCB tracesunderneathoradjacenttotheXIN and XOUT pins. (e) Use assemblymaterialsand praxistoavoidany parasiticloadon theoscillatorXIN and XOUT pins. (f)Ifconformalcoatingisused,ensurethatitdoes notinducecapacitiveorresistiveleakagebetween theoscillatorpins. (2) When XT1BYPASS isset,XT1 circuitsareautomaticallypowered down. Inputsignalisa digitalsquarewave withparametricsdefinedin theSchmitt-triggerInputssectionofthisdatasheet. (3) Maximum frequencyofoperationoftheentiredevicecannotbe exceeded. (4) Oscillationallowanceisbased on a safetyfactorof5 forrecommended crystals.The oscillationallowanceisa functionofthe XT1DRIVEx settingsand theeffectiveload.Ingeneral,comparableoscillatorallowancecan be achievedbased on thefollowing guidelines,butshouldbe evaluatedbased on theactualcrystalselectedfortheapplication: (a) ForXT1DRIVEx = 0,C L,eff≤ 6 pF (b) ForXT1DRIVEx = 1,6 pF ≤ C L,eff≤ 9 pF (c)ForXT1DRIVEx = 2,6 pF ≤ C L,eff≤ 10 pF (d) ForXT1DRIVEx = 3,C L,eff≥ 6 pF (5) Includesparasiticbond and package capacitance(approximately2 pF perpin). SincethePCB adds additionalcapacitance,itisrecommended toverifythecorrectloadby measuringtheACLK frequency.Fora correctsetup,theeffectiveloadcapacitanceshouldalwaysmatch thespecificationoftheused crystal. (6) Requiresexternalcapacitorsatbothterminals.Valuesarespecifiedby crystalmanufacturers. (7) FrequenciesbelowtheMIN specificationsetthefaultflag.Frequenciesabove theMAX specificationdo notsetthefaultflag. Frequenciesinbetween mightsettheflag. (8) Measured withlogic-levelinputfrequencybutalsoappliestooperationwithcrystals. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 49

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com InternalVery-Low-Power Low-Frequency Oscillator(VLO) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT fVLO VLO frequency Measured atACLK 1.8V to3.6V 6 9.4 14 kHz dfVLO /dT VLO frequencytemperaturedrift Measured atACLK (1) 1.8V to3.6V 0.5 %/°C dfVLO /dVCC VLO frequencysupplyvoltagedrift Measured atACLK (2) 1.8V to3.6V 4 %/V Dutycycle Measured atACLK 1.8V to3.6V 40 50 60 % (1) Calculatedusingthebox method:(MAX(-40to85°C) -MIN(-40to85°C))/MIN(-40to85°C) /(85°C -(-40°C)) InternalReference,Low-Frequency Oscillator(REFO) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT IREFO REFO oscillatorcurrentconsumption TA = 25°C 1.8V to3.6V 3 µA fREFO REFO frequencycalibrated Measured atACLK 1.8V to3.6V 32768 Hz REFO absolutetolerancecalibrated Fulltemperaturerange 1.8V to3.6V ±3.5 % REFO absolutetolerancecalibrated TA = 25°C 3 V ±1.5 % dfREFO /dT REFO frequencytemperaturedrift Measured atACLK (1) 1.8V to3.6V 0.01 %/°C dfREFO /dVCC REFO frequencysupplyvoltagedrift Measured atACLK (2) 1.8V to3.6V 1.0 %/V Dutycycle Measured atACLK 1.8V to3.6V 40 50 60 % tSTART REFO startuptime 40%/60% dutycycle 1.8V to3.6V 25 µs (1) Calculatedusingthebox method:(MAX(-40to85°C) -MIN(-40to85°C))/MIN(-40to85°C) /(85°C -(-40°C))

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Typical DCO Frequency, V = 3.0 V, T = 25°CCC A DCORSEL 100 0.1 f – MHzDCO DCOx = 31 DCOx = 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 DCO Frequency overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT fDCO(0,0) DCO frequency(0,0)(1) DCORSELx = 0,DCOx = 0,MODx = 0 0.07 0.20 MHz fDCO(0,31) DCO frequency(0,31)(1) DCORSELx = 0,DCOx = 31,MODx = 0 0.70 1.70 MHz fDCO(1,0) DCO frequency(1,0)(1) DCORSELx = 1,DCOx = 0,MODx = 0 0.15 0.36 MHz fDCO(1,31) DCO frequency(1,31)(1) DCORSELx = 1,DCOx = 31,MODx = 0 1.47 3.45 MHz fDCO(2,0) DCO frequency(2,0)(1) DCORSELx = 2,DCOx = 0,MODx = 0 0.32 0.75 MHz fDCO(2,31) DCO frequency(2,31)(1) DCORSELx = 2,DCOx = 31,MODx = 0 3.17 7.38 MHz fDCO(3,0) DCO frequency(3,0)(1) DCORSELx = 3,DCOx = 0,MODx = 0 0.64 1.51 MHz fDCO(3,31) DCO frequency(3,31)(1) DCORSELx = 3,DCOx = 31,MODx = 0 6.07 14.0 MHz fDCO(4,0) DCO frequency(4,0)(1) DCORSELx = 4,DCOx = 0,MODx = 0 1.3 3.2 MHz fDCO(4,31) DCO frequency(4,31)(1) DCORSELx = 4,DCOx = 31,MODx = 0 12.3 28.2 MHz fDCO(5,0) DCO frequency(5,0)(1) DCORSELx = 5,DCOx = 0,MODx = 0 2.5 6.0 MHz fDCO(5,31) DCO frequency(5,31)(1) DCORSELx = 5,DCOx = 31,MODx = 0 23.7 54.1 MHz fDCO(6,0) DCO frequency(6,0)(1) DCORSELx = 6,DCOx = 0,MODx = 0 4.6 10.7 MHz fDCO(6,31) DCO frequency(6,31)(1) DCORSELx = 6,DCOx = 31,MODx = 0 39.0 88.0 MHz fDCO(7,0) DCO frequency(7,0)(1) DCORSELx = 7,DCOx = 0,MODx = 0 8.5 19.6 MHz fDCO(7,31) DCO frequency(7,31)(1) DCORSELx = 7,DCOx = 31,MODx = 0 60 135 MHz Frequencystepbetween rangeSDCORSEL SRSEL = fDCO(DCORSEL+1,DCO) /fDCO(DCORSEL,DCO) 1.2 2.3 ratioDCORSEL and DCORSEL + 1 Frequencystepbetween tapSDCO SDCO = fDCO(DCORSEL,DCO+1) /fDCO(DCORSEL,DCO) 1.02 1.12 ratioDCO and DCO + 1 Dutycycle Measured atSMCLK 40 50 60 % dfDCO /dT DCO frequencytemperaturedriftfDCO = 1 MHz 0.1 %/°C dfDCO /dVCC DCO frequencyvoltagedrift fDCO = 1 MHz 1.9 %/V (1) When selectingtheproperDCO frequencyrange(DCORSELx), thetargetDCO frequency,fDCO ,shouldbe settoresidewithinthe rangeoffDCO(n, 0),MAX ≤ fDCO ≤ fDCO(n, 31),MIN,where fDCO(n, 0),MAX representsthemaximum frequencyspecifiedfortheDCO frequency, rangen,tap0 (DCOx = 0)and fDCO(n,31),MINrepresentstheminimum frequencyspecifiedfortheDCO frequency,rangen,tap31 (DCOx = 31).ThisensuresthatthetargetDCO frequencyresideswithintherangeselected.Itshouldalsobe notedthatiftheactual fDCO frequencyfortheselectedrangecausestheFLL ortheapplicationtoselecttap0 or31,theDCO faultflagissettoreportthatthe selectedrangeisatitsminimum ormaximum tapsetting. Figure16. TypicalDCO frequency Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 51

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PMM, Brown-Out Reset (BOR) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT BOR H on voltage,V(DV CC _BOR_IT-) |dDV CC /dt|< 3 V/s 1.45 VDV CC fallinglevel BOR H offvoltage,V(DV CC _BOR_IT+) |dDV CC /dt|< 3 V/s 0.80 1.30 1.50 VDV CC risinglevel V(DV CC _BOR_hys) BOR H hysteresis 60 250 mV tRESET PulsedurationrequiredatRST/NMI pintoaccepta reset 2 µs PMM, Core Voltage overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCORE3 (AM) Core voltage,activemode, PMMCOREV = 3 2.4V ≤ DV CC ≤ 3.6V 1.90 V VCORE2 (AM) Core voltage,activemode, PMMCOREV = 2 2.2V ≤ DV CC ≤ 3.6V 1.80 V VCORE1 (AM) Core voltage,activemode, PMMCOREV = 1 2.0V ≤ DV CC ≤ 3.6V 1.60 V VCORE0 (AM) Core voltage,activemode, PMMCOREV = 0 1.8V ≤ DV CC ≤ 3.6V 1.40 V VCORE3 (LPM) Core voltage,low-currentmode, PMMCOREV = 3 2.4V ≤ DV CC ≤ 3.6V 1.93 V VCORE2 (LPM) Core voltage,low-currentmode, PMMCOREV = 2 2.2V ≤ DV CC ≤ 3.6V 1.90 V VCORE1 (LPM) Core voltage,low-currentmode, PMMCOREV = 1 2.0V ≤ DV CC ≤ 3.6V 1.70 V VCORE0 (LPM) Core voltage,low-currentmode, PMMCOREV = 0 1.8V ≤ DV CC ≤ 3.6V 1.50 V

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PMM, SVS High Side overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSHE = 0,DV CC = 3.6V 0 nA I(SVSH) SVS currentconsumption SVSHE = 1,DV CC = 3.6V,SVSHFP = 0 200 nA SVSHE = 1,DV CC = 3.6V,SVSHFP = 1 1.5 µA SVSHE = 1,SVSHRVL = 0 1.55 1.62 1.69 SVSHE = 1,SVSHRVL = 1 1.75 1.82 1.89 V(SVSH_IT-) SVS H on voltagelevel(1) V SVSHE = 1,SVSHRVL = 2 1.95 2.02 2.09 SVSHE = 1,SVSHRVL = 3 2.05 2.12 2.19 SVSHE = 1,SVSMHRRL = 0 1.60 1.70 1.80 SVSHE = 1,SVSMHRRL = 1 1.80 1.90 2.00 SVSHE = 1,SVSMHRRL = 2 2.00 2.10 2.20 SVSHE = 1,SVSMHRRL = 3 2.10 2.20 2.30 V(SVSH_IT+) SVS H offvoltagelevel(1) V SVSHE = 1,SVSMHRRL = 4 2.25 2.35 2.50 SVSHE = 1,SVSMHRRL = 5 2.52 2.65 2.78 SVSHE = 1,SVSMHRRL = 6 2.85 3.00 3.15 SVSHE = 1,SVSMHRRL = 7 2.85 3.00 3.15 SVSHE = 1,dVDVCC /dt= 10 mV/µs,SVSHFP = 1 2.5 tpd(SVSH) SVS H propagationdelay µs SVSHE = 1,dVDVCC /dt= 1 mV/µs,SVSHFP = 0 20 SVSHE = 0 → 1,dVDVCC /dt= 10 mV/µs,SVSHFP = 1 12.5 t(SVSH) SVS H on oroffdelaytime µs SVSHE = 0 → 1,dVDVCC /dt= 1 mV/µs,SVSHFP = 0 100 dVDVCC /dt DV CC risetime 0 1000 V/s (1) The SVS H settingsavailabledepend on theVCORE (PMMCOREVx) setting.See thePower Management Module and SupplyVoltage SupervisorchapterintheCC430 FamilyUser's Guide (SLAU259 )on recommended settingsand use. PMM, SVM High Side overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVMHE = 0,DV CC = 3.6V 0 nA I(SVMH) SVM H currentconsumption SVMHE= 1,DV CC = 3.6V,SVMHFP = 0 200 nA SVMHE = 1,DV CC = 3.6V,SVMHFP = 1 1.5 µA SVMHE = 1,SVSMHRRL = 0 1.60 1.70 1.80 SVMHE = 1,SVSMHRRL = 1 1.80 1.90 2.00 SVMHE = 1,SVSMHRRL = 2 2.00 2.10 2.20 SVMHE = 1,SVSMHRRL = 3 2.10 2.20 2.30 V(SVMH) SVM H on oroffvoltagelevel(1) SVMHE = 1,SVSMHRRL = 4 2.25 2.35 2.50 V SVMHE = 1,SVSMHRRL = 5 2.52 2.65 2.78 SVMHE = 1,SVSMHRRL = 6 2.85 3.00 3.15 SVMHE = 1,SVSMHRRL = 7 2.85 3.00 3.15 SVMHE = 1,SVMHOVPE = 1 3.75 SVMHE = 1,dVDVCC /dt= 10 mV/µs,SVMHFP = 1 2.5 tpd(SVMH) SVM H propagationdelay µs SVMHE = 1,dVDVCC /dt= 1 mV/µs,SVMHFP = 0 20 SVMHE = 0 → 1,dVDVCC /dt= 10 mV/µs,SVMHFP = 1 12.5 t(SVMH) SVM H on oroffdelaytime µs SVMHE = 0 → 1,dVDVCC /dt= 1 mV/µs,SVMHFP = 0 100 (1) The SVM H settingsavailabledepend on theVCORE (PMMCOREVx) setting.See thePower Management Module and SupplyVoltage SupervisorchapterintheCC430 FamilyUser's Guide (SLAU259 )on recommended settingsand use. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 53

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PMM, SVS Low Side overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVSLE = 0,PMMCOREV = 2 0 nA I(SVSL) SVS L currentconsumption SVSLE = 1,PMMCOREV = 2,SVSLFP = 0 200 nA SVSLE = 1,PMMCOREV = 2,SVSLFP = 1 1.5 µA SVSLE = 1,dVCORE /dt= 10 mV/µs,SVSLFP = 1 2.5 tpd(SVSL) SVS L propagationdelay µs SVSLE = 1,dVCORE /dt= 1 mV/µs,SVSLFP = 0 20 SVSLE = 0 → 1,dVCORE /dt= 10 mV/µs,SVSLFP = 1 12.5 t(SVSL) SVS L on oroffdelaytime µs SVSLE = 0 → 1,dVCORE /dt= 1 mV/µs,SVSLFP = 0 100 PMM, SVM Low Side overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SVMLE = 0,PMMCOREV = 2 0 nA I(SVML) SVM L currentconsumption SVMLE= 1,PMMCOREV = 2,SVMLFP = 0 200 nA SVMLE= 1,PMMCOREV = 2,SVMLFP = 1 1.5 µA SVMLE = 1,dVCORE /dt= 10 mV/µs,SVMLFP = 1 2.5 tpd(SVML) SVM L propagationdelay µs SVMLE = 1,dVCORE /dt= 1 mV/µs,SVMLFP = 0 20 SVMLE = 0 → 1,dVCORE /dt= 10 mV/µs,SVMLFP = 1 12.5 t(SVML) SVM L on oroffdelaytime µs SVMLE = 0 → 1,dVCORE /dt= 1 mV/µs,SVMLFP = 0 100 Wake-up From Low-Power Modes and Reset overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PMMCOREV = SVSMLRRL = n fMCLK ≥ 4.0MHz 5tWAKE-UP- Wake-up timefromLPM2, LPM3, or (wheren = 0,1,2,or3), µs FAST LPM4 toactivemode (1) fMCLK < 4.0MHz 6SVSLFP = 1 tWAKE-UP- Wake-up timefromLPM2, LPM3 or PMMCOREV = SVSMLRRL = n (wheren = 0,1,2,or3), 150 165 µs SLOW LPM4 toactivemode (2) SVSLFP = 0 tWAKE-UP- Wake-up timefromLPMx.5 toactive 2 3 ms LPM5 mode (3) tWAKE-UP- Wake-up timefromRST orBOR 2 3 ms RESET eventtoactivemode (3) (1) Thisvaluerepresentsthetimefromthewakeup eventtothefirstactiveedge ofMCLK. The wakeup timedepends on theperformance mode ofthelow-sidesupervisor(SVSL)and lowsidemonitor(SVM L).Fastestwakeup timesarepossiblewithSVS Land SVM L infull performancemode ordisabledwhen operatinginAM, LPM0, and LPM1. VariousoptionsareavailableforSVS Land SVM L while operatinginLPM2, LPM3, and LPM4. See thePower Management Module and SupplyVoltageSupervisorchapterintheCC430 Family User's Guide (SLAU259 ). (2) Thisvaluerepresentsthetimefromthewakeup eventtothefirstactiveedge ofMCLK. The wakeup timedepends on theperformance mode ofthelow-sidesupervisor(SVSL)and lowsidemonitor(SVM L).Inthiscase,theSVS Land SVM L areinnormalmode (lowcurrent) mode when operatinginAM, LPM0, and LPM1. VariousoptionsareavailableforSVS Land SVM L whileoperatinginLPM2, LPM3, and LPM4. See thePower Management Module and SupplyVoltageSupervisorchapterintheCC430 FamilyUser's Guide (SLAU259 ). (3) Thisvaluerepresentsthetimefromthewakeup eventtotheresetvectorexecution. Timer_A overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal:SMCLK, ACLK, 1.8V,fTA Timer_A inputclockfrequency External:TACLK, 25 MHz3.0VDutycycle= 50% ± 10% Allcaptureinputs,minimum pulse 1.8V,tTA,cap Timer_A capturetiming 20 nsdurationrequiredforcapture 3.0V

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 USCI (UART Mode) Recommended OperatingConditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal:SMCLK, ACLK fUSCI USCI inputclockfrequency External:UCLK fSYSTEM MHz Dutycycle= 50% ± 10% BITCLK clockfrequencyfBITCLK 1 MHz(equalsbaud rateinMBaud) USCI (UART Mode) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 2.2V 50 600 tτ UART receivedeglitchtime(1) ns

3 V 50 600

(1) Pulseson theUART receiveinput(UCxRX) shorterthantheUART receivedeglitchtimearesuppressed.To ensurethatpulsesare correctlyrecognizedtheirwidthshouldexceed themaximum specificationofthedeglitchtime. USCI (SPIMaster Mode) Recommended OperatingConditions PARAMETER CONDITIONS VCC MIN TYP MAX UNIT Internal:SMCLK, ACLKfUSCI USCI inputclockfrequency fSYSTEM MHzDutycycle= 50% ± 10% USCI (SPIMaster Mode) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwise noted)(1)Figure17Figure18 PMMPARAMETER TEST CONDITIONS VCC MIN TYP MAX UNITCOREVx 1.8V 55 0 ns 3.0V 38 tSU,MI SOMI inputdatasetuptime 2.4V 30 3 ns 3.0V 25 1.8V 0 0 ns 3.0V 0 tHD,MI SOMI inputdataholdtime 2.4V 0 3 ns 3.0V 0 1.8V 20 0 ns 3.0V 18UCLK edge toSIMO valid,tVALID,MO SIMO outputdatavalidtime(2) C L = 20 pF 2.4V 16 3 ns 3.0V 15 1.8V -10 0 ns 3.0V -8 tHD,MO SIMO outputdataholdtime(3) C L = 20 pF 2.4V -10 3 ns 3.0V -8 (1) fUCxCLK = 1/2tLO/HI withtLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave),tSU,MI(USCI)+ tVALID,SO(Slave)). Fortheslave's parameterstSU,SI(Slave)and tVALID,SO(Slave)see theSPI parametersoftheattachedslave. (2) SpecifiesthetimetodrivethenextvaliddatatotheSIMO outputaftertheoutputchangingUCLK clockedge.See thetimingdiagrams inFigure17 and Figure18. (3) Specifieshow longdataon theSIMO outputisvalidaftertheoutputchangingUCLK clockedge.Negativevaluesindicatethatthedata on theSIMO outputcan become invalidbeforetheoutputchangingclockedge observedon UCLK. See thetimingdiagramsin Figure17 and Figure18. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 55

tSU,MI tHD,MI UCLK SOMI SIMO tV ALID,MO CKPL =□0 CKPL =□1 1/fUCxCLK tHD,MO tLO/HI tLO/HI tSU,MI tHD,MI UCLK SOMI SIMO tV ALID,MO tHD,MO CKPL =□0 CKPL =□1 tLO/HI tLO/HI 1/fUCxCLK ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Figure17. SPI Master Mode, CKPH = 0 Figure18. SPI Master Mode, CKPH = 1

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 USCI (SPISlaveMode) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwise noted)(1)Figure19Figure20 PMMPARAMETER TEST CONDITIONS VCC MIN TYP MAX UNITCOREVx 1.8V 11 3.0V 8 tSTE,LEAD STE leadtime,STE lowtoclock ns 2.4V 7 3.0V 6 1.8V 3 3.0V 3 tSTE,LAG STE lagtime,LastclocktoSTE high ns 2.4V 3 3.0V 3 1.8V 66 3.0V 50STE accesstime,STE lowtoSOMItSTE,ACC nsdataout 2.4V 36 3.0V 30 1.8V 30 3.0V 23STE disabletime,STE hightoSOMItSTE,DIS nshighimpedance 2.4V 16 3.0V 13 1.8V 5 3.0V 5 tSU,SI SIMO inputdatasetuptime ns 2.4V 2 3.0V 2 1.8V 5 3.0V 5 tHD,SI SIMO inputdataholdtime ns 2.4V 5 3.0V 5 1.8V 76 3.0V 60UCLK edge toSOMI valid,tVALID,SO SOMI outputdatavalidtime(2) nsC L = 20 pF 2.4V 44 3.0V 40 1.8V 18 3.0V 12 tHD,SO SOMI outputdataholdtime(3) C L = 20 pF ns 2.4V 10 3.0V 8 (1) fUCxCLK = 1/2tLO/HI withtLO/HI ≥ max(tVALID,MO(Master)+ tSU,SI(USCI),tSU,MI(Master)+ tVALID,SO(USCI)). Forthemaster's parameterstSU,MI(Master)and tVALID,MO(Master)see theSPI parametersoftheattachedmaster. (2) SpecifiesthetimetodrivethenextvaliddatatotheSOMI outputaftertheoutputchangingUCLK clockedge.See thetimingdiagrams inFigure17 and Figure18. (3) Specifieshow longdataon theSOMI outputisvalidaftertheoutputchangingUCLK clockedge.See thetimingdiagramsinFigure17 and Figure18. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 57

CKPL =□0 CKPL =□1 SOMI SIMO tSU,SI tHD,SI tV ALID,SO tSTE,LEAD 1/fUCxCLK tSTE,LAG tSTE,DIStSTE,ACC tHD,MO tLO/HI tLO/HI STE UCLK CKPL =□0 CKPL =□1 SOMI SIMO tSU,SI tHD,SI tV ALID,SO tSTE,LEAD 1/fUCxCLK tLO/HI tLO/HI tSTE,LAG tSTE,DIStSTE,ACC tHD,SO ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Figure19. SPI SlaveMode, CKPH = 0 Figure20. SPI SlaveMode, CKPH = 1

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tHD,DA T tSU,DA T tHD,ST A tHIGHtLOW tBUFtHD,ST AtSU,ST A tSP tSU,STO ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 USCI (I2CMode) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(seeFigure21) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT Internal:SMCLK, ACLK, fUSCI USCI inputclockfrequency External:UCLK, fSYSTEM MHz Dutycycle= 50% ± 10% fSCL SCL clockfrequency 2.2V,3 V 0 400 kHz fSCL ≤ 100 kHz 4.0 tHD,STA Holdtime(repeated)START 2.2V,3 V µs fSCL > 100 kHz 0.6 fSCL ≤ 100 kHz 4.7 tSU,STA Setuptimefora repeatedSTART 2.2V,3 V µs fSCL > 100 kHz 0.6 tHD,DAT Data holdtime 2.2V,3 V 0 ns tSU,DAT Data setuptime 2.2V,3 V 250 ns fSCL ≤ 100 kHz 4.0 tSU,STO SetuptimeforSTOP 2.2V,3 V µs fSCL > 100 kHz 0.6 2.2V 50 600Pulsedurationofspikessuppressedby inputtSP nsfilter 3 V 50 600 Figure21. I2C Mode Timing Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 59

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com LCD_B Recommended OperatingConditions PARAMETER CONDITIONS MIN NOM MAX UNIT Supplyvoltagerange,internalVCC,LCD_B,int.bias LCDCPEN = 0,VLCDEXT = 0 2.4 3.6 Vbiasing,chargepump disabled Supplyvoltagerange,externalVCC,LCD_B,ext.bias LCDCPEN = 0,VLCDEXT = 0 2.4 3.6 Vbiasing,chargepump disabled Supplyvoltagerange,external VCC,LCD_B,VLCDEXT LCD voltage,internalorexternal LCDCPEN = 0,VLCDEXT = 1 2.0 3.6 V biasing,chargepump disabled ExternalLCD voltageat VLCDCAP/R33 LCDCAP/R33, internalorexternalLCDCPEN = 0,VLCDEXT = 1 2.4 3.6 V biasing,chargepump disabled Capacitoron LCDCAP when LCDCPEN = 1,VLCDx > 0000C LCDCAP 4.7 10 µFchargepump enabled (chargepump enabled) fLCD = 2 × mux × fFRAMEfFrame LCD framefrequencyrange 0 100 Hzwithmux = 1 (static),2,3,4 fACLK,in ACLK inputfrequencyrange 30 32 40 kHz C Panel Panelcapacitance 100-Hz framefrequency 10000 pF VCC +VR33 AnaloginputvoltageatR33 LCDCPEN = 0,VLCDEXT = 1 2.4 V0.2 VR03 + 2/3LCDREXT = 1,LCDEXTBIAS = 1,VR23,1/3bias AnaloginputvoltageatR23 VR13 *(VR33 - VR33 VLCD2B = 0 VR03 ) VR03 + 1/3AnaloginputvoltageatR13 with LCDREXT = 1,LCDEXTBIAS = 1,VR13,1/3bias VR03 *(VR33 - VR23 V1/3biasing LCD2B = 0 VR03 ) VR03 + 1/2AnaloginputvoltageatR13 with LCDREXT = 1,LCDEXTBIAS = 1,VR13,1/2bias VR03 *(VR33 - VR33 V1/2biasing LCD2B = 1 VR03 ) VR03 AnaloginputvoltageatR03 R0EXT = 1 VSS V Voltagedifferencebetween VLCD VCC +VLCD -VR03 LCDCPEN = 0,R0EXT = 1 2.4 Vand R03 0.2 ExternalLCD referencevoltageVLCDREF/R13 VLCDREFx = 01 0.8 1.2 1.5 VappliedatLCDREF/R13

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 LCD_B ElectricalCharacteristics overoperatingfree-airtemperaturerange(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VLCD LCD voltage,withinternal VLCDx = 0000,VLCDEXT = 0 2.4V to3.6V VCC V reference LCDCPEN = 1,VLCDx = 0001 2.0V to3.6V 2.59 LCDCPEN = 1,VLCDx = 0010 2.65 LCDCPEN = 1,VLCDx = 0011 2.71 LCDCPEN = 1,VLCDx = 0100 2.78 LCDCPEN = 1,VLCDx = 0101 2.84 LCDCPEN = 1,VLCDx = 0110 2.91 LCDCPEN = 1,VLCDx = 0111 2.97 LCDCPEN = 1,VLCDx = 1000 3.03 LCDCPEN = 1,VLCDx = 1001 3.09 LCDCPEN = 1,VLCDx = 1010 3.15 LCDCPEN = 1,VLCDx = 1011 3.22 LCDCPEN = 1,VLCDx = 1100 3.28 LCDCPEN = 1,VLCDx = 1101 2.2V to3.6V 3.34 LCDCPEN = 1,VLCDx = 1110 3.40 LCDCPEN = 1,VLCDx = 1111 3.46 3.53 ICC,Peak,CP Peak supplycurrentsdue to LCDCPEN = 1,VLCDx = 1111 2.2V 200 µA chargepump activities tLCD,CP,on Time tochargeC LCD when C LCDCAP = 4.7µF, 2.2V 100 500 ms discharge LCDCPEN = 0→1,VLCDx = 1111 ICP,Load Maximum chargepump load LCDCPEN = 1,VLCDx = 1111 2.2V 50 µA current R LCD,Seg LCD driveroutputimpedance, LCDCPEN = 1,VLCDx = 1000, 2.2V 10 kΩ segment lines ILOAD = ±10 µA R LCD,COM LCD driveroutputimpedance, LCDCPEN = 1,VLCDx = 1000, 2.2V 10 kΩ common lines ILOAD = ±10 µA Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 61

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com 10-BitADC, Power Supply and InputRange Conditions overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AV CC and DV CC areconnectedtogether, AV CC Analogsupplyvoltage AV SS and DV SS areconnectedtogether, 1.8 3.6 V V(AVSS) = V(DVSS) = 0 V V(Ax) Analoginputvoltagerange(2) AllADC10_A pins:P1.0toP1.5,P3.6,P3.7 AV CC V fADC10CLK = 5 MHz, ADC10ON = 1,REFON = 0, 2.2V 70 105Operatingsupplycurrentinto AVCC terminal.REF module µASHT0 = 0,SHT1 = 0,ADC10DIV = 0, 3 V 80 115and referencebufferoff. ADC10SREF = 00 fADC10CLK = 5 MHz, ADC10ON = 1,REFON = 1,Operatingsupplycurrentinto AVCC terminal.REF module 3 V 130 185 µASHT0 = 0,SHT1 = 0,ADC10DIV = 0, on,referencebufferon. ADC10SREF = 01 IADC10_A fADC10CLK = 5 MHz, ADC10ON = 1,REFON = 0,Operatingsupplycurrentinto AVCC terminal.REF module 3 V 120 170 µASHT0 = 0,SHT1 = 0,ADC10DIV = 0, off,referencebufferon. ADC10SREF = 10,VEREF = 2.5V fADC10CLK = 5 MHz, ADC10ON = 1,REFON = 0,Operatingsupplycurrentinto AVCC terminal.REF module 3 V 85 120 µASHT0 = 0,SHT1 = 0,ADC10DIV = 0, off,referencebufferoff. ADC10SREF = 11,VEREF = 2.5V Onlyone terminalAx can be selectedatone time C I Inputcapacitance fromthepad totheADC10_A capacitorarray 2.2V 3.5 pF includingwiringand pad. AV CC > 2.0V,0 V ≤ VAx ≤ AV CC 36 R I InputMUX ON resistance kΩ 1.8V < AV CC < 2.0V,0 V ≤ VAx ≤ AV CC 96 (1) The leakagecurrentisdefinedintheleakagecurrenttablewithP2.x/Axparameter. (2) The analoginputvoltagerangemust be withintheselectedreferencevoltagerangeVR+ toVR-forvalidconversionresults.The external referencevoltagerequiresdecouplingcapacitors.See (). 10-BitADC, Timing Parameters overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT ForspecifiedperformanceofADC10_A linearityfADC10CLK 2.2V,3 V 0.45 5 5.5 MHzparameters InternalADC10_AfADC10OSC ADC10DIV = 0,fADC10CLK = fADC10OSC 2.2V,3 V 4.2 4.8 5.4 MHzoscillator(1) REFON = 0,Internaloscillator,12 ADC10CLK cycles, 2.2V,3 V 2.4 3.010-bitmode, fADC10OSC = 4 MHz to5 MHz tCONVERT Conversiontime µs ExternalfADC10CLK fromACLK, MCLK orSMCLK, ADC10SSEL ≠ 0 Turnon settlingtimeof(2)tADC10ON See (3) 100 nstheADC R S = 1000 Ω,R I= 96 kΩ,C I= 3.5pF (4) 1.8V 3 µs tSample Samplingtime R S = 1000 Ω,R I= 36 kΩ,C I= 3.5pF (4) 3 V 1 µs (1) The ADC10OSC issourceddirectlyfromMODOSC insidetheUCS. (2) 12 × ADC10DIV × 1/fADC10CLK (3) The conditionisthattheerrorina conversionstartedaftertADC10ON islessthan±0.5LSB. The referenceand inputsignalarealready settled. (4) ApproximatelyeightTau (τ)areneeded togetan erroroflessthan±0.5LSB

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 10-BitADC, LinearityParameters overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT 1.4V ≤ (VEREF+ -VEREF-)min ≤ 1.6V -1.0 +1.0 EI Integrallinearityerror LSB 1.6V < (VEREF+ -VEREF-)min ≤ VAVCC -1.0 +1.0 (VEREF+ -VEREF-)min ≤ (VEREF+ -VEREF-),ED Differentiallinearityerror -1.0 +1.0 LSBC VEREF+ = 20 pF (VEREF+ -VEREF-)min ≤ (VEREF+ -VEREF-), EO Offseterror Internalimpedance ofsourceR S < 100 Ω, -1.0 +1.0 LSB C VEREF+ = 20 pF Gain error,externalreference -1.0 +1.0 LSB(VEREF+ -VEREF-)min ≤ (VEREF+ -VEREF-), Gain error,externalreference, C VEREF+ = 20 pFEG -5 +5 LSBbuffered Gain error,internalreference See (1) -1.5 +1.5 %V REF Totalunadjustederror,external -2.0 ±1.0 +2.0 LSBreference (VEREF+ -VEREF-)min ≤ (VEREF+ -VEREF-), C VEREF+ = 20 pFTotalunadjustederror,externalET -5 ±1.0 +5 LSBreference,buffered Totalunadjustederror,internal See (1) -1.5 ±1.0 +1.5 %V REFreference (1) Dominatedby theabsolutevoltageoftheintegratedreferencevoltage. REF, ExternalReference overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT PositiveexternalVEREF+ VEREF+ > VEREF- (2) 1.4 AV CC Vreferencevoltageinput NegativeexternalVEREF- VEREF+ > VEREF- (3) 0 1.2 Vreferencevoltageinput VEREF+ - Differentialexternal VEREF+ > VEREF- (4) 1.4 AV CC VreferencevoltageinputVEREF- 1.4V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 VI(VEREF+) Staticinputcurrent fADC10CLK = 5 MHz, ADC10SHTx = 0x0001, 2.2V,3 V ±8.5 ±26 µAI(VEREF-) Conversionrate200 ksps 1.4V ≤ VEREF+ ≤ V(AVCC), VEREF- = 0 VI(VEREF+) Staticinputcurrent fADC10CLK = 5 MHZ, ADC10SHTX = 0x1000, 2.2V,3 V ±1 µAI(VEREF-) Conversionrate20 ksps CapacitanceatVEREF+C (VEREF+/-) See (5) 10 µForVEREF- terminal (1) The externalreferenceisused duringADC conversiontochargeand dischargethecapacitancearray.The inputcapacitance,C I,isalso thedynamicloadforan externalreferenceduringconversion.The dynamicimpedance ofthereferencesupplyshouldfollowthe recommendationson analog-sourceimpedance toallowthechargetosettlefor12-bitaccuracy. (2) The accuracylimitstheminimum positiveexternalreferencevoltage.Lower referencevoltagelevelsmay be appliedwithreduced accuracyrequirements. (3) The accuracylimitsthemaximum negativeexternalreferencevoltage.Higherreferencevoltagelevelsmay be appliedwithreduced accuracyrequirements. (4) The accuracylimitsminimum externaldifferentialreferencevoltage.Lower differentialreferencevoltagelevelsmay be appliedwith reducedaccuracyrequirements. (5) Two decouplingcapacitors,10 µF and 100 nF,shouldbe connectedtoVEREF todecouplethedynamiccurrentrequiredforan external referencesourceifitisused fortheADC10_A. See alsotheCC430 FamilyUser's Guide (SLAU259 ). Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 63

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com REF, Built-InReference overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT REFVSEL = {2}for2.5V,VEREF+ Positivebuilt-inreferencevoltage 3 V 2.5 ±1.5% VREFON = REFOUT = 1 REFVSEL = {1}for2.0V,VEREF+ Positivebuilt-inreferencevoltage 3 V 2.01 ±1.5% VREFON = REFOUT = 1 REFVSEL = {0}for1.5V, 2.2V,VEREF+ Positivebuilt-inreferencevoltage 1.505 ±1.5% VREFON = REFOUT = 1 3 V AVCC minimum voltage,PositiveAV CC(min) REFVSEL = {0}for1.5V 1.8 Vbuilt-inreferenceactive AVCC minimum voltage,PositiveAV CC(min) REFVSEL = {1}for2.0V 2.3 Vbuilt-inreferenceactive AVCC minimum voltage,PositiveAV CC(min) REFVSEL = {2}for2.5V 2.8 Vbuilt-inreferenceactive fADC10CLK = 5 MHz, REFON = 1,REFBURST = 0, 3 V 15.5 19 µA REFVSEL = {0}for1.5V fADC10CLK = 5 MHz,OperatingsupplycurrentintoIREF+ REFON = 1,REFBURST = 0, 3 V 18 24 µAAVCC terminal(2) REFVSEL = {1}for2.0V fADC10CLK = 5 MHz, REFON = 1,REFBURST = 0, 3 V 21 30 µA REFVSEL = {2}for2.5V OperatingsupplycurrentintoIREF+,REFO REFON = 1,REFOUT = 1,AVCC terminalwithREF output 3 V 0.9 1.7 mA UT REFBURST = 0bufferenabled REFVSEL = {0,1,2}, Load-currentregulation,VREF+ ILoad,VREF+ = +10 µA or-1000µA, µV/IL(VREF+) 2500terminal(3) mAAV CC = AV CC (min)foreach referencelevel, REFON = REFOUT = 1 C VREF+ CapacitanceatVREF+ terminals REFON = REFOUT = 1 20 100 pF Temperaturecoefficientofbuilt-in ppm/TC REF+ REFVSEL = {0,1,2},REFON = 1 30 50reference(4) °C 2.2V 150 180REFON = 0,INCH = 0Ah,OperatingsupplycurrentintoISENSOR µAAVCC terminal(5) ADC10ON = NA, TA = 30°C 3 V 150 190 2.2V 765 VSENSOR See (6) ADC10ON = 1,INCH = 0Ah,TA = 30°C mV

3 V 765

ADC10ON = 1,INCH = 0Ah,tSENSOR Sample timerequiredif 30 µs (sample) channel10 isselected(7) Errorofconversionresult≤ 1 LSB ADC10ON = 1,INCH = 0Bh,tVMID Sample timerequiredif 1 µs (sample) channel11 isselected(8) Errorofconversionresult≤ 1 LSB AV CC = AV CC (min)-AV CC(max), PSRR_DC Power supplyrejectionratio(dc) TA = 25°C, 120 300 µV/V REFVSEL = {0,1,2},REFON = 1 (1) The leakagecurrentisdefinedintheleakagecurrenttablewithP2.x/Axparameter. (2) The internalreferencecurrentissuppliedviaterminalAVCC. ConsumptionisindependentoftheADC10ON controlbit,unlessa conversionisactive.The REFON bitenablestosettlethebuilt-inreferencebeforestartingan A/D conversion. (3) Contributiononlydue tothereferenceand bufferincludingpackage.Thisdoes notincluderesistancedue toPCB traceand other factors.Positiveloadcurrentsareflowingintothedevice. (4) Calculatedusingthebox method:(MAX(-40to85°C) -MIN(-40to85°C))/MIN(-40to85°C)/(85°C -(-40°C)). (5) The sensorcurrentISENSOR isconsumed if(ADC10ON = 1 and REFON = 1)or(ADC10ON = 1 and INCH = 0Ah and sample signalis high).When REFON = 1,ISENSOR isalreadyincludedinIREF+ . (6) The temperaturesensoroffsetcan be as much as ±20°C. A single-pointcalibrationisrecommended tominimizetheoffseterrorofthe built-intemperaturesensor. (7) The typicalequivalentimpedance ofthesensoris51 kΩ.The sample timerequiredincludesthesensor-ontimetSENSOR(on) . (8) The on-timetVMID(on) isincludedinthesamplingtimetVMID(sample);no additionalon timeisneeded.

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-40 -30 -20 -10 0 10 20 30 40 50 60 70 80 Typical Temperature Sensor Voltage - mV Ambient Temperature - ˚C ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 REF, Built-InReference(continued) overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT AV CC = AV CC (min)-AV CC(max), PSRR_AC Power supplyrejectionratio(ac) TA = 25°C, f= 1 kHz,ΔVpp = 100 mV, 6.4 mV/V REFVSEL = (0,1,2},REFON = 1 TA = -40°C toAV CC = AV CC(min) - 23 12585°CAV CC(max),SettlingtimeofreferencetSETTLE µsvoltage(9) TA = 25°C 23 50REFVSEL = {0,1,2}, REFON = 0 → 1 TA = 85°C 16 25 (9) The conditionisthattheerrorina conversionstartedaftertREFON islessthan±0.5LSB. Figure22. TypicalTemperature Sensor Voltage Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 65

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Comparator_B overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC Supplyvoltage 1.8 3.6 V 1.8V 40 CBPWRMD = 00,CBON = 1,CBRSx = 00 2.2V 31 50Comparatoroperating supplycurrentinto 3 V 32 65 IAVCC_COMP AVCC. Excludes µA2.2V,CBPWRMD = 01,CBON = 1,CBRSx = 00 10 17referenceresistor 3 Vladder. 2.2V,CBPWRMD = 10,CBON = 1,CBRSx = 00 0.2 0.853 V CBREFACC = 0,CBREFLx = 01,CBRSx = 10, 2.2V,Quiescentcurrentof 10 17 µAREFON = 0,CBON = 0 3 VresistorladderintoIAVCC_REF AVCC. IncludesREF CBREFACC = 1,CBREFLx = 01,CBRSx = 10, 2.2V, 33 40 µAmodule current. REFON = 0,CBON = 0 3 V VREF Referencevoltagelevel CBREFLx = 01,CBREFACC = 0 ≥1.8V 1.49 ±1.5% V VREF Referencevoltagelevel CBREFLx = 10,CBREFACC = 0 ≥2.2V 1.988 ±1.5% V VREF Referencevoltagelevel CBREFLx = 11,CBREFACC = 0 ≥3.0V 2.5 ±1.5% V Common mode inputVIC 0 VCC -1 Vrange VOFFSET Inputoffsetvoltage CBPWRMD = 00 ±20 mV VOFFSET Inputoffsetvoltage CBPWRMD = 01,10 ±10 mV C IN Inputcapacitance 5 pF ON -switchclosed 3 4 kΩ R SIN Seriesinputresistance OFF -switchopened 50 M Ω CBPWRMD = 00,CBF = 0 450 ns Propagationdelay,tPD CBPWRMD = 01,CBF = 0 600 nsresponsetime CBPWRMD = 10,CBF = 0 50 µs CBPWRMD = 00,CBON = 1,CBF = 1, 0.35 0.6 1.5 µsCBFDLY = 00 CBPWRMD = 00,CBON = 1,CBF = 1, 1.8 3.4 6.5 µsCBFDLY = 11 CBON = 0 toCBON = 1,CBPWRMD = 00,01 1 2 µs tEN_CMP Comparatorenabletime CBON = 0 toCBON = 1,CBPWRMD = 10 1.5 µs ResistorreferencetEN_REF CBON = 0 toCBON = 1 1.0 1.5 µsenabletime Temperaturecoefficient ppm/TC CB_REF 50referenceofVCB_REF °C VIN × VIN × VIN ×VIN = referenceintoresistorladder,ReferencevoltageforaVCB_REF (n+0.5) (n+1) (n+1.5) Vgiventap n = 0 to31 /32 /32 /32

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 FlashMemory overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) TESTPARAMETER MIN TYP MAX UNITCONDITIONS DV CC(PGM/ERASE) Program orerasesupplyvoltage 1.8 3.6 V IPGM AveragesupplycurrentfromDVCC duringprogram 3 5 mA IERASE AveragesupplycurrentfromDVCC duringerase 2 6.5 mA AveragesupplycurrentfromDVCC duringmass eraseorbankIMERASE ,IBANK 2 6.5 mAerase tCPT Cumulativeprogramtime(1) 16 ms Program and eraseendurance 104 105 cycles tRetention Data retentionduration TJ = 25°C 100 years tWord Word orbyteprogramtime(2) 64 85 µs tBlock,0 Blockprogramtimeforfirstbyteorword(2) 49 65 µs Blockprogramtimeforeach additionalbyteorword,exceptforlasttBlock,1-(N-1) 37 49 µsbyteorword(2) tBlock,N Blockprogramtimeforlastbyteorword(2) 55 73 µs Erasetimeforsegment erase,mass erase,and bank erasewhentErase 23 32 msavailable(2) MCLK frequencyinmarginalreadmodefMCLK,MGR 0 1 MHz(FCTL4.MGR0 = 1 orFCTL4. MGR1 = 1) (1) The cumulativeprogramtimemust notbe exceeded when writingtoa 128-byteflashblock.Thisparameterappliestoallprogramming methods:individualword/bytewriteand blockwritemodes. (2) These valuesarehardwiredintotheflashcontroller's statemachine. JTAG and Spy-Bi-WireInterface overrecommended rangesofsupplyvoltageand operatingfree-airtemperature(unlessotherwisenoted) TESTPARAMETER MIN TYP MAX UNITCONDITIONS fSBW Spy-Bi-Wireinputfrequency 2.2V,3 V 0 20 MHz tSBW,Low Spy-Bi-Wirelowclockpulselength 2.2V,3 V 0.025 15 µs Spy-Bi-Wireenabletime(TEST hightoacceptanceoffirstclocktSBW, En 2.2V,3 V 1 µsedge)(1) tSBW,Rst Spy-Bi-Wirereturntonormaloperationtime 15 100 µs 2.2V 0 5 MHz fTCK TCK inputfrequency-4-wireJTAG (2)

3 V 0 10 MHz

R internal Internalpull-downresistanceon TEST 2.2V,3 V 45 60 80 kΩ (1) ToolsaccessingtheSpy-Bi-Wireinterfaceneed towaitfortheminimum tSBW,En timeafterpullingtheTEST/SBWTCK pinhighbefore applyingthefirstSBWTCK clockedge. (2) fTCK may be restrictedtomeet thetimingrequirementsofthemodule selected. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 67

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com RF1A CC1101-Based Radio Parameters RF1A Recommended OperatingConditions PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Supplyvoltagerangeduringradiooperation 2.0 3.6 V PMMCOREVx Core voltagerange,PMMCOREVx settingduringradiooperation 2 3

300 MHz range 300 348

RF frequencyrange 400 MHz range 389(1) 464 MHz 800 and 900 MHz range 779 928 2-FSK 0.6 500 Data rate 2-GFSK, OOK, and ASK 0.6 250 kBaud (Shaped)MSK (alsoknown as differentialoffsetQPSK) (2) 26 500 RF crystalfrequency 26 27 MHz RF crystaltolerance Totaltoleranceincludinginitialtolerance,crystalloading,agingand ±40 ppm temperaturedependency(3) RF crystalloadcapacitance 10 13 20 pF RF crystaleffectiveseries 100 Ω resistance (1) Ifusinga 27-MHz crystal,thelowerfrequencylimitforthisband is392 MHz. (2) IfusingoptionalManchesterencoding,thedatarateinkbps ishalfthebaud rate. (3) The acceptablecrystaltolerancedepends on frequencyband,channelbandwidth,and spacing.Alsosee designnoteDN005 --CC11xx SensitivityversusFrequencyOffsetand CrystalAccuracy(SWRA122 ). RF CrystalOscillator,XT2 TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Start-uptime(2) 150 810 µs Dutycycle 45 50 55 % (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) The start-uptimedepends toa verylargedegreeon theused crystal. CurrentConsumption, Reduced-Power Modes TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT RF crystaloscillatoronly(forexample,SLEEP statewith 100 µAMCSM0.OSC_FORCE_ON = 1) Currentconsumption IDLE state(includingRF crystaloscillator) 1.7 mA FSTXON state(onlythefrequencysynthesizerisrunning)(2) 9.5 mA (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Thiscurrentconsumptionisalsorepresentativeofotherintermediatestateswhen goingfromIDLE toRX orTX, includingthecalibration state.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 CurrentConsumption, Receive Mode TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1)(2) DATAFREQUENCYPARAMETER RATE TEST CONDITIONS MIN TYP MAX UNIT(MHz) (kBaud) Inputat-100dBm (close 17tosensitivitylimit) 1.2 Inputat-40dBm (well 16above sensitivitylimit) Inputat-100dBm (close 17tosensitivitylimit)Registersettingsoptimized315 38.4 forreducedcurrent Inputat-40dBm (well 16above sensitivitylimit) Inputat-100dBm (close 18tosensitivitylimit) 250 Inputat-40dBm (well 16.5above sensitivitylimit) Inputat-100dBm (close 18tosensitivitylimit) 1.2 Inputat-40dBm (well 17above sensitivitylimit) Inputat-100dBm (close 18Current tosensitivitylimit)Registersettingsoptimizedconsumption, 433 38.4 mAforreducedcurrent Inputat-40dBm (wellRX 17above sensitivitylimit) Inputat-100dBm (close 18.5tosensitivitylimit) 250 Inputat-40dBm (well 17above sensitivitylimit) Inputat-100dBm (close 16tosensitivitylimit) 1.2 Inputat-40dBm (well 15above sensitivitylimit) Inputat-100dBm (close 16tosensitivitylimit)Registersettingsoptimized868,915 38.4 forreducedcurrent(3) Inputat-40dBm (well 15above sensitivitylimit) Inputat-100dBm (close 16tosensitivitylimit) 250 Inputat-40dBm (well 15above sensitivitylimit) (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Reduced currentsetting(MDMCFG2.DEM_DCFILT_OFF = 1)givesa slightlylowercurrentconsumptionatthecostofa reductionin sensitivity.See tables"RF Receive"foradditionaldetailson currentconsumptionand sensitivity. (3) For868 or915 MHz, see Figure23 forcurrentconsumptionwithregistersettingsoptimizedforsensitivity. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 69

-100 -80 -60 -40 -20 Input Power [dBm] Radio Current [mA] TA = 85°C TA = 25°C TA = -40°C -100 -80 -60 -40 -20 Input Power [dBm] Radio Current [mA] TA = 85°C TA = 25°C TA = -40°C -100 -80 -60 -40 -20 Input Power [dBm] Radio Current [mA] TA = 85°C TA = 25°C TA = -40°C -100 -80 -60 -40 -20 Input Power [dBm] Radio Current [mA] TA = 85°C TA = 25°C TA = -40°C 1.2 kBaud GFSK 250 kBaud GFSK 38.4 kBaud GFSK 500 kBaud MSK ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Figure23. TypicalRX CurrentConsumption Over Temperature and InputPower Level,868 MHz, Sensitivity-OptimizedSetting

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 CurrentConsumption, TransmitMode TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1)(2) FREQUENCY PATABLE OUTPUTPARAMETER MIN TYP MAX UNIT(MHz) Setting POWER (dBm) 0xC0 max. 26 mA 0xC4 +10 25 mA 315 0x51 0 15 mA 0x29 -6 15 mA 0xC0 max. 33 mA 0xC6 +10 29 mA 433 0x50 0 17 mA 0x2D -6 17 mA Currentconsumption,TX 0xC0 max. 36 mA 0xC3 +10 33 mA 868 0x8D 0 18 mA 0x2D -6 18 mA 0xC0 max. 35 mA 0xC3 +10 32 mA 915 0x8D 0 18 mA 0x2D -6 18 mA (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Reduced currentsetting(MDMCFG2.DEM_DCFILT_OFF = 1)givesa slightlylowercurrentconsumptionatthecostofa reductionin sensitivity.See tables"RF Receive"foradditionaldetailson currentconsumptionand sensitivity. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 71

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com TypicalTX CurrentConsumption, 315 MHz, 25°C OutputPATABLEPARAMETER Power VCC 2.0V 3.0V 3.6V UNITSetting (dBm) 0xC0 max. 27.5 26.4 28.1 Current 0xC4 +10 25.1 25.2 25.3 consumption, mA 0x51 0 14.4 14.6 14.7TX 0x29 -6 14.2 14.7 15.0 TypicalTX CurrentConsumption, 433 MHz, 25°C OutputPATABLEPARAMETER Power VCC 2.0V 3.0V 3.6V UNITSetting (dBm) 0xC0 max. 33.1 33.4 33.8 Current 0xC6 +10 28.6 28.8 28.8 consumption, mA 0x50 0 16.6 16.8 16.9TX 0x2D -6 16.8 17.5 17.8 TypicalTX CurrentConsumption, 868 MHz Output VCC 2.0V 3.0V 3.6VPATABLEPARAMETER Power UNITSetting TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C(dBm) consumption, mA TypicalTX CurrentConsumption, 915 MHz Output VCC 2.0V 3.0V 3.6VPATABLEPARAMETER Power UNITSetting TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C(dBm) consumption, mA

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 RF Receive,Overall TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Digitalchannelfilterbandwidth(2) 58 812 kHz

25 MHz to1 GHz -68 -57

Spuriousemissions(3)(4) dBm Above 1 GHz -66 -47 RX latency Serialoperation(5) 9 bit (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) User programmable.The bandwidthlimitsareproportionaltocrystalfrequency(givenvaluesassume a 26.0MHz crystal) (3) Typicalradiatedspuriousemissionis-49dBm measured attheVCO frequency (4) Maximum figureistheETSI EN 300 220 limit (5) Time fromstartofreceptionuntildataisavailableon thereceiverdataoutputpinisequalto9 bit. RF Receive,315 MHz TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) 2-FSK,1% packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwisenoted) DATA RATEPARAMETER TEST CONDITIONS MIN TYP MAX UNIT(kBaud) 0.6 14.3-kHzdeviation,58-kHzdigitalchannelfilterbandwidth -117 1.2 5.2-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(2) -111 Receiversensitivity 38.4 20-kHzdeviation,100-kHzdigitalchannelfilterbandwidth(3) -103 dBm 250 127-kHzdeviation,540-kHzdigitalchannelfilterbandwidth(4) -95

500 MSK, 812-kHzdigitalchannelfilterbandwidth(4) -86

(1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Sensitivitycan be tradedforcurrentconsumptionby settingMDMCFG2.DEM_DCFILT_OFF=1. The typicalcurrentconsumptionisthen reducedby approximately2 mA closetothesensitivitylimit.The sensitivityistypicallyreducedto-109dBm. (3) Sensitivitycan be tradedforcurrentconsumptionby settingMDMCFG2.DEM_DCFILT_OFF=1. The typicalcurrentconsumptionisthen reducedby approximately2 mA closetothesensitivitylimit.The sensitivityistypicallyreducedto-102dBm. (4) MDMCFG2.DEM_DCFILT_OFF=1 can notbe used fordatarates≥ 250 kBaud. RF Receive,433 MHz TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) 2-FSK,1% packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF = 0 (unless otherwisenoted) DATA RATEPARAMETER TEST CONDITIONS MIN TYP MAX UNIT(kBaud) 0.6 14.3-kHzdeviation,58-kHzdigitalchannelfilterbandwidth -114 1.2 5.2-kHzdeviation,58-kHzdigitalchannelfilterbandwidth(2) -111 Receiversensitivity 38.4 20-kHzdeviation,100-kHzdigitalchannelfilterbandwidth(3) -104 dBm 250 127-kHzdeviation,540-kHzdigitalchannelfilterbandwidth(4) -93

500 MSK, 812-kHzdigitalchannelfilterbandwidth(4) -85

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com RF Receive,868 MHz and 915 MHz TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) 1% packeterrorrate,20-bytepacketlength,Sensitivityoptimized,MDMCFG2.DEM_DCFILT_OFF = 0 (unlessotherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 0.6-kBauddatarate,2-FSK,14.3-kHzdeviation,58-kHz digitalchannel filterbandwidth (unlessotherwisenoted) Receiversensitivity -115 dBm 1.2-kBauddatarate,2-FSK,5.2-kHzdeviation,58-kHz digitalchannel filterbandwidth (unlessotherwisenoted) -109 Receiversensitivity(2) dBm2-GFSK modulationby settingMDMCFG2.MOD_FORMAT=2, -109GaussianfilterwithBT = 0.5 Saturation FIFOTHR.CLOSE_IN_RX=0 (3) -28 dBm -100-kHzoffset 39Adjacentchannel Desiredchannel3 dB above thesensitivitylimit, dBrejection 100 kHz channelspacing(4) +100-kHz offset 39 IFfrequency152 kHz,desiredchannel3 dB aboveImage channelrejection 29 dBthesensitivitylimit ±2 MHz offset -48 dBm Blocking Desiredchannel3 dB above thesensitivitylimit(5) ±10 MHz offset -40 dBm 38.4-kBauddatarate,2-FSK,20-kHz deviation,100-kHz digitalchannel filterbandwidth (unlessotherwisenoted) -102 Receiversensitivity(6) dBm2-GFSK modulationby settingMDMCFG2.MOD_FORMAT = 2, -101GaussianfilterwithBT = 0.5 Saturation FIFOTHR.CLOSE_IN_RX=0 (3) -19 dBm -200-kHzoffset 20Adjacentchannel Desiredchannel3 dB above thesensitivitylimit, dBrejection 200 kHz channelspacing(5) +200-kHz offset 25 Image channelrejectionIFfrequency152 kHz,Desiredchannel3 dB above thesensitivitylimit 23 dB ±2-MHz offset -48 dBm Blocking Desiredchannel3 dB above thesensitivitylimit(5) ±10-MHz offset -40 dBm 250-kBaud datarate,2-FSK,127-kHz deviation,540-kHz digitalchannel filterbandwidth (unlessotherwisenoted) -90 Receiversensitivity(7) dBm2-GFSK modulationby settingMDMCFG2.MOD_FORMAT = 2, -90GaussianfilterwithBT = 0.5 Saturation FIFOTHR.CLOSE_IN_RX=0 (3) -19 dBm -750-kHzoffset 24Adjacentchannel Desiredchannel3 dB above thesensitivitylimit, dBrejection 750-kHzchannelspacing(8) +750-kHz offset 30 Image channelrejectionIFfrequency304 kHz,Desiredchannel3 dB above thesensitivitylimit 18 dB ±2-MHz offset -53 dBm Blocking Desiredchannel3 dB above thesensitivitylimit(8) ±10-MHz offset -39 dBm 500-kBaud datarate,MSK, 812-kHz digitalchannel filterbandwidth (unlessotherwisenoted) Receiversensitivity(7) -84 dBm Image channelrejectionIFfrequency355 kHz,Desiredchannel3 dB above thesensitivitylimit -2 dB ±2-MHz offset -53 dBm Blocking Desiredchannel3 dB above thesensitivitylimit(9) ±10-MHz offset -38 dBm (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Sensitivitycan be tradedforcurrentconsumptionby settingMDMCFG2.DEM_DCFILT_OFF=1. The typicalcurrentconsumptionisthen reducedby approximately2 mA closetothesensitivitylimit.The sensitivityistypicallyreducedto-107dBm (3) See designnoteDN010 Close-inReceptionwithCC1101 (SWRA147 ). (4) See Figure24 forblockingperformanceatotheroffsetfrequencies. (5) See Figure25 forblockingperformanceatotheroffsetfrequencies. (6) Sensitivitycan be tradedforcurrentconsumptionby settingMDMCFG2.DEM_DCFILT_OFF=1. The typicalcurrentconsumptionisthen reducedby approximately2 mA closetothesensitivitylimit.The sensitivityistypicallyreducedto-100dBm. (7) MDMCFG2.DEM_DCFILT_OFF = 1 cannotbe used fordatarates≥ 250 kBaud. (8) See Figure26 forblockingperformanceatotheroffsetfrequencies. (9) See Figure27 forblockingperformanceatotheroffsetfrequencies.

-20 -10 -40 -30 -20 -10 0 10 20 30 40 Offs e t [M H z] Blocking [dB] -20 -10 Offs e t [M H z] Selectivity [dB] -20 -10 -40 -30 -20 -10 0 10 20 30 40 Offs e t [M H z] Blocking [dB] -10 Offs e t [M H z] Selectivity [dB] ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 NOTE: 868.3MHz, 2-FSK,5.2-kHzdeviation,IFfrequencyis152.3kHz,digitalchannelfilterbandwidthis58 kHz Figure24. TypicalSelectivityat1.2-kBaudData Rate NOTE: 868 MHz, 2-FSK,20 kHz deviation,IFfrequencyis152.3kHz,digitalchannelfilterbandwidthis100 kHz Figure25. TypicalSelectivityat38.4-kBaudData Rate Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 75

-20 -10 -40 -30 -20 -10 0 10 20 30 40 Offs e t [M H z] Blocking [dB] -20 -10 -3 -2 -1 0 1 2 3 Offs e t [M H z] Selectivity [dB] -20 -10 -40 -30 -20 -10 0 10 20 30 40 Offs e t [M H z] Blocking [dB] -20 -10 -3 -2 -1 0 1 2 3 Offs e t [M H z] Selectivity [dB] ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com NOTE: 868 MHz, 2-FSK,IFfrequencyis304 kHz,digitalchannelfilterbandwidthis540 kHz Figure26. TypicalSelectivityat250-kBaud Data Rate NOTE: 868 MHz, 2-FSK,IFfrequencyis355 kHz,digitalchannelfilterbandwidthis812 kHz Figure27. TypicalSelectivityat500-kBaud Data Rate

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 TypicalSensitivity,315 MHz, SensitivityOptimizedSetting VCC 2.0V 3.0V 3.6V PARAMETER DATA RATE (kBaud) UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 1.2 -112 -112 -110 -112 -111 -109 -112 -111 -108 Sensitivity, 38.4 -105 -105 -104 -105 -103 -102 -105 -104 -102 dBm315 MHz 250 -95 -95 -92 -94 -95 -92 -95 -94 -91 TypicalSensitivity,433 MHz, SensitivityOptimizedSetting VCC 2.0V 3.0V 3.6V PARAMETER DATA RATE (kBaud) UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 1.2 -111 -110 -108 -111 -111 -108 -111 -110 -107 Sensitivity, 38.4 -104 -104 -101 -104 -104 -101 -104 -103 -101 dBm433 MHz 250 -93 -94 -91 -93 -93 -90 -93 -93 -90 TypicalSensitivity,868 MHz, SensitivityOptimizedSetting VCC 2.0V 3.0V 3.6V PARAMETER DATA RATE (kBaud) UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 1.2 -109 -109 -107 -109 -109 -106 -109 -108 -106 38.4 -102 -102 -100 -102 -102 -99 -102 -101 -99Sensitivity, dBm868 MHz 250 -90 -90 -88 -89 -90 -87 -89 -90 -87 500 -84 -84 -81 -84 -84 -80 -84 -84 -80 TypicalSensitivity,915 MHz, SensitivityOptimizedSetting VCC 2.0V 3.0V 3.6V PARAMETER DATA RATE (kBaud) UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 1.2 -109 -109 -107 -109 -109 -106 -109 -108 -105 38.4 -102 -102 -100 -102 -102 -99 -103 -102 -99Sensitivity, dBm915 MHz 250 -92 -92 -89 -92 -92 -88 -92 -92 -88 500 -87 -86 -81 -86 -86 -81 -86 -85 -80 Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 77

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com RF Transmit TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1),PTX = +10 dBm (unlessotherwisenoted) FREQPARAMETER TEST CONDITIONS MIN TYP MAX UNIT(MHz) 315 122 + j31 Differentialload 433 116 + j41 Ωimpedance(2) 868,915 86.5+ j43 315 +12 433 +13Outputpower,highest Deliveredtoa 50Ω single-endedloadviaCC430 reference dBmsetting(3) design's RF matchingnetwork868 +11 915 +11 Outputpower,lowest Deliveredtoa 50Ω single-endedloadviaCC430 reference -30 dBmsetting(3) design's RF matchingnetwork Second harmonic -56 433 Thirdharmonic -57 Second harmonic -50Harmonics, 868 dBmradiated(4)(5)(6) Thirdharmonic -52 Second harmonic -50 915 Thirdharmonic -54 Frequenciesbelow960 MHz < -38 315 +10 dBm CW Frequenciesabove 960 MHz < -48 Frequenciesbelow1 GHz -45 433 +10 dBm CW Frequenciesabove 1 GHz < -48 Harmonics,conducted dBm Second harmonic -59 868 +10 dBm CW Otherharmonics < -71 Second harmonic -53 915 +11 dBm CW (7) Otherharmonics < -47 Frequenciesbelow960 MHz < -58 315 +10 dBm CW Frequenciesabove 960 MHz < -53 Frequenciesbelow1 GHz < -54 Frequenciesabove 1 GHz < -54433 +10 dBm CW Frequencieswithin47 to74,87.5to118, < -63Spuriousemissions, 174 to230,470 to862 MHz conducted,harmonics dBm Frequenciesbelow1 GHz < -46notincluded(8) Frequenciesabove 1 GHz < -59868 +10 dBm CW Frequencieswithin47 to74,87.5to118, < -56174 to230,470 to862 MHz Frequenciesbelow960 MHz < -49 915 +11 dBm CW Frequenciesabove 960 MHz < -63 TX latency(9) Serialoperation 8 bits (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) Differentialimpedance as seen fromtheRF-port(RF_P and RF_N) towardstheantenna.FollowtheCC430 referencedesignsavailable fromtheTIwebsite. (3) Outputpower isprogrammable,and fullrangeisavailableinallfrequencybands.Outputpower may be restrictedby regulatorylimits. See alsoapplicationnoteAN050 UsingtheCC1101 intheEuropean 868 MHz SRD Band (SWRA146 )and designnoteDN013 Programming OutputPower on CC1101 (SWRA151 ),whichgivestheoutputpower and harmonicswhen usingmulti-layerinductors. The outputpower isthentypically+10 dBm when operatingat868 or915 MHz. (4) The antennasused duringtheradiatedmeasurements (SMAFF-433 fromR.W.Badlandand Nearson S331 868 or915)playa partin attenuatingtheharmonics. (5) Measured on EM430F6137RF900 withCW, maximum outputpower (6) Allharmonicsarebelow-41.2dBm when operatinginthe902 to928 MHz band. (7) Requirementis-20dBc underFCC 15.247 (8) AllradiatedspuriousemissionsarewithinthelimitsofETSI.Alsosee designnoteDN017 CC11xx 868/915MHz RF Matching (SWRA168 ). (9) Time fromsamplingthedataon thetransmitterdatainputpinuntilitisobservedon theRF outputports

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Optimum PATABLE SettingsforVariousOutput Power Levelsand Frequency Bands TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) PATABLE SETTING OUTPUT POWER (dBm)

315 MHz 433 MHz 868 MHz 915 MHz

-30 0x12 0x05 0x03 0x03 -12 0x33 0x26 0x25 0x25 -6 0x29 0x2D 0x2D 0x2D 0 0x51 0x50 0x8D 0x8D 10 0xC4 0xC4 0xC3 0xC3 max. 0xC0 0xC0 0xC0 0xC0 (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 79

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com TypicalOutput Power, 315 MHz (1) VCC 2.0V 3.0V 3.6V PARAMETER PATABLE Setting UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 0xC0 (max) 11.9 11.8 11.8 0xC4 (10dBm) 10.3 10.3 10.3 Outputpower, 0xC6 (default) 9.3 dBm315 MHz 0x51 (0dBm) 0.7 0.6 0.7 (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). TypicalOutput Power, 433 MHz (1) VCC 2.0V 3.0V 3.6V PARAMETER PATABLE Setting UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C 0xC0 (max) 12.6 12.6 12.6 0xC4 (10dBm) 10.3 10.2 10.2 Outputpower, 0xC6 (default) 10.0 dBm433 MHz 0x50 (0dBm) 0.3 0.3 0.3 (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). TypicalOutput Power, 868 MHz (1) VCC 2.0V 3.0V 3.6V PARAMETER PATABLE Setting UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C Outputpower, 0xC6 (default) 8.8 dBm868 MHz (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). TypicalOutput Power, 915 MHz (1) VCC 2.0V 3.0V 3.6V PARAMETER PATABLE Setting UNIT TA -40°C 25°C 85°C -40°C 25°C 85°C -40°C 25°C 85°C Outputpower, 0xC6 (default) 8.8 dBm915 MHz (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49).

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Frequency SynthesizerCharacteristics TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) MIN figuresaregivenusinga 27-MHz crystal.TYP and MAX figuresaregivenusinga 26-MHz crystal. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Programmed frequencyresolution(2) 26 to27 MHz crystal 397 fXOSC /216 412 Hz Synthesizerfrequencytolerance(3) ±40 ppm 50-kHzoffsetfromcarrier -95 100-kHzoffsetfromcarrier -94 200-kHzoffsetfromcarrier -94 500-kHzoffsetfromcarrier -98 RF carrierphase noise dBc/Hz 1-MHz offsetfromcarrier -107 2-MHz offsetfromcarrier -112 5-MHz offsetfromcarrier -118 10-MHz offsetfromcarrier -129 PLL turn-onand hop time(4) Crystaloscillatorrunning 85.1 88.4 µs PLL RX toTX settlingtime(5) 9.3 9.6 µs PLL TX toRX settlingtime(6) 20.7 21.5 µs PLL calibrationtime(7) 694 721 µs (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). (2) The resolution(inHz) isequalforallfrequencybands. (3) Depends on crystalused.Requiredaccuracy(includingtemperatureand aging)depends on frequencyband and channelbandwidth/ spacing. (4) Time fromleavingtheIDLE stateuntilarrivingintheRX, FSTXON, orTX statewhen notperformingcalibration. (5) Settlingtimeforthe1-IFfrequencystepfromRX toTX (6) Settlingtimeforthe1-IFfrequencystepfromTX toRX (7) Calibrationcan be initiatedmanuallyorautomaticallybeforeenteringorafterleavingRX/TX Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 81

-120 -100 -80 -60 -40 -20 -120 -100 -80 -60 -40 -20 0 Input Pow e r [dB m ] RSSI Readout [dBm] 1.2k B aud 38.4k B aud -120 -100 -80 -60 -40 -20 -120 -100 -80 -60 -40 -20 0 Input Pow e r [dB m ] RSSI Readout [dBm] 250k B aud 500k B aud ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com TypicalRSSI_offsetValues TA = 25°C, VCC = 3 V (unlessotherwisenoted)(1) RSSI_OFFSET (dB) DATA RATE (kBaud)

433 MHz 868 MHz

1.2 74 74 38.4 74 74 250 74 74 500 74 74 (1) Allmeasurement resultsareobtainedusingtheEM430F6137RF900 withBOM accordingtotestedfrequencyrange(seeTable49). Figure28. TypicalRSSI Value vs InputPower LevelforDifferentData Rates at868 MHz

RF_N RF_P AVCC_RFAVCC_RFAVCC_RFAVCC_RFGUARD C7C3 C23 C29 C28 C27 C24C25 C26 SMA STRAIGHT JACK, SMT R_BIAS 26MHz C22 C21 RF_XOUT RF_XIN VDD DVCC VDD C11 C10 C19 DVCCVCORE TDOTDI/TCLKTMS (JTAG / SBW signals) AVDD C16 C17 C18 VDD C14 C15 R2 C20 DVCC nRST/NMI/SBWTDIO TCK TEST/SBWTCK AVDD C12 C13 AVCC AVSS (May be added close to the respective pinsto reduce emissions at 5GHz to levelsrequired by ETSI.) CC430F61xx 1764 1863 1962 2061 2160 2259 2952 3051 3150 3249 2358 2457 2556 2655 2754 2853 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 APPLICATION CIRCUIT Fora completereferencedesignincludinglayoutsee theCC430 WirelessDevelopmentToolsand related documentation. Figure29. TypicalApplicationCircuitCC430F61xx Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 83

RF_NRF_P AVCC_RFAVCC_RFAVCC_RFAVCC_RFGUARD C7C3 C23 C29 C28 C27 C24C25 C26 SMA STRAIGHT JACK, SMT R_BIAS 26MHz C22 C21 RF_XOUT RF_XIN VDD DVCC VDD C11 C10 C19 DVCCVCORE TDOTDI/TCLK (JTAG / SBW signals) AVDD C16 C17 C18 VDD C14 C15 R2 C20 DVCC nRST/NMI/SBWTDIO TCK TEST/SBWTCK AVDD C12 C13 AVCC TMS AVSS 12114321 1098765 13 14 15 16 17 18 21 22 24252627282930313233343536 47 46 45 44 43 40 39 CC430F51xx (May be added close to the respective pinsto reduce emissions at 5GHz to levelsrequired by ETSI.) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Fora completereferencedesignincludinglayout,see theCC430 WirelessDevelopmentToolsand related documentation. Figure30. TypicalApplicationCircuitCC430F51xx

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table49.BillofMaterials COMPONENTS FOR 315 MHz FOR 433 MHz FOR 868,915 MHz COMMENT C1,3,4,5,7,9,11,13,15 100 nF Decouplingcapacitors C8,10,12,14 10 µF Decouplingcapacitors C2,6,16,17,18 2 pF Decouplingcapacitors C19 470 nF VCORE capacitor RST decouplingcapC20 2.2nF (optimizedforSBW) Load capacitorsforC21,22 27 pF 26 MHz crystal(1) R1 56 kΩ R_BIAS (±1% required) R2 47kΩ RST pullup L1,2 Capacitors:220 pF 0.016µH 0.012µH L3,4 0.033µH 0.027µH 0.018µH L5 0.033µH 0.047µH 0.015µH L6 dnp(2) dnp(2) 0.0022µH L7 0.033µH 0.051µH 0.015µH C23 dnp(2) 2.7pF 1 pF C24 220 pF 220 pF 100 pF C25 6.8pF 3.9pF 1.5pF C26 6.8pF 3.9pF 1.5pF C27 220 pF 220 pF 1.5pF C28 10 pF 4.7pF 8.2pF C29 220 pF 220 pF 1.5pF (1) The loadcapacitanceC L seen by thecrystalisC L = 1/((1/C21)+(1/C22))+ C parasitic.The parasiticcapacitanceC parasiticincludespin capacitanceand PCB straycapacitance.Itcan be typicallyestimatedtobe approximately2.5pF. (2) dnp = do notpopulate Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 85

P1.0/P1MAP0(/S18) P1.1/P1MAP1(/S19) P1.2/P1MAP2(/S20) P1.3/P1MAP3(/S21) P1.4/P1MAP4(/S22) Direction 0: Input 1: Output P1SEL.x 0P1DIR.x P1IN.x P1IRQ.x EN to Port Mapping from Port Mapping P1OUT .x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x 0DVSS DVCC P1DS.x 0: Low drive 1: High drive D from Port Mapping S18...S22 (n/a CC430F514x and CC430F512x) LCDS18...LCDS22 Pad Logic P1REN.x P1MAP .x = PMAP_ANALOG Bus Keeper ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com INPUT/OUTPUT SCHEMATICS PortP1,P1.0toP1.4,Input/OutputWith SchmittTrigger NOTE: CC430F514x and CC430F512x devicesdo notprovideLCD functionality.

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table50.PortP1 (P1.0toP1.4)Pin Functions CONTROL BITS/SIGNALS PIN NAME (P1.x) x FUNCTION LCDS19 toP1DIR.x P1SEL.x P1MAPx LCDS22 (1) P1.0/P1MAP/S18 0 P1.0(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S18 (notavailableon CC430F514x and CC430F512x) X X X 1 P1.1/P1MAP1/S19 1 P1.1(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S19 (notavailableon CC430F514x and CC430F512x) X X X 1 P1.2/P1MAP2/S20 2 P1.2(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S22 (notavailableon CC430F514x and CC430F512x) X X X 1 P1.3/P1MAP3/S21 3 P1.3(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S21 (notavailableon CC430F514x and CC430F512x) X X X 1 P1.4/P1MAP4/S22 4 P1.4(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S22 (notavailableon CC430F514x and CC430F512x) X X X 1 (1) LCDSx notavailableinCC430F514x and CC430F512x. (2) Accordingtomapped function(seeTable10) Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 87

P1.5/P1MAP5(/R23) P1.6/P1MAP6(/R13) P1.7/P1MAP7(/R03) P1SEL.x 0P1DIR.x P1IN.x P1IRQ.x EN to Port Mapping from Port Mapping P1OUT .x Interrupt Edge Select Q EN Set P1SEL.x P1IES.x P1IFG.x P1IE.x 0DVSS DVCC P1DS.x 0: Low drive 1: High drive D from Port Mapping to LCD_B Pad Logic Bus Keeper Direction 0: Input 1: Output P1REN.x P1MAP .x = PMAP_ANALOG (n/a CC430F514x and CC430F512x ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PortP1,P1.5toP1.7,Input/OutputWith SchmittTrigger NOTE: CC430F514x and CC430F512x devicesdo notprovideLCD functionality.

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Table51.PortP1 (P1.5toP1.7)Pin Functions CONTROL BITS/SIGNALS PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1MAPx P1.5/P1MAP5/R23 5 P1.5(I/O) I:0;O: 1 0 X Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) R23 (2)(notavailableon CC430F514x and CC430F512x) X 1 = 31 P1.6/P1MAP6/R13/ 6 P1.6(I/O) I:0;O: 1 0 X LCDREF Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) R13/LCDREF (2)(notavailableon CC430F514x and X 1 = 31CC430F512x) P1.7/P1MAP7/R03 7 P1.7(I/O) I:0;O: 1 0 X Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) R03 (2)(notavailableon CC430F514x and CC430F512x) X 1 = 31 (1) Accordingtomapped function(seeTable10) (2) SettingP1SEL.x bittogetherwithP1MAPx = PM_ANALOG disablestheoutputdriverand theinputSchmitttrigger. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 89

P2.0/P2MAP0/CB0(/A0) P2.1/P2MAP2/CB1(/A1) P2.2/P2MAP2/CB2(/A2) P2.3/P2MAP3/CB3(/A3) Direction 0: Input 1: Output P2SEL.x 0P2DIR.x P2IN.x P2IRQ.x EN to Port Mapping from Port Mapping P2OUT .x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x 0DVSS DVCC P2DS.x 0: Low drive 1: High drive D from Port Mapping To Comparator_B from Comparator_B Pad Logic To ADC10_A (n/a CC430F512x) INCHx = x CBPD.x P2REN.x P2MAP .x = PMAP_ANALOG Bus Keeper ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PortP2,P2.0toP2.3,Input/OutputWith SchmittTrigger

P2.4/P2MAP4/CB4(/A4/VeREF-) P2SEL.x 0P2DIR.x P2IN.x P2IRQ.x EN to Port Mapping from Port Mapping P2OUT .x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x 0DVSS DVCC P2DS.x 0: Low drive 1: High drive D from Port Mapping To Comparator_B from Comparator_B Pad Logic to ADC10_A INCHx = x (n/a CC430F512x) Bus Keeper ADC10_A ext. Reference Input VeREF- (n/a CC430F512x) Direction 0: Input 1: Output CBPD.x P2REN.x P2MAP .x = PMAP_ANALOG ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP2,P2.4,Input/OutputWith SchmittTrigger Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 91

P2.5/P2MAP5/CB5(/A5/VREF+/VeREF+) P2SEL.x 0P2DIR.x P2IN.x P2IRQ.x EN to Port Mapping from Port Mapping P2OUT .x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x 0DVSS DVCC P2DS.x 0: Low drive 1: High drive D from Port Mapping To Comparator_B from Comparator_B Pad Logic to ADC10_A INCHx = x (n/a CC430F512x) Bus Keeper ADC10_A ext. Reference Input VeREF+ 1.5V/2.0V/2.5V from shared REF (n/a CC430F512x) (n/a CC430F512x) Direction 0: Input 1: Output CBPD.x P2REN.x P2MAP .x = PMAP_ANALOG REFCTL0.REFOUT Buffer ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PortP2,P2.5,Input/OutputWith SchmittTrigger

P2.6/P2MAP6(/CB6/A6) P2.7/P2MAP7(/CB7/A7) Direction 0: Input 1: Output P2SEL.x 0P2DIR.x P2IN.x P2IRQ.x EN to Port Mapping from Port Mapping P2OUT .x Interrupt Edge Select Q EN Set P2SEL.x P2IES.x P2IFG.x P2IE.x 0DVSS DVCC P2DS.x 0: Low drive 1: High drive D from Port Mapping To Comparator_B from Comparator_B Pad Logic To ADC10_A INCHx = x (n/a )CC430F514x and CC430F512x (n/a )CC430F514x and CC430F512x (n/a )CC430F514x and CC430F512x CBPD.x P2REN.x P2MAP .x = PMAP_ANALOG Bus Keeper ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP2,P2.6and P2.7,Input/OutputWith SchmittTrigger CC430F514x and CC430F512x devicesdo notprovideanalogfunctionalityon portP2.6and P2.7pins. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 93

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table52.PortP2 (P2.0toP2.7)Pin Functions CONTROL BITS/SIGNALS PIN NAME (P2.x) x FUNCTION P2DIR.x P2SEL.x P2MAPx CBPD.x P2.0/P2MAP0/CB0 0 P2.0(I/O) I:0;O: 1 0 X 0 (/A0) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A0 (notavailableon CC430F512x) (2) X 1 = 31 X CB0 (3) X X X 1 P2.1/P2MAP1/CB1 1 P2.1(I/O) I:0;O: 1 0 X 0 (/A1) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A1 (notavailableon CC430F512x) (2) X 1 = 31 X CB1 (3) X X X 1 P2.2/P2MAP2/CB2 2 P2.2(I/O) I:0;O: 1 0 X 0 (/A2) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A2 (notavailableon CC430F512x) (2) X 1 = 31 X CB2 (3) X X X 1 P2.3/P2MAP3/CB3 3 P2.3(I/O) I:0;O: 1 0 X 0 (/A3) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A3 (notavailableon CC430F512x) (2) X 1 = 31 X CB3 (3) X X X 1 P2.4/P2MAP4/CB4 4 P2.4(I/O) I:0;O: 1 0 X 0 (/A4/VeREF-) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A4/VeREF- (notavailableon CC430F512x) (2) X 1 = 31 X CB4 (3) X X X 1 P2.5/P2MAP5/CB5 5 P2.5(I/O) I:0;O: 1 0 X 0 (/A5/VREF+/VeREF+) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A5/VREF+VeREF+ (notavailableon CC430F512x) (2) X 1 = 31 X CB5 (3) X X X 1 P2.6/P2MAP6(/CB6) 6 P2.6(I/O) I:0;O: 1 0 X 0 (/A6) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A6 (notavailableon CC430F514x and X 1 = 31 XCC430F512x) (2) CB6 (notavailableon CC430F514x and X X X 1CC430F512x) (3) P2.7/P2MAP7(/CB7) 7 P2.7(I/O) I:0;O: 1 0 X 0 (/A7) Mapped secondarydigitalfunction(seeTable10) 0;1(1) 1 ≤ 30(1) 0 A7 (notavailableon CC430F514x and X 1 = 31 XCC430F512x) (2) CB7 (notavailableon CC430F514x and X X X 1CC430F512x) (3) (1) Accordingtomapped function(seeTable10) (2) SettingP2SEL.x bittogetherwithP2MAPx = PM_ANALOG disablestheoutputdriverand theinputSchmitttrigger. (3) SettingtheCBPD.x bitdisablestheoutputdriverand theinputSchmitttriggertopreventparasiticcrosscurrentswhen applyinganalog signals.SelectingtheCBx inputpintothecomparatormultiplexerwiththeCBx bitsautomaticallydisablesoutputdriverand inputbuffer forthatpin,regardlessofthestateoftheassociatedCBPD.x bit.

P3.4/P3MAP4(/S14) P3.5/P3MAP5(/S15) P3.6/P3MAP6(/S16) P3.7/P3MAP7(/S17) P3.0/P3MAP0(/S10) P3.1/P3MAP1(/S11) P3.2/P3MAP2(/S12) P3.3/P3MAP3(/S13) Direction 0: Input 1: Output P3SEL.x 0P3DIR.x P3IN.x EN to Port Mapping from Port Mapping P3OUT .x 0DVSS DVCC P3DS.x 0: Low drive 1: High drive D from Port Mapping S10...S17 LCDS10...LCDS17 Pad Logic P3REN.x P3MAP .x = PMAP_ANALOG Bus Keeper (n/a CC430F514x and CC430F512x) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP3,P3.0toP3.7,Input/OutputWith SchmittTrigger CC430F514x and CC430F512x devicesdo notprovideLCD functionality. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 95

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table53.PortP3 (P3.0toP3.7)Pin Functions CONTROL BITS/SIGNALS P3.0/P3MAP0/S10 0 P3.0(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S10 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.1/P3MAP1/S11 1 P3.1(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S11 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.2/P3MAP7/S12 2 P3.2(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S12 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.3/P3MAP3/S13 3 P3.3(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S13 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.4/P3MAP4/S14 4 P3.4(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S14 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.5/P3MAP5/S15 5 P3.5(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S15 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.6/P3MAP6/S16 6 P3.6(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S16 (notavailableon CC430F514x and CC430F512x) X X X 1 P3.7/P3MAP7/S17 7 P3.7(I/O) I:0;O: 1 0 X 0 Mapped secondarydigitalfunction(seeTable10) 0;1(2) 1 ≤ 30(2) 0 Outputdriverand inputSchmitttriggerdisabled X 1 = 31 0 S17 (notavailableon CC430F514x and CC430F512x) X X X 1 (1) LCDSx notavailableinCC430F514x and CC430F512x. (2) Accordingtomapped function(seeTable10)

P4.4/S6 P4.5/S7 P4.6/S8 P4.7/S9 P4.0/S2 P4.1/S3 P4.2/S4 P4.3/S5 Direction 0:□Input 1:□Output P4SEL.x 0P4DIR.x P4IN.x EN Not□Used DVSS P4OUT .x 0DVSS DVCC P4DS.x 0:□Low□drive 1:□High□drive D S2...S9 LCDS2...LCDS9 Pad□Logic P4REN.x Bus Keeper ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP4,P4.0toP4.7,Input/OutputWith SchmittTrigger(CC430F614x only) Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 97

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table54.PortP4 (P4.0toP4.7)Pin Functions(CC430F614x only) CONTROL BITS/SIGNALS PIN NAME (P4.x) x FUNCTION P4.0/P4MAP0/S2 0 P4.0(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S2 X X 1 P4.1/P4MAP1/S3 1 P4.1(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S3 X X 1 P4.2/P4MAP7/S4 2 P4.2(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S4 X X 1 P4.3/P4MAP3/S5 3 P4.3(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S5 X X 1 P4.4/P4MAP4/S6 4 P4.4(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S6 X X 1 P4.5/P4MAP5/S7 5 P4.5(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S7 X X 1 P4.6/P4MAP6/S8 6 P4.6(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S8 X X 1 P4.7/P4MAP7/S9 7 P4.7(I/O) I:0;O: 1 0 0 N/A 0 1 0 DVSS 1 1 0 S9 X X 1

P5.0/XIN P5SEL.0 0P5DIR.0 P5IN.0 EN Module□X□IN Module□X□OUT P5OUT .0 0DVSS DVCC P5REN.0 Pad□Logic P5DS.x 0:□Low□drive 1:□High□drive D Bus Keeper to□XT1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP5,P5.0,Input/OutputWith SchmittTrigger Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 99

P5.1/XOUTP5SEL.0 XT1BYPASS 0P5DIR.1 P5IN.1 EN Module□X□IN Module□X□OUT P5OUT .1 0DVSS DVCC P5REN.1 Pad□Logic P5DS.x 0:□Low□drive 1:□High□drive D Bus Keeper to□XT1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PortP5,P5.1,Input/OutputWith SchmittTrigger Table55.PortP5 (P5.0and P5.1)Pin Functions CONTROL BITS/SIGNALS (1) PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.0 P5SEL.1 XT1BYPASS P5.0/XIN 0 P5.0(I/O) I:0;O: 1 0 X X XIN crystalmode (2) X 1 X 0 XIN bypassmode (2) X 1 X 1 P5.1/XOUT 1 P5.1(I/O) I:0;O: 1 0 X X XOUT crystalmode (3) X 1 X 0 P5.1(I/O)(3) X 1 X 1 (1) X = Don 'tcare (2) SettingP5SEL.0 causesthegeneral-purposeI/Otobe disabled.PendingthesettingofXT1BYPASS, P5.0isconfiguredforcrystal mode orbypassmode. (3) SettingP5SEL.0 causesthegeneral-purposeI/Otobe disabledincrystalmode. When usingbypassmode, P5.1can be used as general-purposeI/O.

P5.2/S0 P5.3/S1 P5.4/S23 P5SEL.x 0P5DIR.x P5IN.x EN Not Used DVSS P5OUT .x 0DVSS DVCC P5REN.x Pad Logic P5DS.x 0: Low drive 1: High drive D Bus Keeper LCDS0(P5.2)/LCDS1(P5.3)/LCDS23(P5.4) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortP5,P5.2toP5.4,Input/OutputWith SchmittTrigger(CC430F614x only) Table56.PortP5 (P5.2toP5.3)Pin Functions(CC430F614x only) CONTROL BITS/SIGNALS PIN NAME (P5.x) x FUNCTION N/A 0 1 0 DVSS 1 1 0 S0 X X 1 N/A 0 1 0 DVSS 1 1 0 S1 X X 1 Table57.PortP5 (P5.4)Pin Functions(CC430F614x only) CONTROL BITS/SIGNALS PIN NAME (P5.x) x FUNCTION P5DIR.x P5SEL.x LCDS23 N/A 0 1 0 DVSS 1 1 0 S23 X X 1 Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 101

P5.5/COM3/S24 P5.6/COM2/S25 P5.7/COM1/S26 P5SEL.x P5DIR.x P5IN.x P5OUT .x 0DVSS DVCC P5REN.x Pad□Logic P5DS.x 0:□Low□drive 1:□High□drive Bus Keeper COM3(P5.5)/COM2(P5.6)/COM1(P5.7) LCDS24(P5.5)/LCDS25(P5.6)/LCDS26(P5.7) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com PortP5,P5.5toP5.7,Input/OutputWith SchmittTrigger(CC430F614x only) Table58.PortP5 (P5.5toP5.7)Pin Functions(CC430F614x only) CONTROL BITS/SIGNALS PIN NAME (P5.x) x FUNCTION LCDS24 toP5DIR.x P5SEL.x LCDS26 P5.5/COM3/S24 5 P5.5(I/O) I:0;O: 1 0 0 COM3 (1) X 1 X S24 (1) X 0 1 P5.6/COM2/S25 6 P5.6(I/O) I:0;O: 1 0 0 COM2 (1) X 1 X S25 (1) X 0 1 P5.7/COM1/S26 7 P5.7(I/O) I:0;O: 1 0 0 COM1 (1) X 1 X S26 (1) X 0 1 (1) SettingP5SEL.x bitdisablestheoutputdriverand theinputSchmitttrigger.

PJ.1/TDI/TCLK PJ.2/TMS PJ.3/TCK From□JTAG 0PJDIR.x PJIN.x EN From□JTAG PJOUT .x 0DVSS DVCC PJREN.x Pad□Logic PJDS.x 0:□Low□drive 1:□High□drive D DVSS To□JTAG PJ.0/TDO From□JTAG 0PJDIR.0 PJIN.0 From□JTAG PJOUT .0 0DVSS DVCC PJREN.0 Pad□Logic PJDS.0 0:□Low□drive 1:□High□drive DVCC ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 PortJ,J.0JTAG pinTDO, Input/OutputWith SchmittTriggeror Output PortJ,J.1toJ.3JTAG pinsTMS, TCK, TDI/TCLK,Input/OutputWith SchmittTriggeror Output Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 103

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table59.PortPJ (PJ.0toPJ.3)Pin Functions CONTROL BITS/ SIGNALS (1) PIN NAME (PJ.x) x FUNCTION PJDIR.x PJ.0/TDO 0 PJ.0(I/O)(2) I:0;O: 1 TDO (3) X PJ.1/TDI/TCLK 1 PJ.1(I/O)(2) I:0;O: 1 TDI/TCLK(3)(4) X PJ.2/TMS 2 PJ.2(I/O)(2) I:0;O: 1 TMS (3)(4) X PJ.3/TCK 3 PJ.3(I/O)(2) I:0;O: 1 TCK (3)(4) X (1) X = Don 'tcare (2) Defaultcondition (3) The pindirectioniscontrolledby theJTAG module. (4) InJTAG mode, pullupsareactivatedautomaticallyon TMS, TCK, and TDI/TCLK.PJREN.x aredon'tcare.

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 Device DescriptorStructures Table 60 liststhe contentof the device descriptortag-length-value(TLV) structureforCC430F614x and CC430F514x devicetypes. Table61 liststhecontentofthedevicedescriptortag-length-value(TLV)structureforCC430F512x devicetypes. Table60.Device DescriptorTableCC430F614x and CC430F514x F6147 F6145 F6143 F5147 F5145 F5143SizeDescription Address bytes Value Value Value Value Value Value InfoBlock Infolength 01A00h 1 06h 06h 06h 06h 06h 06h CRC length 01A01h 1 06h 06h 06h 06h 06h 06h CRC value 01A02h 2 perunit perunit perunit perunit perunit perunit DeviceID 01A04h 1 035h 036h 037h 038h 039h 03Ah DeviceID 01A05h 1 081h 081h 081h 081h 081h 081h Hardware revision 01A06h 1 perunit perunit perunit perunit perunit perunit Firmwarerevision 01A07h 1 perunit perunit perunit perunit perunit perunit Die Record DieRecord Tag 01A08h 1 08h 08h 08h 08h 08h 08h DieRecord length 01A09h 1 0Ah 0Ah 0Ah 0Ah 0Ah 0Ah Lot/WaferID 01A0Ah 4 perunit perunit perunit perunit perunit perunit DieX position 01A0Eh 2 perunit perunit perunit perunit perunit perunit DieY position 01A10h 2 perunit perunit perunit perunit perunit perunit Testresults 01A12h 2 perunit perunit perunit perunit perunit perunit ADC10 ADC10 01A14h 1 13h 13h 13h 13h 13h 13hCalibration CalibrationTag ADC10 01A15h 1 10h 10h 10h 10h 10h 10hCalibrationlength ADC Gain Factor 01A16h 2 perunit perunit perunit perunit perunit perunit ADC Offset 01A18h 2 perunit perunit perunit perunit perunit perunit ADC 1.5V Reference 01A1Ah 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 30°C ADC 1.5V Reference 01A1Ch 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 85°C ADC 2.0V Reference 01A1Eh 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 30°C ADC 2.0V Reference 01A20h 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 85°C ADC 2.5V Reference 01A22h 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 30°C ADC 2.5V Reference 01A24h 2 perunit perunit perunit perunit perunit perunitTemp. Sensor 85°C REF REF Calibration 01A26h 1 12h 12h 12h 12h 12h 12hCalibration Tag REF Calibration 01A27h 1 06h 06h 06h 06h 06h 06hlength Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 105

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailableCC430F614x CC430F514x CC430F512x SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013 www.ti.com Table60.Device DescriptorTableCC430F614x and CC430F514x (continued) F6147 F6145 F6143 F5147 F5145 F5143SizeDescription Address bytes Value Value Value Value Value Value 1.5VReference 01A28h 2 perunit perunit perunit perunit perunit perunitFactor 2.0VReference 01A2Ah 2 perunit perunit perunit perunit perunit perunitFactor 2.5VReference 01A2Ch 2 perunit perunit perunit perunit perunit perunitFactor Peripheral Peripheral 01A2Eh 1 02h 02h 02h 02h 02h 02hDescriptor DescriptorTag (PD) Peripheral 01A2Fh 1 5Dh 5Dh 5Dh 5Bh 5Bh 5BhDescriptorLength Table61.Device DescriptorTableCC430F512x F5125 F5123SizeDescription Address bytes Value Value InfoBlock Infolength 01A00h 1 06h 06h CRC length 01A01h 1 06h 06h CRC value 01A02h 2 perunit perunit DeviceID 01A04h 1 03Bh 03Ch DeviceID 01A05h 1 081h 081h Hardware revision 01A06h 1 perunit perunit Firmwarerevision 01A07h 1 perunit perunit Die Record DieRecord Tag 01A08h 1 08h 08h DieRecord length 01A09h 1 0Ah 0Ah Lot/WaferID 01A0Ah 4 perunit perunit DieX position 01A0Eh 2 perunit perunit DieY position 01A10h 2 perunit perunit Testresults 01A12h 2 perunit perunit Empty Empty Tag 01A14h 1 05h 05hDescriptor Empty Tag length 01A15h 1 10h 10h 01A16h 16 undefined undefined ADC Offset 01A18h 2 perunit perunit REF REF Calibration 01A26h 1 12h 12hCalibration Tag REF Calibration 01A27h 1 06h 06hlength 1.5VReference 01A28h 2 perunit perunitFactor 2.0VReference 01A2Ah 2 perunit perunitFactor 2.5VReference 01A2Ch 2 perunit perunitFactor Peripheral Peripheral 01A2Eh 1 02h 02hDescriptor DescriptorTag (PD) Peripheral 01A2Fh 1 59h 59hDescriptorLength

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable CC430F614x CC430F514x CC430F512x www.ti.com SLAS555A –NOVEMBER 2012–REVISED FEBRUARY 2013

REVISION HISTORY

SLAS555 ProductionData release Recommended OperatingConditions,Added testconditionsfortypicalcharacteristics. DCO Frequency,Added note(1).SLAS555A Comparator_B,Changed symboland descriptionofTC CB_REF parameter. FlashMemory ,Changed IERASE and IMERASE values. Copyright© 2012–2013,Texas InstrumentsIncorporated SubmitDocumentationFeedback 107

www.ti.com 24-Apr-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CC430F5123IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5123 CC430F5123IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5123 CC430F5125IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5125 CC430F5125IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5125 CC430F5143IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5143 CC430F5143IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5143 CC430F5145IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5145 CC430F5145IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5145 CC430F5147IRGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5147 CC430F5147IRGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430 F5147 CC430F6143IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430F6143 CC430F6145IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430F6145 CC430F6147IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430F6147 CC430F6147IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR -40 to 85 CC430F6147 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

www.ti.com 24-Apr-2015 Addendum-Page 2 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC430F5123IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CC430F5123IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 CC430F5125IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CC430F5125IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 CC430F5143IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CC430F5143IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 CC430F5145IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CC430F5145IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 CC430F5147IRGZR VQFN RGZ 48 2500 336.6 336.6 28.6 CC430F5147IRGZT VQFN RGZ 48 250 213.0 191.0 55.0 CC430F6143IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 CC430F6145IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 CC430F6147IRGCR VQFN RGC 64 2000 336.6 336.6 28.6 CC430F6147IRGCT VQFN RGC 64 250 213.0 191.0 55.0 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2015 Pack Materials-Page 2

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Product Information

CC430F5145IRGZT specifications and overview.

Summary

MSP430 SoC With RF Core

Description

MSP430 SoC With RF Core

Source title CC430F5145IRGZT Datasheet(PDF) - Texas Instruments

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