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1 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)
1.1 System ControlModule (SYS) Introduction
1.2 System Resetand Initialization
1.2.1 DeviceInitialConditionsAfterSystem Reset
1.3 Interrupts
1.3.2 SNMI Timing
1.3.3 MaskableInterrupts
1.3.4 InterruptProcessing
1.3.5 InterruptNesting
1.3.6 InterruptVectors
1.3.7 SYS InterruptVectorGenerators
1.4 OperatingModes
1.4.1 Enteringand ExitingLow-Power Modes LPM0 ThroughLPM4
1.4.3 ExtendedTime inLow-Power Modes
1.5 PrinciplesforLow-Power Applications
1.6 ConnectionofUnused Pins
1.7 ResetPin(RST /NMI)Configuration
1.8 ConfiguringJTAG pins
1.9 BootCode
1.10 BootstrapLoader(BSL)
1.11 Memory Map – Uses and Abilities
1.11.1 VacantMemory Space
1.11.2 JTAG Lock Mechanism viatheElectronicFuse
1.12 JTAG Mailbox(JMB) System
1.12.1 JMB Configuration
1.12.2 JMBOUT0 and JMBOUT1 OutgoingMailbox
1.12.3 JMBIN0 and JMBIN1 IncomingMailbox
1.12.4 JMB NMI Usage
1.13 DeviceDescriptorTable
1.13.1 IdentifyingDeviceType
1.13.2 TLV Descriptors
1.13.3 PeripheralDiscoveryDescriptor
1.13.4 CRC Computation
1.13.5 CalibrationValues
1.14 SFR Registers
1.14.1 SFRIE1 Register
1.14.2 SFRIFG1 Register
1.14.3 SFRRPCR Register
1.15 SYS Registers
1.15.1 SYSCTL Register
1.15.2 SYSBSLC Register
1.15.3 SYSJMBC Register

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CC430 Family User's Guide LiteratureNumber: SLAU259E May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ListofFigures 15SLAU259E –May 2009–RevisedJanuary2013 ListofFigures SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com 25-9. FIFO_THR = 13 vs Number ofBytesinFIFO (GDOx_CFG = 0x00 inRX and GDOx_CFG = 0x02 in 23SLAU259E –May 2009–RevisedJanuary2013 ListofFigures SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ListofTables 25SLAU259E –May 2009–RevisedJanuary2013 ListofTables SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Preface SLAU259E –May 2009–RevisedJanuary2013 Read ThisFirst About ThisManual Thismanual describesthemodules and peripheralsoftheCC430 familyofdevices.Each description presentsthemodule orperipheralina generalsense.Not allfeaturesand functionsofallmodules or peripheralsmay be presenton alldevices.Inaddition,modules orperipheralsmay differintheirexact implementationbetween devicefamilies,ormay notbe fullyimplementedon an individualdeviceor devicefamily. Pinfunctions,internalsignalconnections,and operationalparametersdifferfromdevicetodevice.The usershouldconsultthedevice-specificdatasheetforthesedetails. RelatedDocumentation From Texas Instruments Forrelateddocumentationsee theweb sitehttp://www.ti.com/msp430. FCC Warning Thisequipmentisintendedforuse ina laboratorytestenvironmentonly.Itgenerates,uses,and can radiateradiofrequencyenergyand has notbeen testedforcompliancewiththelimitsofcomputing devicespursuanttosubpartJ ofpart15 ofFCC rules,whicharedesignedtoprovidereasonable protectionagainstradiofrequencyinterference.Operationofthisequipmentinotherenvironmentsmay cause interferencewithradiocommunications,inwhichcase theuserathisown expense willbe required totakewhatevermeasures may be requiredtocorrectthisinterference. NotationalConventions Program examples,areshown ina specialtypeface. Glossary ACLK AuxiliaryClock;see Section3.1 ADC Analog-to-DigitalConverter BOR Brown-OutReset;see Section1.2 BSL BootstrapLoader;see www.ti.com/msp430forapplicationreports CPU CentralProcessingUnit;see Section4.1 DAC Digital-to-AnalogConverter DCO DigitallyControlledOscillator;see Section3.2.6 dst Destination;see Section4.5 FLL FrequencyLocked Loop;see Section3.2.7 GIE Modes GeneralInterruptEnable;see Section1.3.3 INT(N/2) IntegerportionofN/2 I/O Input/Output;see Chapter8 ISR InterruptServiceRoutine LSB Least-SignificantBit LSD Least-SignificantDigit 33SLAU259E –May 2009–RevisedJanuary2013 Read ThisFirst SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com LPM Low-Power Mode; see Section1.4;alsonamed PM forPower Mode MAB Memory AddressBus MCLK MasterClock;see Section3.1 MDB Memory Data Bus MSB Most-SignificantBit MSD Most-SignificantDigit NMI (Non)-MaskableInterrupt;see Section1.3.1;alsosplittoUNMI and SNMI PC Program Counter;see Section4.3.1 PM Power Mode; see Section1.4 POR Power-On Reset;see Section1.2 PUC Power-Up Clear;see Section1.2 RAM Random Access Memory SCG System ClockGenerator;see Section4.3.3 SFR SpecialFunctionRegister;Section1.14 SMCLK Sub-System MasterClock;see Section3.1 SNMI System NMI; see Section1.3.1 SP StackPointer;see Section4.3.2 SR StatusRegister;see Section4.3.3 src Source;see Section4.5 TOS Top ofstack;see Section4.3.2 UNMI User NMI; see Section1.3.1 WDT Watchdog Timer;see Chapter12 z16 16-bitaddressspace RegisterBitConventions Each registerisshown witha key indicatingtheaccessibilityoftheeach individualbit,and theinitial condition: RegisterBitAccessibilityand InitialCondition Key BitAccessibility rw Read/write r Read only r0 Read as 0 r1 Read as 1 w Writeonly w0 Writeas 0 w1 Writeas 1 (w) No registerbitimplemented;writinga 1 resultsina pulse.The registerbitisalwaysreadas 0. h0 Clearedby hardware h1 Setby hardware -0,-1 ConditionafterPUC -(0),-(1) ConditionafterPOR -[0],-[1] ConditionafterBOR -{0},-{1} ConditionafterBrownout

34 Read ThisFirst SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter1 SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS) The system controlmodule (SYS) isavailableon alldevices.The followinglistshows thebasicfeatureset ofSYS.

Brownoutreset(BOR) and power on reset(POR) handling
Power up clear(PUC) handling
(Non)maskableinterrupt(SNMI and UNMI) eventsourceselectionand management
Addressdecoding
A userdata-exchangemechanism usingtheJTAG mailbox(JMB)
Bootstraploader(BSL)entrymechanism
Configurationmanagement (devicedescriptors)
Providesinterruptvectorgeneratorsforresetand NMIs 35SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.1 System ControlModule (SYS) Introduction

SYS isresponsiblefortheinteractionbetween variousmodules throughoutthesystem.The functionsthat SYS providesforarenotinherenttothemodules themselves.Addressdecoding,bus arbitration,interrupt eventconsolidation,and resetgenerationaresome examplesofthemany functionsthatSYS provides.

1.2 System Reset and Initialization

The systemresetcircuitryisshown inFigure1-1and sourcesa brownoutreset(BOR),a power on reset (POR),and a power up clear(PUC).Differenteventstriggertheseresetsignalsand differentinitial conditionsexistdependingon whichsignalwas generated. A BOR isa devicereset.A BOR isonlygeneratedby thefollowingevents:

Poweringup thedevice
A lowsignalon RST/NMI pinwhen configuredintheresetmode
A wakeup eventfromLPMx.5 (LPM3.5 orLPM4.5) modes
A softwareBOR event A POR isalwaysgeneratedwhen a BOR isgenerated,buta BOR isnotgeneratedby a POR. The followingeventstriggera POR:
A BOR signal
A SVS H and/orSVS M lowconditionwhen enabled(seethePMM chapterfordetails)
A SVS L and/orSVS L lowconditionwhen enabled(seethePMM chapterfordetails)
A softwarePOR event A PUC isalwaysgeneratedwhen a POR isgenerated,buta POR isnotgeneratedby a PUC. The followingeventstriggera PUC:
A POR signal
Watchdog timerexpirationwhen watchdogmode only(seetheWDT_A chapterfordetails)
Watchdog timerpasswordviolation(seetheWDT_A chapterfordetails)
A Flashmemory passwordviolation(seetheFlashControllerchapterfordetails)
Power Management Module passwordviolation(seethePMM chapterfordetails)
Fetchfromperipheralarea NOTE: The number and typeofresetsavailablemay varyfromdevicetodevice.See thedevice- specificdatasheetforallresetsourcesavailable. 36 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

BOR□shadow brownout□circuit PMMRSTIFG RST/NMI SYSNMI s s PMMBORIFG PMMSWBOR□event s Delay BOR SVSHIFG PMMPORIFG PMMSWPOR□event s from□SVSH s SVSHPE SVMHVLRIFG from□SVMH s SVMHVLRPE SVSLIFG from□SVSL s SVSLPE SVMHLVLRIFG from□SVML s SVMLVLRPE Delay POR WDTIFG Watchdog□Timer s EN from□port wakeup□logic s PUC□Logic Module PUCs MCLK notRST Delay clr clr clr ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com System Resetand Initialization Figure1-1.BOR/POR/PUC Reset Circuit 37SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.2.1 Device InitialConditionsAfterSystem Reset

Aftera BOR, theinitialdeviceconditionsare:

The RST/NMI pinisconfiguredintheresetmode. See Section1.7on configuringtheRST/NMI pin.
I/Opinsareswitchedtoinputmode as describedintheDigitalI/Ochapter.
Otherperipheralmodules and registersareinitializedas describedintheirrespectivechaptersinthis manual.
Statusregister(SR)isreset.
The watchdogtimerpowers up activeinwatchdogmode.
Program counter(PC)isloadedwiththebootcode addressand bootcode executionbeginsatthat address.See Section1.9formore informationregardingthebootcode.Upon completionoftheboot code,thePC isloadedwiththeaddresscontainedattheSYSRSTIV resetlocation(0FFFEh). Aftera systemreset,usersoftwaremust initializethedevicefortheapplicationrequirements.The followingmust occur:
Initializethestackpointer(SP),typicallytothetopofRAM.
Initializethewatchdogtotherequirementsoftheapplication.
Configureperipheralmodules totherequirementsoftheapplication. NOTE: A devicethatisunprogrammed orblankisdefinedas havingitsresetvectorvalue,residing atmemory addressFFFEh, equaltoFFFFh. Upon systemresetofa blankdevice,thedevice entersoperatingmode LPM4 automatically.See Section1.4forinformationon operating modes and Section1.3.6fordetailson interruptvectors. NOTE: Some SRAM locationscan be modifiedby thebootcode (refertoSection1.9)aftera BOR event.These SRAM locations,when available,areatSRAM locations01CFAh through 01CFFh and 023FAh through023FFh.

1.3 Interrupts

The interruptprioritiesarefixedand definedby thearrangementofthemodules intheconnectionchainas shown inFigure1-2.Interruptprioritiesdeterminewhat interruptistakenwhen more thanone interruptis pendingsimultaneously. Therearethreetypesofinterrupts:

System reset
(Non)maskable
Maskable NOTE: The typesofinterruptsourcesavailableand theirrespectiveprioritiescan change from devicetodevice.See thedevice-specificdatasheetforallinterruptsourcesand their priorities. 38 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

daisy□chain and□vectors CPU PUC INT NMI RST/NMI Password□violations . . . MAB - 6LSBs Module_A_int Module_B_int Module_C_int Module_D_int high□priority low□priority GIE System□NMI User□NMI . . . . POR BOR ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Interrupts Figure1-2.InterruptPriority 1.3.1 (Non)Maskable Interrupts(NMIs) Ingeneral,NMIs arenotmasked by thegeneralinterruptenable(GIE)bit.The familysupportstwo levels ofNMIs — systemNMI (SNMI)and userNMI (UNMI).The NMI sourcesareenabledby individualinterrupt enablebits.When an NMI interruptisaccepted,otherNMIs ofthatlevelareautomaticallydisabledto preventnestingofconsecutiveNMIs ofthesame level.Program executionbeginsattheaddressstoredin theNMI vectoras shown inTable1-1.To allowsoftwarebackwardcompatibilitytousersofearlier MSP430 families,thesoftwaremay, butdoes notneed to,reenableNMI sources.The blockdiagramfor NMI sourcesisshown inFigure1-3. A UNMI interruptcan be generatedby followingsources:

An edge on theRST/NMI pinwhen configuredinNMI mode
An oscillatorfaultoccurs
An accessviolationtotheflashmemory A SNMI interruptcan be generatedby followingsources:
Power Management Module (PMM) SVM L/SVM H supplyvoltagefault
PMM high/lowsidedelayexpiration
Vacantmemory access
JTAG mailbox(JMB) event NOTE: The number and typesofNMI sourcesmay varyfromdevicetodevice.See thedevice- specificdatasheetforallNMI sourcesavailable. 39SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

...IFG ...IE OSC□Fault OFIFG OFIE User□NMI S R . . User□NMI _IRQA SVML SVMLIFG SVMLIE SVMH SVMHIFG SVMHIE ...IFG ...IE JMB□event SYSJMBIFG SYSJMBIE S R PUC RETI . . System□NMI _IRQA System□NMI PUC RETI Del.□FF ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Interrupts www.ti.com

1.3.2 SNMI Timing

ConsecutiveSNMIs thatoccurata higherratethantheycan be handled(interruptstorm)allowthemain programtoexecuteone instructionaftertheSNMI handlerisfinishedwitha RETI instruction,beforethe SNMI handlerisexecutedagain.ConsecutiveSNMIs arenotinterruptedby UNMIs inthiscase.This avoidsa blockingbehavioron highSNMI rates. Figure1-3.NMIs With Reentrance Protection 40 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.3.3 Maskable Interrupts

Maskableinterruptsarecaused by peripheralswithinterruptcapability.Each maskableinterruptsource can be disabledindividuallyby an interruptenablebit,orallmaskableinterruptscan be disabledby the generalinterruptenable(GIE)bitinthestatusregister(SR). Each individualperipheralinterruptisdiscussedinitsrespectivemodule chapterinthismanual.

1.3.4 InterruptProcessing

When an interruptisrequestedfroma peripheraland theperipheralinterruptenablebitand GIE bitare set,theinterruptserviceroutineisrequested.Onlytheindividualenablebitmust be setfor(non)- maskableinterrupts(NMI)tobe requested.

1.3.4.1 InterruptAcceptance

The interruptlatencyissixcycles,startingwiththeacceptanceofan interruptrequest,and lastinguntilthe startofexecutionofthefirstinstructionoftheinterruptserviceroutine,as shown inFigure1-4.The interruptlogicexecutesthefollowing: 1. Any currentlyexecutinginstructioniscompleted. 2. The PC, whichpointstothenextinstruction,ispushed ontothestack. 3. The SR ispushed ontothestack. 4. The interruptwiththehighestpriorityisselectedifmultipleinterruptsoccurredduringthelast instructionand arependingforservice. 5. The interruptrequestflagresetsautomaticallyon single-sourceflags.Multiplesourceflagsremainset forservicingby software. 6. AllbitsofSR areclearedexceptSCG0, therebyterminatingany low-powermode. Because theGIE bit iscleared,furtherinterruptsaredisabled. 7. The contentoftheinterruptvectorisloadedintothePC; theprogramcontinueswiththeinterrupt serviceroutineatthataddress. Figure1-4.InterruptProcessing NOTE: Enable and DisableInterrupt Due tothepipelinedCPU architecture,theinstructionfollowingtheenableinterrupt instruction(EINT)isalwaysexecuted,even ifan interruptservicerequestispendingwhen theinterruptsareenabled. Iftheenableinterruptinstruction(EINT)isimmediatelyfollowedby a disableinterrupt instruction(DINT),a pendinginterruptmightnotbe serviced.FurtherinstructionsafterDINT mightexecuteincorrectlyand resultinunexpectedCPU execution.Itisrecommended to alwaysinsertatleastone instructionbetween EINT and DINT.Note thatany alternative instructionuse thatsetsand immediatelyclearstheCPU statusregisterGIE bitmust be consideredinthesame fashion. 41SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.3.4.2 Return From Interrupt

The interrupthandlingroutineterminateswiththeinstruction: RETI//returnfromaninterruptserviceroutine The returnfromtheinterrupttakesfivecyclestoexecutethefollowingactionsand isillustratedin Figure1-5. 1. The SR withallprevioussettingspops fromthestack.AllprevioussettingsofGIE,CPUOFF, etc.are now ineffect,regardlessofthesettingsused duringtheinterruptserviceroutine. 2. The PC pops fromthestackand beginsexecutionatthepointwhere itwas interrupted. Figure1-5.Return From Interrupt

1.3.5 InterruptNesting

InterruptnestingisenablediftheGIE bitissetinsidean interruptserviceroutine.When interruptnesting isenabled,any interruptoccurringduringan interruptserviceroutineinterruptstheroutine,regardlessof theinterruptpriorities.

1.3.6 InterruptVectors

The interruptvectorsarelocatedintheaddressrange0FFFFh to0FF80h,fora maximum of64 interrupt sources.A vectorisprogrammed by theuserand pointstothestartlocationofthecorrespondinginterrupt serviceroutine.Table1-1isan example oftheinterruptvectorsavailable.See thedevice-specificdata sheetforthecompleteinterruptvectorlist. Table1-1.InterruptSources,Flags,and Vectors SystemInterruptSource InterruptFlag Word Address PriorityInterrupt power up,externalreset WDTIFG Reset 0FFFEh Highest watchdog, KEYV flashpassword System NMI: (Non)maskable 0FFFCh … PMM NMI, oscillatorfault, NMIIFG (Non)maskable 0FFFAh … flashmemory access OFIFG (Non)maskable violation ACCVIFG (Non)maskable Devicespecific 0FFF8h … Devicespecific … … Reserved Maskable … Lowest 42 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Interrupts Some interruptenablebits,and interruptflags,as wellas,controlbitsfortheRST/NMI pinarelocatedin thespecialfunctionregisters(SFR).The SFR arelocatedintheperipheraladdressrangeand arebyte and word accessible.See thedevice-specificdatasheetfortheSFR configuration.

1.3.6.1 AlternateInterruptVectors

Itispossibletouse theRAM as an alternatelocationfortheinterruptvectorlocations.Settingthe SYSRIVECT bitinSYSCTL causestheinterruptvectorstobe remapped tothetopofRAM. Once set,any interruptvectorstothealternatelocationsnow residinginRAM. Because SYSRIVECT isautomatically clearedon a BOR, itiscriticalthattheresetvectoratlocation0FFFEh stillbe availableand handled properlyinfirmware.

1.3.7 SYS InterruptVectorGenerators

SYS collectsallsystemNMI (SNMI)sources,userNMI (UNMI) sources,and BOR/POR/PUC (reset) sourcesofalltheothermodules.They arecombined intothreeinterruptvectors.The interruptvector registersSYSRSTIV, SYSSNIV, SYSUNIV areused todeterminewhichflagsrequestedan interruptora reset.The interruptwiththehighestpriorityofa group,when enabled,generatesa number inthe correspondingSYSRSTIV, SYSSNIV, SYSUNIV register.Thisnumber can be directlyadded tothe programcounter,causinga branchtotheappropriateportionoftheinterruptserviceroutine.Disabled interruptsdo notaffecttheSYSRSTIV, SYSSNIV, SYSUNIV values.ReadingSYSRSTIV, SYSSNIV, SYSUNIV registerautomaticallyresetsthehighestpendinginterruptflagofthatregister.Ifanother interruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt.Writingto theSYSRSTIV, SYSSNIV, SYSUNIV registerautomaticallyresetsallpendinginterruptflagsofthegroup.

1.3.7.1 SYSSNIV SoftwareExample

The followingsoftwareexample shows therecommended use ofSYSSNIV. The SYSSNIV valueisadded tothePC toautomaticallyjump totheappropriateroutine.ForSYSRSTIV and SYSUNIV, a similar softwareapproachcan be used.The followingisan example fora genericdevice.Vectorscan change in priorityfora givendevice.The devicespecificdatasheetshouldbe referencedforthevectorlocations.All vectorsshouldbe coded symbolicallytoallowforeasy portabilityofcode. SNI_ISR:ADD &SYSSNIV,PC;Addoffsettojumptable RETI ;Vector0:Nointerrupt JMP SVML_ISR;Vector2:SVMLIFG JMP SVMH_ISR;Vector4:SVMHIFG JMP DLYL_ISR;Vector6:SVSMLDLYIFG JMP DLYH_ISR;Vector8:SVSMHDLYIFG JMP VMA_ISR ;Vector10:VMAIFG JMP JMBI_ISR;Vector12:JMBINIFG JMBO_ISR: ;Vector14:JMBOUTIFG ... ;Task_Estartshere RETI ;Return SVML_ISR: ;Vector2 ... ;Task_2startshere RETI ;Return SVMH_ISR: ;Vector4 ... ;Task_4startshere RETI ;Return DLYL_ISR: ;Vector6 ... ;Task_6startshere RETI ;Return DLYH_ISR: ;Vector8 ... ;Task_8startshere RETI ;Return VMA_ISR: ;VectorA ... ;Task_Astartshere RETI ;Return JMBI_ISR: ;VectorC ... ;Task_Cstartshere RETI ;Return 43SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.3.7.2 SYSBERRIV Bus ErrorInterruptVectorGenerator

Some devices,forexample thosethatcontaintheUSB module,includean additionalsysteminterrupt vectorgenerator,SYSBERRIV. Ingeneral,any typeofsystemrelatedbus errorortimeouterroris associatedwitha userNMI event.Upon thisevent,theSYSUNIV containsan offsetvaluecorresponding toa bus errorevent(BUSIFG).Thisoffsetcan be added tothePC toautomaticallyjump tothe appropriateNMI routine.Similarly,SYSBERRIV alsocontainsan offsetvaluecorrespondingtowhich specificeventcaused thebus errorevent.The offsetvalueinSYSBERRIV can be added insidetheNMI routinetoautomaticallyjump totheappropriateroutine.Inthisway,theSYSBERRIV can be thoughtofas an extensiontotheuserNMI vectors.

1.4 OperatingModes

The MSP430 familyisdesignedforultralow-powerapplicationsand uses differentoperatingmodes shown inFigure1-6. The operatingmodes takeintoaccountthreedifferentneeds:

Ultralowpower
Speed and datathroughput
Minimizationofindividualperipheralcurrentconsumption The low-powermodes LPM0 throughLPM4 areconfiguredwiththeCPUOFF, OSCOFF, SCG0, and SCG1 bitsintheSR. The advantageofincludingtheCPUOFF, OSCOFF, SCG0, and SCG1 mode-control bitsintheSR isthatthepresentoperatingmode issaved ontothestackduringan interruptservice routine.Program flowreturnstothepreviousoperatingmode ifthesaved SR valueisnotalteredduring theinterruptserviceroutine.Program flowcan be returnedtoa differentoperatingmode by manipulating thesaved SR valueon thestackinsideoftheinterruptserviceroutine.When settingany ofthemode- controlbits,theselectedoperatingmode takeseffectimmediately.Peripheralsoperatingwithany disabled clockaredisableduntiltheclockbecomes active.Peripheralsmay alsobe disabledwiththeirindividual controlregistersettings.AllI/Oportpinsand RAM/registersareunchanged.Wakeup fromLPM0 through LPM4 ispossiblethroughallenabledinterrupts. When LPMx.5 (LPM3.5 orLPM4.5) isentered,thevoltageregulatorofthePower Management Module (PMM) isdisabled.AllRAM and registercontentsarelost.AlthoughtheI/Oregistercontentsarelost,the I/Opinstatesarelockedupon LPMx.5 entry.See theDigitalI/Ochapterforfurtherdetails.Wakeup from LPM4.5 ispossibleviaa power sequence,a RST event,orfromspecificI/O.Wakeup fromLPM3.5 is possibleviaa power sequence,a RST event,RTC event,orfromspecificI/O. NOTE: LPM3.5 and LPM4.5 lowpower modes arenotavailableon alldevices.See thedevice specificdatasheettosee whichLPMx.5 power modes areavailable. NOTE: The TEST/SBWTCK pinisused forinterfacingtothedevelopmenttoolsviaSpy-Bi-Wireand JTAG. When theTEST/SBWTCK pinishigh,wakeup timesfromLPM2, LPM3, and LPM4 may be differentcompared towhen TEST/SBWTCK islow.Pay carefulattentiontothereal- timebehaviorwhen exitingfromLPM2, LPM3, and LPM4 withthedeviceconnectedtoa developmenttool(forexample,MSP-FET430UIF). See thePMM chapterfordetails. 44 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Time□expired,□Overflow WDT Active Password□violation Flash Password□violation RST/NMI (Reset□wakeup) Port□wakeup Peripheral□area□fetch SVSH□fault SVSL fault DoPOR□event Load□calibration□data Active□Mode:□CPU□is Active Various□Modules□are□active LPM0: CPU/MCLK□=□off FLL =□on ACLK□=□on V =□onCORE LPM1: CPU/MCLK□=□off FLL =□off ACLK□=□on =□onVCORE LPM2: CPU/MCLK□=□off FLL =□off ACLK□=□on =□onVCORE LPM3: CPU/MCLK□=□off FLL =□off ACLK□=□on =□onVCORE LPM4: CPU/MCLK□=□off FLL =□off ACLK□=□off =□onVCORE LPMx.5: =□off (all□modules□off optional□RTC) VCORE CPUOFF=1 OSCOFF=0 SCG0=0 SCG1=0 CPUOFF=1 OSCOFF=0 SCG0=1 SCG1=0 CPUOFF=1 OSCOFF=0 SCG0=0 SCG1=1 CPUOFF=1 OSCOFF=0 SCG0=1 SCG1=1 CPUOFF=1 OSCOFF=1 SCG0=1 SCG1=1 PMMREGOFF□=□1 PMM Password□violation to□LPMx.5 SVMH□OVP-fault SVML OVP-fault From□active□mode Events Operating□modes/Reset□phases Arbitrary□transitions † Any□enabled□interrupt□and□NMI□performs□this□transition ‡ An□enabled□reset□always□restarts□the□device RST/NMI (Reset□event) Brownout fault RTC□wakeup ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com OperatingModes Figure1-6.OperationModes 45SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. OperatingModes www.ti.com Table1-2.OperationModes OSCOFF CPUOFFSCG1 (1) SCG0 Mode CPU and Clocks Status(2) (1) (1) 0 0 0 0 Active CPU, MCLK areactive. ACLK isactive.SMCLK optionallyactive(SMCLKOFF = 0). DCO isenabledifsourcesACLK, MCLK, orSMCLK (SMCLKOFF = 0). DCO biasisenabledifDCO isenabledorDCO sourcesMCLK orSMCLK (SMCLKOFF = 0). FLL isenabledifDCO isenabled. 0 0 0 1 LPM0 CPU, MCLK aredisabled. ACLK isactive.SMCLK optionallyactive(SMCLKOFF = 0). DCO isenabledifsourcesACLK orSMCLK (SMCLKOFF = 0). DCO biasisenabledifDCO isenabledorDCO sourcesMCLK orSMCLK (SMCLKOFF = 0). FLL isenabledifDCO isenabled. 0 1 0 1 LPM1 CPU, MCLK aredisabled. ACLK isactive.SMCLK optionallyactive(SMCLKOFF = 0). DCO isenabledifsourcesACLK orSMCLK (SMCLKOFF = 0). DCO biasisenabledifDCO isenabledorDCO sourcesMCLK orSMCLK (SMCLKOFF = 0). FLL isdisabled. 1 0 0 1 LPM2 CPU, MCLK aredisabled. ACLK isactive.SMCLK isdisabled. DCO isenabledifsourcesACLK. FLL isdisabled. 1 1 0 1 LPM3 CPU, MCLK aredisabled. ACLK isactive.SMCLK isdisabled. DCO isenabledifsourcesACLK. FLL isdisabled. 1 1 1 1 LPM4 CPU and allclocksaredisabled. 1 1 1 1 LPM3.5 (3) When PMMREGOFF = 1,regulatorisdisabled.No memory retention.Inthis mode, RTC operationispossiblewhen configuredproperly.See theRTC module forfurtherdetails. 1 1 1 1 LPM4.5 (3) When PMMREGOFF = 1,regulatorisdisabled.No memory retention.Inthis mode, allclocksourcesaredisabled;thatis,no RTC operationispossible. (1) Thisbitisautomaticallyresetwhen exitinglowpower modes. PleaserefertoSection1.4.1fordetails. (2) The low-powermodes and,hence,thesystemclockscan be affectedby theclockrequestsystem.See theUCS chapterfor details. (3) LPM3.5 and LPM4.5 modes arenotavailableon alldevices.See thedevice-specificdatasheetforavailability. 46 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com OperatingModes

1.4.1 Enteringand ExitingLow-Power Modes LPM0 Through LPM4

An enabledinterrupteventwakes thedevicefromlow-poweroperatingmodes LPM0 throughLPM4. The programflowforexitingLPM0 throughLPM4 is:

Enterinterruptserviceroutine – The PC and SR arestoredon thestack. – The CPUOFF, SCG1, and OSCOFF bitsareautomaticallyreset.
Optionsforreturningfromtheinterruptserviceroutine – The originalSR ispopped fromthestack,restoringthepreviousoperatingmode. – The SR bitsstoredon thestackcan be modifiedwithintheinterruptserviceroutinereturningtoa differentoperatingmode when theRETI instructionisexecuted. ;EnterLPM0Example BIS#GIE+CPUOFF,SR ;EnterLPM0 ; ... ;Programstopshere ;ExitLPM0InterruptServiceRoutine BIC#CPUOFF,0(SP) ;ExitLPM0onRETI RETI ;EnterLPM3Example BIS#GIE+CPUOFF+SCG1+SCG0,SR;EnterLPM3 ; ... ;Programstopshere ;ExitLPM3InterruptServiceRoutine BIC#CPUOFF+SCG1+SCG0,0(SP);ExitLPM3onRETI RETI ;EnterLPM4Example BIS#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR;EnterLPM4 ; ... ;Programstopshere ;ExitLPM4InterruptServiceRoutine BIC#CPUOFF+OSCOFF+SCG1+SCG0,0(SP);ExitLPM4onRETI RETI 1.4.2 Enteringand ExitingLow-Power Modes LPMx.5 LPMx.5 entryand exitishandleddifferentlythantheotherlowpower modes. LPMx.5,when used properly,givesthelowestpower consumptionavailableon a device.To achievethis,entrytoLPMx.5 disablestheLDO ofthePMM module,removingthesupplyvoltagefromthecoreofthedevice.Sincethe supplyvoltageisremoved fromthecore,allregistercontents,as wellas,SRAM contentsarelost.Exit fromLPMx.5 causesa BOR event,whichforcesa completeresetofthesystem.Therefore,itisthe application'sresponsibilitytoproperlyreconfigurethedeviceupon exitfromLPMx.5. The wakeup timefromLPMx.5 issignificantlylongerthanthewakeup timefromtheotherpower modes (pleasesee thedevicespecificdatasheet).Thisisprimarilydue tothefactsthatafterexitfromLPMx.5, timeisrequiredforthecorevoltagesupplytobe regenerated,as wellas,bootcode executiontocomplete beforetheapplicationcode can begin.Therefore,theusage ofLPMx.5 isrestrictedtoverylowdutycycle events. See thedevicespecificdatasheettosee whichLPMx.5 power modes areavailable.LPM4.5 allowsfor thelowestpower consumptionavailable.No clocksourcesareactiveduringLPM4.5.LPM3.5 issimilarto LPM4.5,buthas theadditionalcapabilityofhavinga RTC mode available.Inadditiontothewakeup eventspossibleinLPM4.5,RTC wakeup eventsarealsopossibleinLPM3.5. 47SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. OperatingModes www.ti.com The programflowforenteringLPMx.5 is: 1. ConfigureI/Oappropriately.See theDigitalI/Ochapterforcompletedetailson configuringI/Ofor LPMx.5.

SetallportstogeneralpurposeI/O.Configureeach porttoensureno floatinginputsbased on the applicationrequirements.
Ifwakeup fromI/Oisdesired,configureinputportswithinterruptcapabilityappropriately. 2. IfLPM3.5 isavailable,and desired,enableRTC operation.Inaddition,configureany RTC interrupts,if desiredforLPM3.5 wakeup event.See theRTC Overviewchapterforcompletedetails. 3. EnsureclocksystemsettingsallowLPMx.5 entryaccordingtoTable3-1inUCS chapter. 4. EnterLPMx.5 by settingPMMREGOFF=1 and LPM4 statusregisterbits.The followingcode example shows how toenterLPMx.5 mode. See thePMM chapterforfurtherdetails. ;EnterLPMx.5Example MOV.B#PMMPW_H,&PMMCTL0_H ;OpenPMMregistersforwrite BIS.B#PMMREGOFF,&PMMCTL0_L ; BIS#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR;EnterLPMx.5whenPMMREGOFFisset. NOTE: Itisnotpossibletowakeup fromLPMx.5 ifitsrespectiveinterruptflagisalreadyasserted.It isrecommended thattherespectiveflagbe clearedpriortoenteringLPMx.5.Itisalso recommended thatGIE = 1 be setpriortoentryintoLPMx.5.Any pendingflagsinthiscase couldthenbe servicedpriortoLPMx.5 entry. Althoughitisrecommended tosetGIE = 1 priortoenteringLPMx.5,itisnotrequired.Device wakeup fromLPMx.5 withan enabledwakeup functionwillstillcause thedevicetowake up fromLPMx.5 even withGIE = 0.IfGIE = 0 priortoLPMx.5,additionalcaremay be required. ShouldtherespectiveinterrupteventshouldoccurduringLPMx.5 entry,thedevicemay not recognizethisorany futureinterruptwakeup eventon thisfunction. ExitfromLPMx.5 ispossiblewitha RST event,a power on cycle,orviaspecificI/O.Any exitfromLPMx.5 causesa BOR. Program executioncontinuesatthelocationstoredinthesystemresetvectorlocation 0FFFEh afterexecutionofthebootcode.The PMMLPM5IFG bitinsidethePMM module issetindicating thatthedevicewas inLPMx.5 priortothewakeup event.Additionally,SYSRSTIV = 08h whichcan be used togeneratean efficientresethandlerroutine.DuringLPMx.5,allI/Opinconditionsareautomatically lockedtothecurrentstate.Upon exitfromLPMx.5,theI/Opinconditionsremainlockeduntilthe applicationunlocksthem.See theDigitalI/Ochapterforcompletedetails.IfLPM3.5 was ineffect,RTC operationcontinuesuninterruptedupon wake-up.The programflowforexitingLPMx.5 is:
Entersystemresetserviceroutine – Reconfiguresystemas requiredfortheapplication. – ReconfigureI/Oas requiredfortheapplication.

1.4.3 Extended Time inLow-Power Modes

The temperaturecoefficientoftheDCO shouldbe consideredwhen theDCO isdisabledforextendedlow- power mode periods.Ifthetemperaturechanges significantly,theDCO frequencyatwakeup may be significantlydifferentfromwhen thelow-powermode was enteredand may be outofthespecified operatingrange.To avoidthis,theDCO can be settoitlowestvaluebeforeenteringthelow-powermode forextendedperiodsoftimewhere temperaturecan change. ;EnterLPM4ExamplewithlowestDCOSetting BIC#SCG0,SR ;DisableFLL MOV#0100h,&UCSCTL0 ;SetDCOtaptofirsttap,clear modulation. BIC#DCORSEL2+DCORSEL1+DCORSEL0,&UCSCTL1;LowestDCORSEL BIS#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR;EnterLPM4 ; ... ;Programstops ;InterruptServiceRoutine BIC#CPUOFF+OSCOFF+SCG1+SCG0,0(SR);ExitLPM4onRETI 48 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com OperatingModes RETI 49SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PrinciplesforLow-Power Applications www.ti.com

1.5 PrinciplesforLow-Power Applications

Often,themost importantfactorforreducingpower consumptionisusingthedeviceclocksystemto maximizethetimeinLPM3 orLPM4 modes whenever possible.

Use interruptstowake theprocessorand controlprogramflow.
Peripheralsshouldbe switchedon onlywhen needed.
Use low-powerintegratedperipheralmodules inplaceofsoftwaredrivenfunctions.Forexample, Timer_A and Timer_B can automaticallygeneratePWM and captureexternaltimingwithno CPU resources.
Calculatedbranchingand fasttablelook-upsshouldbe used inplaceofflagpollingand longsoftware calculations.
Avoidfrequentsubroutineand functioncallsdue tooverhead.
Forlongersoftwareroutines,single-cycleCPU registersshouldbe used.
OverwriteRAM controlregisterRCCTL0 withallnotavailableand unused segments settopowered down (=1).Forinformationaboutused RAM segments see thedevice-specificdatasheet. Iftheapplicationhas lowdutycycle,slowresponsetimeevents,maximizingtimeinLPMx.5 can further reducepower consumptionsignificantly.

1.6 Connection ofUnused Pins

The correctterminationofallunused pinsislistedinTable1-3. Table1-3.Connection ofUnused Pins(1) Pin Potential Comment AVCC DV CC AVSS DV SS Px.0toPx.7 Open Switchedtoportfunction,outputdirection(PxDIR.n= 1) XIN DV SS FordedicatedXIN pinsonly.XIN pinswithsharedGPIO functionsshouldbe programmed toGPIO and followPx.0toPx.7recommendations. XOUT Open FordedicatedXOUT pinsonly.XOUT pinswithsharedGPIO functionsshouldbe programmed toGPIO and followPx.0toPx.7recommendations. XT2IN DV SS FordedicatedXT2IN pinsonly.XT2IN pinswithsharedGPIO functionsshouldbe programmed toGPIO and followPx.0toPx.7recommendations. XT2OUT Open FordedicatedXT2OUT pinsonly.XT2OUT pinswithsharedGPIO functionsshould be programmed toGPIO and followPx.0toPx.7recommendations. LCDCAP DV SS RST/NMI DV CC orVCC 47-kΩ pulluporinternalpullupselectedwith10-nF(2.2nF)pulldown(2) PJ.0/TDO Open The JTAG pinsaresharedwithgeneralpurposeI/Ofunction(PJ.x).Ifnotbeing PJ.1/TDI used,theseshouldbe switchedtoportfunction,outputdirection(PJDIR.n= 1). PJ.2/TMS When used as JTAG pins,thesepinsshouldremainopen. PJ.3/TCK TEST Open Thispinalwayshas an internalpulldownenabled. GUARD DV CC Ifradiomodule isnotused intheapplication R_BIAS DV SS Ifradiomodule isnotused intheapplication AVCC_RF DV CC Ifradiomodule isnotused intheapplication RF_N Open Ifradiomodule isnotused intheapplication RF_P Open Ifradiomodule isnotused intheapplication RF_XIN DV SS Ifradiomodule isnotused intheapplication RF_XOUT Open Ifradiomodule isnotused intheapplication V18 Open ForUSB devicesonlywhen USB module isnotbeingused intheapplication (1) Any unused pinwitha secondaryfunctionthatissharedwithgeneralpurposeI/OshouldfollowthePx.0toPx.7unused pin connectionguidelines. (2) The pulldowncapacitorshouldnotexceed 2.2nF when usingdeviceswithSpy-Bi-WireinterfaceinSpy-Bi-Wiremode orin4- wireJTAG mode withTItoolssuch as FET interfacesorGANG programmers. 50 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ResetPin(RST /NMI)Configuration Table1-3.Connection ofUnused Pins(1)(continued) Pin Potential Comment PUR (3) DV SS ForUSB devicesonlywhen USB module isnotbeingused intheapplication VUSB Open ForUSB devicesonlywhen USB module isnotbeingused intheapplication PU.0/DP Open ForUSB devicesonlywhen USB module isnotbeingused intheapplication PU.1/DM VBUS, VSSU DV SS ForUSB devicesonlywhen USB module isnotbeingused intheapplication LDOI DV SS FordeviceswithLDO-PWR module when notbeingused intheapplication. LDOO Open FordeviceswithLDO-PWR module when notbeingused intheapplication. (3) The defaultUSB BSL evaluatesthestateofthePUR pinaftera BOR reset.Ifitispulledhighexternally,thentheBSL is invoked.Therefore,unlessinvokingtheBSL, itisimportanttokeep PUR pulledlowaftera BOR reset,even ifBSL orUSB is neverused.A 1-MΩ resistortogroundisrecommended.

1.7 Reset Pin (RST/NMI) Configuration

The resetpincan be configuredas a resetfunction(default)oras an NMI functionviatheSpecial FunctionRegister(SFR),SFRRPCR. SettingSYSNMI causestheRST/NMI pintobe configuredas an externalNMI source.The externalNMI isedge sensitive,and itsedge isselectableby SYSNMIIES. SettingtheNMIIE enablestheinterruptoftheexternalNMI. Upon an externalNMI event,theNMIIFG is set. The RST/NMI pincan have eithera pulluporpulldownpresentornot.SYSRSTUP selectseitherpullupor pulldownand SYSRSTRE causesthepulluporpulldowntobe enabledornot.IftheRST/NMI pinis unused,itisrequiredtohave eithertheinternalpullupselectedand enabledoran externalresistor connectedtotheRST/NMI pinas shown inTable1-3. NOTE: AlldevicesexcepttheMSP430F543x (non-Adevices)have theinternalpullupenabled.In thiscase,no externalpullupresistorisrequired.

1.8 ConfiguringJTAG pins

The JTAG pinsaresharedwithgeneralpurposeI/Opins.Thereareseveralways thattheJTAG pinscan be selectedforfourwireJTAG mode viasoftware.Normally,upon a BOR, SYSJTAGPIN iscleared.With SYSJTAGPIN cleared,theJTAG areconfiguredas general-purposeI/O.See theDigitalI/Ochapterfor detailson controllingtheJTAG pinsas generalpurposeI/O.IfSYSJTAG = 1,theJTAG pinsare configuredtofourwireJTAG mode and remaininthismode untilanotherBOR conditionoccurs. Therefore,SYSJTAGPIN isa writeonlyonce function.Clearingitby softwareisnotpossible,and the devicedoes notchange fromfourwireJTAG mode togeneralpurposeI/O.

1.9 Boot Code

The bootcode isalwaysexecutedaftera BOR. The bootcode loadsfactorystoredcalibrationvaluesof theoscillatorand referencevoltages.Inaddition,itchecksforthepresenceofa user-definedbootstrap loader(BSL).

1.10 BootstrapLoader (BSL)

The BSL issoftwarethatisexecutedafterstart-upwhen a certainBSL entryconditionisapplied.The BSL enablestheusertocommunicatewiththeembedded memory inthemicrocontrollerduringtheprototyping phase,finalproduction,and inservice.Allmemory mapped resources,theprogrammablememory (flash memory),thedatamemory (RAM),and theperipherals,can be modifiedby theBSL as required.The user can definecustom BSL code forflash-baseddevicesand protectitagainsterasureand unintentionalor unauthorizedaccess. 51SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. BootstrapLoader(BSL) www.ti.com On deviceswithoutUSB, a basicBSL programisprovidedby TI.Thissupportsthecommonly used UART protocolwithRS232 interfacing,allowingflexibleuse ofbothhardwareand software.To use theBSL, a specificBSL entrysequence must be appliedtospecificdevicepins.The correctentrysequence causes SYSBSLIND tobe set.An added sequence ofcommands initiatesthedesiredfunction.A boot-loading sessioncan be exitedby continuingoperationata defineduserprogramaddressorby applyingthe standardresetsequence.Access tothedevicememory viatheBSL isprotectedagainstmisuseby a user-definedpassword.DeviceswithUSB have a USB based BSL programprovidedby TI.Formore details,see theMSP430 Programming ViatheBootstrapLoaderUser'sGuide (SLAU319 )at www.ti.com/msp430. The amount ofBSL memory thatisavailableisdevicespecific.The BSL memory sizeisorganizedinto segments and can be setusingtheSYSBSLSIZE bits.See thedevicespecificdatasheetforthenumber and sizeofthesegments available.Itispossibletoassigna smallamount ofRAM totheallocatedBSL memory. SettingSYSBSLR allocatesthelowest16 bytesofRAM fortheBSL. When theBSL memory is protected,accesstotheseRAM locationsisonlypossiblefromwithintheprotectedBSL memory segments. Itmay be desirableinsome BSL applicationstoonlyallowchangingofthePower Management Module settingsfromtheprotectedBSL segments.ThisispossiblewiththeSYSPMMPE bit.Normally,thisbitis clearedand allowsaccessofthePMM controlregistersfromany memory location.SettingSYSPMMPE, allowsaccesstothePMM controlregistersonlyfromtheprotectedBSL memory. Once set,SYSPMMPE can onlybe clearedby a BOR event. 52 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Memory Map – Uses and Abilities

1.11 Memory Map – Uses and Abilities

Thismemory map representstheMSP430F5438 device.Though theaddressrangesdiffersfromdevice todevice,overallbehaviorremainsthesame. Can generateNMI on read/write/fetch GeneratesPUC on fetchaccess Protectableforread/writeaccesses AlwaysabletoaccessPMM registersfrom(1);Mass eraseby userpossible Mass eraseby userpossible Bank eraseby userpossible Segment eraseby userpossible Address Range Name and Usage Properties 00000h-00FFFh Peripheralswithgaps 00000h-000FFh Reservedforsystemextension 00100h-00FEFh Peripherals x 00FF0h-00FF3h Descriptortype(2) x 00FF4h-00FF7h Startaddressofdescriptorstructure x 01000h-011FFh BSL 0 x x 01200h-013FFh BSL 1 x x 01400h-015FFh BSL 2 x x 01600h-017FFh BSL 3 x x x 017FCh-017FFh BSL SignatureLocation 01800h-0187Fh InfoD x 01880h-018FFh InfoC x 01900h-0197Fh InfoB x 01980h-019FFh InfoA x 01A00h-01A7Fh DeviceDescriptorTable x 01C00h-05BFFh RAM 16 KB 05B80-05BFFh AlternateInterruptVectors 05C00h-0FFFFh Program x x(1) x 0FF80h-0FFFFh InterruptVectors 10000h-45BFFh Program x x x 45C00h-FFFFFh Vacant x(3) (1) Access rightsareseparatelyprogrammableforSYS and PMM. (2) FixedID forallMSP430 devices.See Section1.13.1forfurtherdetails. (3) On vacantmemory space,thevalue03FFFh isdrivenon thedatabus.

1.11.1 Vacant Memory Space

Vacantmemory isnon-existentmemory space.Accessestovacantmemory space generatea system (non)maskableinterrupt(SNMI)when enabled(VMAIE = 1).Reads fromvacantmemory resultsinthe value3FFFh. Inthecase ofa fetch,thisistakenas JMP $.Fetchaccessesfromvacantperipheralspace resultina PUC. Afterthebootcode isexecuted,itbehaves likevacantmemory space and alsocausesan NMI on access.

1.11.2 JTAG Lock Mechanism viatheElectronicFuse

A devicecan be protectedfromunauthorizedaccessby disablingtheJTAG and SBW interface.Thisis achievedby programmingtheelectronicfuse.Programming theelectronicfuse,completelydisablesthe debug and accesscapabilitiesassociatedwiththeJTAG and Spy-Bi-Wireinterface.The JTAG islocked by programminga certainsignatureintothedevice's'flashmemory atdedicatedaddresses.The JTAG securitylockkey residesattheend ofthebootstraploader(BSL)memory ataddresses17FCh through 17FFh.Anythingotherthan0h orFFFFFFFFh programmed totheseaddresseslockstheJTAG interface. 53SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. JTAG Mailbox(JMB) System www.ti.com Allofthe5xx MSP430 devicescome witha preprogrammed BSL (TI-BSL)code that,by default,protects itselffromunintendederaseand writeaccess.Thisisdone by settingSYSBSLPE intheSYSBSLC register.SincetheJTAG securitylockkey residesintheBSL memory addressrange,appropriateaction must be takentounprotecttheBSL memory areabeforeprogrammingtheprotectionkey.Formore detailson theelectronicfusesee theMSP430 Programming ViatheJTAG InterfaceUser'sGuide (SLAU320 )atwww.ti.com/msp430. Some JTAG commands arestillpossibleafterthedeviceissecured,includingtheBYPASS command (seeIEEE1149-2001Standard)and theJMB_EXCHANGE command whichallowsaccesstotheJTAG MailboxSystem (seeSection1.12fordetails). NOTE: Ifa devicehas been protected,Texas Instrumentscannotaccessthedevicefora customer return.Access isonlypossibleifa BSL isprovidedwithitscorrespondingkey oran unlock mechanism isprovidedby thecustomer.

1.12 JTAG Mailbox(JMB) System

The SYS module providesthecapabilitytoexchange userdataviatheregularJTAG test/debuginterface. The ideabehindtheJMB istohave a directinterfacetotheCPU duringdebugging,programming,and testthatisidenticalforall'430devicesofthisfamilyand uses onlyfew orno userapplicationresources. The JTAG interfacewas chosen because itisavailableon all'430devicesand isa dedicatedresourcefor debugging,programmingand test. ApplicationsoftheJMB are:

Providingentrypasswordfordevicelock/unlockprotection
Run-timedataexchange (RTDX)

1.12.1 JMB Configuration

The JMB supportstwo transfermodes, 16-bitand 32-bit.SettingJMBMODE enables32-bittransfermode. ClearingJMBMODE enables16-bittransfermode.

1.12.2 JMBOUT0 and JMBOUT1 Outgoing Mailbox

Two 16-bitregistersareavailableforoutgoingmessages totheJTAG port.JMBOUT0 isonlyused when using16-bittransfermode (JMBMODE = 0).JMBOUT1 isused inadditiontoJMBOUT0 when using32-bit transfermode (JMBMODE = 1).When theapplicationwishestosend a message totheJTAG port,it writesdatatoJMBOUT0 for16-bitmode, orJMBOUT0 and JMBOUT1 for32-bitmode. JMBOUT0FG and JMBOUT1FG arereadonlyflagsthatindicatethestatusofJMBOUT0 and JMBOUT1, respectively.When JMBOUT0FG isset,JMBOUT0 has been readby theJTAG portand isreadyto receivenew data.When JMBOUT0FG isreset,theJMBOUT0 isnotreadytoreceivenew data. JMBOUT1FG behaves similarly.

1.12.3 JMBIN0 and JMBIN1 Incoming Mailbox

Two 16-bitregistersareavailableforincomingmessages fromtheJTAG port.OnlyJMBIN0 isused when in16-bittransfermode (JMBMODE = 0).JMBIN1 isused inadditiontoJMBIN0 when using32-bittransfer mode (JMBMODE = 1).When theJTAG portwishestosend a message totheapplication,itwritesdata toJMBIN0 for16-bitmode, orJMBIN0 and JMBIN1 for32-bitmode. JMBIN0FG and JMBIN1FG areflagsthatindicatethestatusofJMBIN0 and JMBIN1, respectively.When JMBIN0FG isset,JMBIN0 has datathatisavailableforreading.When JMBIN0FG isreset,no new datais availableinJMBIN0. JMBIN1FG behaves similarly. JMBIN0FG and JMBIN1FG can be configuredtoclearautomaticallyby clearingJMBCLR0OFF and JMBCLR1OFF, respectively.Otherwise,theseflagsmust be clearedby software. 54 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DeviceDescriptorTable

1.12.4 JMB NMI Usage

The JMB handshake mechanism can be configuredtouse interruptstoavoidunnecessarypollingif desired.In16-bitmode, JMBOUTIFG issetwhen JMBOUT0 has been readby theJTAG portand is readytoreceivedata.In32-bitmode, JMBOUTIFG issetwhen bothJMBOUT0 and JMBOUT1 has been readby theJTAG portand arereadytoreceivedata.IfJMBOUTIE isset,theseeventscause a system NMI. In16-bitmode, JMBOUTIFG isclearedautomaticallywhen dataiswrittentoJMBOUT0. In32-bit mode, JMBOUTIFG Isclearedautomaticallywhen dataiswrittentobothJMBOUT0 and JMBOUT1. In addition,theJMBOUTIFG can be clearedwhen readingSYSSNIV. ClearingJMBOUTIE disablestheNMI interrupt. In16-bitmode, JMBINIFG issetwhen JMBIN0 isavailableforreading.In32-bitmode, JMBINIFG isset when bothJMBIN0 and JMBIN1 areavailableforreading.IfJMBOUTIE isset,theseeventscause a systemNMI. In16-bitmode, JMBINIFG isclearedautomaticallywhen JMBIN0 isread.In32-bitmode, JMBINIFG Isclearedautomaticallywhen bothJMBIN0 and JMBIN1 areread.Inaddition,theJMBINIFG can be clearedwhen readingSYSSNIV. ClearingJMBINIE disablestheNMI interrupt.

1.13 Device DescriptorTable

Each deviceprovidesa datastructureinmemory thatallowsan unambiguous identificationofthedevice, as wellas,a more detaileddescriptionoftheavailablemodules on a givendevice.SYS providesthis informationand can be used by device-adaptiveSW toolsand librariestoclearlyidentifya particular deviceand allmodules and capabilitiescontainedwithinit.The validityofthedevicedescriptorcan be verifiedby cyclicredundancycheck(CRC).Figure1-7shows thelogicalorderand structureofthedevice descriptortable.The completedevicedescriptortableand itscontentscan be foundinthedevicespecific datasheet. 55SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Info_length CRC_length CRC_value DeviceID Firmware□revision Hardware□revision Tag□1 Len□1 Value□field□1 Tag□N Len□N Value□field□N Information□block Device□ID□and□Revision Information First TLV□entry (optional) Additional TLV□entries (optional) Final TLV□entry (optional) Descriptor□start□address ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DeviceDescriptorTable www.ti.com Figure1-7.Devices DescriptorTable

1.13.1 IdentifyingDevice Type

The valuereadataddresslocation00FF0h identifiesthefamilybranchofthedevice.Allvaluesstarting with80h indicatea hierarchicalstructureconsistingoftheinformationblockand a TLV tag-length-value (TLV)structurecontainingthevariousdescriptors.Any othervaluethan80h readataddresslocation 00FF0h indicatesthedeviceisofan olderfamilyand containsa flatdescriptorbeginningatlocation 0FF0h.The informationblock,shown inFigure1-7containsthedeviceID,dierevisions,firmware revisions,and othermanufacturerand toolrelatedinformation.The descriptorscontainsinformationabout theavailableperipherals,theirsubtypesand addressesand providestheinformationrequiredtobuild adaptivehardwaredriversforoperatingsystems. The lengthofthedescriptorsrepresentedby Info_lengthiscomputed as follows: Length= 2Info_lengthin32-bitwords (1) Forexample,ifInfo_length= 5,thenthelengthofthedescriptorsequals128 bytes. 56 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DeviceDescriptorTable

1.13.2 TLV Descriptors

The TLV descriptorsfollowtheinformationblock.Because theinformationblockisalwaysa fixedlength, thestartlocationoftheTLV descriptorsisfixedfora givendevicefamily.FortheMSP430x5xx family,this locationis01A08h.See thedevice-specificdatasheetforthecompleteTLV structureand what descriptorsareavailable. The TLV descriptorsareuniquetotheirrespectiveTLV blockand arealwaysfollowedby thedescriptor blocklength. Each TLV descriptorcontainsa tagfieldwhichidentifiesthedescriptortype.Table1-4shows thecurrently supportedtags. Table1-4.Tag Values ShortName Value Description LDTAG 01h Legacy descriptor(1xx,2xx,4xx families) PDTAG 02h Peripheraldiscoverydescriptor Reserved 03h Futureusage Reserved 04h Futureusage BLANK 05h Blankdescriptor Reserved 06h Futureusage ADCCAL 11h ADC calibration REFCAL 12h REF calibration Reserved 13h -FDh Futureusage TAGEXT FEh Tag extender Each tagfieldisuniquetoitsrespectivedescriptorand isalwaysfollowedby a lengthfield.The length fieldisone byteifthetagvalueis01h through0FDh and representsthelengthofthedescriptorinbytes. Ifthetagvalueequals0FEh (TAGEXT), thenextbyteextendsthetagvalues,and thefollowingtwo bytes representthelengthofthedescriptorinbytes.Inthisway,a usercan searchthroughtheTLV descriptor tablefora particulartagvalue,usinga routinesimilartobelowwritteninpseudo code: //IdentifythedescriptorID(d_ID_value)fortheTLVdescriptorofinterest: descriptor_address=TLV_STARTaddress; while(valueatdescriptor_address!=d_ID_value&&descriptor_address!=TLV_TAGEND&& descriptor_address<TLV_END) //Pointtonextdescriptor descriptor_address=descriptor_address+(lengthofthecurrentTLVblock)+2; if(valueatdescriptor_address==d_ID_value){ //AppropriateTLVdecriptorhasbeenfound! Returnlengthofdescriptor&descriptor_addressasthelocationoftheTLVdescriptor }else{ //NoTLVdescriptorfoundwithamatchingd_ID_value Returnafailingcondition 57SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.13.3 PeripheralDiscoveryDescriptor

Thisdescriptortypecan describeconcatenatedordistributedmemory orperipheralmappings,as wellas, thenumber ofinterruptvectorsand theirorder.The peripheraldiscoverydescriptorhas tagvalue02h (PDTAG). Table1-5shows thestructureoftheperipheraldiscoverydescriptor. NOTE: PeripheralDiscoveryDescriptorisnotavailableineverydevice.See theDeviceDescriptors sectioninthedevice-specificdatasheetfortheavailabilityand detailson Peripheral DiscoveryDescriptor. Table1-5.PeripheralDiscoveryDescriptor Element Size(bytes) Comments memory entry1 2 Optional memory entry2 2 Optional ... 2 Optional delimiter(00h) 1 Mandatory peripheralcount 1 Mandatory peripheralentry1 2 Optional peripheralentry2 2 Optional ... 2 Optional InterruptpriorityN-3 1 Optional InterruptpriorityN-4 1 Optional ... 1 Optional delimiter(00h) 1 Mandatory The structuresfora memory entryand peripheralentryareshown below.A memory entryconsistsoftwo bytes(oneword).Table1-6shows theindividualbitfieldsofa memory entryword and theirrespective meanings.Similarly,a peripheralentryconsistsoftwo bytes(oneword).Table1-7shows theindividualbit fieldsofa peripheralentryword and theirrespectivemeanings. Table1-6.Values forMemory Entry Bitfields Memory type Size More UnitSize Address value 000:None 0000:0 B 0:End Entry 0:0200h 0000000 001:RAM 0001:128 B 1:More Entries 1:010000h 0000001 58 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DeviceDescriptorTable Table1-6.Values forMemory Entry(continued) Bitfields Memory type Size More UnitSize Address value 010:EEPROM 0010:256 B 0000010 011:Reserved 0011:512 B 0000011 100:FLASH 0100:1 KB 0000100 101:ROM 0101:2KB 0000101 110:MemType 0110:4 KB 0000110appended 111:Undefined 0111:8 KB 0000111 1000:16 KB 0001000 1001:32 KB 0001001 1010:64 KB 0001010 1011:128 KB 0001011 1100:256 KB 0001100 1101:512 KB ... 1110:Size ...appended 1111:Undefined 1111111 Table1-7.Values forPeripheralEntry Bitfields [15:8] [7] [6:0] PeripheralID (PID)(1) UnitSize AdrVal Any PID 0:010h 0000000 Any PID 1:0800h 0000001 Any PID 0000010 Any PID 0000011 Any PID 0000100 Any PID 0000101 Any PID ... Any PID ... Any PID 1111111 (1) The PeripheralIDsarelistedinTable1-8.Thisisnota completelist,butshown as an example. Table1-8.PeripheralIDs(1) Peripheralor Module PID No Module 00h WDT 01h SFR 02h UCS 03h SYS 04h PMM 05h FlashController 08h CRC16 09h Port1,2 51h (1) Thistableisnota completelistofallperipheralIDsavailableon a device,butisshown herefor illustrativepurposesonly. 59SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DeviceDescriptorTable www.ti.com Table1-8.PeripheralIDs(1) (continued) Peripheralor Module PID Port3,4 52h Port5,6 53h Port7,8 54h Port9,10 55h PortJ 5Fh TimerA0 81h TimerA1 82h Specialinfoappended FEh Undefinedmodule FFh 60 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DeviceDescriptorTable Table1-9shows a simpleexample fora peripheraldiscoverydescriptorofa hypotheticaldevice: Table1-9.Sample PeripheralDiscoveryDescriptor Hex Binary Entrytype Description 030h,0Eh 001_1000_ 0_0_0001110 memory RAM 16 KB; Startaddress= 01C00h (0Eh *0200h)(1) 09Bh,02Eh 100_1011_0_0_0101110 memory FLASH 128 KB Startaddress= 05C00h (2Eh *0200h) 00h 0000_0000_0000_0000 delimiter No more memory entries 0Fh 0000_1111 peripheralcount Peripheralcount= 15 02h,10h 00000010_0_0010000 peripheral SFR ataddress= 0100h (10h*10h) 01h,01h 00000001_0_0000001 peripheral WDT ataddress= 0110h (0100h+ 10h) 05h,01h 00000101_0_0000001 peripheral PMM ataddress= 0120h (0110h+ 10h) 03h,01h 00000011_0_0000001 peripheral UCS ataddress= 0130h (0120h+ 10h) 08h,01h 00001000_0_0000001 peripheral FLCTL ataddress= 0140h (0130h+ 10h) 09h,01h 00001001_0_0000001 peripheral CRC16 ataddress= 0150h (0140h+ 10h) 04h,01h 00000100_0_0000001 peripheral SYS ataddress= 0160h (0150h+ 10h) 51h,0Ah 01010001_0_0001010 peripheral Port1,2 ataddress= 0200h (0160h+ 10h *10h) 52h,02h 01010010_0_0000010 peripheral Port3,4 ataddress= 0220h (0200h+ 02h *10h) 53h,02h 01010011_0_0000010 peripheral Port5,6 ataddress= 0240h (0220h+ 02h *10h) 54h,02h 01010100_0_0000010 peripheral Port7,8 ataddress= 0260h (0240h+ 02h *10h) 55h,02h 01010101_0_0000010 peripheral Port9,10 ataddress= 0280h (0260h+ 02h *10h) 5Fh,0Ah 01011111_0_0001010 peripheral PortJ ataddress= 0320h (0280h+ 0Ah *10h) 81h,02h 10000001_0_0000010 peripheral TimerA0 ataddress= 0340h (0320h+ 02h *10h) 82h,04h 10000010_0_0000100 peripheral TimerA1 ataddress= 0380h (0340h+ 04h *10h) – No appended entries SYSRSTIV @0FFFEh (implied) SYSSNIV @0FFFC (implied) SYSUNIV @ 0FFFA (implied) 81h 1000_0001 interrupt TA0 CCR0 @ 0FFF8 81h 1000_0001 interrupt TA0 CCR1, CCR1, TA0IFG@ 0FFF6 51h 0101_0001 interrupt Port1 @ 0FFF4 82h 1000_0010 interrupt TA1CCR0 @ 0FFF2 51h 0101_0001 interrupt Port2 @ 0FFF0 81h 1000_0010 interrupt TA1 CCR1, CCR1, TA1IFG@ 0FFEE 00h 0000_0000 delimiter No more interruptentries (1) Inthisexample,thememory typeisRAM (bits[15:13]= 001),thesizeis16KB (bits[12:9]= 1000),and thestartingaddressis 01C00h. The startingaddressiscomputed by takingthesizefieldindicatedby bit[7](inthiscase 0200h)and multiplyingitby theaddressvalue(bits[6:0]= 0001110.Inthiscase,we have 0200h *00Eh = 01C00h. NOTE: The interruptorderinghas some impliedrules:

Fortimers,CCR0 interrupthas higherpriorityoverallotherCCRn interrupts.
Forcommunicationports,RX has higherpriorityoverTX
Forportpairs,Port1 has higherpriorityoverPort2,Port3 has higherpriorityoverPort 4,etc. 61SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.13.4 CRC Computation

The CRC checksum fortheTLV structureisstoredatmemory locations0x1A02 and 0x1A03.The least significantbyte(LSB)and most significantbyte(MSB) resideatmemory locations0x1A02 and 0x1A03, respectively.The checksum iscomputed usingdatastoredatmemory locations0x1A04 through0x1AFF. The CRC checksum can be easilycomputed usingtheCRC16 module.The followingsimplifiedC code utilizestheCRC16 module tocompute thechecksum.Pleasesee theCRC16 chapterforfurtherdetailson theCRC algorithmimplementation. NOTE: The CRC module on theCC430F613x, CC430F612x, and CC430F513x devicesdoes not supportthebit-wisereversefeatureused inthiscode example.RegistersCRCDIRB and CRCRESR, alongwiththeirrespectivefunctionality,arenotavailable. unsignedinti; unsignedcharCRCRESULT_LSB,CRCRESULT_MSB; WDTCTL=WDTPW+WDTHOLD; CRCINIRES=0xFFFF; for(i=0x01A04;i<=0x01AFF;i++){ CRCDIRB_L=*(unsignedchar*)(i); CRCRESULT_LSB=CRCINIRES_L;//valuestored@0x1A02 CRCRESULT_MSB=CRCINIRES_H;//valuestored@0x1A03 62 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

1521___ /c180/c61 GAINF ACTORGAINADCCAL OFFSETADCCALrawADCcorrectedoffsetADC __)()_( /c43/c61 152 1_15_)()( /c180/c180/c61 F ACTORVREFADCCALrawADCcorr ectedADC 152 1_20_)()( /c180/c180/c61 F ACTORVREFADCCALrawADCcorrectedADC 152 1_25_)()( /c180/c180/c61 F AC T O RVREFAD CC ALrawAD Ccorr ectedAD C 1525 . 1_15__ /c180/c61 /c43 V VF ACTORVREFADCCAL REF 1520 . 2_20__ /c180/c61 /c43 V VF ACTORVREFADCCAL REF 1 525 . 2_2 5__ /c180/c61 /c43 V VF A C TO RV R E FA D CC A L R E F ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DeviceDescriptorTable

1.13.5 CalibrationValues

The TLV structurecontainscalibrationvaluesthatcan be used toimprovethemeasurement capabilityof variousfunctions.The calibrationvaluesavailableon a givendeviceareshown intheTLV structureofthe device-specificdatasheet. 1.13.5.1REF Calibration The calibrationdatafortheREF module consistsofthreewords,one word foreach referencevoltage valuesarenormalizedby 1.5/2.0/2.5V beforebeingstoredintotheTLV structure: (2) Inthisway,a conversionresultiscorrectedby multiplyingitwiththeCAL_15VREF_FACTOR (or CAL_20VREF_FACTOR, CAL_25VREF_FACTOR) and dividingtheresultby 215 as shown foreach ofthe respectivereferencevoltages: (3) Inthefollowingexample,theintegrated1.5-Vreferencevoltageisused duringa conversion.

Conversionresult:0x0100 = 256 decimal
Referencevoltagecalibrationfactor(CAL_15VREF_FACTOR) :0x7BBB The followingstepsshow how theADC conversionresultcan be corrected:
Multiplytheconversionresultby 2 (thisstepsimplifiesthefinaldivision):0x0100 x 0x0002 = 0x0200
Multiplytheresultby CAL_15VREF_FACTOR: 0x200 x 0x7FEE = 0x00F7_7600
Dividetheresultby 216:0x00F7_7600 /0x0001_0000 = 0x0000_00F7 = 247 decimal 1.13.5.2ADC Offsetand Gain Calibration The offsetoftheADC isdeterminedand storedas a twos-complementnumber intheTLV structure.The offseterrorcorrectionisdone by addingtheCAL_ADC_OFFSET totheconversionresult. (4) The gainoftheADC12 iscalculatedby Equation5: (5) The conversionresultisgaincorrectedby multiplyingitwiththeCAL_ADC_GAIN_FACTOR and dividing theresultby 215: 63SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

/c40 /c41 303015__8515__ /c248 /c246 /c231/c231 /c232 /c230 /c45 /c45/c180/c45/c61 TADCCALTADCCALTADCCALrawADCT emp /c40 /c41 303020__8520__ /c248 /c246 /c231/c231 /c232 /c230 /c45 /c45/c180/c45/c61 TADCCALTADCCALTADCCALrawADCT emp /c40 /c41 303025__8525__ /c248 /c246 /c231/c231 /c232 /c230 /c45 /c45/c180/c45/c61 TADCCALTADCCALTADCCALrawADCT emp SENSORSENSORSENSE VT empTCV /c43/c180/c61 152 1___)()_( /c180/c180/c61 FACTORGAINADCCALrawADCcorrectedgainADC OFFSETADCCALcorrectedgainADCfinalADC __)_()( /c43/c61 152 1___)()_( /c180/c180/c61 F ACTORGAINADCCALrawADCcorrectedgainADC ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DeviceDescriptorTable www.ti.com (6) Ifbothgainand offsetarecorrected,thegaincorrectionisdone first: (7) 1.13.5.3Temperature Sensor Calibration The temperaturesensoriscalibratedusingtheinternalvoltagereferences.Each referencevoltage (1.5/2.0/2.5V) containsa measured valuefortwo temperatures,30°C ±3°C and 85°C ±3°C and arestored intheTLV structure.The characteristicequationofthetemperaturesensorvoltage,inmV is: (8) The temperaturecoefficient,TC SENSOR inmV/°C, representstheslopeoftheequation.VSENSOR ,inmV, representsthey-interceptoftheequation.Temp, in°C, isthetemperatureofinterest. The temperature(Temp,°C) can be computed as followsforeach ofthereferencevoltagesused inthe ADC measurement: (9) 64 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com SFR Registers

1.14 SFR Registers

The SFRs arelistedinTable1-11.The base addressfortheSFRs islistedinTable1-10.Many ofthebits insidetheSFRs aredescribedinotherchaptersthroughoutthisuser'sguide.These bitsaremarked with a noteand a reference.See thespecificchapteroftherespectivemodule fordetails. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table1-10.SFR Base Address Module Base Address SFR 00100h Table1-11.SFR Registers Offset Acronym RegisterName Type Access Reset Section 00h SFRIE1 InterruptEnable Read/write Word 0000h Section5.4.4 00h SFRIE1_L (IE1) Read/write Byte 00h 01h SFRIE1_H (IE2) Read/write Byte 00h 02h SFRIFG1 InterruptFlag Read/write Word 0082h Section1.14.2 02h SFRIFG1_L (IFG1) Read/write Byte 82h 03h SFRIFG1_H (IFG2) Read/write Byte 00h 04h SFRRPCR ResetPinControl Read/write Word 0000h Section1.14.3 04h SFRRPCR_L Read/write Byte 00h 05h SFRRPCR_H Read/write Byte 00h 65SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.14.1 SFRIE1 Register

Figure1-8.SFRIE1 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 JMBOUTIE JMBINIE ACCVIE (1) NMIIE VMAIE Reserved OFIE (2) WDTIE (3) rw-0 rw-0 rw-0 rw-0 rw-0 r0 rw-0 rw-0 (1) See theFlashControllerchapterfordetails. (2) See theUCS chapterfordetails. (3) See theWDT_A chapterfordetails. Table1-12.SFRIE1 RegisterDescription Bit Field Type Reset Description 15-8 Reserved R 0h Reserved.Alwaysreadsas 0.

7 JMBOUTIE RW 0h JTAG mailboxoutputinterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled

6 JMBINIE RW 0h JTAG mailboxinputinterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled

5 ACCVIE RW 0h Flashcontrolleraccessviolationinterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled

4 NMIIE RW 0h NMI pininterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled

3 VMAIE RW 0h Vacantmemory accessinterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled 2 Reserved R 0h Reserved.Alwaysreadsas 0.

1 OFIE RW 0h Oscillatorfaultinterruptenableflag

0b = Interruptsdisabled 1b = Interruptsenabled 0 WDTIE RW 0h Watchdog timerinterruptenable.ThisbitenablestheWDTIFG interruptfor intervaltimermode. Itisnotnecessarytosetthisbitforwatchdogmode. Because otherbitsin~IE1 may be used forothermodules,itisrecommended to setorclearthisbitusingBIS.BorBIC.Binstructions,ratherthanMOV.B or CLR.B instruction 0b = Interruptsdisabled 1b = Interruptsenabled 66 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.14.2 SFRIFG1 Register

Figure1-9.SFRIFG1 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 JMBOUTIFG JMBINIFG Reserved NMIIFG VMAIFG Reserved OFIFG (1) WDTIFG (2) rw-(1) rw-(0) r0 rw-0 rw-0 r0 rw-(1) rw-0 (1) See theUCS chapterfordetails. (2) See theWDT_A chapterfordetails. Table1-13.SFRIFG1 RegisterDescription Bit Field Type Reset Description 15-8 Reserved R 0h Reserved.Alwaysreadsas 0.

7 JMBOUTIFG RW 1h JTAG mailboxoutputinterruptflag

0b = No interruptpending.When in16-bitmode (JMBMODE = 0),thisbitis clearedautomaticallywhen JMBO0 has been writtenwitha new message tothe JTAG module by theCPU. When in32-bitmode (JMBMODE = 1),thisbitis clearedautomaticallywhen bothJMBO0 and JMBO1 have been writtenwithnew messages totheJTAG module by theCPU. Thisbitisalsoclearedwhen the associatedvectorinSYSUNIV has been read. 1b = Interruptpending,JMBO registersarereadyfornew messages.In16-bit mode (JMBMODE = 0),JMBO0 has been receivedby theJTAG module and is readyfora new message fromtheCPU. In32-bitmode (JMBMODE = 1), JMBO0 and JMBO1 have been receivedby theJTAG module and arereadyfor new messages fromtheCPU.

6 JMBINIFG RW 0h JTAG mailboxinputinterruptflag

0b = No interruptpending.When in16-bitmode (JMBMODE = 0),thisbitis clearedautomaticallywhen JMBI0 isreadby theCPU. When in32-bitmode (JMBMODE = 1),thisbitisclearedautomaticallywhen bothJMBI0 and JMBI1 have been readby theCPU. Thisbitisalsoclearedwhen theassociatedvector inSYSUNIV has been read 1b = Interruptpending,a message iswaitingintheJMBIN registers.In16-bit mode (JMBMODE = 0)when JMBI0 has been writtenby theJTAG module.In 32-bitmode (JMBMODE = 1)when JMBI0 and JMBI1 have been writtenby the JTAG module. 5 Reserved R 0h Reserved.Alwaysreadsas 0.

4 NMIIFG RW 0h NMI pininterruptflag

0b = No interruptpending 1b = Interruptpending

3 VMAIFG RW 0h Vacantmemory accessinterruptflag

0b = No interruptpending 1b = Interruptpending 2 Reserved R 0h Reserved.Alwaysreadsas 0.

1 OFIFG RW 1h Oscillatorfaultinterruptflag

0b = No interruptpending 1b = Interruptpending 67SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. SFR Registers www.ti.com Table1-13.SFRIFG1 RegisterDescription(continued) Bit Field Type Reset Description 0 WDTIFG RW 0h Watchdog timerinterruptflag.Inwatchdogmode, WDTIFG willselfclearupon a watchdogtimeoutevent.The SYSRSTIV can be readtodetermineifthereset was caused by a watchdogtimeoutevent.Inintervalmode, WDTIFG isreset automaticallyby servicingtheinterrupt,orcan be resetby software.Because otherbitsin~IFG1 may be used forothermodules,itisrecommended tosetor clearWDTIFG by usingBIS.BorBIC.Binstructions,ratherthanMOV.B or CLR.B instructions. 0b = No interruptpending 1b = Interruptpending 68 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.14.3 SFRRPCR Register

Figure1-10.SFRRPCR Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved SYSRSTRE (1) SYSRSTUP (1) SYSNMIIES SYSNMI r0 r0 r0 r0 rw-1 rw-1 rw-0 rw-0 (1) AlldevicesexcepttheMSP430F5438 (non-A)defaulttopullupenabledon theresetpin. Table1-14.SFRRPCR RegisterDescription Bit Field Type Reset Description 15-4 Reserved R 0h Reserved.Alwaysreadsas 0.

3 SYSRSTRE RW 1h Resetpinresistorenable

0b = Pullup/pulldownresistorattheRST/NMI pinisdisabled 1b = Pullup/pulldownresistorattheRST/NMI pinisenabled

2 SYSRSTUP RW 1h Resetresistorpinpullup/pulldown

0b = Pulldownisselected 1b = Pullupisselected 1 SYSNMIIES RW 0h NMI edge select.Thisbitselectstheinterruptedge fortheNMI when SYSNMI = 1.Modifyingthisbitcan triggeran NMI. Modifythisbitwhen SYSNMI = 0 to avoidtriggeringan accidentalNMI. 0b = NMI on risingedge 1b = NMI on fallingedge 0 SYSNMI RW 0h NMI select.ThisbitselectsthefunctionfortheRST/NMI pin. 0b = Resetfunction 1b = NMI function 69SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15 SYS Registers

The SYS configurationregistersarelistedinTable1-16and thebase addressislistedinTable1-15.A detaileddescriptionofeach registerand itsbitsisalsoprovided.Each registerstartsata word boundary. Eitherword orbytedatacan be writtentotheSYS configurationregisters. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table1-15.SYS Base Address Module Base Address SYS 00180h Table1-16.SYS Registers Offset Acronym RegisterName Type Access Reset Section 00h SYSCTL System Control Read/write Word 0000h Section1.15.1 00h SYSCTL_L Read/write Byte 00h 01h SYSCTL_H Read/write Byte 00h 02h SYSBSLC BootstrapLoaderConfiguration Read/write Word 0003h Section1.15.2 02h SYSBSLC_L Read/write Byte 03h 03h SYSBSLC_H Read/write Byte 00h 06h SYSJMBC JTAG MailboxControl Read/write Word 0000h Section1.15.3 06h SYSJMBC_L Read/write Byte 00h 07h SYSJMBC_H Read/write Byte 00h 08h SYSJMBI0 JTAG MailboxInput0 Read/write Word 0000h Section1.15.4 08h SYSJMBI0_L Read/write Byte 00h 09h SYSJMBI0_H Read/write Byte 00h 0Ah SYSJMBI1 JTAG MailboxInput1 Read/write Word 0000h Section1.15.5 0Ah SYSJMBI1_L Read/write Byte 00h 0Bh SYSJMBI1_H Read/write Byte 00h 0Ch SYSJMBO0 JTAG MailboxOutput0 Read/write Word 0000h Section1.15.6 0Ch SYSJMBO0_L Read/write Byte 00h 0Dh SYSJMBO0_H Read/write Byte 00h 0Eh SYSJMBO1 JTAG MailboxOutput1 Read/write Word 0000h Section1.15.7 0Eh SYSJMBO1_L Read/write Byte 00h 0Fh SYSJMBO1_H Read/write Byte 00h 18h SYSBERRIV Bus ErrorVectorGenerator Read Word 0000h Section1.15.11 1Ah SYSUNIV User NMI VectorGenerator Read Word 0000h Section1.15.8 1Ch SYSSNIV System NMI VectorGenerator Read Word 0000h Section1.15.9 1Eh SYSRSTIV ResetVectorGenerator Read Word 0002h Section1.15.10 70 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com SYS Registers

1.15.1 SYSCTL Register

Figure1-11.SYSCTL Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved SYSJTAGPIN SYSBSLIND Reserved SYSPMMPE Reserved SYSRIVECT r0 r0 rw-[0] r-0 r0 rw-[0] r0 rw-[0] Table1-17.SYSCTL RegisterDescription Bit Field Type Reset Description 15-6 Reserved R 0h Reserved.Alwaysreadsas 0. 5 SYSJTAGPIN RW 0h DedicatedJTAG pinsenable.Settingthisbitdisablesthesharedfunctionalityof theJTAG pinsand permanentlyenablestheJTAG function.Thisbitcan onlybe setonce.Once itissetitremainssetuntila BOR occurs. 0b = Shared JTAG pins(JTAG mode selectableviaSBW sequence) 1b = DedicatedJTAG pins(explicit4-wireJTAG mode selection) 4 SYSBSLIND RW 0h BSL entryindication.Thisbitindicatesa BSL entrysequence detectedon the Spy-Bi-Wirepins. 0b = No BSL entrysequence detected 1b = BSL entrysequence detected 3 Reserved R 0h Reserved.Alwaysreadsas 0. 2 SYSPMMPE RW 0h PMM accessprotect.ThiscontrolstheaccessibilityofthePMM controlregisters. Once setto1,itonlycan be clearedby a BOR. 0b = Access fromanywhere inmemory 1b = Access onlyfromtheprotectedBSL segments 1 Reserved R 0h Reserved.Alwaysreadsas 0.

0 SYSRIVECT RW 0h RAM-based interruptvectors

0b = Interruptvectorsgeneratedwithend addressTOP oflower64k flashFFFFh 1b = Interruptvectorsgeneratedwithend addressTOP ofRAM 71SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.2 SYSBSLC Register

BootstrapLoaderConfigurationRegister Figure1-12.SYSBSLC Register 15 14 13 12 11 10 9 8 SYSBSLPE SYSBSLOFF Reserved rw-[0] rw-[0] r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved SYSBSLR SYSBSLSIZE r0 r0 r0 r0 r0 rw-[0] rw-[1] rw-[1] Table1-18.SYSBSLC RegisterDescription Bit Field Type Reset Description 15 SYSBSLPE RW 0h Bootstraploadermemory protectionenableforthesizecoveredinSYSBSLSIZE. By default,thisbitisclearedby hardwarewitha BOR event(asindicatedabove), however thebootcode thatchecksforan availableBSL may setthisbitvia softwareinordertoprotecttheBSL. Sincedevicesnormallycome witha TIBSL preprogrammed and protected,thebootcode setsthisbit. 0b = Area notprotected.Read, program,and eraseofBSL memory ispossible. 1b = Area protected

14 SYSBSLOFF RW 0h Bootstraploadermemory disableforthesizecoveredinSYSBSLSIZE

0b = BSL memory isaddressedwhen thisareaisread. 1b = BSL memory behaves likevacantmemory. Reads cause 3FFFh tobe read. Fetchescause JMP $ tobe executed. 13-3 Reserved R 0h Reserved.Alwaysreadsas 0.

2 SYSBSLR RW 0h RAM assignedtoBSL

0b = No RAM assignedtoBSL area 1b = Lowest16 bytesofRAM assignedtoBSL 1-0 SYSBSLSIZE RW 03h Bootstraploadersize.Definesthespace and sizeofflashmemory thatis reservedfortheBSL. 00b = Size:BSL segment 3 01b = Size:BSL segments 2 and 3 10b = Size:BSL segments 1,2,and 3 11b = Size:BSL segments 1,2,3,and 4 72 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.3 SYSJMBC Register

JTAG MailboxControlRegister Figure1-13.SYSJMBC Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 JMBCLR1OFF JMBCLR0OFF Reserved JMBM0DE JMBOUT1FG JMBOUT0FG JMBIN1FG JMBIN0FG rw-(0) rw-(0) r0 rw-0 r-(1) r-(1) rw-(0) rw-(0) Table1-19.SYSJMBC RegisterDescription Bit Field Type Reset Description 15-8 Reserved R 0h Reserved.Alwaysreadsas 0.

7 JMBCLR1OFF RW 0h IncomingJTAG Mailbox1 flagauto-cleardisable

0b = JMBIN1FG clearedon readofJMB1IN register 1b = JMBIN1FG clearedby software

6 JMBCLR0OFF RW 0h IncomingJTAG Mailbox0 flagauto-cleardisable

0b = JMBIN0FG clearedon readofJMB0IN register 1b = JMBIN0FG clearedby software 5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 JMBMODE RW 0h Thisbitdefinestheoperationmode ofJMB forJMBI0/1and JMBO0/1. Before switchingthisbit,pad and flushoutany partialcontenttoavoiddatadrops. 0b = 16-bittransfersusingJMBO0 and JMBI0 only 1b = 32-bittransfersusingJMBO0/1 and JMBI0/1 3 JMBOUT1FG RW 1h OutgoingJTAG Mailbox1 flag.Thisbitisclearedautomaticallywhen a message iswrittentotheupperbyteofJMBO1 oras word access(bytheCPU, DMA, … ) and issetafterthemessage was readviaJTAG. 0b = JMBO1 isnotreadytoreceivenew data. 1b = JMBO1 isreadytoreceivenew data. 2 JMBOUT0FG RW 1h OutgoingJTAG Mailbox0 flag.Thisbitisclearedautomaticallywhen a message iswrittentotheupperbyteofJMBO0 oras word access(bytheCPU, DMA, … ) and issetafterthemessage was readviaJTAG. 0b = JMBO0 isnotreadytoreceivenew data. 1b = JMBO0 isreadytoreceivenew data. 1 JMBIN1FG RW 0h IncomingJTAG Mailbox1 flag.Thisbitissetwhen a new message (providedvia JTAG) isavailableinJMBI1.Thisflagisclearedautomaticallyon readofJMBI1 when JMBCLR1OFF = 0 (autoclearmode).On JMBCLR1OFF = 1,JMBIN1FG needs tobe clearedby SW. 0b = JMBI1 has no new data. 1b = JMBI1 has new dataavailable. 0 JMBIN0FG RW 0h IncomingJTAG Mailbox0 flag.Thisbitissetwhen a new message (providedvia JTAG) isavailableinJMBI0.Thisflagisclearedautomaticallyon readofJMBI0 when JMBCLR0OFF = 0 (autoclearmode).On JMBCLR0OFF = 1,JMBIN0FG needs tobe clearedby SW. 0b = JMBI1 has no new data. 1b = JMBI1 has new dataavailable. 73SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.4 SYSJMBI0 Register

JTAG MailboxInput0 Register Figure1-14.SYSJMBI0 Register 15 14 13 12 11 10 9 8 MSGHI r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 MSGLO r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 Table1-20.SYSJMBI0 RegisterDescription Bit Field Type Reset Description 15-8 MSGHI R 0h JTAG mailboxincomingmessage highbyte 7-0 MSGLO R 0h JTAG mailboxincomingmessage lowbyte

1.15.5 SYSJMBI1 Register

JTAG MailboxInput0 Register Figure1-15.SYSJMBI1 Register 15 14 13 12 11 10 9 8 MSGHI r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 MSGLO r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 Table1-21.SYSJMBI1 RegisterDescription Bit Field Type Reset Description 15-8 MSGHI R 0h JTAG mailboxincomingmessage highbyte 7-0 MSGLO R 0h JTAG mailboxincomingmessage lowbyte 74 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.6 SYSJMBO0 Register

JTAG MailboxOutput0 Register Figure1-16.SYSJMBO0 Register 15 14 13 12 11 10 9 8 MSGHI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 MSGL0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table1-22.SYSJMBO0 RegisterDescription Bit Field Type Reset Description 15-8 MSGHI RW 0h JTAG mailboxoutgoingmessage highbyte 7-0 MSGLO RW 0h JTAG mailboxoutgoingmessage lowbyte

1.15.7 SYSJMBO1 Register

JTAG MailboxOutput1 Register Figure1-17.SYSJMBO1 Register 15 14 13 12 11 10 9 8 MSGHI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 MSGL0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table1-23.SYSJMBO1 RegisterDescription Bit Field Type Reset Description 15-8 MSGHI RW 0h JTAG mailboxoutgoingmessage highbyte 7-0 MSGLO RW 0h JTAG mailboxoutgoingmessage lowbyte 75SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.8 SYSUNIV Register

NOTE: Additionaleventsformore complexdevicesareappended tothistable;sourcesthatare removed reducethelengthofthistable.The vectorsareexpectedtobe accessedsymbolic onlywiththecorrespondingincludefileofthedeviceinuse. Figure1-18.SYSUNIV Register 15 14 13 12 11 10 9 8 SYSUNVEC r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSUNVEC r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table1-24.SYSUNIV RegisterDescription Bit Field Type Reset Description 15-0 SYSUNIV R 0h User NMI vector.Generatesa valuethatcan be used as addressoffsetforfast interruptserviceroutinehandling.Writingtothisregisterclearsallpendinguser NMI flags. 00h = No interruptpending 02h = NMIIFG interruptpending(highestpriority) 04h = OFIFG interruptpending 06h = ACCVIFG interruptpending 08h = BUSIFG interruptpending(Notpresenton alldevices.See device-specific datasheet) 76 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com SYS Registers

1.15.9 SYSSNIV Register

NOTE: Additionaleventsformore complexdevicesareappended tothistable;sourcesthatare removed reducethelengthofthistable.The vectorsareexpectedtobe accessedsymbolic onlywiththecorrespondingincludefileoftheused device. Figure1-19.SYSSNIV Register 15 14 13 12 11 10 9 8 SYSSNVEC r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSSNVEC r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table1-25.SYSSNIV RegisterDescription Bit Field Type Reset Description 15-0 SYSSNIV R 0h System NMI vector.Generatesa valuethatcan be used as addressoffsetfor fastinterruptserviceroutinehandling.Writingtothisregisterclearsallpending systemNMI flags. 00h = No interruptpending 02h = SVMLIFG interruptpending(highestpriority) 04h = SVMHIFG interruptpending 06h = SVSMLDLYIFG interruptpending 08h = SVSMHDLYIFG interruptpending 0Ah = VMAIFG interruptpending 0Ch = JMBINIFG interruptpending 0Eh = JMBOUTIFG interruptpending 10h = SVMLVLRIFG interruptpending 12h = SVMHVLRIFG interruptpending 14h = Reserved 77SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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1.15.10 SYSRSTIV Register

ResetInterruptVectorRegister NOTE: Additionaleventsformore complexdevicesareappended tothistable;sourcesthatareremoved reducethelengthofthistable.The vectorsareexpectedtobe accessedsymboliconlywiththe correspondingincludefileoftheused device. Figure1-20.SYSRSTIV Register 15 14 13 12 11 10 9 8 SYSRSTVEC r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSRSTVEC r0 r0 r-0 r-0 r-0 r-0 r-1 r0 Table1-26.SYSRSTIV RegisterDescription Bit Field Type Reset Description 15-0 SYSRSTIV R 0h Resetinterruptvector.Generatesa valuethatcan be used as addressoffsetfor fastinterruptserviceroutinehandlingtoidentifythelastcause ofa reset(BOR, POR, PUC) .Writingtothisregisterclearsallpendingresetsourceflags. 00h = No interruptpending 02h = Brownout(BOR) (highestpriority) 04h = RST/NMI (BOR) 06h = PMMSWBOR (BOR) 08h = Wakeup fromLPMx.5 (BOR) 0Ah = Securityviolation(BOR) 0Ch = SVSL (POR) 0Eh = SVSH (POR) 10h = SVML_OVP (POR) 12h = SVMH_OVP (POR) 14h = PMMSWPOR (POR) 16h = WDT timeout(PUC) 18h = WDT passwordviolation(PUC) 1Ah = Flashpasswordviolation(PUC) 1Ch = Reserved 1Eh = PERF peripheral/configurationareafetch(PUC) 20h = PMM passwordviolation(PUC) 22h to3Eh = Reserved 78 System Resets,Interrupts,and OperatingModes, System ControlModule SLAU259E –May 2009–RevisedJanuary2013 (SYS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com SYS Registers

1.15.11 SYSBERRIV Register

System Bus ErrorInterruptVectorRegister NOTE: Additionaleventsformore complexdevicesareappended tothistable;sourcesthatareremoved reducethelengthofthistable.The vectorsareexpectedtobe accessedsymboliconlywiththe correspondingincludefileoftheused device. Figure1-21.SYSBERRIV Register 15 14 13 12 11 10 9 8 SYSBERRIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 SYSBERRIV r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table1-27.SYSBERRIV RegisterDescription Bit Field Type Reset Description 15-0 SYSBERRIV R 0h System bus errorinterruptvector.Generatesa valuethatcan be used as an addressoffsetforfastinterruptserviceroutinehandling.Writingtothisregister clearsallpendingflags. 00h = No interruptpending 02h = USB module timedout.Waitstatetimeoutof8 clockcycles.16 clock cyclesonlyon theF552x and F551x devices. 04h = Reservedforfutureextensions 06h = Reservedforfutureextensions 08h = Reservedforfutureextensions 79SLAU259E –May 2009–RevisedJanuary2013 System Resets,Interrupts,and OperatingModes, System ControlModule (SYS)SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter2 SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and Supply Voltage Supervisor This chapter describes the operation of the Power Management Module (PMM) and SupplyVoltageSupervisor(SVS).

80 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

2.01.8 System□Frequency□-□MHz Supply□Voltage□-□V The□numbers□within□the□fields□denote□the□supported□PMMCOREVx□settings. 2.2 2.4 3.6 1,□2,□31,□21 2,□3 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Power Management Module (PMM) Introduction

2.1 Power Management Module (PMM) Introduction

PMM featuresinclude:

Wide supplyvoltage(DVCC )range:1.8V to3.6V
Generationofvoltageforthedevicecore(VCORE )withup tofourprogrammablelevels
Supplyvoltagesupervisor(SVS) forDV CC and VCORE withprogrammablethresholdlevels
Supplyvoltagemonitor(SVM) forDV CC and VCORE withprogrammablethresholdlevels
Brownoutreset(BOR)
Softwareaccessiblepower-failindicators
I/Oprotectionduringpower-failcondition
Softwareselectablesupervisorormonitorstateoutput(optional) The PMM manages allfunctionsrelatedtothepower supplyand itssupervisionforthedevice.Itsprimary functionsarefirsttogeneratea supplyvoltageforthecorelogic,and second,provideseveral mechanisms forthesupervisionand monitoringofboththevoltageappliedtothedevice(DVCC )and the voltagegeneratedforthecore(VCORE ). The PMM uses an integratedlow-dropoutvoltageregulator(LDO) toproducea secondarycorevoltage (VCORE )fromtheprimaryone appliedtothedevice(DVCC ).Ingeneral,VCORE suppliestheCPU, memories (flashand RAM), and thedigitalmodules,whileDV CC suppliestheI/Osand allanalogmodules (including theoscillators).The VCORE outputismaintainedusinga dedicatedvoltagereference.VCORE is programmableup tofoursteps,toprovideonlyas much power as isneeded forthespeed thathas been selectedfortheCPU. Thisenhances power efficiencyofthesystem.The inputorprimarysideofthe regulatorisreferredtointhischapteras itshighside.The outputorsecondarysideisreferredtointhis chapteras itslowside. The requiredminimum voltageforthecoredepends on theselectedMCLK rate.Figure2-1shows the relationshipbetween thesystemfrequencyfora givencorevoltagesetting,as wellas theminimum requiredvoltageappliedtothedevice.Figure2-1isonlyan example— see thedevice-specificdatasheet todeterminewhichcorevoltagelevelsaresupportedand what levelofsystemfrequencyperformanceis possiblefora givendevice. Figure2-1.System Frequency,Supply Voltage,and Core Voltage– See Device-SpecificData Sheet 81SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

H H Regulator SVS SVM L L DVCC Reference VCORE OR To reset logic NORPorts ON BOR Control bits PMMCOREV To reset logic ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Power Management Module (PMM) Introduction www.ti.com The PMM module providesmeans forDV CC and VCORE tobe supervisedand monitored.Bothofthese functionsdetectwhen a voltagefallsundera specificthreshold.Ingeneral,thedifferenceisthat supervisionresultsina power-onreset(POR) event,whilemonitoringresultsinthegenerationofan interruptflagthatsoftwaremay thenhandle.As such,DV CC issupervisedand monitoredby thehigh-side supervisor(SVSH )and high-sidemonitor(SVM H ),respectively.VCORE issupervisedand monitoredby the low-sidesupervisor(SVSL)and low-sidemonitor(SVM L),respectively.Thus,therearefourseparate supervisionand monitoringmodules thatcan be activeatany giventime.The thresholdsenforcedby thesemodules arederivedfromthesame voltagereferenceused by theregulatortogenerateVCORE . InadditiontotheSVS H ,SVM H ,SVS L,and SVM L modules,VCORE isfurthermonitoredby thebrownoutreset (BOR) circuit.As DV CC ramps up from0 V atpower up,theBOR keeps thedeviceinresetuntilVCORE isat a sufficientlevelforoperationatthedefaultMCLK rateand fortheSVS H and SVS L mechanisms tobe activated.Duringoperation,theBOR alsogeneratesa resetifVCORE fallsbelowa presetthreshold.BOR can be used toprovidean even lower-powermeans ofmonitoringthesupplyrailiftheflexibilityofthe SVS L isnotrequired. The blockdiagramofthePMM isshown inFigure2-2. Figure2-2.PMM Block Diagram

82 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Operation

2.2 PMM Operation

2.2.1 VCORE and theRegulator

DV CC can be powered froma wideinputvoltagerange,butthecorelogicofthedevicemust be keptata voltagelowerthanwhat thisrangeallows.Forthisreason,a regulatorhas been integratedintothePMM. The regulatorderivesthenecessarycorevoltage(VCORE )fromDV CC . HigherMCLK speeds requirehigherlevelsofVCORE .HigherlevelsofVCORE consume more power,and so thecorevoltagehas been made programmableinup tofourstepstoallowittoprovideonlyas much power as isrequiredfora givenMCLK setting.The leveliscontrolledby thePMMCOREV bits.Note that thedefaultsetting,thelowestvalueofPMMCOREV, enablesoperationofMCLK overa verywide frequencyrange.As such,no PMM changes arerequiredformany applications.See thedevice-specific datasheetforperformancecharacteristicsand coresteplevelssupported. BeforeincreasingMCLK toa higherspeed,itisnecessaryforsoftwaretoensurethattheVCORE levelis sufficientlyhighforthechosen frequency.Failuretodo so may forcetheCPU toattemptoperationwithout sufficientpower,whichcan cause unpredictableresults.See Section2.2.4formore informationon the appropriateproceduretoraiseVCORE forhigherMCLK frequencies. The regulatorsupportstwo differentloadsettingstooptimizepower.The high-currentmode isrequired when:

The CPU isinactive,LPM0, orLPM1 modes
A clocksourcegreaterthan32 kHz isused todriveany module
An interruptisexecuted Otherwise,thelow-currentmode isused.The hardwarecontrolstheloadsettingsautomatically,according tothecriteriaabove.

2.2.2 Supply VoltageSupervisorand Monitor

The high-sidesupervisorand monitor(SVSH and SVM H )overseeDV CC ,and thelow-sidesupervisorand monitor(SVSL and SVM L)overseeVCORE .By default,allofthesemodules areactive,buteach can be disabledusingthecorrespondingenablebit(SVSHE, SVMHE, SVSLE, SVMLE), resultinginsome power savings. Typicalapplicationscenariosforsupplyvoltagesupervisorsand monitorsare:

High-SideSupervisor,SVSH – Supervisionofexternalpower supply(DVCC) – Deviceresetbecause oflowbatteryorsupplyvoltage
High-SideMonitor,SVMH – Monitoringofexternalpower supply(DVCC) – Detectionoflowbatteryvoltage(Pre-warning)
Low-SideSupervisor,SVSL – Supervisionofinternalcorevoltageused tosupplydigitalcore – Deviceresetbecause ofdisruptiveconditionsatexternalVCORE pin(forexample a short).The internalcorevoltageneverdropsbelowa criticallevelifparasiticeventsattheexternalVCORE pin areavoided.
Low-SideMonitor,SVML – Monitoringofinternalcorevoltageused tosupplydigitalcore – Detectionofcorrectinternalvoltagelevelswhen changing(especiallyincreasing)thecorevoltage levelbeforechanging,forexample,tohighersystemfrequencies(alsosee Section2.2.4).

2.2.2.1 SVS and SVM Thresholds

The voltagethresholdsenforcedby theSVS and SVM modules areselectable.Table2-1shows theSVS and SVM thresholdregisters,thevoltagethresholdtheycontrol,and thenumber ofthresholdoptions. 83SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PMM Operation www.ti.com Table2-1.SVS and SVM Thresholds Register Description Threshold AvailableSteps SVSHRVL SVS H resetvoltagelevel SVS H_IT- 4 SVSMHRRL SVS H ,SVM H resetreleasevoltagelevel SVS H_IT+,SVM H 8 SVSLRVL SVS L resetvoltagelevel SVS L_IT- 4 SVSMLRRL SVS L,SVM L resetreleasevoltagelevel SVS L_IT+,SVM L 4(1) (1) The registersettingssupportup toeightlevels(0through7);however,levels3 through7 areidentical. 2.2.2.1.1Recommended SVS L Settings Foreach ofthecorevoltages,therearetwo supplyvoltagesupervisorlevelsavailable.The SVSLRVL bits definethevoltagelevelofVCORE belowwhichtheresetisactivated.The SVSMLRRL bitsdefinethe voltagelevelofVCORE atwhichtheresetisreleased.Althoughvarioussettingscan be chosen,thereis one setofSVSLRVL and SVSMLRRL settingsthatiswellsuitedforeach corevoltageselectedby PMMCOREV. By default,an SVS L eventalwaysgeneratesa POR (SVSLPE = 1),and itisrecommended toalwaysconfigureSVSLPE = 1 forreliabledevicestartup.The most commonly used and recommended settingsareshown inTable2-2. Table2-2.Recommended SVS L Settings SVSMLRRL[2:0]SVSLRVL[1:0]PMMCOREV[1:0] DVCC (V) Sets SVS L_IT+ and SVM LSetsSVS L_IT-Level levels 00 ≥ 1.8 00 000 01 ≥ 2.0 01 001 10 ≥ 2.2 10 010 11 ≥ 2.4 11 011 Forthehigh-sidesupply,therearetwo supplyvoltagesupervisorlevelsavailable.The SVSMHRRL bits definethevoltagelevelofDVCC atwhichtheresetisreleased.The SVSHRVL registerdefinesthe voltagelevelofDVCC belowwhichtheresetisturnedon.These settingsshouldbe selectedaccordingto theminimum voltagesrequiredfordeviceoperationina givenapplication,as wellas systempower supply characteristics.See thedevice-specificdatasheetforthresholdvaluescorrespondingtothesettings shown here.Althoughvarioussettingsareavailable,themost common arebased on themaximum frequencyrequiredwhich,inturn,determinestheminimum DVCC levelsupervised.By default,an SVS H eventalwaysgeneratesa POR (SVSHPE = 1),and itisrecommended toalwaysconfigureSVSHPE = 1 forreliabledevicestartup.The most commonly used and recommended settingsareshown inTable2-3. Table2-3.Recommended SVS H Settings SVSMHRRL[2:0]fSYS Max DVCC SVSHRVL[1:0] Sets SVS H_IT+ and PMMCOREV1:0 (V) SetsSVS H_IT-Level SVM H Levels 8 >1.8 00 000 00 12 >2.0 01 001 01 20 >2.2 10 010 10 25 >2.4 11 011 11 The availablevoltagethresholdsettingsofSVS H and SVM H aredependenton thevoltagelevelsettingof VCORE. Table2-4summarizesallthepossiblesettingsavailable.Allothersettingsnotlistedareinvalid and shouldnotbe used.Figure2-3shows theavailablesettingsfortheSVM H .

84 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

111 (7) 110 (6) 101 (5) 100 (4) 011 (3) 010 (2) 001 (1) 000 (0) 11100100 PMMCOREVx Invalid Invalid Valid ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Operation Table2-4.AvailableSVS H and SVM H SettingsVersus VCORE Settings SVSHRVL[1:0] SVSMHRRL[2:0]PMMCOREV[1:0] SetsSVS H_IT-Level Sets SVS H_IT+ and SVM H Levels 00 00 through11 000 through011 01 00 through11 001 through100 10 00 through11 010 through101 11 00 through11 011 through111 Figure2-3.AvailableSVM H SettingsVersus VCORE Settings The behavioroftheSVS and SVM accordingtothesethresholdsisbestportrayedgraphically.Figure2-4 shows how thesupervisorsand monitorsrespondtovarioussupplyfailureconditions. As Figure2-4shows,thereishysteresisbuiltintothesupervisionthresholds,such thatthethresholdsin forcedepend on whetherthevoltagerailisgoingup ordown. Thereisno hysteresisinthemonitoring thresholds. 85SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

SVM ,SVSL _IT+ L SVSL_IT- SVM ,SVSH H_IT+ SVSH_IT- Time Set SVMHIFG Set SVSHIFG POR Set SVMLIFG Set SVSLIFG Set SVMHVLRIFG Set SVMLVLRIFG ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PMM Operation www.ti.com Figure2-4.High-Sideand Low-Side VoltageFailureand ResultingPMM Actions

2.2.2.2 High-SideSupervisor(SVSH )and High-SideMonitor(SVM H )

The SVS H and SVM H modules areenabledby default.They can be disabledby clearingtheSVSHE and SVMHE bits,respectively.Theirblockdiagramsareshown inFigure2-5.

86 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Operation Figure2-5.High-SideSVS and SVM IfDV CC fallsbelowtheSVS H level,SVSHIFG (SVSH interruptflag)isset.IfDV CC remainsbelowtheSVS H leveland softwareattemptstoclearSVSHIFG, itisimmediatelysetagainby hardware.IftheSVSHPE (SVSH POR enable)bitissetwhen SVSHIFG getsset,a POR isgenerated. IfDV CC fallsbelowtheSVM H level,SVMHIFG (SVM H interruptflag)isset.IfDV CC remainsbelowtheSVM H leveland softwareattemptstoclearSVMHIFG, itisimmediatelysetagainby hardware.IftheSVMHIE (SVM H interruptenable)bitissetwhen SVMHIFG getsset,an interruptisgenerated.Ifa POR isdesired when SVMHIFG isset,theSVM H can be configuredtodo so by settingtheSVMHVLRPE (SVM H voltage levelreachedPOR enable)bitwhileSVMHOVPE bitiscleared. IfDV CC risesabove theSVM H level,theSVMHVLRIFG (SVM H voltagelevelreached)interruptflagisset.If SVMHVLRIE (SVM H voltagelevelreachedinterruptenable)issetwhen thisoccurs,an interruptisalso generated. AlternativelytheSVM H module can be used forovervoltagedetection,butonlywiththehighestcore voltagesetting(PMMCOREV = 11b),.Thisisaccomplishedby settingtheSVMHOVPE (SVM H overvoltagePOR enable)bitinadditiontosettingSVMHVLRPE. Under theseconditions,ifa risingDVCC exceedssafedeviceoperation,a POR isgenerated. The SVS H and SVM H modules have configurableperformancemodes forpower-savingoperation.(See Section2.2.9formore information.)IftheseSVS H and SVM H power modes aremodified,orifa voltage levelismodified,a delayelementmasks theinterruptsand POR sourcesuntiltheSVS H and SVM H circuits have settled.When SVSMHDLYST (delaystatus)readszero,thedelayhas expired.Inaddition,the SVSMHDLYIFG (SVSH and SVM H delayexpired)interruptflagisset.IftheSVSMHDLYIE (SVSH and SVM H delayexpiredinterruptenable)issetwhen thisoccurs,an interruptisalsogenerated. 87SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PMM Operation www.ti.com Incase ofpower-failconditions,settingSVSHMD causestheSVS H interruptflagtobe setinLPM2, LPM3, and LPM4. IfSVSHMD isnotset,theSVS H interruptflagisnotsetinLPM2, LPM3, and LPM4. Inaddition, allSVS H and SVM H eventscan be masked by settingSVSMHEVM. Formost applications,SVSMHEVM shouldbe cleared. AlltheinterruptflagsofSVS H and SVM H remainsetuntilclearedby a BOR orby software.

2.2.2.3 Low-Side Supervisor(SVSL)and Low-Side Monitor(SVM L)

The SVS L and SVM L modules areenabledby default.They can be disabledby clearingSVSLE and SVMLE bits,respectively.Theirblockdiagramsareshown inFigure2-6. Figure2-6.Low-Side SVS and SVM IfVCORE fallsbelowtheSVS L level,SVSLIFG (SVSL interruptflag)isset.IfVCORE remainsbelowtheSVS L leveland softwareattemptstoclearSVSLIFG, itisimmediatelysetagainby hardware.IftheSVSLPE (SVSL POR enable)bitissetwhen SVSLIFG getsset,a POR isgenerated. IfVCORE fallsbelowtheSVM L level,SVMLIFG (SVM L interruptflag)isset.IfVCORE remainsbelowtheSVM L leveland softwareattemptstoclearSVMLIFG, itisimmediatelysetagainby hardware.IftheSVMLIE (SVM L interruptenable)bitissetwhen SVMLIFG getsset,an interruptisgenerated.Ifa POR isdesired when SVMLIFG isset,theSVM L can be configuredtodo so by settingtheSVMLVLRPE (SVM L voltage levelreachedPOR enable)bitwhileSVMLOVPE bitiscleared. IfVCORE risesabove theSVM L level,theSVMLVLRIFG (SVM L voltagelevelreached)interruptflagisset.If SVMLVLRIE (SVM L voltagelevelreachedinterruptenable)issetwhen thisoccurs,an interruptisalso generated.

88 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

SVSH_IT+ SVSL_IT+ TimePOR Reset from SVSH Reset from SVSL ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Operation The SVM L module can alsobe used forovervoltagedetection.Thisisaccomplishedby settingthe SVMLOVPE (SVM L overvoltagePOR enable)bit,inadditiontosettingSVMLVLRPE. Under these conditions,ifVCORE exceedssafedeviceoperation,a POR isgenerated. The SVS L and SVM L modules have configurableperformancemodes forpower-savingoperation.(See Section2.2.9formore information.)IftheseSVS L and SVM L power modes aremodified,orifa voltage levelismodified,a delayelementmasks theinterruptsand POR sourcesuntiltheSVS L and SVM L circuits have settled.When SVSMLDLYST (delaystatus)readszero,thedelayhas expired.Inaddition,the SVSMLDLYIFG (SVSL/SVM L delayexpired)interruptflagisset.IftheSVSMLDLYIE (SVSL /SVM L delay expiredinterruptenable)issetwhen thisoccurs,an interruptisalsogenerated. Incase ofpower-failconditions,settingSVSLMD causestheSVS L interruptflagtobe setinLPM2, LPM3, and LPM4. IfSVSLMD isnotset,theSVS L interruptflagisnotsetinLPM2, LPM3, and LPM4. Inaddition, allSVS L and SVM L eventscan be masked by settingSVSMLEVM. Formost applications,SVSMLEVM shouldbe cleared. AlltheinterruptflagsofSVS L and SVM L remainsetuntilclearedby a BOR orby software.

2.2.3 Supply VoltageSupervisorand Monitor-Power-Up

When thedeviceispoweringup,theSVS H and SVS L functionsareenabledby default.Initially,DV CC is low,and thereforethePMM holdsthedeviceinPOR reset.When boththeSVS H and SVS L levelsaremet, theresetisreleased.Figure2-7shows thisprocess. Figure2-7.PMM ActionatDevice Power-Up Afterthispoint,bothvoltagedomains aresupervisedand monitoredwhiletherespectivemodules are enabled.

2.2.4 IncreasingVCORE toSupport HigherMCLK Frequencies

Witha reset,VCORE and allthePMM thresholds,defaulttotheirlowestpossiblelevels.These default settingsallowa widerangeofMCLK operation,and inmany applicationsno change totheselevelsis required.However,iftheapplicationrequirestheperformanceprovidedby higherMCLK frequencies, softwareshouldensurethatVCORE has been raisedtoa sufficientvoltagelevelbeforechangingMCLK, sincefailingtosupplysufficientvoltagetotheCPU couldproduceunpredictableresults.Fora given device,minimum VCORE levelsrequiredformaximum MCLK frequencieshave been established(See the devicedatasheetforspecificvalues). 89SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PMM Operation www.ti.com AftersettingPMMCOREV toincreaseVCORE ,thereisa timedelayuntilthenew voltagehas been established.Softwaremust notraiseMCLK untilthenecessarycorevoltagehas settled.SVM L can be used toverifythatVCORE has met therequiredminimum value,priortoincreasingMCLK. Figure2-8shows thisprocedure. Figure2-8.Changing VCORE and SVM L and SVS L Levels ItiscriticalthattheVCORE levelbe increasedby onlyone levelata time.The followingsteps1 through4 show theproceduretoincreaseVCORE by one level.Thissequence isrepeatedtochange theVCORE level untilthetargetedlevelisobtained:

Step1:Program theSVM H and SVS H tothenextleveltoensureDV CC ishighenough forthenextVCORE level.Program theSVM L tothenextleveland waitfor(SVSMLDLYIFG) tobe set.
Step2:Program PMMCOREV tothenextVCORE level.
Step3:Waitforthevoltagelevelreached(SVMLVLRIFG) flag.
Step4:Program theSVS L tothenextlevel. As a reference,thefollowingisa C code example forincreasingVCORE .The sample librariesprovide routinesforincreasingand decreasingtheVCORE and shouldbe used whenever possible. ;CCodeexampleforincreasingcorevoltage. ;Note:Changecorevoltageonelevelatatime. voidSetVCoreUp(unsignedintlevel) //OpenPMMregistersforwriteaccess PMMCTL0_H=0xA5; //Makesurenoflagsaresetforiterativesequences while((PMMIFG&SVSMHDLYIFG)==0); while((PMMIFG&SVSMLDLYIFG)==0); //SetSVS/SVMhighsidenewlevel SVSMHCTL=SVSHE+SVSHRVL0*level+SVMHE+SVSMHRRL0*level; //SetSVMlowsidetonewlevel SVSMLCTL=SVSLE+SVMLE+SVSMLRRL0*level; //WaittillSVMissettled while((PMMIFG&SVSMLDLYIFG)==0); //Clearalreadysetflags PMMIFG&=~(SVMLVLRIFG+SVMLIFG); //SetVCoretonewlevel PMMCTL0_L=PMMCOREV0*level; //Waittillnewlevelreached if((PMMIFG&SVMLIFG)) while((PMMIFG&SVMLVLRIFG)==0); //SetSVS/SVMlowsidetonewlevel SVSMLCTL=SVSLE+SVSLRVL0*level+SVMLE+SVSMLRRL0*level; //LockPMMregistersforwriteaccess PMMCTL0_H=0x00;

90 Power Management Module and SupplyVoltageSupervisor SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Operation NOTE: See theMSP430x5xx and MSP430x6xx Core Libraries(SLAA448 ).These librariescontain usefuland ready-to-usefunctionsforeasilyconfiguringand usingthePMM module.

2.2.5 DecreasingVCORE forPower Optimization

The riskposed by increasingMCLK frequencydoes notexistwhen decreasingMCLK fromthecurrent VCORE orhighersettings,because higherVCORE levelscan stillsupportMCLK frequenciesbelowtheones forwhichtheywere intended.However,significantpower efficiencygainscan be made by operatingVCORE atthelowestvaluerequiredfora givenMCLK frequency.ItiscriticalthattheVCORE levelbe decreasedby onlyone levelata time.The followingstepsshow theproceduretodecreaseVCORE by one level.This sequence isrepeatedtochange theVCORE leveluntilthetargetedlevelisobtained: Steps5 through6 show theproceduretodecreaseVCORE :

Step5:Program theSVM L and SVS L tothenew leveland waitfor(SVSMLDLYIFG) tobe set.
Step6:Program PMMCOREV tothenew VCORE level. Itiscriticalwhen loweringtheVCORE settingthatthemaximum MCLK frequencyforthenew VCORE settingis notviolated(seethedevice-specificdatasheet).

2.2.6 TransitionFrom LPM3 and LPM4 Modes toAM

The LDO requirestimetosettlewhen theapplicationtransitionsfromlow-powermodes toactivemodes. If a transitionfromLPM3 orLPM4 occursand thedevicesdoes notstayinactivemode longenough,the LDO does nothave timetosettlesufficiently.CircuitryinsidetheLDO ensuresthattheLDO has its minimum requiredtimetosettletoitsproperoperatingvoltage.The circuitryensuresthateveryeighth transitionfromLPM3 orLPM4 causestheLDO toremainon longenough toproperlysettle.Thisis handledautomaticallyand requiresno settingby theapplication. 2.2.7 LPM3.5 and LPM4.5 LPM3.5 and LMP4.5 areadditionallow-powermodes inwhichtheregulatorofthePMM iscompletely disabled,providingadditionalpower savings.Not alldevicessupportallLPMx.5 modes, so see the device-specificdatasheet.Because thereisno power suppliedtoVCORE duringLPMx.5,theCPU and alldigitalmodules includingRAM areunpowered.Thisdisablestheentiredeviceand,as a result,the contentsoftheregistersand RAM arelost.Any essentialvaluesshouldbe storedtoflashpriortoentering LPMx.5.PMMREGOFF bitisused todisabletheregulator.See theSYS module forcompletedescriptions and properuses ofLMPx.5. Because theregulatorofthePMM isdisabledupon enteringLPMx.5,allI/Oregisterconfigurationsare lost.Therefore,theconfigurationofI/Opinsmust be handleddifferentlytoensurethatallpinsinthe applicationbehave ina controlledmanner upon enteringand exitingLPMx.5.ProperlysettingtheI/Opins iscriticaltoachievingthelowestpossiblepower consumptioninLPMx.5,as wellas preventingany possibleuncontrolledinputoroutputI/Ostateintheapplication.The applicationhas completecontrolof theI/Opinconditionspreventingthepossibilityofunwanted spuriousactivityupon entryand exitfrom LPMx.5.The I/Opinstateisheldand lockedbased on thesettingspriortoLPMx.5 entry.Upon entryinto LPMx.5,theLOCKLPM5 bitinPM5CTL0 ofthePMM module issetautomatically.Note thatonlythepin conditionisretained.Allotherportconfigurationregistersettingsarelost.See theDigitalI/Ochapterfor furtherdetails.

2.2.8 Brownout Reset (BOR),SoftwareBOR, SoftwarePOR

The primaryfunctionofthebrownoutreset(BOR) circuitoccurswhen thedeviceispoweringup.Itis functionalveryearlyinthepower-upramp,generatinga POR thatinitializesthesystem.Italsofunctions when no SVS isenabledand a brownoutconditionoccurs.Itsustainsthisresetuntiltheinputpower is sufficientforthelogic,forproperresetofthesystem. 91SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PMM Operation www.ti.com Inan application,itmay be desiredtocause a BOR viasoftware.SettingPMMSWBOR causesa software-drivenBOR. PMMBORIFG issetaccordingly.Note thata BOR alsoinitiatesa POR and PUC. PMMBORIFG can be clearedby softwareorby readingSYSRSTIV. Similarly,itispossibletocause a POR viasoftwareby settingPMMSWPOR. PMMPORIFG issetaccordingly.A POR alsoinitiatesa PUC. PMMPORIFG can be clearedby softwareorby readingSYSRSTIV. BothPMMSWBOR and PMMSWPOR areselfclearing.See theSYS module forcompletedescriptionsofBOR, POR, and PUC resets.

2.2.9 SVS and SVM Performance Modes and Wakeup Times

The supervisors/monitorscan functioninone oftwo modes: normaland fullperformance.The difference isa tradeoffinresponsetimeversusthepower consumed; full-performancemode has a fasterresponse timebutconsumes considerablymore power thannormalmode. Full-performancemode mightbe consideredinapplicationsinwhichthedecouplingoftheexternalpower supplycannotadequatelyprevent fastspikeson DV CC fromoccurring,orwhen theapplicationhas a particularintolerancetofailure.Insuch cases,full-performancemode providesan additionallayerofprotection. Therearetwo ways tocontroltheperformancemode: manual and automatic.Inmanual mode, the normal/full-performanceselectionisthesame foreveryoperationalmode exceptLPMx.5 (theSVS and SVM arealwaysdisabledinLPMx.5).Inthiscase,thenormalorfull-performanceselectionismade with theSVSHFP, SVMHFP, SVSLFP, orSVMLFP bit,fortheirrespectivemodules. Inautomaticmode, hardwarechanges thenormalorfull-performanceselectiondependingon the operationalmode ineffect. The wakeup timeofthedevicefromlow-powermodes isaffectedby thesettingsoftheSVS L and SVM L performancemodes as listedinTable2-6,Table2-7,Table2-8,and Table2-9.The wakeup timefrom low-powermodes isnotaffectedby thesettingsoftheSVS H and SVM H .Allwake-upsfromLPMx.5 (LPM3.5 orLPM4.5),aredefinedby thedatasheetparametric,tWAKE-UP-LPM5 ,regardlessoftheperformance modes forSVS L orSVM L,because thesearedisabledinLPMx.5. performancemodes forSVS L,SVM L,SVS H ,and SVM H . NOTE: Low-Power Modes Even iftheCPU requestsa specificlow-powermode, thedevicemightnotgo intothatstate because ofmodules requestingclocksthatshouldbe switchedofforhave higher frequenciesorbecause ofmodules requestinga higherdrivecapabilityoftheLDO. The low- power modes mentionedinthetablesassume thatthedeviceisactuallyintherequested state;thatis,no module isrequestinga deviatingclocksettingordrivecapability.

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2.2.9.1 Low-Side SVS and SVM Controland Performance Mode Selection

Table2-5.SVS L and SVM L ControlMode Selection SVSMLACE SVSLMD SVS L ControlMode SVM L ControlMode 0 0 Automatic(seeTable2-6) Manual (seeTable2-8) 0 1 Manual (seeTable2-7) Manual (seeTable2-8) 1 0 Automatic(seeTable2-6) Automatic(seeTable2-9) 1 1 Automatic(seeTable2-6) Automatic(seeTable2-9) Table2-6.SVS L Automatic Performance Control AM, LPM0, LPM1 LPM2, LPM3, LPM4 Wakeup TimeSVSLE SVSLMD SVSLFP SVS L State SVS L State LPM2, LPM3, LPM4 0 x x Off Off tWAKE-UP-FAST 1 0 0 Normal Off tWAKE-UP-SLOW 1 0 1 Fullperformance Off tWAKE-UP-FAST 1 1 0 Normal Off tWAKE-UP-SLOW 1 1 1 Fullperformance Normal tWAKE-UP-FAST Table2-7.SVS L Manual Performance Modes AM, LPM0, LPM1 LPM2, LPM3, LPM4 Wakeup TimeSVSLE SVSLFP SVS L State SVS L State LPM2, LPM3, LPM4 0 x Off Off tWAKE-UP-FAST 1 0 Normal Normal tWAKE-UP-SLOW 1 1 Fullperformance Fullperformance tWAKE-UP-FAST Table2-8.SVM L Automatic Performance Control AM, LPM0, LPM1 LPM2, LPM3, LPM4 Wakeup TimeSVMLE SVMLFP SVM L State SVM L State LPM2, LPM3, LPM4 0 x Off Off tWAKE-UP-FAST 1 0 Normal Off tWAKE-UP-SLOW 1 1 Fullperformance Normal tWAKE-UP-FAST Table2-9.SVM L Manual Performance Modes AM, LPM0, LPM1 LPM2, LPM3, LPM4 Wakeup TimeSVMLE SVMLFP SVM L State SVM L State LPM2, LPM3, LPM4 0 x Off Off tWAKE-UP-FAST 1 0 Normal Normal tWAKE-UP-SLOW 1 1 Fullperformance Fullperformance tWAKE-UP-FAST 93SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.2.9.2 High-SideSVS and SVM Controland Performance Mode Selection

Table2-10.SVS H and SVM H ControlMode Selection SVSMHACE SVSHMD SVS H ControlMode SVM H ControlMode 0 0 Automatic(seeTable2-11) Manual (seeTable2-13) 0 1 Manual (seeTable2-12) Manual (seeTable2-13) 1 0 Automatic(seeTable2-11) Automatic(seeTable2-14) 1 1 Automatic(seeTable2-11) Automatic(seeTable2-14) Table2-11.SVS H Automatic Performance Control AM, LPM0, LPM1 LPM2, LPM3, LPM4SVSHE SVSHMD SVSHFP SVS H State SVS H State 0 x x Off Off 1 0 0 Normal Off 1 0 1 Fullperformance Off 1 1 0 Normal Off 1 1 1 Fullperformance Normal Table2-12.SVS H Manual Performance Modes AM, LPM0, LPM1 LPM2, LPM3, LPM4SVSHE SVSHFP SVS H State SVS H State 0 x Off Off 1 0 Normal Normal 1 1 Fullperformance Fullperformance Table2-13.SVM H Automatic Performance Control AM, LPM0, LPM1 LPM2, LPM3, LPM4SVMHE SVMHFP SVMH State SVM H State 0 x Off Off 1 0 Normal Off 1 1 Fullperformance Normal Table2-14.SVM H Manual Performance Modes AM, LPM0, LPM1 LPM2, LPM3, LPM4SVMHE SVMHFP SVM H State SVM H State 0 x Off Off 1 0 Normal Normal 1 1 Fullperformance Fullperformance

2.2.9.3 Wakeup Times inDebug Mode

The TEST/SBWTCK pinisused forinterfacingtothedevelopmenttoolsviaSpy-Bi-Wireand JTAG. When theTEST/SBWTCK pinishigh,wakeup timesfromLPM2, LPM3, and LPM4 may be differentcompared to when TEST/SBWTCK islow.When theTEST/SBWTCK pinishigh,alldelaysassociatedwiththeSVS L and SVM L settingshave no effectand thedevicewakes withintWAKE-UP-FAST .Pay carefulattentiontothe real-timebehaviorwhen exitingfromLPM2, LPM3, and LPM4 withthedeviceconnectedtoa development tool(forexample,MSP-FET430UIF).

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2.2.10 PMM Interrupts

Interruptflagsgeneratedby thePMM areroutedtothesystemNMI interruptvectorgeneratorregister, SYSSNIV. When thePMM causesa reset,a valueisgeneratedinthesystemresetinterruptvector generatorregister,SYSRSTIV, correspondingtothesourceofthereset.These registersaredefined withintheSYS module.More informationon therelationshipbetween thePMM and SYS modules is availableintheSYS chapter.

2.2.11 PortI/OControl

The PMM providesa means ofensuringthatI/Opinscannotbehave inuncontrolledfashionduringan undervoltageevent.Duringthesetimes,outputsaredisabled,bothnormaldriveand theweak pullup/pulldownfunction.IftheCPU isfunctioningnormally,and thenan undervoltageeventoccurs,any pinconfiguredas an inputhas itsPxIN registervaluelockedinatthepointtheeventoccurs,untilvoltage isrestored.Duringtheundervoltageevent,externalvoltagechanges on thepinarenotregistered internally.Thishelpspreventerraticbehaviorfromoccurring.

2.2.12 Supply VoltageMonitorOutput (SVMOUT, Optional)

The stateofSVMLIFG, SVMLVLRIFG, SVMHIFG, and SVMLVLRIFG can be monitoredon theexternal SVMOUT pin.Each oftheseinterruptflagscan be enabled(SVMLOE, SVMLVLROE, SVMHOE, SVMLVLROE) togeneratean outputsignal.The polarityoftheoutputisselectedby theSVMOUTPOL bit. IfSVMOUTPOL isset,theoutputissetto1 ifan enabledinterruptflagisset. 95SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.3 PMM Registers

The PMM registersarelistedinTable2-15.The base addressofthePMM module can be foundinthe device-specificdatasheet.The addressoffsetofeach PMM registerisgiveninTable2-15.The password, PMMPW, definedinthePMMCTL0 registercontrolsaccesstoallPMM, SVS, and SVM registers.Once thecorrectpasswordiswritten,thewriteaccessisenabled.The writeaccessisdisabledby writinga wrong passwordinbytemode tothePMMCTL0 upperbyte.Word accessestoPMMCTL0 witha wrong passwordtriggersa PUC. A writeaccesstoa registerotherthanPMMCTL0 whilewriteaccessisnot enabledcausesa PUC. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table2-15.PMM Registers Offset Acronym RegisterName Type Access Reset Section 00h PMMCTL0 PMM controlregister0 Read/write Word 9600h Section2.3.1 00h PMMCTL0_L Read/write Byte 00h 01h PMMCTL0_H Read/write Byte 96h 02h PMMCTL1 PMM controlregister1 Read/write Word 0000h Section2.3.2 02h PMMCTL1_L Read/write Byte 00h 03h PMMCTL1_H Read/write Byte 00h 04h SVSMHCTL SVS and SVM highsidecontrolregister Read/write Word 4400h Section2.3.3 04h SVSMHCTL_L Read/write Byte 00h 05h SVSMHCTL_H Read/write Byte 44h 06h SVSMLCTL SVS and SVM lowsidecontrolregister Read/write Word 4400h Section2.3.4 06h SVSMLCTL_L Read/write Byte 00h 07h SVSMLCTL_H Read/write Byte 44h 08h SVSMIO SVSIN and SVMOUT controlregister Read/write Word 0020h Section2.3.5 (optional) 08h SVSMIO_L Read/write Byte 20h 09h SVSMIO_H Read/write Byte 00h 0Ch PMMIFG PMM interruptflagregister Read/write Word 0000h Section2.3.6 0Ch PMMIFG_L Read/write Byte 00h 0Dh PMMIFG_H Read/write Byte 00h 0Eh PMMRIE PMM interruptenableregister Read/write Word 1100h Section2.3.7 0Eh PMMRIE_L Read/write Byte 00h 0Fh PMMRIE_H Read/write Byte 11h 10h PM5CTL0 Power mode 5 controlregister0 Read/write Word 0000h Section2.3.8 10h PM5CTL0_L Read/write Byte 00h 11h PM5CTL0_H Read/write Byte 00h

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2.3.1 PMMCTL0 Register

Power Management Module ControlRegister0 Figure2-9.PMMCTL0 Register 15 14 13 12 11 10 9 8 PMMPW rw-1 rw-0 rw-0 rw-1 rw-0 rw-1 rw-1 rw-0 7 6 5 4 3 2 1 0 PMMHPMRE Reserved PMMREGOFF PMMSWPOR PMMSWBOR PMMCOREV rw-0 r-0 r-0 rw-0 rw-0 rw-0 rw-[0] rw-[0] Table2-16.PMMCTL0 RegisterDescription Bit Field Type Reset Description 15-8 PMMPW RW 96h PMM password.Alwaysreadas 096h.When usingword operations,must be writtenwith0A5h ora PUC isgenerated.When usingbyteoperation,writing 0A5h unlocksallPMM registers.When usingbyteoperation,writinganything differentthan0A5h locksallPMM registers. 7 PMMHPMRE RW 0h Globalhighpower module requestenable.IfthePMMHPMRE bitisset,any module isabletorequestthePMM high-powermode. 6-5 Reserved R 0h Reserved.Alwaysreadsas 0.

4 PMMREGOFF RW 0h Regulatoroff(seetheSYS chapterfordetails)

3 PMMSWPOR RW 0h Softwarepower-onreset.Settingthisbitto1 triggersa POR. Thisbitisself clearing. 2 PMMSWBOR RW 0h Softwarebrownoutreset.Settingthisbitto1 triggersa BOR. Thisbitisself clearing. 1-0 PMMCOREV RW 0h Core voltage(seethedevice-specificdatasheetforsupportedlevelsand correspondingvoltages) 00b = V(CORE) level0 01b = V(CORE) level1 10b = V(CORE) level2 11b = V(CORE) level3 97SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.3.2 PMMCTL1 Register

Power Management Module ControlRegister1 Figure2-10.PMMCTL1 Register 15 14 13 12 11 10 9 8 Reserved r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 Reserved Reserved Reserved Reserved r-0 r-0 rw-[0] rw-[0] r-0 r-0 rw-0 rw-0 Table2-17.PMMCTL1 RegisterDescription Bit Field Type Reset Description 15-6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-4 Reserved RW 0h Reserved.Must alwaysbe writtenwith0. 3-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1-0 Reserved RW 0h Reserved.Must alwaysbe writtenwith0.

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2.3.3 SVSMHCTL Register

SupplyVoltageSupervisorand MonitorHigh-SideControlRegister Figure2-11.SVSMHCTL Register 15 14 13 12 11 10 9 8 SVMHFP SVMHE Reserved SVMHOVPE SVSHFP SVSHE SVSHRVL rw-[0] rw-1 r-0 rw-[0] rw-[0] rw-1 rw-[0] rw-[0] 7 6 5 4 3 2 1 0 SVSMHACE SVSMHEVM Reserved SVSHMD SVSMHDLYST SVSMHRRL rw-[0] rw-0 r-0 rw-0 r-0 rw-[0] rw-[0] rw-[0] Table2-18.SVSMHCTL RegisterDescription Bit Field Type Reset Description 15 SVMHFP RW 0h SVM high-sidefull-performancemode. Ifthisbitisset,theSVMH operatesin full-performancemode. 0b = Normal mode. See thedevice-specificdatasheetforresponsetimes. 1b = Full-performancemode. See thedevice-specificdatasheetforresponse times. 14 SVMHE RW 1h SVM high-sideenable.Ifthisbitisset,theSVMH isenabled. 13 Reserved R 0h Reserved.Alwaysreadsas 0. 12 SVMHOVPE RW 0h SVM high-sideovervoltageenable.Ifthisbitisset,theSVMH overvoltage detectionisenabled.IfSVMHVLRPE isalsoset,a POR occurson an overvoltagecondition. 11 SVSHFP RW 0h SVS high-sidefull-performancemode. Ifthisbitisset,theSVSH operatesinfull- performancemode. 0b = Normal mode. See thedevice-specificdatasheetforresponsetimes. 1b = Full-performancemode. See thedevice-specificdatasheetforresponse times. 10 SVSHE RW 1h SVS high-sideenable.Ifthisbitisset,theSVSH isenabled. 9-8 SVSHRVL RW 0h SVS high-sideresetvoltagelevel.IfDVCC fallsshortoftheSVSH voltagelevel selectedby SVSHRVL, a resetistriggered(ifSVSHPE = 1).The voltagelevels aredefinedinthedevice-specificdatasheet. 7 SVSMHACE RW 0h SVS and SVM high-sideautomaticcontrolenable.Ifthisbitisset,thelow-power mode oftheSVSH and SVMH circuitsisunderhardwarecontrol. 6 SVSMHEVM RW 0h SVS and SVM high-sideeventmask. Ifthisbitisset,theSVSH and SVMH eventsaremasked. 0b = No eventsaremasked. 1b = Alleventsaremasked. 5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 SVSHMD RW 0h SVS high-sidemode. Ifthisbitisset,theSVSH interruptflagissetinLPM2, LPM3, and LPM4 incase ofpower-failconditions.Ifthisbitisnotset,theSVSH interruptisnotsetinLPM2, LPM3, and LPM4. 3 SVSMHDLYST RW 0h SVS and SVM high-sidedelaystatus.Ifthisbitisset,theSVSH and SVMH eventsaremasked forsome delaytime.The delaytimedepends on thepower mode oftheSVSH and SVMH. IfSVMHFP = 1 and SVSHFP = 1 (thatis,full- performancemode),thedelayisshorter.See thedevice-specificdatasheetfor details.The bitisclearedby hardwareifthedelayhas expired. 2-0 SVSMHRRL RW 0h SVS and SVM high-sideresetreleasevoltagelevel.These bitsdefinethereset releasevoltageleveloftheSVSH. Itisalsoused fortheSVMH todefinethe voltagereachedlevel.The voltagelevelsaredefinedinthedevice-specificdata sheet. 99SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.3.4 SVSMLCTL Register

SupplyVoltageSupervisorand MonitorLow-SideControlRegister Figure2-12.SVSMLCTL Register 15 14 13 12 11 10 9 8 SVMLFP SVMLE Reserved SVMLOVPE SVSLFP SVSLE SVSLRVL rw-[0] rw-1 r-0 rw-[0] rw-[0] rw-1 rw-[0] rw-[0] 7 6 5 4 3 2 1 0 SVSMLACE SVSMLEVM Reserved SVSLMD SVSMLDLYST SVSMLRRL rw-[0] rw-0 r-0 rw-0 r-0 rw-[0] rw-[0] rw-[0] Table2-19.SVSMLCTL RegisterDescription Bit Field Type Reset Description 15 SVMLFP RW 0h SVM low-sidefull-performancemode. Ifthisbitisset,theSVML operatesinfull- performancemode. 0b = Normal mode. See thedevice-specificdatasheetforresponsetimes. 1b = Full-performancemode. See thedevice-specificdatasheetforresponse times. 14 SVMLE RW 1h SVM low-sideenable.Ifthisbitisset,theSVML isenabled. 13 Reserved R 0h Reserved.Alwaysreadsas 0. 12 SVMLOVPE RW 0h SVM low-sideovervoltageenable.Ifthisbitisset,theSVML overvoltage detectionisenabled. 11 SVSLFP RW 0h SVS low-sidefull-performancemode. Ifthisbitisset,theSVSL operatesinfull- performancemode. 0b = Normal mode. See thedevice-specificdatasheetforresponsetimes. 1b = Full-performancemode. See thedevice-specificdatasheetforresponse times. 10 SVSLE RW 1h SVS low-sideenable.Ifthisbitisset,theSVSL isenabled. 9-8 SVSLRVL RW 0h SVS low-sideresetvoltagelevel.IfV(CORE) fallsshortoftheSVSL voltage levelselectedby SVSLRVL, a resetistriggered(ifSVSLPE = 1). 7 SVSMLACE RW 0h SVS and SVM low-sideautomaticcontrolenable.Ifthisbitisset,thelow-power mode oftheSVSL and SVML circuitsisunderhardwarecontrol. 6 SVSMLEVM RW 0h SVS and SVM low-sideeventmask. Ifthisbitisset,theSVSL and SVML events aremasked. 0b = No eventsaremasked. 1b = Alleventsaremasked. 5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 SVSLMD RW 0h SVS low-sidemode. Ifthisbitisset,theSVSL interruptflagissetinLPM2, LPM3 and LPM4 incase ofpower-failconditions.Ifthisbitisnotset,theSVSL interruptisnotsetinLPM2, LPM3, and LPM4. 3 SVSMLDLYST RW 0h SVS and SVM low-sidedelaystatus.Ifthisbitisset,theSVSL and SVML events aremasked fora delaytime.The delaytimedepends on thepower mode ofthe SVSL and SVML. IfSVMLFP = 1 and SVSLFP = 1 (thatis,full-performance mode),thedelayisshorter.The bitisclearedby hardwareifthedelayhas expired. 2-0 SVSMLRRL RW 0h SVS and SVM low-sideresetreleasevoltagelevel.These bitsdefinethereset releasevoltageleveloftheSVSL. Itisalsoused fortheSVML todefinethe voltagereachedlevel.

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2.3.5 SVSMIO Register

SVSIN and SVMOUT ControlRegister Figure2-13.SVSMIO Register 15 14 13 12 11 10 9 8 Reserved SVMHVLROE SVMHOE Reserved r-0 r-0 r-0 rw-[0] rw-[0] r-0 r-0 r-0 7 6 5 4 3 2 1 0 Reserved SVMOUTPOL SVMLVLROE SVMLOE Reserved r-0 r-0 rw-[1] rw-[0] rw-[0] r-0 r-0 r-0 Table2-20.SVSMIO RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12 SVMHVLROE RW 0h SVM high-sidevoltagelevelreachedoutputenable.Ifthisbitisset,the SVMHVLRIFG bitisoutputtothedeviceSVMOUT pin.The device-specificport logichas tobe configuredaccordingly. 11 SVMHOE RW 0h SVM high-sideoutputenable.Ifthisbitisset,theSVMHIFG bitisoutputtothe deviceSVMOUT pin.The device-specificportlogichas tobe configured accordingly. 10-6 Reserved R 0h Reserved.Alwaysreadsas 0. 5 SVMOUTPOL RW 1h SVMOUT pinpolarity.Ifthisbitisset,SVMOUT isactivehigh.An errorcondition issignaledby a 1 atSVMOUT. IfSVMOUTPOL iscleared,theerrorconditionis signaledby a 0 attheSVMOUT pin. 4 SVMLVLROE RW 0h SVM low-sidevoltagelevelreachedoutputenable.Ifthisbitisset,the SVMLVLRIFG bitisoutputtothedeviceSVMOUT pin.The device-specificport logichas tobe configuredaccordingly. 3 SVMLOE RW 0h SVM low-sideoutputenable.Ifthisbitisset,theSVMLIFG bitisoutputtothe deviceSVMOUT pin.The device-specificportlogichas tobe configured accordingly. 2-0 Reserved R 0h Reserved.Alwaysreadsas 0. 101SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.3.6 PMMIFG Register

Power Management Module InterruptFlagRegister Figure2-14.PMMIFG Register 15 14 13 12 11 10 9 8 PMMLPM5IFG Reserved SVSLIFG (1) SVSHIFG (1) Reserved PMMPORIFG PMMRSTIFG PMMBORIFG rw-[0] r-0 rw-[0] rw-[0] r-0 rw-[0] rw-[0] rw-[0] 7 6 5 4 3 2 1 0 Reserved SVMHVLRIFG ( SVMHIFG SVSMHDLYIF Reserved SVMLVLRIFG (1 SVMLIFG SVSMLDLYIFG 1) G ) r-0 rw-[0] rw-[0] rw-0 r-0 rw-[0] rw-[0] rw-0 (1) Afterpower up,theresetvaluedepends on thepower sequence. (1) Afterpower up,theresetvaluedepends on thepower sequence. Table2-21.PMMIFG RegisterDescription Bit Field Type Reset Description 15 PMMLPM5IFG RW 0h LPMx.5 flag.Thisbitissetifthesystemwas inLPMx.5 before.The bitiscleared by softwareorby readingtheresetvectorword.A power failureon theDVCC domain clearsthebit. 0b = No interruptpending 1b = Interruptpending 14 Reserved R 0h Reserved.Alwaysreadsas 0. 13 SVSLIFG RW 0h SVS low-sideinterruptflag.The bitisclearedby softwareorby readingthereset vectorword. 0b = No interruptpending 1b = Interruptpending 12 SVSHIFG RW 0h SVS high-sideinterruptflag.The bitisclearedby softwareorby readingthe resetvectorword. 0b = No interruptpending 1b = Interruptpending 11 Reserved R 0h Reserved.Alwaysreadsas 0. 10 PMMPORIFG RW 0h PMM softwarepower-onresetinterruptflag.Thisinterruptflagissetifa software POR istriggered.The bitisclearedby softwareorby readingtheresetvector word,SYSRSTIV. 0b = No interruptpending 1b = Interruptpending 9 PMMRSTIFG RW 0h PMM resetpininterruptflag.ThisinterruptflagissetiftheRST/NMI pinisthe resetsource.The bitisclearedby softwareorby readingtheresetvectorword. 0b = No interruptpending 1b = Interruptpending 8 PMMBORIFG RW 0h PMM softwarebrownoutresetinterruptflag.Thisinterruptflagissetifa software BOR (PMMSWBOR) istriggered.The bitisclearedby softwareorby readingthe resetvectorword,SYSRSTIV. 0b = No interruptpending 1b = Interruptpending 7 Reserved R 0h Reserved.Alwaysreadsas 0. 6 SVMHVLRIFG RW 0h SVM high-sidevoltagelevelreachedinterruptflag.The bitisclearedby software orby readingtheresetvector(SVSHPE = 1)word orby readingtheinterrupt vector(SVSHPE = 0)word. 0b = No interruptpending 1b = Interruptpending 5 SVMHIFG RW 0h SVM high-sideinterruptflag.The bitisclearedby software. 0b = No interruptpending 1b = Interruptpending

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PMM Registers Table2-21.PMMIFG RegisterDescription(continued) Bit Field Type Reset Description 4 SVSMHDLYIFG RW 0h SVS and SVM high-sidedelayexpiredinterruptflag.Thisinterruptflagissetif thedelayelementexpired.The bitisclearedby softwareorby readingthe interruptvectorword. 0b = No interruptpending 1b = Interruptpending 3 Reserved R 0h Reserved.Alwaysreadsas 0. 2 SVMLVLRIFG RW 0h SVM low-sidevoltagelevelreachedinterruptflag.The bitisclearedby software orby readingtheresetvector(SVSLPE = 1)word orby readingtheinterrupt vector(SVSLPE = 0)word. 0b = No interruptpending 1b = Interruptpending 1 SVMLIFG RW 0h SVM low-sideinterruptflag.The bitisclearedby software. 0b = No interruptpending 1b = Interruptpending 0 SVSMLDLYIFG RW 0h SVS and SVM low-sidedelayexpiredinterruptflag.Thisinterruptflagissetifthe delayelementexpired.The bitisclearedby softwareorby readingtheinterrupt vectorword. 0b = No interruptpending 1b = Interruptpending 103SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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2.3.7 PMMRIE Register

Power Management Module Resetand InterruptEnableRegister Figure2-15.PMMRIE Register 15 14 13 12 11 10 9 8 Reserved SVMHVLRPE SVSHPE Reserved SVMLVLRPE SVSLPE r-0 r-0 rw-[0] rw-[1] r-0 r-0 rw-[0] rw-[1] 7 6 5 4 3 2 1 0 Reserved SVMHVLRIE SVMHIE SVSMHDLYIE Reserved SVMLVLRIE SVMLIE SVSMLDLYIE r-0 rw-0 rw-0 rw-0 r-0 rw-0 rw-0 rw-0 Table2-22.PMMRIE RegisterDescription Bit Field Type Reset Description 15-14 Reserved R 0h Reserved.Alwaysreadsas 0. 13 SVMHVLRPE RW 0h SVM high-sidevoltagelevelreachedpower-onresetenable.Ifthisbitisset, exceedingtheSVMH voltageleveltriggersa POR. 12 SVSHPE RW 1h SVS high-sidepower-onresetenable.Ifthisbitisset,fallingbelowtheSVSH voltageleveltriggersa POR. 11-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9 SVMLVLRPE RW 0h SVM low-sidevoltagelevelreachedpower-onresetenable.Ifthisbitisset, exceedingtheSVML voltageleveltriggersa POR. 8 SVSLPE RW 1h SVS low-sidepower-onresetenable.Ifthisbitisset,fallingbelowtheSVSL voltageleveltriggersa POR. 7 Reserved R 0h Reserved.Alwaysreadsas 0.

6 SVMHVLRIE RW 0h SVM high-sideresetvoltagelevelinterruptenable

5 SVMHIE RW 0h SVM high-sideinterruptenable.Thisbitisclearedby softwareoriftheinterrupt vectorword isread.

4 SVSMHDLYIE RW 0h SVS and SVM high-sidedelayexpiredinterruptenable

3 Reserved R 0h Reserved.Alwaysreadsas 0.

2 SVMLVLRIE RW 0h SVM low-sideresetvoltagelevelinterruptenable

1 SVMLIE RW 0h SVM low-sideinterruptenable.Thisbitisclearedby softwareoriftheinterrupt vectorword isread.

0 SVSMLDLYIE RW 0h SVS and SVM low-sidedelayexpiredinterruptenable

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2.3.8 PM5CTL0 Register

Power Mode 5 ControlRegister0 Figure2-16.PM5CTL0 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved LOCKLPM5 r0 r0 r0 r0 r0 r0 r0 rw-[0] Table2-23.PM5CTL0 RegisterDescription Bit Field Type Reset Description 15-1 Reserved R 0h Reserved.Alwaysreadsas 0. 0 LOCKLPM5 RW 0h Lock I/Opinconfigurationupon entrytoorexitfromLPMx.5.When power is appliedtothedevice,thisbit,once set,can onlybe clearedby theuserorvia anotherpower cycle. Note:Thisbitwas formerlynamed LOCKIO, and some applicationreportsand code examplesmay continuetouse thisterminology. 0b = I/Opinconfigurationisnotlockedand defaultstoitsresetcondition. 1b = I/Opinconfigurationremainslocked.PinstateisheldduringLPMx.5 entry and exit. 105SLAU259E –May 2009–RevisedJanuary2013 Power Management Module and SupplyVoltageSupervisor SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter3 SLAU259E –May 2009–RevisedJanuary2013 UnifiedClock System (UCS) The UnifiedClockSystem (UCS) module providesthevariousclocksfora device.Thischapterdescribes theoperationoftheUCS module,whichisimplementedinalldevices.

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3.1 UnifiedClock System (UCS) Introduction

The UCS module supportslowsystemcostand ultralowpower consumption.Usingthreeinternalclock signals,theusercan selectthebestbalanceofperformanceand lowpower consumption.The UCS module can be configuredtooperatewithoutany externalcomponents,withone ortwo externalcrystals, orwithresonators,underfullsoftwarecontrol. The UCS module includesup tofiveclocksources:

XT1CLK: Low-frequencyoscillatorthatcan be used withlow-frequency32768-Hz watchcrystals
VLOCLK: Internalverylowpower,lowfrequencyoscillatorwith10 kHz typicalfrequency
REFOCLK: Internal,trimmed,low-frequencyoscillatorwith32768 Hz typicalfrequency,withtheability tobe used as a clockreferenceintotheFLL
DCOCLK: Internaldigitally-controlledoscillator(DCO) thatcan be stabilizedby theFLL
XT2CLK: RF XT2 oscillatorrequiredforradiofunctionality ThreeclocksignalsareavailablefromtheUCS module:
ACLK: Auxiliaryclock.The ACLK issoftwareselectableas XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and when available,XT2CLK. DCOCLKDIV istheDCOCLK frequencydividedby 1,2,4, 8,16,or32 withintheFLL block.ACLK can be dividedby 1,2,4,8,16,or32.ACLK/n isACLK dividedby 1,2,4,8,16,or32 and isavailableexternallyata pin.ACLK issoftwareselectableby individualperipheralmodules.
MCLK: Masterclock.MCLK issoftwareselectableas XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and XT2CLK. DCOCLKDIV istheDCOCLK frequencydividedby 1,2,4,8,16,or32 withintheFLL block.MCLK can be dividedby 1,2,4,8,16,or32.MCLK isused by theCPU and system.
SMCLK: Subsystem masterclock.SMCLK issoftwareselectableas XT1CLK, REFOCLK, VLOCLK, DCOCLK, DCOCLKDIV, and XT2CLK. DCOCLKDIV istheDCOCLK frequencydividedby 1,2,4,8, 16,or32 withintheFLL block.SMCLK can be dividedby 1,2,4,8,16,or32.SMCLK issoftware selectableby individualperipheralmodules. The blockdiagramoftheUCS module isshown inFigure3-1. 107SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

RF_XIN RF_XOUT RF□Oscillator XT2□Oscillator Fault Detection XIN XOUT XCAP XT XT2 LF 0 V 0 V VLOCLK XT 1CLK 2 2 XT 1DRIVE REFOCLK Oscillator XT2CLK XT 1BYP ASS REFO VLO 10-bit Frequency Integrator DCO Modulator DC Generator DCORSELSCG 1 off SCG0 off PUC Reset FLLD −Divider /(N+1) Prescaler DCO, MOD FLLREFDIV FLLN10 DISMOD FLL Divider /1/2/4/8/12/16 MODOSC MODOSC_REQEN MODOSC_REQ MODCLK Unconditonal□MODOSC requests . EN XT 1 Fault Detection 000 001 010 01 1 100 101 110 111 SELREF FLLREFCLK DCOCLK DCOCLKDIV ACLK□Enable□Logic OSCOFF ACLK_REQEN ACLK_REQ 000 001 010 01 1 100 101 110 111 SELA ACLK/n ACLK Divider DIVP A Divider DIV A EN MCLK□Enable□Logic CPUOFF MCLK_REQEN MCLK_REQ 000 001 010 01 1 100 101 110 111 SELM MCLK Divider DIVM EN SMCLK□Enable□Logic SMCLKOFF SMCLK_REQEN SMCLK _REQ 000 001 010 01 1 100 101 110 111 SELS SMCLK to□Radio Divider DIVS EN /1/2/4/8/16/32 /1/2/4/8/16/32 /1/2/4/8/16/32 /1/2/4/8/16/32 /1/2/4/8/16/32 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UnifiedClockSystem (UCS) Introduction www.ti.com Figure3-1.UCS Block Diagram

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3.2 UCS Operation

Aftera PUC, theUCS module defaultconfigurationis:

XT1 isselectedas theoscillatorsourceforXT1CLK. XT1CLK isselectedforACLK.
DCOCLKDIV isselectedforMCLK.
DCOCLKDIV isselectedforSMCLK.
FLL operationisenabledand XT1CLK isselectedas theFLL referenceclock,FLLREFCLK.
XIN and XOUT pinsaresettogeneral-purposeI/Osand XT1 remainsdisableduntiltheI/Oportsare configuredforXT1 operation.
RF oscillatorsourcingXT2CLK disabled. As previouslystated,FLL operationwithXT1 isselectedby default,butXT1 isdisabled.The crystalpins (XIN,XOUT) aresharedwithgeneral-purposeI/Os.To enableXT1, thePSEL bitsassociatedwiththe crystalpinsmust be set.When a 32,768Hz crystalisused forXT1CLK, thefaultcontrollogicimmediately causesACLK tobe sourcedby theREFOCLK, because XT1 isnotstableimmediately(see Section3.2.12).Once crystalstartupisobtainedand settled,theFLL stabilizesMCLK and SMCLK to 1.048576MHz and fDCO = 2.097152MHz. Statusregistercontrolbits(SCG0, SCG1, OSCOFF, and CPUOFF) configuretheMSP430 operating modes and enableordisableportionsoftheUCS module (seetheSYS chapter).RegistersUCSCTL0 throughUCSCTL8, configuretheUCS module. The UCS module can be configuredorreconfiguredby softwareatany timeduringprogramexecution. NOTE: FordevicesusingRTC_B, RTC_C, orRTC_D (RTC modules supportingLPM3.5) settingbit RTCHOLD = 0 inregisterRTCCTL1 alsoenablesXT1, independentfromUCS configuration.

3.2.1 UCS Module FeaturesforLow-Power Applications

Conflictingrequirementstypicallyexistinbattery-poweredapplications:

Low clockfrequencyforenergyconservationand timekeeping
Highclockfrequencyforfastresponsetimesand fastburstprocessingcapabilities
Clockstabilityoveroperatingtemperatureand supplyvoltage
Low-costapplicationswithless-constrainedclockaccuracyrequirements The UCS module addressestheseconflictingrequirementsby allowingtheusertoselectfromthethree availableclocksignals:ACLK, MCLK, and SMCLK. Allthreeavailableclocksignalscan be sourcedviaany oftheavailableclocksources(XT1CLK, VLOCLK, REFOCLK, DCOCLK, DCOCLKDIV, orXT2CLK), givingcompleteflexibilityinthesystemclock configuration.A flexibleclockdistributionand dividersystemisprovidedtofinetunetheindividualclock requirements.

3.2.2 InternalVery-Low-Power Low-Frequency Oscillator(VLO)

The internalVLO providesa typicalfrequencyof10 kHz (seedevice-specificdatasheetforparameters) withoutrequiringa crystal.The VLO providesfora low-costultralow-powerclocksourceforapplications thatdo notrequirean accuratetimebase. The VLO isenabledwhen itisused tosourceACLK, MCLK, orSMCLK (SELA = {1}orSELM = {1}or SELS = {1}). 109SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.2.3 InternalTrimmed Low-Frequency ReferenceOscillator(REFO)

The internaltrimmedlow-frequencyREFO can be used forcost-sensitiveapplicationswhere a crystalis notrequiredordesired.REFO isinternallytrimmedto32.768kHz typicaland providesfora stable referencefrequencythatcan be used as FLLREFCLK. REFO, combined withtheFLL,providesfora flexiblerangeofsystemclocksettingswithouttheneed fora crystal.REFO consumes no power when not beingused. REFO isenabledunderany ofthefollowingconditions:

REFO isa sourceforACLK (SELA = {2})and inactivemode (AM) throughLPM3 (OSCOFF = 0)
REFO isa sourceforMCLK (SELM = {2})and inactivemode (AM) (CPUOFF = 0)
REFO isa sourceforSMCLK (SELS = {2})and inactivemode (AM) throughLPM1 (SMCLKOFF = 0)
REFO isa sourceforFLLREFCLK (SELREF = {2})and theDCO isa sourceforACLK (SELA = {3,4}) and inactivemode (AM) throughLPM3 (OSCOFF = 0)
REFO isa sourceforFLLREFCLK (SELREF = {2})and theDCO isa sourceforMCLK (SELM = {3,4}) and inactivemode (AM) (CPUOFF = 0)
REFO isa sourceforFLLREFCLK (SELREF = {2})and theDCO isa sourceforSMCLK (SELS = {3,4})and inactivemode (AM) throughLPM1 (SMCLKOFF = 0)

3.2.4 XT1 Oscillator

The XT1 oscillatorsupportsultralow-currentconsumptionusinga 32,768Hz watchcrystal.A watchcrystal connectstoXIN and XOUT withoutany otherexternalcomponents.The software-selectableXCAP bits configuretheinternallyprovidedloadcapacitancefortheXT1 crystalinLF mode. Thiscapacitancecan be selectedas 2 pF,6 pF,9 pF,or12 pF (typical).Additionalexternalcapacitorscan be added ifnecessary. The drivesettingsofXT1 can be increasedwiththeXT1DRIVE bits.Atpower up,theXT1 startswiththe highestdrivesettingsforfast,reliablestartup.Ifneeded,usersoftwarecan reducethedrivestrengthto furtherreducepower.. XT1 may be used withan externalclocksignalon theXIN pinineitherLF orHF mode by setting XT1BYPASS. When used withan externalsignal,theexternalfrequencymust meet thedatasheet parametersforthechosen mode. XT1 ispowered down when used inbypassmode. Some devicessupportXT1 bypassoperationwithexternalclockinputsthatresideon a differentexternal supplydomain,calledDV IO.Pleaserefertothedevicespecificdatasheet.On thesedevices,DV IO has a voltagerangeof1.8V± 10 %. When usingtheXT1 bypassoperationwithexternalclockinputsthatreside on DV IO,itisrequiredthatXT1BYPASSLV = 1.Forexample,when XT1BYPASSLV = 1,itisassumed the externalclocksignalswingsfrom0V toDV IO.WithXT1BYPASS = 0,itisassumed theexternalclock signalswingsfrom0V toDV CC .The usage ofXT1BYPASSLV allowsforinterfacingtoexternalclock sourcesthatresideon eithertheDV CC orDV IO supplydomains.When used withan externalsignal,the externalfrequencymust meet thedatasheetparametersforthechosen mode. XT1 ispowered down when used inbypassmode. The XT1 pinsaresharedwithgeneral-purposeI/Oports.Atpower up,thedefaultoperationisXT1. However,XT1 remainsdisableduntiltheportssharedwithXT1 areconfiguredforXT1 operation.The configurationofthesharedI/Oisdeterminedby thePSEL bitassociatedwithXIN and theXT1BYPASS bit.SettingthePSEL bitcausestheXIN and XOUT portstobe configuredforXT1 operation.If XT1BYPASS isalsoset,XT1 isconfiguredforbypassmode ofoperation,and theoscillatorassociated withXT1 ispowered down. Inbypassmode ofoperation,XIN can acceptan externalclockinputsignal and XOUT isconfiguredas a general-purposeI/O.The PSEL bitassociatedwithXOUT isa don'tcare. IfthePSEL bitassociatedwithXIN iscleared,bothXIN and XOUT portsareconfiguredas general- purposeI/Os,and XT1 isdisabled. XT1 isenabledunderany ofthefollowingconditions:

XT1 isa sourceforACLK (SELA = {0})and inactivemode (AM) throughLPM3 (OSCOFF = 0)
XT1 isa sourceforMCLK (SELM = {0})and inactivemode (AM) (CPUOFF = 0)
XT1 isa sourceforSMCLK (SELS = {0})and inactivemode (AM) throughLPM1 (SMCLKOFF = 0)
XT1 isa sourceforFLLREFCLK (SELREF = {0})and theDCO isa sourceforACLK (SELA = {3,4}) and inactivemode (AM) throughLPM3 (OSCOFF = 0)

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XT1 isa sourceforFLLREFCLK (SELREF = {0})and theDCO isa sourceforMCLK (SELM = {3,4}) and inactivemode (AM) (CPUOFF = 0)
XT1 isa sourceforFLLREFCLK (SELREF = {0})and theDCO isa sourceforSMCLK (SELS = {3,4}) and inactivemode (AM) throughLPM1 (SMCLKOFF = 0)
XT1OFF = 0.XT1 enabledinactivemode (AM) throughLPM4. FordevicesthatsupportLPMx.5,XT1 alsoremainsenabled.

3.2.5 RF XT2 Oscillator

The RF XT2 oscillator'smain purposeistoprovidea referenceclocktotheon-chipradiomodule.Butit alsosourcesXT2CLK and XT2CLK can be used tosourceACLK, MCLK, SMCLK orFLLREFCLK. The RF oscillatorisenabledifitisused by theradio;thatis,iftheradiomodule isnotinitssleepstate. WithXT2OFF = 0 theRF oscillatorispermanentlyenabledeven when theradioisinsleepmode. With XT2OFF = 1 theRF oscillatorisdisabledwhen theradioenterssleepmode. When theRF oscillatoris disabledthecorrespondingfaultflagXT2OFFG issetand iftheRF oscillatorisselectedtosourceACLK, MCLK, SMCLK orFLLREFCLK thecorrespondingfail-safemechanism takesover.

3.2.6 Digitally-ControlledOscillator(DCO)

The DCO isan integrateddigitallycontrolledoscillator.The DCO frequencycan be adjustedby software usingtheDCORSEL, DCO, and MOD bits.The DCO frequencycan be optionallystabilizedby theFLL to a multiplefrequencyofFLLREFCLK/n. The FLL can acceptdifferentreferencesourcesselectableviathe SELREF bits.ReferencesourcesincludeXT1CLK, REFOCLK, orXT2CLK. The valueofn isdefinedby theFLLREFDIV bits(n= 1,2,4,8,12,or16).The defaultisn = 1.Theremay be scenariosinwhichFLL operationisnotrequiredordesired;inthesecases,no FLLREFCLK isnecessary.Thiscan be accomplishedby settingSELREF = {7}. The FLLD bitsconfiguretheFLL prescalerdividervalueD to1,2,4,8,16,or32.By default,D = 2,and MCLK and SMCLK aresourcedfromDCOCLKDIV, providinga clockfrequencyDCOCLK/2. The divider(N + 1)and thedividervalueD definetheDCOCLK and DCOCLKDIV frequencies,where N > 0.WritingN = 0 causesthedividertobe setto2. fDCOCLK = D × (N + 1)× (fFLLREFCLK ÷ n) fDCOCLKDIV = (N + 1)× (fFLLREFCLK ÷ n) AdjustingDCO Frequency By default,FLL operationisenabled.FLL operationcan be disabledby settingSCG0 orSCG1. Once disabled,theDCO continuestooperateatthecurrentsettingsdefinedinUCSCTL0 and UCSCTL1. The DCO frequencycan be adjustedmanuallyifdesired.Otherwise,theDCO frequencyisstabilizedby the FLL operation. Aftera PUC, DCORSEL = {2}and DCO = {0}.MCLK and SMCLK aresourcedfromDCOCLKDIV. Because theCPU executescode fromMCLK, whichissourcedfromthefast-startingDCO, code executionbeginsfromPUC inlessthan5 µs. The frequencyofDCOCLK issetby thefollowingfunctions:

The threeDCORSEL bitsselectone ofeightnominalfrequencyrangesfortheDCO. These rangesare definedforan individualdeviceinthedevice-specificdatasheet.
The fiveDCO bitsdividetheDCO rangeselectedby theDCORSEL bitsinto32 frequencysteps, separatedby approximately8%.
The fiveMOD bitsswitchbetween thefrequencyselectedby theDCO bitsand thenext-higher frequencysetby {DCO + 1}.When DCO = {31},theMOD bitshave no effect,because theDCO is alreadyatthehighestsettingfortheselectedDCORSEL range.

3.2.7 Frequency Locked Loop (FLL)

The FLL continuouslycountsup ordown a frequencyintegrator.The outputofthefrequencyintegrator thatdrivestheDCO can be readinUCSCTL0, UCSCTL1 (bitsMOD and DCO). The countisadjusted+1 withthefrequencyfFLLREFCLK /n(n= 1,2,4,8,12,or16)or–1 withthefrequencyfDCOCLK /[D× (N+1)]. 111SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Lower DCO Tap Frequency fDCO Upper DCO Tap Frequency fDCO+1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UCS Operation www.ti.com NOTE: Reading MOD and DCO bits The integratorisupdatedviatheDCOCLK, whichmay differinfrequencyofoperationof MCLK. Itispossiblethatimmediatereadsofa previouslywrittenvaluearenotvisibletothe usersincetheupdatetotheintegratorhas notoccurred.Thisisnormal.Once theintegrator isupdatedatthenextsuccessiveDCOCLK, thecorrectvaluecan be read. Inaddition,sincetheMCLK can be asynchronoustotheintegratorupdates,readingthe valuesmay be cause a corruptedvaluetobe readunderthiscondition.Inthiscase,a majorityvotemethod shouldbe performed. Fiveoftheintegratorbits(UCSCTL0 bits12 to8)settheDCO frequencytap.Thirty-twotapsare implementedfortheDCO, and each isapproximately8% higherthantheprevious.The modulatormixes two adjacentDCO frequenciestoproducefractionaltaps. Fora givenDCO biasrangesetting,timemust be allowedfortheDCO tosettleon thepropertapfor normaloperation.(n× 32)fFLLREFCLK cyclesarerequiredbetween tapsrequiringa worstcase of (n× 32 × 32)fFLLREFCLK cyclesfortheDCO tosettle.The valuen isdefinedby theFLLREFDIV bits(n= 1, 2,4,8,12,or16).

3.2.8 DCO Modulator

The modulatormixestwo DCO frequencies,fDCO and fDCO +1 toproducean intermediateeffective frequencybetween fDCO and fDCO +1 and spreadtheclockenergy,reducingelectromagneticinterference (EMI).The modulatormixesfDCO and fDCO +1 for32 DCOCLK clockcyclesand isconfiguredwiththeMOD bits.When MOD = {0},themodulatorisoff. The modulatormixingformulais: t= (32– MOD) × tDCO + MOD × tDCO+1 Figure3-2shows themodulatoroperation. When FLL operationisenabled,themodulatorsettingsand DCO arecontrolledby theFLL hardware.If FLL operationisnotdesired,themodulatorsettingsand DCO controlcan be configuredwithsoftware. Figure3-2.ModulatorPatterns

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3.2.9 DisablingFLL Hardware and Modulator

The FLL isdisabledwhen thestatusregisterbitsSCG0 orSCG1 areset.When theFLL isdisabled,the DCO runsatthepreviouslyselectedtapand DCOCLK isnotautomaticallystabilized. The DCO modulatorisdisabledwhen DISMOD isset.When theDCO modulatorisdisabled,theDCOCLK isadjustedtotheDCO tapselectedby theDCO bits. NOTE: DCO operationwithoutFLL When theFLL operationisdisabled,theDCO continuestooperateatthecurrentsettings. Because itisnotstabilizedby theFLL,temperatureand voltagevariationsinfluencethe frequencyofoperation.See thedevice-specificdatasheetforvoltageand temperature coefficientstoensurereliableoperation.

3.2.10 FLL OperationFrom Low-Power Modes

An interruptservicerequestclearsSCG1, CPUOFF, and OSCOFF ifset,butdoes notclearSCG0. This means thatforFLL operationfromwithinan interruptserviceroutineenteredfromLPM1, 3,or4,theFLL remainsdisabledand theDCO operatesattheprevioussettingas definedinUCSCTL0 and UCSCTL1. SCG0 can be clearedby usersoftwareifFLL operationisrequired.

3.2.11 OperationFrom Low-Power Modes, Requested by PeripheralModules

A peripheralmodule requestsitsclocksourcesautomaticallyfromtheUCS module ifrequiredforits properoperation,regardlessofthecurrentmode ofoperation,as shown inFigure3-3. A peripheralmodule assertsone ofthreepossibleclockrequestsignalsbased on itscontrolbits: ACLK_REQ, MCLK_REQ, orSMCLK_REQ. These requestsignalsarebased on theconfigurationand clockselectionoftherespectivemodule.Forexample,ifa timerselectsACLK as itsclocksourceand the timerisenabled,thetimergeneratesan ACLK_REQ signaltotheUCS system.The UCS, inturn,enables ACLK regardlessoftheLPM settings. Any clockrequestfroma peripheralmodule causesitsrespectiveclockoffsignaltobe overridden,but does notchange thesettingofclockoffcontrolbit.Forexample,a peripheralmodule may requireACLK thatiscurrentlydisabledby theOSCOFF bit(OSCOFF = 1).The module can requestACLK by generating an ACLK_REQ. ThiscausestheOSCOFF bittohave no effect,therebyallowingACLK tobe availableto therequestingperipheralmodule.The OSCOFF bitremainsatitscurrentsetting(OSCOFF = 1). Iftherequestedsourceisnotactive,thesoftwareNMI handlermust takecareoftherequiredactions.For thepreviousexample,ifACLK was sourcedby XT1 and XT1 was notenabled,an oscillatorfaultcondition occursand thesoftwaremust handletheevent.The watchdog,due toitssecurityrequirement,actively selectstheVLOCLK sourceiftheoriginallyselectedclocksourceisnotavailable. Due totheclockrequestfeature,caremust be takenintheapplicationwhen enteringlow-powermodes to save power.Althoughthedeviceenterstheselectedlow-powermode, a clockrequestmay exhibitmore currentconsumptionthanthespecifiedvaluesinthedatasheet. 113SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ACLK_REQ MCLK_REQ SMCLK_REQ Watch□Dog□Timer□Module UCS Module□n−1 Module□n WDTACLKON WDTSMCLKON ACLK_REQ MCLK_REQ SMCLK_REQ ACLK_REQ MCLK_REQ SMCLK_REQ ACLK MCLK SMCLK Direct□clock□request in□Watchdog□mode Module□n−2 ACLK_REQ MCLK_REQ SMCLK_REQ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UCS Operation www.ti.com Figure3-3.Module Request Clock System By default,theclockrequestlogicisenabled.The clockrequestlogiccan be disabledby clearing ACLKREQEN, MCLKREQEN, orSMCLKREQEN, foreach respectivesystemclock.When ACLKREQEN orMCLKREQEN bitsareset,oractive,theclockisavailabletothesystemand preventsentryintoa low- power mode untilallmodules requestingtheclockaredisabled.When ACLKREQEN orMCLKREQEN bits arecleared,ordisabled,theclockisalwayshaltedas definedby thelow-powermodes. The SMCLKREQEN logicbehaves similarly,butisalsoinfluencedby theSMCLKOFF bitintheUCSCTL6 register.Table3-1shows therelationshipbetween thesystemclocksand thelow-powermodes in conjunctionwiththeclockrequestlogic. Table3-1.Clock Request System and Power Modes ACLK MCLK SMCLK SMCLKOFF = 0 SMCLKOFF = 1 ACLKREQEN ACLKREQEN MCLKREQEN MCLKREQENMode SMCLKREQEN SMCLKREQEN SMCLKREQEN SMCLKREQEN= 0 = 1 = 0 = 1 = 0 = 1 = 0 = 1 AM Active Active Active Active Active Active Disabled Active LPM0 Active Active Disabled Active Active Active Disabled Active LPM1 Active Active Disabled Active Active Active Disabled Active LPM2 Active Active Disabled Active Disabled Active Disabled Active LPM3 Active Active Disabled Active Disabled Active Disabled Active LPM4 Disabled Active Disabled Active Disabled Active Disabled Active LPM3.5 Disabled(2) Disabled(3) Disabled Disabled Disabled Disabled Disabled Disabled(1) LPM4.5 Disabled(2) Disabled(3) Disabled Disabled Disabled Disabled Disabled Disabled(1) when XT1OFF = 0 orXT2OFF = 0,theLPMx.5 requestisignoredand thedevicedoes notenterLPMx.5. (2) Watchdog mode requestingACLK preventsLPMx.5 entry. (3) Any module requestingACLK preventsLPMx.5 entry.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com UCS Operation WhileACLK isrequestedby atleastone module (ACLKREQEN = 1),LPMx.5 cannotbe entered.After clearingtheACLK requestenablesignal(ACLKREQEN = 0),thedeviceisabletoenterLPMx.5 (except forwatchdogmode –see followingnote).See Enteringand ExitingLow-Power Modes LPMx.5 fordetails on how toenterLPMx.5. NOTE: Watchdog Mode Using ACLK When a deviceisconfiguredtouse watchdogmode (WDTTMSEL = 0)and issourcedby ACLK (WDTSSEL = 01b),thedevicecannotenterLPMx.5 regardlessofwhetherornotthe ACLK requestenablesignal(ACLKREQEN) iscleared.

3.2.12 UCS Module Fail-SafeOperation

The UCS module incorporatesan oscillator-faultfail-safefeature.Thisfeaturedetectsan oscillatorfaultfor XT1, DCO, and XT2 as shown inFigure3-4.The availablefaultconditionsare:

Low-frequencyoscillatorfault(XT1LFOFFG) forXT1 inLF mode
High-frequencyoscillatorfault(XT1HFOFFG) forXT1 inHF mode
High-frequencyoscillatorfault(XT2OFFG) forXT2
DCO faultflag(DCOFFG) fortheDCO The crystaloscillatorfaultbitsXT1LFOFFG, XT1HFOFFG, and XT2OFFG aresetifthecorresponding crystaloscillatoristurnedon and notoperatingproperly.Once set,thefaultbitsremainsetuntilresetin software,regardlessifthefaultconditionno longerexists.Iftheuserclearsthefaultbitsand thefault conditionstillexists,thefaultbitsareautomaticallyset,otherwisetheyremaincleared. When usingXT1 operationinLF mode as thereferencesourceintotheFLL (SELREF = {0}),a crystal faultautomaticallycausestheFLL referencesource,FLLREFCLK, tobe sourcedby theREFO. XT1LFOFFG isset.When usingXT1 operationinHF mode as thereferencesourceintotheFLL,a crystal faultcausesno FLLREFCLK signaltobe generatedand theFLL continuestocountdown tozeroinan attempttolockFLLREFCLK and DCOCLK/[D × (N + 1)].The DCO tapmoves tothelowestposition(DCO arecleared)and theDCOFFG isset.DCOFFG isalsosetiftheN-multipliervalueissettoohighforthe selectedDCO frequencyrange,resultingintheDCO tapmoving tothehighestposition(UCSCTL0.12 to UCSCTL0.8 areset).The DCOFFG remainssetuntilclearedby theuser.IftheuserclearstheDCOFFG and thefaultconditionremains,itisautomaticallyset,otherwiseitremainscleared.XT1HFOFFG isset. When usingXT2 as thereferencesourceintotheFLL,a crystalfaultcausesno FLLREFCLK signaltobe generated,and theFLL continuestocountdown tozeroinan attempttolockFLLREFCLK and DCOCLK/[D × (N + 1)].The DCO tapmoves tothelowestposition(DCO arecleared)and theDCOFFG is set.DCOFFG isalsosetiftheN-multipliervalueissettoohighfortheselectedDCO frequencyrange, resultingintheDCO tapmoving tothehighestposition(UCSCTL0.12 toUCSCTL0.8 areset).The DCOFFG remainssetuntilclearedby theuser.IftheuserclearstheDCOFFG and thefaultcondition remains,itisautomaticallyset,otherwiseitremainscleared.XT2OFFG isset. The OFIFG oscillator-faultinterruptflagissetand latchedatPOR orwhen any oscillatorfault (XT1LFOFFG, XT1HFOFFG, XT2OFFG, orDCOFFG) isdetected.When OFIFG issetand OFIE isset, theOFIFG requestsan NMI. When theinterruptisgranted,theOFIE isnotresetautomaticallyas itisin previousMSP430 families.Itisno longerrequiredtoresettheOFIE.NMI entryand exitcircuitryremoves thisrequirement.The OFIFG flagmust be clearedby software.The sourceofthefaultcan be identifiedby checkingtheindividualfaultbits. Ifa faultisdetectedfortheoscillatorsourcingMCLK, MCLK isautomaticallyswitchedtotheDCO forits clocksource(DCOCLKDIV) forallclocksourcesexceptXT1 LF mode. IfMCLK issourcedfromXT1 inLF mode, an oscillatorfaultcausesMCLK tobe automaticallyswitchedtotheREFO foritsclocksource (REFOCLK). Thisdoes notchange theSELM bitsettings.Thisconditionmust be handledby user software. 115SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UCS Operation www.ti.com Ifa faultisdetectedfortheoscillatorsourcingSMCLK, SMCLK isautomaticallyswitchedtotheDCO for itsclocksource(DCOCLKDIV) forallclocksourcesexceptXT1 LF mode. IfSMCLK issourcedfromXT1 inLF mode, an oscillatorfaultcausesSMCLK tobe automaticallyswitchedtotheREFO foritsclock source(REFOCLK). Thisdoes notchange theSELS bitsettings.Thisconditionmust be handledby user software. Ifa faultisdetectedfortheoscillatorsourcingACLK, ACLK isautomaticallyswitchedtotheDCO forits clocksource(DCOCLKDIV) forallclocksourcesexceptXT1 LF mode. IfACLK issourcedfromXT1 inLF mode, an oscillatorfaultcausesACLK tobe automaticallyswitchedtotheREFO foritsclocksource (REFOCLK). Thisdoes notchange theSELA bitsettings.Thisconditionmust be handledby user software. NOTE: DCO activeduringoscillatorfault DCOCLKDIV isactiveeven atthelowestDCO tap.The clocksignalisavailablefortheCPU toexecutecode and servicean NMI duringan oscillatorfault.

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S R Q S R Q S Q XT 1 LFOFFG Q S RPUC NMI _ IRQA OFIFG OFIE NMIRS XT 1 _ LFOF S R Q S R Q XT 1 HFOFFG S R Q S R Q XT 2 OFFG S R Q S R Q DCOFFG XT 1 _ HFOF XT 2 _ OF DCO _ OF POR DCO _ Fault XT 1 _ LF _ OscFault XT 1 _ HF _ OscFault XT 2 _ OscFault OscFault_Clr OscFault_Set Q R R R R R ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com UCS Operation Figure3-4.OscillatorFaultLogic 117SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UCS Operation www.ti.com NOTE: Faultconditions DCO_Fault: DCOFFG issetifDCO bitsinUCSCTL0 registervalueequals{0}or{31}. XT1_LF_OscFault: ThissignalissetaftertheXT1 (LFmode) oscillatorhas stopped operationand clearedafteroperationresumes.The faultconditioncausesXT1LFOFFG to be setand remainset.IftheuserclearsXT1LFOFFG and thefaultconditionstillexists, XT1LFOFFG remainsset. XT1_HF_OscFault: ThissignalissetaftertheXT1 (HF mode) oscillatorhas stopped operationand clearedafteroperationresumes.The faultconditioncausesXT1HFOFFG to be setand remainset.IftheuserclearsXT1HFOFFG and thefaultconditionstillexists, XT1HFOFFG remainsset. XT2_OscFault:ThissignalissetaftertheXT2 oscillatorhas stoppedoperationand cleared afteroperationresumes.The faultconditioncausesXT2OFFG tobe setand remainset.If theuserclearsXT2OFFG and thefaultconditionstillexists,XT2OFFG remainsset. NOTE: Faultlogic Pleasenotethatas longas a faultconditionstillexists,theOFIFG remainsset.The applicationmust takespecialcarewhen clearingtheOFIFG signal.Ifno faultcondition remainswhen theOFIFG signaliscleared,theclocklogicswitchesback totheoriginaluser settingspriortothefaultcondition. NOTE: Faultlogiccounters Each crystaloscillatorcircuithas hardwarecounters.These countersarereseteach timea faultconditionoccurson itsrespectiveoscillator,causingthefaultflagtobe set.The countersbegintocountafterthefaultconditionisremoved.Once themaximum countis reached,thefaultflagisremoved. InXT1 LF mode, themaximum countis8192.InXT1 HF mode (andXT2 when available), themaximum countis1024.Inbypassmodes, regardlessofLF orHF settings,the maximum countis8192.

3.2.13 SynchronizationofClock Signals

When switchingMCLK orSMCLK fromone clocksourcetotheanother,theswitchissynchronizedto avoidcriticalraceconditionsas shown inFigure3-5:

The currentclockcyclecontinuesuntilthenextrisingedge.
The clockremainshighuntilthenextrisingedge ofthenew clock.
The new clocksourceisselectedand continueswitha fullhighperiod. Figure3-5.Switch MCLK from DCOCLK toXT1CLK

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Module Oscillator(MODOSC)

3.3 Module Oscillator(MODOSC)

The UCS module alsosupportsan internaloscillator,MODOSC, thatisused by theflashmemory controllermodule and,optionally,by othermodules inthesystem.The MODOSC sourcesMODCLK.

3.3.1 MODOSC Operation

To conservepower,MODOSC ispowered down when notneeded and enabledonlywhen required.When theMODOSC sourceisrequired,therespectivemodule requestsit.MODOSC isenabledbased on unconditionaland conditionalrequests.SettingMODOSCREQEN enablesconditionalrequests. Unconditionalrequestsarealwaysenabled.ItisnotnecessarytosetMODOSCREQEN formodules that use unconditionalrequests;forexample,flashcontrollerorADC12_A. The flashmemory controlleronlyrequiresMODCLK when performingwriteoreraseoperations.When performingsuch operations,theflashmemory controllerissuesan unconditionalrequestfortheMODOSC source.Upon doingso,theMODOSC sourceisenabled,ifnotalreadyenabledfromothermodules' previousrequests. The ADC12_A may optionallyuse MODOSC as a clocksourceforitsconversionclock.The userchooses theADC12OSC as theconversionclocksource.Duringa conversion,theADC12_A module issuesan unconditionalrequestfortheADC12OSC clocksource.Upon doingso,theMODOSC sourceisenabled,if notalreadyenabledfromothermodules'previousrequests. 119SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4 UCS Module Registers

The UCS module registersarelistedinTable3-2.The base addresscan be foundinthedevice-specific datasheet.The addressoffsetislistedinTable3-2. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table3-2.UCS Registers Offset Acronym RegisterName Type Access Reset Section 00h UCSCTL0 UnifiedClockSystem Control0 Read/write Word 0000h Section3.4.1 00h UCSCTL0_L Read/write Byte 00h 01h UCSCTL0_H Read/write Byte 00h 02h UCSCTL1 UnifiedClockSystem Control1 Read/write Word 0020h Section3.4.2 02h UCSCTL1_L Read/write Byte 20h 03h UCSCTL1_H Read/write Byte 00h 04h UCSCTL2 UnifiedClockSystem Control2 Read/write Word 101Fh Section3.4.3 04h UCSCTL2_L Read/write Byte 1Fh 05h UCSCTL2_H Read/write Byte 10h 06h UCSCTL3 UnifiedClockSystem Control3 Read/write Word 0000h Section3.4.4 06h UCSCTL3_L Read/write Byte 00h 07h UCSCTL3_H Read/write Byte 00h 08h UCSCTL4 UnifiedClockSystem Control4 Read/write Word 0044h Section3.4.5 08h UCSCTL4_L Read/write Byte 44h 09h UCSCTL4_H Read/write Byte 00h 0Ah UCSCTL5 UnifiedClockSystem Control5 Read/write Word 0000h Section3.4.6 0Ah UCSCTL5_L Read/write Byte 00h 0Bh UCSCTL5_H Read/write Byte 00h 0Ch UCSCTL6 UnifiedClockSystem Control6 Read/write Word C1CDh Section3.4.7 0Ch UCSCTL6_L Read/write Byte CDh 0Dh UCSCTL6_H Read/write Byte C1h 0Eh UCSCTL7 UnifiedClockSystem Control7 Read/write Word 0703h Section3.4.8 0Eh UCSCTL7_L Read/write Byte 03h 0Fh UCSCTL7_H Read/write Byte 07h 10h UCSCTL8 UnifiedClockSystem Control8 Read/write Word 0707h Section3.4.9 10h UCSCTL8_L Read/write Byte 07h 11h UCSCTL8_H Read/write Byte 07h 12h UCSCTL9 UnifiedClockSystem Control9(1) Read/write Word 0000h Section3.4.10 12h UCSCTL9_L Read/write Byte 00h 13h UCSCTL9_H Read/write Byte 00h (1) Thisregisterisnotavailableon alldevices.See thedevice-specificdatasheet.

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3.4.1 UCSCTL0 Register

UnifiedClockSystem Control0 Register Figure3-6.UCSCTL0 Register 15 14 13 12 11 10 9 8 Reserved DCO r0 r0 r0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 MOD Reserved rw-0 rw-0 rw-0 rw-0 rw-0 r0 r0 r0 Table3-3.UCSCTL0 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12-8 DCO RW 0h DCO tapselection.These bitsselecttheDCO tapand aremodifiedautomatically duringFLL operation. 7-3 MOD RW 0h Modulationbitcounter.These bitsselectthemodulationpattern.AllMOD bits aremodifiedautomaticallyduringFLL operation.The DCO registervalueis incrementedwhen themodulationbitcounterrollsoverfrom31 to0.Ifthe modulationbitcounterdecrementsfrom0 tothemaximum count,theDCO registervalueisalsodecremented. 2-0 Reserved R 0h Reserved.Alwaysreadsas 0. 121SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4.2 UCSCTL1 Register

UnifiedClockSystem Control1 Register Figure3-7.UCSCTL1 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved DCORSEL Reserved Reserved DISMOD r0 rw-0 rw-1 rw-0 r0 r0 rw-0 rw-0 Table3-4.UCSCTL1 RegisterDescription Bit Field Type Reset Description 15-7 Reserved R 0h Reserved.Alwaysreadsas 0. 6-4 DCORSEL RW 2h DCO frequencyrangeselect.These bitsselecttheDCO frequencyrangeof operationdefinedinthedevice-specificdatasheet. 3-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 Reserved RW 0h Reserved.Alwaysreadsas 0. 0 DISMOD RW 0h Modulation.Thisbitenablesordisablesthemodulation. 0b = Modulationenabled 1b = Modulationdisabled

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3.4.3 UCSCTL2 Register

UnifiedClockSystem Control2 Register Figure3-8.UCSCTL2 Register 15 14 13 12 11 10 9 8 Reserved FLLD Reserved FLLN r0 rw-0 rw-0 rw-1 r0 r0 rw-0 rw-0 7 6 5 4 3 2 1 0 FLLN rw-0 rw-0 rw-0 rw-1 rw-1 rw-1 rw-1 rw-1 Table3-5.UCSCTL2 RegisterDescription Bit Field Type Reset Description 15 Reserved R 0h Reserved.Alwaysreadsas 0. 14-12 FLLD RW 1h FLL loopdivider.These bitsdividef(DCOCLK) intheFLL feedbackloop.This resultsinan additionalmultiplierforthemultiplierbits.See alsomultiplierbits. 000b = f(DCOCLK)/1 001b = f(DCOCLK)/2 010b = f(DCOCLK)/4 011b = f(DCOCLK)/8 100b = f(DCOCLK)/16 101b = f(DCOCLK)/32 110b = Reservedforfutureuse.Defaultstof(DCOCLK)/32. 111b = Reservedforfutureuse.Defaultstof(DCOCLK)/32. 11-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9-0 FLLN RW 1Fh Multiplierbits.These bitssetthemultipliervalueN oftheDCO. N must be greaterthan0.WritingzerotoFLLN causesN tobe setto1. 123SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4.4 UCSCTL3 Register

UnifiedClockSystem Control3 Register Figure3-9.UCSCTL3 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved SELREF Reserved FLLREFDIV r0 rw-0 rw-0 rw-0 r0 rw-0 rw-0 rw-0 Table3-6.UCSCTL3 RegisterDescription Bit Field Type Reset Description 15-7 Reserved R 0h Reserved.Alwaysreadsas 0. 6-4 SELREF RW 0h FLL referenceselect.These bitsselecttheFLL referenceclocksource. 000b = XT1CLK 001b = Reservedforfutureuse.DefaultstoXT1CLK. 010b = REFOCLK 011b = Reservedforfutureuse.DefaultstoREFOCLK. 100b = Reservedforfutureuse.DefaultstoREFOCLK. 101b = XT2CLK when available,otherwiseREFOCLK. 110b = Reservedforfutureuse.XT2CLK when available,otherwiseREFOCLK. 111b = 3 Reserved R 0h Reserved.Alwaysreadsas 0. 2-0 FLLREFDIV RW 0h FLL referencedivider.These bitsdefinethedividefactorforf(FLLREFCLK).The dividedfrequencyisused as theFLL referencefrequency. 000b = f(FLLREFCLK)/1 001b = f(FLLREFCLK)/2 010b = f(FLLREFCLK)/4 011b = f(FLLREFCLK)/8 100b = f(FLLREFCLK)/12 101b = f(FLLREFCLK)/16 110b = Reservedforfutureuse.Defaultstof(FLLREFCLK)/16. 111b = Reservedforfutureuse.Defaultstof(FLLREFCLK)/16.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com UCS Module Registers

3.4.5 UCSCTL4 Register

UnifiedClockSystem Control4 Register Figure3-10.UCSCTL4 Register 15 14 13 12 11 10 9 8 Reserved SELA r0 r0 r0 r0 r0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 Reserved SELS Reserved SELM r0 rw-1 rw-0 rw-0 r0 rw-1 rw-0 rw-0 Table3-7.UCSCTL4 RegisterDescription Bit Field Type Reset Description 15-11 Reserved R 0h Reserved.Alwaysreadsas 0. 10-8 SELA RW 0h SelectstheACLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available,otherwiseDCOCLKDIV 110b = Reservedforfutureuse.DefaultstoXT2CLK. 111b = Reservedforfutureuse.DefaultstoXT2CLK. 7 Reserved R 0h Reserved.Alwaysreadsas 0. 6-4 SELS RW 4h SelectstheSMCLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available,otherwiseDCOCLKDIV 110b = Reservedforfutureuse.DefaultstoXT2CLK. 111b = Reservedforfutureuse.DefaultstoXT2CLK. 3 Reserved R 0h Reserved.Alwaysreadsas 0. 2-0 SELM RW 4h SelectstheMCLK source 000b = XT1CLK 001b = VLOCLK 010b = REFOCLK 011b = DCOCLK 100b = DCOCLKDIV 101b = XT2CLK when available,otherwiseDCOCLKDIV 110b = Reservedforfutureuse.DefaultstoXT2CLK. 111b = Reservedforfutureuse.DefaultstoXT2CLK. 125SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4.6 UCSCTL5 Register

UnifiedClockSystem Control5 Register Figure3-11.UCSCTL5 Register 15 14 13 12 11 10 9 8 Reserved DIVPA Reserved DIVA r0 rw-0 rw-0 rw-0 r0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 Reserved DIVS Reserved DIVM r0 rw-0 rw-0 rw-0 r0 rw-0 rw-0 rw-0 Table3-8.UCSCTL5 RegisterDescription Bit Field Type Reset Description 15 Reserved R 0h Reserved.Alwaysreadsas 0. 14-12 DIVPA RW 0h ACLK sourcedivideravailableatexternalpin.DividesthefrequencyofACLK and presentsittoan externalpin. 000b = f(ACLK)/1 001b = f(ACLK)/2 010b = f(ACLK)/4 011b = f(ACLK)/8 100b = f(ACLK)/16 101b = f(ACLK)/32 110b = Reservedforfutureuse.Defaultstof(ACLK)/32. 111b = Reservedforfutureuse.Defaultstof(ACLK)/32. 11 Reserved R 0h Reserved.Alwaysreadsas 0. 10-8 DIVA RW 0h ACLK sourcedivider.DividesthefrequencyoftheACLK clocksource. 000b = f(ACLK)/1 001b = f(ACLK)/2 010b = f(ACLK)/4 011b = f(ACLK)/8 100b = f(ACLK)/16 101b = f(ACLK)/32 110b = Reservedforfutureuse.Defaultstof(ACLK)/32. 111b = Reservedforfutureuse.Defaultstof(ACLK)/32. 7 Reserved R 0h Reserved.Alwaysreadsas 0. 6-4 DIVS RW 0h SMCLK sourcedivider 000b = f(SMCLK)/1 001b = f(SMCLK)/2 010b = f(SMCLK)/4 011b = f(SMCLK)/8 100b = f(SMCLK)/16 101b = f(SMCLK)/32 110b = Reservedforfutureuse.Defaultstof(SMCLK)/32. 111b = Reservedforfutureuse.Defaultstof(SMCLK)/32. 3 Reserved R 0h Reserved.Alwaysreadsas 0.

126 UnifiedClockSystem (UCS) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com UCS Module Registers Table3-8.UCSCTL5 RegisterDescription(continued) Bit Field Type Reset Description 2-0 DIVM RW 0h MCLK sourcedivider 000b = f(MCLK)/1 001b = f(MCLK)/2 010b = f(MCLK)/4 011b = f(MCLK)/8 100b = f(MCLK)/16 101b = f(MCLK)/32 110b = Reservedforfutureuse.Defaultstof(MCLK)/32. 111b = Reservedforfutureuse.Defaultstof(MCLK)/32. 127SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4.7 UCSCTL6 Register

UnifiedClockSystem Control6 Register Figure3-12.UCSCTL6 Register 15 14 13 12 11 10 9 8 Reserved XT2OFF r0 r0 r0 r0 r0 r0 r0 rw-1 7 6 5 4 3 2 1 0 XT1DRIVE (1) XTS XT1BYPASS XCAP (1) SMCLKOFF XT1OFF rw-1 rw-1 rw-0 rw-0 rw-1 rw-1 rw-0 rw-1 (1) The configurationofthesebitsisretainedduringLPM3.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPM3.5 beforeclearingLOCKLPM5 isrequired. Table3-9.UCSCTL6 RegisterDescription Bit Field Type Reset Description 15-9 Reserved R 0h Reserved.Alwaysreadsas 0.

8 XT2OFF RW 1h TurnsofftheXT2 oscillator

0b = XT2 ison 1b = XT2 isoffifitisnotused by theradio;thatis,iftheradioisnotinsleep state 7-6 XT1DRIVE RW 3h The XT1 oscillatorcurrentcan be adjustedtoitsdriveneeds.Initially,itstarts withthehighestsupplycurrentforreliableand quickstartup.Ifneeded,user softwarecan reducethedrivestrength. 00b = LowestcurrentconsumptionforXT1 LF mode. XT1 oscillatoroperating rangeinHF mode is4 MHz to8 MHz. 01b = IncreaseddrivestrengthforXT1 LF mode. XT1 oscillatoroperatingrange inHF mode is8 MHz to16 MHz. 10b = IncreaseddrivecapabilityforXT1 LF mode. XT1 oscillatoroperatingrange inHF mode is16 MHz to24 MHz. 11b = Maximum drivecapabilityand maximum currentconsumptionforXT1 LF mode. XT1 oscillatoroperatingrangeinHF mode is24 MHz to32 MHz.

5 XTS RW 0h XT1 mode select

0b = Low-frequencymode. XCAP bitsdefinethecapacitanceattheXIN and XOUT pins. 1b = High-frequencymode. XCAP bitsarenotused.

4 XT1BYPASS RW 0h XT1 bypassselect

0b = XT1 sourcedinternally 1b = XT1 sourcedexternallyfrompin 3-2 XCAP RW 3h Oscillatorcapacitorselection.These bitsselectthecapacitorsappliedtotheLF crystalorresonatorintheLF mode (XTS = 0).The effectivecapacitance(seen by thecrystal)isC(eff)≈ (C(XIN)+ 2 pF)/2.Itisassumed that C(XIN)= C(XOUT) and thata parasiticcapacitanceof2 pF isadded by the package and theprintedcircuitboard.Fordetailsaboutthetypicalinternaland theeffectivecapacitors,see thedevice-specificdatasheet. 1 SMCLKOFF RW 0h SMCLK off.ThisbitturnsofftheSMCLK. 0b = SMCLK on 1b = SMCLK off 0 XT1OFF RW 1h XT1 off.ThisbitturnsofftheXT1. 0b = XT1 ison ifXT1 isselectedviatheportselectionand XT1 isnotinbypass mode ofoperation. 1b = XT1 isoffifitisnotused as a sourceforACLK, MCLK, orSMCLK orisnot used as a referencesourcerequiredforFLL operation.

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3.4.8 UCSCTL7 Register

UnifiedClockSystem Control7 Register Figure3-13.UCSCTL7 Register 15 14 13 12 11 10 9 8 Reserved Reserved Reserved Reserved r0 r0 rw-0 rw-(0) rw-(1) rw-(1) r-1 r-1 7 6 5 4 3 2 1 0 Reserved Reserved XT2OFFG (1) XT1HFOFFG (1) XT1LFOFFG DCOFFG r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(1) rw-(1) (1) Not availableon alldevices.When notavailable,thisbitisreserved. Table3-10.UCSCTL7 RegisterDescription Bit Field Type Reset Description 15-14 Reserved R 0h Reserved.Alwaysreadsas 0. 13-12 Reserved RW 0h Reserved.Must alwaysbe writtenwith0. 11-10 Reserved RW 3h Reserved.The statesofthesebitsshouldbe ignored. 9-8 Reserved R 3h Reserved.The statesofthesebitsshouldbe ignored. 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 Reserved RW 0h Reserved.The stateofthisbitshouldbe ignored. 3 XT2OFFG (1) RW 0h XT2 oscillatorfaultflag.Ifthisbitisset,theOFIFG flagisalsoset.XT2OFFG is setifa XT2 faultconditionexists.XT2OFFG can be clearedviasoftware.Ifthe XT2 faultconditionstillremains,XT2OFFG isset. 0b = No faultconditionoccurredafterthelastreset. 1b = XT2 fault.An XT2 faultoccurredafterthelastreset. 2 XT1HFOFFG (1) RW 0h XT1 oscillatorfaultflag(HF mode).Ifthisbitisset,theOFIFG flagisalsoset. XT1HFOFFG issetifa XT1 faultconditionexists.XT1HFOFFG can be cleared viasoftware.IftheXT1 faultconditionstillremains,XT1HFOFFG isset. 0b = No faultconditionoccurredafterthelastreset. 1b = XT1 fault.An XT1 faultoccurredafterthelastreset. 1 XT1LFOFFG RW 1h XT1 oscillatorfaultflag(LFmode).Ifthisbitisset,theOFIFG flagisalsoset. XT1LFOFFG issetifa XT1 faultconditionexists.XT1LFOFFG can be cleared viasoftware.IftheXT1 faultconditionstillremains,XT1LFOFFG isset. 0b = No faultconditionoccurredafterthelastreset. 1b = XT1 fault(LFmode).A XT1 faultoccurredafterthelastreset. 0 DCOFFG RW 1h DCO faultflag.Ifthisbitisset,theOFIFG flagisalsoset.The DCOFFG bitis setifDCO = {0}orDCO = {31}.DCOFFG can be clearedviasoftware.Ifthe DCO faultconditionstillremains,DCOFFG isset. 0b = No faultconditionoccurredafterthelastreset. 1b = DCO fault.A DCO faultoccurredafterthelastreset. (1) Not availableon alldevices.When notavailable,thisbitisreserved. 129SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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3.4.9 UCSCTL8 Register

UnifiedClockSystem Control8 Register Figure3-14.UCSCTL8 Register 15 14 13 12 11 10 9 8 Reserved Reserved r0 r0 r0 r0 r0 rw-(1) rw-(1) rw-(1) 7 6 5 4 3 2 1 0 Reserved Reserved MODOSCREQ SMCLKREQEN MCLKREQEN ACLKREQEN EN r0 r0 r0 rw-(0) rw-(0) rw-(1) rw-(1) rw-(1) Table3-11.UCSCTL8 RegisterDescription Bit Field Type Reset Description 15-11 Reserved R 0h Reserved.Alwaysreadsas 0. 10-8 Reserved R 0h Reserved.Must alwaysbe writtenas 1. 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 Reserved R 0h Reserved.Must alwaysbe writtenas 0. 3 MODOSCREQEN RW 0h MODOSC clockrequestenable.Settingthisenablesconditionalmodule requests forMODOSC. 0b = MODOSC conditionalrequestsaredisabled. 1b = MODOSC conditionalrequestsareenabled. 2 SMCLKREQEN RW 1h SMCLK clockrequestenable.Settingthisenablesconditionalmodule requests forSMCLK 0b = SMCLK conditionalrequestsaredisabled. 1b = SMCLK conditionalrequestsareenabled. 1 MCLKREQEN RW 1h MCLK clockrequestenable.Settingthisenablesconditionalmodule requestsfor MCLK 0b = MCLK conditionalrequestsaredisabled. 1b = MCLK conditionalrequestsareenabled. 0 ACLKREQEN RW 1h ACLK clockrequestenable.Settingthisenablesconditionalmodule requestsfor ACLK 0b = ACLK conditionalrequestsaredisabled. 1b = ACLK conditionalrequestsareenabled.

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3.4.10 UCSCTL9 Register

UnifiedClockSystem Control9 Register Thisregisterisnotavailableon alldevices.See thedevice-specificdatasheet. Figure3-15.UCSCTL9 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved XT2BYPASSLV XT1BYPASSLV r0 r0 r0 r0 r0 r0 rw-0 rw-0 Table3-12.UCSCTL9 RegisterDescription Bit Field Type Reset Description 15-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 XT2BYPASSLV RW 0h SelectsXT2 bypassinputswinglevel.Must be setforreducedswingoperation. 0b = Inputrangefrom0 toDVCC 1b = Inputrangefrom0 toDVIO 0 XT1BYPASSLV RW 0h SelectsXT1 bypassinputswinglevel.Must be setforreducedswingoperation. 0b = Inputrangefrom0 toDVCC 1b = Inputrangefrom0 toDVIO 131SLAU259E –May 2009–RevisedJanuary2013 UnifiedClockSystem (UCS) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter4 SLAU259E –May 2009–RevisedJanuary2013 CPUX ThischapterdescribestheextendedMSP430X 16-bitRISC CPU (CPUX) with1MB memory access,its addressingmodes, and instructionset. NOTE: The MSP430X CPU implementedon thesedeviceshas,insome cases,slightlydifferent cyclecountsfromtheMSP430X CPU implementedon the2xx and 4xx families.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430X CPU (CPUX) Introduction

4.1 MSP430X CPU (CPUX) Introduction

The MSP430X CPU incorporatesfeaturesspecificallydesignedformodern programmingtechniques,such as calculatedbranching,tableprocessing,and theuse ofhigh-levellanguagessuch as C. The MSP430X CPU can addressa 1MB addressrangewithoutpaging.The MSP430X CPU iscompletelybackward compatiblewiththeMSP430 CPU. The MSP430X CPU featuresinclude:

RISC architecture
Orthogonalarchitecture
Fullregisteraccessincludingprogramcounter(PC),statusregister(SR),and stackpointer(SP)
Single-cycleregisteroperations
Largeregisterfilereducesfetchestomemory.
20-bitaddressbus allowsdirectaccessand branchingthroughouttheentirememory rangewithout paging.
16-bitdatabus allowsdirectmanipulationofword-widearguments.
Constantgeneratorprovidesthesixmost oftenused immediatevaluesand reducescode size.
Directmemory-to-memorytransferswithoutintermediateregisterholding
Byte,word,and 20-bitaddress-wordaddressing The blockdiagramoftheMSP430X CPU isshown inFigure4-1. 133SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Memory Address Bus - MABMDB - Memor y Data Bus 16/20-bit ALU srcdstZero, Z Carry, C Overflow,V Negative,N MCLK 016 15 R2/SR Status Register ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430X CPU (CPUX) Introduction www.ti.com Figure4-1.MSP430X CPU Block Diagram

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PC.19:16 PC.15:0 SPold SP SR.11:0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Interrupts

4.2 Interrupts

The MSP430X has thefollowinginterruptstructure:

Vectoredinterruptswithno pollingnecessary
Interruptvectorsarelocateddownward fromaddress0FFFEh. The interruptvectorscontain16-bitaddressesthatpointintothelower64-KB memory. Thismeans all interrupthandlersmust startinthelower64-KB memory. Duringan interrupt,theprogramcounter(PC)and thestatusregister(SR)arepushed ontothestackas shown inFigure4-2.The MSP430X architecturestoresthecomplete20-bitPC valueefficientlyby appendingthePC bits19:16tothestoredSR valueautomaticallyon thestack.When theRETI instruction isexecuted,thefull20-bitPC isrestoredmaking returnfrominterrupttoany addressinthememory range possible. Figure4-2.PC Storageon theStack forInterrupts 135SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

PC.19:16 PC.15:0 SPold SP 0Program Counter Bits 19 to 1 19 15 1 016 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CPU Registers www.ti.com

4.3 CPU Registers

The CPU incorporates16 registers(R0 throughR15).RegistersR0, R1, R2, and R3 have dedicated functions.RegistersR4 throughR15 areworkingregistersforgeneraluse.

4.3.1 Program Counter (PC)

The 20-bitProgram Counter(PC,alsocalledR0) pointstothenextinstructiontobe executed.Each instructionuses an even number ofbytes(2,4,6,or8 bytes),and thePC isincrementedaccordingly. Instructionaccessesareperformedon word boundaries,and thePC isalignedtoeven addresses. Figure4-3shows thePC. Figure4-3.Program Counter The PC can be addressedwithallinstructionsand addressingmodes. A few examples: MOV.W#LABEL,PC;BranchtoaddressLABEL(lower64KB) MOVA#LABEL,PC;BranchtoaddressLABEL(1MBmemory) MOV.WLABEL,PC;BranchtoaddressinwordLABEL ;(lower64KB) MOV.W@R14,PC;Branchindirecttoaddressin ;R14(lower64KB) ADDA#4,PC ;Skiptwowords(1MBmemory) The BR and CALL instructionsresettheupperfourPC bitsto0.Onlyaddressesinthelower64-KB addressrangecan be reachedwiththeBR orCALL instruction.When branchingorcalling,addresses beyond thelower64-KB rangecan onlybe reachedusingtheBRA orCALLA instructions.Also,any instructiontodirectlymodifythePC does so accordingtotheused addressingmode. Forexample, MOV.W#value,PCclearstheupperfourbitsofthePC, because itisa .W instruction. The PC isautomaticallystoredon thestackwithCALL (orCALLA) instructionsand duringan interrupt serviceroutine.Figure4-4shows thestorageofthePC withthereturnaddressaftera CALLA instruction. A CALL instructionstoresonlybits15:0ofthePC. Figure4-4.PC Storageon theStack forCALLA The RETA instructionrestoresbits19:0ofthePC and adds 4 tothestackpointer(SP).The RET instructionrestoresbits15:0tothePC and adds 2 totheSP.

4.3.2 Stack Pointer(SP)

The 20-bitStackPointer(SP,alsocalledR1) isused by theCPU tostorethereturnaddressesof subroutinecallsand interrupts.Ituses a predecrement,postincrementscheme. Inaddition,theSP can be used by softwarewithallinstructionsand addressingmodes. Figure4-5shows theSP. The SP is initializedintoRAM by theuser,and isalwaysalignedtoeven addresses.

136 CPUX SLAU259E –May 2009–RevisedJanuary2013

PUSH□SP The□stack□pointer□is□changed□after a□PUSH□SP instruction. SP1 SP2 POP SP The□stack□pointer□is□not□changed□after□a□POP SP instruction.□The□POP SP instruction□places□SP1□into□the stack□pointer□SP (SP2□=□SP1) Item n-1 Item.19:16 Item.15:0 SPold SP 0xxxh 0xxxh - 2 0xxxh - 4 0xxxh - 6 0xxxh - 8 SP 0123h SP I3 SP PUSH #0123h POP R8Address 0Stack Pointer Bits 19 to 1 19 1 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com CPU Registers Figure4-6shows thestackusage.Figure4-7shows thestackusage when 20-bitaddresswords are pushed. Figure4-5.Stack Pointer Figure4-6.Stack Usage Figure4-7.PUSHX.A Format on theStack The specialcasesofusingtheSP as an argumenttothePUSH and POP instructionsaredescribedand shown inFigure4-8. Figure4-8.PUSH SP, POP SP Sequence 137SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.3.3 StatusRegister(SR)

The 16-bitStatusRegister(SR,alsocalledR2),used as a sourceordestinationregister,can onlybe used inregistermode addressedwithword instructions.The remainingcombinationsofaddressingmodes are used tosupporttheconstantgenerator.Figure4-9shows theSR bits.Do notwrite20-bitvaluestothe SR. Unpredictableoperationcan result. Figure4-9.SR Bits Table4-1describestheSR bits. Table4-1.SR BitDescription Bit Description Reserved Reserved V Overflow.Thisbitissetwhen theresultofan arithmeticoperationoverflowsthesigned-variablerange. positive+ positive= negativeADDA negative+ negative= positive otherwisereset positive– negative= negativeSUBA,CMP(.B),CMPX(.B,.A),CMPA negative– positive= positive otherwisereset SCG1 System clockgenerator1.Thisbitmay be used toenableordisablefunctionsintheclocksystemdependingon the devicefamily;forexample,DCO biasenableordisable. SCG0 System clockgenerator0.Thisbitmay be used toenableordisablefunctionsintheclocksystemdependingon the devicefamily;forexample,FLL enableordisable. OSCOFF Oscillatoroff.Thisbit,when set,turnsofftheLFXT1 crystaloscillatorwhen LFXT1CLK isnotused forMCLK or SMCLK. CPUOFF CPU off.Thisbit,when set,turnsofftheCPU. SCG1 The bitsCPUOFF, OSCOFF, SCG0 and SCG1 requestthesystemtoentera low-powermode SCG0 OSCOFF CPUOFF GIE Generalinterruptenable.Thisbit,when set,enablesmaskableinterrupts.When reset,allmaskableinterruptsare disabled. N Negative.Thisbitissetwhen theresultofan operationisnegativeand clearedwhen theresultispositive. Z Zero.Thisbitissetwhen theresultofan operationis0 and clearedwhen theresultisnot0. C Carry.Thisbitissetwhen theresultofan operationproduceda carryand clearedwhen no carryoccurred. NOTE: BitmanipulationsoftheSR shouldbe done by thefollowinginstructions:MOV, BIS,and BIC.

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4.3.4 Constant GeneratorRegisters(CG1 and CG2)

Sixcommonly-usedconstantsaregeneratedwiththeconstantgeneratorregistersR2 (CG1) and R3 (CG2),withoutrequiringan additional16-bitword ofprogramcode.The constantsareselectedwiththe sourceregisteraddressingmodes (As),as describedinTable4-2. Table4-2.Values ofConstant GeneratorsCG1, CG2 Register As Constant Remarks R2 00 – Registermode R2 01 (0) Absoluteaddressmode R2 10 00004h +4,bitprocessing R2 11 00008h +8,bitprocessing R3 00 00000h 0,word processing R3 01 00001h +1 R3 10 00002h +2,bitprocessing R3 11 FFh,FFFFh, FFFFFh –1,word processing The constantgeneratoradvantagesare:

No specialinstructionsrequired
No additionalcode word forthesixconstants
No code memory accessrequiredtoretrievetheconstant The assembleruses theconstantgeneratorautomaticallyifone ofthesixconstantsisused as an immediatesourceoperand.RegistersR2 and R3, used intheconstantmode, cannotbe addressed explicitly;theyactas source-onlyregisters.

4.3.4.1 Constant Generator– Expanded InstructionSet

The RISC instructionsetoftheMSP430 has only27 instructions.However,theconstantgeneratorallows theMSP430 assemblertosupport24 additionalemulatedinstructions.Forexample,thesingle-operand instruction: CLRdst isemulatedby thedouble-operandinstructionwiththesame length: MOVR3,dst where the#0 isreplacedby theassembler,and R3 isused withAs = 00. INCdst isreplacedby: ADD0(R3),dst 139SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0 Register

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4.3.5 General-PurposeRegisters(R4 –R15)

The 12 CPU registers(R4 toR15) contain8-bit,16-bit,or20-bitvalues.Any byte-writetoa CPU register clearsbits19:8.Any word-writetoa registerclearsbits19:16.The onlyexceptionistheSXT instruction. The SXT instructionextendsthesignthroughthecomplete20-bitregister. Figure4-10throughFigure4-14show thehandlingofbyte,word,and address-worddata.Note thereset oftheleadingmost significantbits(MSBs) ifa registeristhedestinationofa byteorword instruction. Figure4-10shows bytehandling(8-bitdata,.Bsuffix).The handlingisshown fora sourceregisterand a destinationmemory byteand fora sourcememory byteand a destinationregister. Figure4-10.Register-Byteand Byte-RegisterOperation Figure4-11and Figure4-12show 16-bitword handling(.W suffix).The handlingisshown fora source registerand a destinationmemory word and fora sourcememory word and a destinationregister. Figure4-11.Register-WordOperation

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Register - Ad dress-Word Operation Register Memory Operation Memory Unused Memory +2 Memory +2 19 16 15 0 8 7 High Byte Low Byte Word-Register Operation Register Memory Operation ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com CPU Registers Figure4-12.Word-RegisterOperation Figure4-13and Figure4-14show 20-bitaddress-wordhandling(.Asuffix).The handlingisshown fora sourceregisterand a destinationmemory address-wordand fora sourcememory address-wordand a destinationregister. Figure4-13.Register– Address-Word Operation 141SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Address-Word - Register Operation Register Memory Operation Register UnusedMemory +2 19 16 15 0 8 7 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com Figure4-14.Address-Word – RegisterOperation

4.4 Addressing Modes

Seven addressingmodes forthesourceoperandand fouraddressingmodes forthedestinationoperand use 16-bitor20-bitaddresses(seeTable4-3).The MSP430 and MSP430X instructionsareusable throughouttheentire1MB memory range. Table4-3.Source and DestinationAddressing As, Ad Addressing Mode Syntax Description 00,0 Register Rn Registercontentsareoperand. 01,1 Indexed X(Rn) (Rn + X) pointstotheoperand.X isstoredinthenextword,orstoredincombinationof theprecedingextensionword and thenextword. 01,1 Symbolic ADDR (PC + X) pointstotheoperand.X isstoredinthenextword,orstoredincombinationof theprecedingextensionword and thenextword.Indexedmode X(PC) isused. word,orstoredincombinationoftheprecedingextensionword and thenextword. Indexedmode X(SR) isused. 10,– IndirectRegister @Rn Rn isused as a pointertotheoperand. 11,– Indirect @Rn+ Rn isused as a pointertotheoperand.Rn isincrementedafterwardsby 1 for.B Autoincrement instructions,by 2 for.W instructions,and by 4 for.Ainstructions. 11,– Immediate #N N isstoredinthenextword,orstoredincombinationoftheprecedingextensionword and thenextword.Indirectautoincrementmode @PC+ isused. The seven addressingmodes areexplainedindetailinthefollowingsections.Most oftheexamplesshow thesame addressingmode forthesourceand destination,butany validcombinationofsourceand destinationaddressingmodes ispossibleinan instruction. NOTE: Use ofLabelsEDE, TONI, TOM, and LEO ThroughoutMSP430 documentation,EDE, TONI, TOM, and LEO areused as genericlabels. They areonlylabelsand have no specialmeaning.

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Before: Address Space PC AA550h BB551h Register After: AA550h.or.11111h = BB551h 1800h21032h xxxxh D546h 21036h 21034h 1800h21032h xxxxh Address Space D506h PC 21036h 21034h AA550h 11111h Register Before: xxxxh Address Space D506h PC21036h 21034h AA550h 0B551h Register After: A550h.or.1111h = B551h ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes

4.4.1 RegisterMode

Operation: The operandisthe8-,16-,or20-bitcontentoftheused CPU register. Length: One, two,orthreewords Comment: Validforsourceand destination Byteoperation: Byteoperationreadsonlytheeightleastsignificantbits(LSBs)ofthesource registerRsrcand writestheresulttotheeightLSBs ofthedestinationregisterRdst. The bitsRdst.19:8arecleared.The registerRsrcisnotmodified. Word operation: Word operationreadsthe16 LSBs ofthesourceregisterRsrcand writestheresult tothe16 LSBs ofthedestinationregisterRdst.The bitsRdst.19:16arecleared. The registerRsrcisnotmodified. Address-word Address-wordoperationreadsthe20 bitsofthesourceregisterRsrcand writesthe operation: resulttothe20 bitsofthedestinationregisterRdst.The registerRsrcisnot modified SXT exception: The SXT instructionistheonlyexceptionforregisteroperation.The signofthelow byteinbit7 isextendedtothebitsRdst.19:8. BIS.WR5,R6;Example: ThisinstructionlogicallyORs the16-bitdatacontainedinR5 withthe16-bit contentsofR6. R6.19:16iscleared. BISX.AR5,R6;Example: ThisinstructionlogicallyORs the20-bitdatacontainedinR5 withthe20-bit contentsofR6. The extensionword containstheA/Lbitfor20-bitdata.The instructionword uses bytemode withbitsA/L:B/W= 01.The resultoftheinstructionis: 143SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0 Memory address

Rn.19:0 Lower 64 KB Rn.19:16 = 0 16-bit byte index 19 16 15 0 S ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.2 Indexed Mode

The Indexedmode calculatestheaddressoftheoperandby addingthesignedindextoa CPU register. The Indexedmode has threeaddressingpossibilities:

Indexedmode inlower64-KB memory
MSP430 instructionwithIndexedmode addressingmemory above thelower64-KB memory
MSP430X instructionwithIndexedmode

4.4.2.1 Indexed Mode inLower 64-KB Memory

IftheCPU registerRn pointstoan addressinthelower64 KB ofthememory range,thecalculated memory addressbits19:16areclearedaftertheadditionoftheCPU registerRn and thesigned16-bit index.Thismeans thecalculatedmemory addressisalwayslocatedinthelower64 KB and does not overfloworunderflowoutofthelower64-KB memory space.The RAM and theperipheralregisterscan be accessedthisway and existingMSP430 softwareisusablewithoutmodificationsas shown inFigure4-15. Figure4-15.Indexed Mode inLower 64 KB Length: Two orthreewords Operation: The signed16-bitindexislocatedinthenextword aftertheinstructionand isadded to theCPU registerRn. The resultingbits19:16areclearedgivinga truncated16-bit memory address,whichpointstoan operandaddressintherange00000h to0FFFFh. The operandisthecontentoftheaddressedmemory location. Comment: Validforsourceand destination.The assemblercalculatestheregisterindexand inserts it. ADD.B1000h(R5),0F000h(R6);Example: Thisinstructionadds the8-bitdatacontainedinsourcebyte1000h(R5)and the destinationbyte0F000h(R6)and placestheresultintothedestinationbyte.Sourceand destinationbytesarebothlocatedinthelower64 KB due totheclearedbits19:16of registersR5 and R6. Source: The bytepointedtoby R5 + 1000h resultsinaddress0479Ch + 1000h = 0579Ch after truncationtoa 16-bitaddress. Destination: The bytepointedtoby R6 + F000h resultsinaddress01778h + F000h = 00778h after truncationtoa 16-bitaddress.

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(sign extended to 20 bits) CPU Register Rn 20-bit signed add Memory address FFFFF 00000 Lower 64 KB 0FFFF 10000 Upper Memory Rn.19:16 > 0 16-bit byte index 1 ... 15 19 16 15 0 S Rn ± 32 KB S Rn.19:0 xxxxh Address Space F000h 1000h PC 1103Ah 11038h 11036h 0479Ch 01778h 01778h +F000h 00778h Register Before: Address Space Register After: 55D6h11034h xxxxh F000h 1000h PC1103Ah 11038h 11036h 0479Ch 01778h 55D6h11034h xxxxh xx45h 0077Ah 00778h xxxxh xx77h 0077Ah 00778h 32h +45h 77h src dst Sum 0479Ch +1000h 0579Ch xxxxh xx32h 0579Eh 0579Ch xxxxh xx32h 0579Eh 0579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes

4.4.2.2 MSP430 InstructionWith Indexed Mode inUpper Memory

IftheCPU registerRn pointstoan addressabove thelower64-KB memory, theRn bits19:16areused fortheaddresscalculationoftheoperand.The operandmay be locatedinmemory intherangeRn ±32 KB, because theindex,X,isa signed16-bitvalue.Inthiscase,theaddressoftheoperandcan overflow orunderflowintothelower64-KB memory space (seeFigure4-16and Figure4-17). Figure4-16.Indexed Mode inUpper Memory 145SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0,FFFF 10000 Rn.19:0 Rn.19:0 Rn.19:0 ±32 KB Rn.19:0 ±32 KB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com Figure4-17.Overflowand Underflow forIndexed Mode Length: Two orthreewords Operation: The sign-extended16-bitindexinthenextword aftertheinstructionisadded tothe 20 bitsoftheCPU registerRn. Thisdeliversa 20-bitaddress,whichpointstoan addressintherange0 toFFFFFh. The operandisthecontentoftheaddressed memory location. Comment: Validforsourceand destination.The assemblercalculatestheregisterindexand insertsit. ADD.W8346h(R5),2100h(R6);Example: Thisinstructionadds the16-bitdatacontainedinthesourceand thedestination addressesand placesthe16-bitresultintothedestination.Sourceand destination operandcan be locatedintheentireaddressrange. Source: The word pointedtoby R5 + 8346h.The negativeindex8346h issignextended, whichresultsinaddress23456h + F8346h = 1B79Ch. Destination: The word pointedtoby R6 + 2100h resultsinaddress15678h + 2100h = 17778h.

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+02100h 17778h Register Before: Address Space Register After: 5596h11034h xxxxh 2100h 8346h PC1103Ah 11038h 11036h 23456h 15678h 5596h11034h xxxxh 2345h 1777Ah 17778h xxxxh 7777h 1777Ah 17778h 05432h +02345h 07777h src dst Sum 23456h +F8346h 1B79Ch xxxxh 5432h 1B79Eh 1B79Ch xxxxh 5432h 1B79Eh 1B79Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes Figure4-18.Example forIndexed Mode

4.4.2.3 MSP430X InstructionWith Indexed Mode

When usingan MSP430X instructionwithIndexedmode, theoperandcan be locatedanywhere inthe rangeofRn + 19 bits. Length: Threeorfourwords Operation: The operandaddressisthesum ofthe20-bitCPU registercontentand the20-bit index.The 4 MSBs oftheindexarecontainedintheextensionword;the16 LSBs arecontainedintheword followingtheinstruction.The CPU registerisnotmodified Comment: Validforsourceand destination.The assemblercalculatestheregisterindexand insertsit. ADDX.A12346h(R5),32100h(R6);Example: Thisinstructionadds the20-bitdatacontainedinthesourceand thedestination addressesand placestheresultintothedestination. Source: Two words pointedtoby R5 + 12346h whichresultsinaddress23456h + 12346h = 3579Ch. Destination: Two words pointedtoby R6 + 32100h whichresultsinaddress45678h + 32100h = 77778h. 147SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

+32100h 77778h Register Before: Address Space Register After: PC 23456h 45678h R60001h 2345h 7777Ah 77778h 0007h 7777h 7777Ah 77778h 65432h +12345h 77777h src dst Sum 0006h 5432h 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 1883h21032h xxxxh2103Ah 2100h 2346h 55D6h 21038h 21036h 21034h 1883h21032h xxxxh2103Ah 23456h +12346h 3579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com The extensionword containstheMSBs ofthesourceindexand ofthedestinationindexand theA/Lbitfor 20-bitdata.The instructionword uses bytemode due tothe20-bitdatalengthwithbitsA/L:B/W= 01.

4.4.3 Symbolic Mode

The Symbolicmode calculatestheaddressoftheoperandby addingthesignedindextothePC. The Symbolicmode has threeaddressingpossibilities:

Symbolicmode inlower64-KB memory
MSP430 instructionwithSymbolicmode addressingmemory above thelower64-KB memory.
MSP430X instructionwithSymbolicmode

4.4.3.1 Symbolic Mode inLower 64 KB

IfthePC pointstoan addressinthelower64 KB ofthememory range,thecalculatedmemory address bits19:16areclearedaftertheadditionofthePC and thesigned16-bitindex.Thismeans thecalculated memory addressisalwayslocatedinthelower64 KB and does notoverfloworunderflowoutofthelower 64-KB memory space.The RAM and theperipheralregisterscan be accessedthisway and existing MSP430 softwareisusablewithoutmodificationsas shown inFigure4-19.

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PC.19:0 Lower 64 KB PC.19:16 = 0 16-bit byte index 19 16 15 0 S ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes Figure4-19.Symbolic Mode Running inLower 64 KB Operation: The signed16-bitindexinthenextword aftertheinstructionisadded temporarilyto thePC. The resultingbits19:16areclearedgivinga truncated16-bitmemory address,whichpointstoan operandaddressintherange00000h to0FFFFh. The operandisthecontentoftheaddressedmemory location. Length: Two orthreewords Comment: Validforsourceand destination.The assemblercalculatesthePC indexand insertsit. ADD.BEDE,TONI;Example: Thisinstructionadds the8-bitdatacontainedinsourcebyteEDE and destination byteTONI and placestheresultintothedestinationbyteTONI. BytesEDE and TONI and theprogramarelocatedinthelower64 KB. Source: ByteEDE locatedataddress0579Ch, pointedtoby PC + 4766h,where thePC index4766h istheresultof0579Ch – 01036h = 04766h.Address01036h isthe locationoftheindexforthisexample. Destination: ByteTONI locatedataddress00778h,pointedtoby PC + F740h,isthetruncated 16-bitresultof00778h – 1038h = FF740h.Address01038h isthelocationofthe indexforthisexample. 149SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

(sign extended to 20 bits) Program counter PC 20-bit signed add Memory address FFFFF 00000 Lower 64 KB 0FFFF 10000 PC.19:0 Upper Memory PC.19:16 > 0 16-bit byte index 1 ... 15 19 16 15 0 S PC ±32 KB S xxxxh Address Space F740h 4766h PC 0103Ah 01038h 01036h 01038h +0F740h 00778h Before: Address Space After: 05D0h01034h xxxxh F740h 4766h PC0103Ah 01038h 01036h 50D0h01034h xxxxh xx45h 0077Ah 00778h xxxxh xx77h 0077Ah 00778h 32h +45h 77h src dst Sum 01036h +04766h 0579Ch xxxxh xx32h 0579Eh 0579Ch xxxxh xx32h 0579Eh 0579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.3.2 MSP430 InstructionWith Symbolic Mode inUpper Memory

IfthePC pointstoan addressabove thelower64-KB memory, thePC bits19:16areused fortheaddress calculationoftheoperand.The operandmay be locatedinmemory intherangePC ± 32 KB, because the index,X,isa signed16-bitvalue.Inthiscase,theaddressoftheoperandcan overfloworunderflowinto thelower64-KB memory space as shown inFigure4-20and Figure4-21. Figure4-20.Symbolic Mode Running inUpper Memory

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PC.19:0 PC.19:0 PC.19:0 ±32 KB PC.19:0 ±32 KB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes Figure4-21.Overflowand Underflow forSymbolic Mode Length: Two orthreewords Operation: The sign-extended16-bitindexinthenextword aftertheinstructionisadded tothe 20 bitsofthePC. Thisdeliversa 20-bitaddress,whichpointstoan addressinthe range0 toFFFFFh. The operandisthecontentoftheaddressedmemory location. Comment: Validforsourceand destination.The assemblercalculatesthePC indexand insertsit ADD.WEDE,&TONI;Example: Thisinstructionadds the16-bitdatacontainedinsourceword EDE and destination word TONI and placesthe16-bitresultintothedestinationword TONI. Forthis example,theinstructionislocatedataddress2F034h. Source: Word EDE ataddress3379Ch, pointedtoby PC + 4766h,whichisthe16-bitresult of3379Ch – 2F036h = 04766h.Address2F036h isthelocationoftheindexforthis example. Destination: Word TONI locatedataddress00778h pointedtoby theabsoluteaddress00778h 151SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

+04766h 3379Ch Before: Address Space After: 5092h2F034h xxxxh 0778h 4766h PC2F03Ah 2F038h 2F036h 5092h2F034h xxxxh 5432h 3379Eh 3379Ch xxxxh 5432h 3379Eh 3379Ch 5432h +2345h 7777h src dst Sum xxxxh 2345h 0077Ah 00778h xxxxh 7777h 0077Ah 00778h ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.3.3 MSP430X InstructionWith Symbolic Mode

When usingan MSP430X instructionwithSymbolicmode, theoperandcan be locatedanywhere inthe rangeofPC + 19 bits. Length: Threeorfourwords Operation: The operandaddressisthesum ofthe20-bitPC and the20-bitindex.The 4 MSBs oftheindexarecontainedintheextensionword;the16 LSBs arecontainedinthe word followingtheinstruction. Comment: Validforsourceand destination.The assemblercalculatestheregisterindexand insertsit. ADDX.BEDE,TONI;Example: Thisinstructionadds the8-bitdatacontainedinsourcebyteEDE and destination byteTONI and placestheresultintothedestinationbyteTONI. Source: ByteEDE locatedataddress3579Ch, pointedtoby PC + 14766h,isthe20-bit resultof3579Ch – 21036h = 14766h.Address21036h istheaddressoftheindex inthisexample. Destination: ByteTONI locatedataddress77778h,pointedtoby PC + 56740h,isthe20-bit resultof77778h – 21038h = 56740h.Address21038h istheaddressoftheindexin thisexample.

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+56740h 77778h Before: Address SpaceAfter: PC xxxxh xx45h 7777Ah 77778h xxxxh xx77h 7777Ah 77778h 32h +45h 77h src dst Sum xxxxh xx32h 3579Eh 3579Ch xxxxh xx32h 3579Eh 3579Ch 18C5h21032h xxxxh2103Ah 6740h 4766h 50D0h 21038h 21036h 21034h 18C5h21032h xxxxh2103Ah 21036h +14766h 3579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes

4.4.4 AbsoluteMode

The Absolutemode uses thecontentsoftheword followingtheinstructionas theaddressoftheoperand. The Absolutemode has two addressingpossibilities:

Absolutemode inlower64-KB memory
MSP430X instructionwithAbsolutemode

4.4.4.1 AbsoluteMode inLower 64 KB

Ifan MSP430 instructionisused withAbsoluteaddressingmode, theabsoluteaddressisa 16-bitvalue and,therefore,pointstoan addressinthelower64 KB ofthememory range.The addressiscalculatedas an indexfrom0 and isstoredintheword followingtheinstructionThe RAM and theperipheralregisters can be accessedthisway and existingMSP430 softwareisusablewithoutmodifications. Length: Two orthreewords Operation: The operandisthecontentoftheaddressedmemory location. Comment: Validforsourceand destination.The assemblercalculatestheindexfrom0 and insertsit. ADD.W&EDE,&TONI;Example: Thisinstructionadds the16-bitdatacontainedintheabsolutesourceand destinationaddressesand placestheresultintothedestination. Source: Word ataddressEDE Destination: Word ataddressTONI 153SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Before: Address SpaceAfter: 5292h21034h xxxxh 7778h 579Ch PC2103Ah 21038h 21036h 5292h21034h xxxxh 2345h 0777Ah 07778h xxxxh 7777h 0777Ah 07778h 5432h +2345h 7777h src dst Sum xxxxh 5432h 0579Eh 0579Ch xxxxh 5432h 0579Eh 0579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.4.2 MSP430X InstructionWith AbsoluteMode

Ifan MSP430X instructionisused withAbsoluteaddressingmode, theabsoluteaddressisa 20-bitvalue and,therefore,pointstoany addressinthememory range.The addressvalueiscalculatedas an index from0.The 4 MSBs oftheindexarecontainedintheextensionword,and the16 LSBs arecontainedin theword followingtheinstruction. Length: Threeorfourwords Operation: The operandisthecontentoftheaddressedmemory location. Comment: Validforsourceand destination.The assemblercalculatestheindexfrom0 and insertsit. ADDX.A&EDE,&TONI;Example: Thisinstructionadds the20-bitdatacontainedintheabsolutesourceand destinationaddressesand placestheresultintothedestination. Source: Two words beginningwithaddressEDE Destination: Two words beginningwithaddressTONI

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Before: Address Space After: PC 0001h 2345h 7777Ah 77778h 0007h 7777h 7777Ah 77778h 65432h +12345h 77777h src dst Sum 0006h 5432h 3579Eh 3579Ch 0006h 5432h 3579Eh 3579Ch 1987h21032h xxxxh2103Ah 7778h 579Ch 52D2h 21038h 21036h 21034h 1987h21032h xxxxh2103Ah ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes

4.4.5 IndirectRegisterMode

The IndirectRegistermode uses thecontentsoftheCPU registerRsrcas thesourceoperand.The IndirectRegistermode alwaysuses a 20-bitaddress. Length: One, two,orthreewords Operation: The operandisthecontenttheaddressedmemory location.The sourceregister Rsrcisnotmodified. Comment: Validonlyforthesourceoperand.The substituteforthedestinationoperandis 0(Rdst). ADDX.W@R5,2100h(R6)Example: Thisinstructionadds thetwo 16-bitoperandscontainedinthesourceand the destinationaddressesand placestheresultintothedestination. Source: Word pointedtoby R5. R5 containsaddress3579Ch forthisexample. Destination: Word pointedtoby R6 + 2100h,whichresultsinaddress45678h + 2100h = 7778h 155SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

+02100h 47778h Register Before: Address Space Register After: xxxxh 2100h 55A6h PC21038h 21036h 21034h 3579Ch 45678h xxxxh 2345h 4777Ah 47778h xxxxh 7777h 4777Ah 47778h 5432h +2345h 7777h src dst Sum xxxxh 5432h 3579Eh 3579Ch xxxxh 5432h 3579Eh 3579Ch R5 R5 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.6 IndirectAutoincrementMode

The IndirectAutoincrementmode uses thecontentsoftheCPU registerRsrcas thesourceoperand.Rsrc isthenautomaticallyincrementedby 1 forbyteinstructions,by 2 forword instructions,and by 4 for address-wordinstructionsimmediatelyafteraccessingthesourceoperand.Ifthesame registerisused for sourceand destination,itcontainstheincrementedaddressforthedestinationaccess.Indirect Autoincrementmode alwaysuses 20-bitaddresses. Length: One, two,orthreewords Operation: The operandisthecontentoftheaddressedmemory location. Comment: Validonlyforthesourceoperand ADD.B@R5+,0(R6)Example: Thisinstructionadds the8-bitdatacontainedinthesourceand thedestination addressesand placestheresultintothedestination. Source: Bytepointedtoby R5. R5 containsaddress3579Ch forthisexample. Destination: Bytepointedtoby R6 + 0h,whichresultsinaddress0778h forthisexample

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+0000h 00778h Register Before: Address Space Register After: xxxxh 0000h 55F6h PC21038h 21036h 21034h 3579Dh 00778h xxxxh xx45h 0077Ah 00778h xxxxh xx77h 0077Ah 00778h 32h +45h 77h src dst Sum xxh 32h 3579Dh 3579Ch xxh xx32h 3579Dh 3579Ch ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AddressingModes

4.4.7 Immediate Mode

The Immediatemode allowsaccessingconstantsas operandsby includingtheconstantinthememory locationfollowingtheinstruction.The PC isused withtheIndirectAutoincrementmode. The PC pointsto theimmediatevaluecontainedinthenextword.Afterthefetchingoftheimmediateoperand,thePC is incrementedby 2 forbyte,word,oraddress-wordinstructions.The Immediatemode has two addressing possibilities:

8-bitor16-bitconstantswithMSP430 instructions
20-bitconstantswithMSP430X instruction

4.4.7.1 MSP430 InstructionsWith Immediate Mode

Ifan MSP430 instructionisused withImmediateaddressingmode, theconstantisan 8-or16-bitvalue and isstoredintheword followingtheinstruction. Length: Two orthreewords.One word lessifa constantoftheconstantgeneratorcan be used fortheimmediateoperand. Operation: The 16-bitimmediatesourceoperandisused togetherwiththe16-bitdestination operand. Comment: Validonlyforthesourceoperand ADD#3456h,&TONIExample: Thisinstructionadds the16-bitimmediateoperand3456h tothedatainthe destinationaddressTONI. Source: 16-bitimmediatevalue3456h Destination: Word ataddressTONI 157SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Before: Address Space After: PC 0001h 2345h 7777Ah 77778h 0003h 579Bh 7777Ah 77778h 23456h +12345h 3579Bh src dst Sum 1907h21032h xxxxh2103Ah 7778h 3456h 50F2h 21038h 21036h 21034h 1907h21032h xxxxh2103Ah xxxxh Address Space 0778h 3456h PC 2103Ah 21038h 21036h Before: Address Space After: 50B2h21034h xxxxh 0778h 3456h PC2103Ah 21038h 21036h 50B2h21034h xxxxh 2345h 0077Ah 00778h xxxxh 579Bh 0077Ah 00778h 3456h +2345h 579Bh src dst Sum ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AddressingModes www.ti.com

4.4.7.2 MSP430X InstructionsWith Immediate Mode

Ifan MSP430X instructionisused withImmediateaddressingmode, theconstantisa 20-bitvalue.The 4 MSBs oftheconstantarestoredintheextensionword,and the16 LSBs oftheconstantarestoredinthe word followingtheinstruction. Length: Threeorfourwords.One word lessifa constantoftheconstantgeneratorcan be used fortheimmediateoperand. Operation: The 20-bitimmediatesourceoperandisused togetherwiththe20-bitdestination operand. Comment: Validonlyforthesourceoperand ADDX.A#23456h,&TONI;Example: Thisinstructionadds the20-bitimmediateoperand23456h tothedatainthe destinationaddressTONI. Source: 20-bitimmediatevalue23456h Destination: Two words beginningwithaddressTONI

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Op-code Rsrc Ad B/W As Rdst Source□or□Destination□15:0 Destination□15:0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions

4.5 MSP430 and MSP430X Instructions

MSP430 instructionsarethe27 implementedinstructionsoftheMSP430 CPU. These instructionsare used throughoutthe1MB memory rangeunlesstheir16-bitcapabilityisexceeded.The MSP430X instructionsareused when theaddressingoftheoperandsorthedatalengthexceedsthe16-bitcapability oftheMSP430 instructions. Therearethreepossibilitieswhen choosingbetween an MSP430 and MSP430X instruction:

To use onlytheMSP430 instructions– The onlyexceptionsaretheCALLA and theRETA instruction. Thiscan be done ifa few,simplerulesaremet: – Placeallconstants,variables,arrays,tables,and datainthelower64 KB. Thisallowstheuse of MSP430 instructionswith16-bitaddressingforalldataaccesses.No pointerswith20-bitaddresses areneeded. – Placesubroutineconstantsimmediatelyafterthesubroutinecode.Thisallowstheuse ofthe symbolicaddressingmode withits16-bitindextoreachaddresseswithintherangeofPC + 32 KB.
To use onlyMSP430X instructions– The disadvantagesofthismethod arethereducedspeed due to theadditionalCPU cyclesand theincreasedprogramspace due tothenecessaryextensionword for any double-operandinstruction.
Use thebestfittinginstructionwhere needed. Section4.5.1listsand describestheMSP430 instructions,and Section4.5.2listsand describesthe MSP430X instructions.

4.5.1 MSP430 Instructions

The MSP430 instructionscan be used,regardlessiftheprogramresidesinthelower64 KB orbeyond it. The onlyexceptionsaretheinstructionsCALL and RET, whicharelimitedtothelower64-KB address range.CALLA and RETA instructionshave been added totheMSP430X CPU tohandlesubroutinesinthe entireaddressrangewithno code sizeoverhead.

4.5.1.1 MSP430 Double-Operand (FormatI)Instructions

Figure4-22shows theformatoftheMSP430 double-operandinstructions.Sourceand destinationwords areappended fortheIndexed,Symbolic,Absolute,and Immediatemodes. Table4-4liststhe12 MSP430 double-operandinstructions. Figure4-22.MSP430 Double-Operand InstructionFormat 159SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Destination□15:0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com Table4-4.MSP430 Double-Operand Instructions StatusBits(1) S-Reg,D-Mnemonic OperationReg V N Z C src,dst src→ dst – – – –MOV(.B) src,dst src+ dst→ dst * * * *ADD(.B) src,dst src+ dst+ C → dst * * * *ADDC(.B) src,dst dst+ .not.src+ 1 → dst * * * *SUB(.B) src,dst dst+ .not.src+ C → dst * * * *SUBC(.B) src,dst dst-src * * * *CMP(.B) src,dst src+ dst+ C → dst(decimally) * * * *DADD(.B) src,dst src.and.dst 0 * * ZBIT(.B) src,dst src.or.dst→ dst – – – –BIS(.B) src,dst src.xor.dst→ dst * * * ZXOR(.B) src,dst src.and.dst→ dst 0 * * ZAND(.B) (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset.

4.5.1.2 MSP430 Single-Operand(FormatII)Instructions

Figure4-23shows theformatforMSP430 single-operandinstructions,exceptRETI.The destinationword isappended fortheIndexed,Symbolic,Absolute,and Immediatemodes. Table4-5liststheseven single- operandinstructions. Figure4-23.MSP430 Single-OperandInstructions Table4-5.MSP430 Single-OperandInstructions StatusBits(1) S-Reg,D-Mnemonic OperationReg V N Z C src SP -2 → SP, src→ SP – – – –PUSH(.B) dst Callsubroutineinlower64 KB – – – –CALL TOS → SR, SP + 2 → SP * * * *RETI TOS → PC,SP + 2 → SP (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset.

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Condition S 10-Bit Signed PC Offset ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions

4.5.1.3 Jump Instructions

Figure4-24shows theformatforMSP430 and MSP430X jump instructions.The signed10-bitword offset ofthejump instructionismultipliedby two,sign-extendedtoa 20-bitaddress,and added tothe20-bitPC. Thisallowsjumps ina rangeof–511 to+512 words relativetothePC inthefull20-bitaddressspace. Jumps do notaffectthestatusbits.Table4-6listsand describestheeightjump instructions. Figure4-24.Format ofConditionalJump Instructions Table4-6.ConditionalJump Instructions Mnemonic S-Reg,D-Reg Operation Label Jump tolabelifzerobitissetJEQ,JZ Label Jump tolabelifzerobitisresetJNE,JNZ Label Jump tolabelifcarrybitissetJC Label Jump tolabelifcarrybitisresetJNC Label Jump tolabelifnegativebitissetJN Label Jump tolabelif(N .XOR. V) = 0JGE Label Jump tolabelif(N .XOR. V) = 1JL Label Jump tolabelunconditionallyJMP

4.5.1.4 Emulated Instructions

InadditiontotheMSP430 and MSP430X instructions,emulatedinstructionsareinstructionsthatmake code easiertowriteand read,butdo nothave op-codesthemselves.Instead,theyarereplaced automaticallyby theassemblerwitha coreinstruction.Thereisno code orperformancepenaltyforusing emulatedinstructions.The emulatedinstructionsarelistedinTable4-7. Table4-7.Emulated Instructions StatusBits(1) Instruction Explanation Emulation V N Z C Add Carrytodst * * * *ADC(.B)dst ADDC(.B)#0,dst Branchindirectlydst – – – –BRdst MOVdst,PC Cleardst – – – –CLR(.B)dst MOV(.B)#0,dst ClearCarrybit – – – 0CLRC BIC#1,SR ClearNegativebit – 0 – –CLRN BIC#4,SR ClearZerobit – – 0 –CLRZ BIC#2,SR Add Carrytodstdecimally * * * *DADC(.B)dst DADD(.B)#0,dst Decrement dstby 1 * * * *DEC(.B)dst SUB(.B)#1,dst Decrement dstby 2 * * * *DECD(.B)dst SUB(.B)#2,dst Disableinterrupt – – – –DINT BIC#8,SR Enableinterrupt – – – –EINT BIS#8,SR Incrementdstby 1 * * * *INC(.B)dst ADD(.B)#1,dst Incrementdstby 2 * * * *INCD(.B)dst ADD(.B)#2,dst Invertdst * * * *INV(.B)dst XOR(.B)#–1,dst (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset. 161SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com Table4-7.Emulated Instructions(continued) StatusBits(1) Instruction Explanation Emulation V N Z C No operation – – – –NOP MOVR3,R3 Pop operandfromstack – – – –POPdst MOV@SP+,dst Returnfromsubroutine – – – –RET MOV@SP+,PC Shiftleftdstarithmetically * * * *RLA(.B)dst ADD(.B)dst,dst ShiftleftdstlogicallythroughCarry * * * *RLC(.B)dst ADDC(.B)dst,dst SubtractCarryfromdst * * * *SBC(.B)dst SUBC(.B)#0,dst SetCarrybit – – – 1SETC BIS#1,SR SetNegativebit – 1 – –SETN BIS#4,SR SetZerobit – – 1 –SETZ BIS#2,SR Testdst(comparewith0) 0 * * 1TST(.B)dst CMP(.B)#0,dst

4.5.1.5 MSP430 InstructionExecution

The number ofCPU clockcyclesrequiredforan instructiondepends on theinstructionformatand the addressingmodes used – nottheinstructionitself.The number ofclockcyclesreferstoMCLK. 4.5.1.5.1InstructionCycles and Length forInterrupt,Reset,and Subroutines Table4-8liststhelengthand theCPU cyclesforreset,interrupts,and subroutines. Table4-8.Interrupt,Return,and Reset Cycles and Length ExecutionTime Length ofInstructionAction (MCLK Cycles) (Words) ReturnfrominterruptRETI 5 1 ReturnfromsubroutineRET 4 1 Interruptrequestservice(cyclesneeded beforefirst 6 –instruction) WDT reset 4 – Reset(RST/NMI) 4 – 4.5.1.5.2Format II(Single-Operand)InstructionCycles and Lengths Table4-9liststhelengthand theCPU cyclesforalladdressingmodes oftheMSP430 single-operand instructions. Table4-9.MSP430 Format IIInstructionCycles and Length No. ofCycles Length ofAddressing Mode ExampleRRA, RRC InstructionPUSH CALLSWPB, SXT Rn 1 3 4 1 SWPBR5 @Rn 3 3 4 1 RRC@R9 @Rn+ 3 3 4 1 SWPB@R10+ #N N/A 3 4 2 CALL#LABEL X(Rn) 4 4 5 2 CALL2(R7) EDE 4 4 5 2 PUSHEDE &EDE 4 4 6 2 SXT&EDE

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions 4.5.1.5.3Jump InstructionsCycles and Lengths Alljump instructionsrequireone code word and taketwo CPU cyclestoexecute,regardlessofwhether thejump istakenornot. 4.5.1.5.4Format I(Double-Operand)InstructionCycles and Lengths Table4-10liststhelengthand CPU cyclesforalladdressingmodes oftheMSP430 FormatIinstructions. Table4-10.MSP430 Format IInstructionsCycles and Length Addressing Mode Length ofNo. ofCycles ExampleInstructionSource Destination Rn Rm 1 1 MOVR5,R8 PC 3 1 BRR9 x(Rm) 4(1) 2 ADDR5,4(R6) EDE 4(1) 2 XORR8,EDE &EDE 4(1) 2 MOVR5,&EDE @Rn Rm 2 1 AND@R4,R5 PC 4 1 BR@R8 x(Rm) 5(1) 2 XOR@R5,8(R6) EDE 5(1) 2 MOV@R5,EDE &EDE 5(1) 2 XOR@R5,&EDE @Rn+ Rm 2 1 ADD@R5+,R6 PC 4 1 BR@R9+ x(Rm) 5(1) 2 XOR@R5,8(R6) EDE 5(1) 2 MOV@R9+,EDE &EDE 5(1) 2 MOV@R9+,&EDE #N Rm 2 2 MOV#20,R9 PC 3 2 BR#2AEh x(Rm) 5(1) 3 MOV#0300h,0(SP) EDE 5(1) 3 ADD#33,EDE &EDE 5(1) 3 ADD#33,&EDE x(Rn) Rm 3 2 MOV2(R5),R7 PC 5 2 BR2(R6) TONI 6(1) 3 MOV4(R7),TONI x(Rm) 6(1) 3 ADD4(R4),6(R9) &TONI 6(1) 3 MOV2(R4),&TONI EDE Rm 3 2 ANDEDE,R6 PC 5 2 BREDE TONI 6(1) 3 CMPEDE,TONI x(Rm) 6(1) 3 MOVEDE,0(SP) &TONI 6(1) 3 MOVEDE,&TONI &EDE Rm 3 2 MOV&EDE,R8 PC 5 2 BR&EDE TONI 6(1) 3 MOV&EDE,TONI x(Rm) 6(1) 3 MOV&EDE,0(SP) &TONI 6(1) 3 MOV&EDE,&TONI (1) MOV, BIT,and CMP instructionsexecuteinone fewercycle. 163SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0 0 0 1 1 Source bits 19:16 A/L 0 0 Destination bits 19:16 15 12 1 1 10 9 8 7 6 5 4 3 0 0001 1 00 ZC # A/L 0 0 (n-1)/Rn ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com

4.5.2 MSP430X Extended Instructions

The extendedMSP430X instructionsgivetheMSP430X CPU fullaccesstoits20-bitaddressspace.Most MSP430X instructionsrequirean additionalword ofop-codecalledtheextensionword.Some extended instructionsdo notrequirean additionalword and arenotedintheinstructiondescription.Alladdresses, indexes,and immediatenumbers have 20-bitvalueswhen precededby theextensionword. Therearetwo typesofextensionwords:

Registerorregistermode forFormatIinstructionsand registermode forFormatIIinstructions
Extensionword forallotheraddressmode combinations

4.5.2.1 RegisterMode ExtensionWord

The registermode extensionword isshown inFigure4-25and describedinTable4-11.An example is shown inFigure4-27. Figure4-25.ExtensionWord forRegisterModes Table4-11.DescriptionoftheExtensionWord BitsforRegisterMode Bit Description 15:11 Extensionword op-code.Op-codes 1800h to1FFFh areextensionwords. 10:9 Reserved ZC Zerocarry 0 The executedinstructionuses thestatusofthecarrybitC. 1 The executedinstructionuses thecarrybitas 0.The carrybitisdefinedby theresultofthefinaloperationafter instructionexecution. # Repetition 0 The number ofinstructionrepetitionsissetby extensionword bits3:0. 1 The number ofinstructionrepetitionsisdefinedby thevalueofthefourLSBs ofRn. See descriptionforbits3:0. A/L Data lengthextension.TogetherwiththeB/W bitsofthefollowingMSP430 instruction,theAL bitdefinestheused data lengthoftheinstruction. A/L B/W Comment 0 0 Reserved 0 1 20-bitaddressword 1 0 16-bitword 1 1 8-bitbyte 5:4 Reserved 3:0 Repetitioncount # = 0 These fourbitssettherepetitioncountn.These bitscontainn – 1. # = 1 These fourbitsdefinetheCPU registerwhose bits3:0setthenumber ofrepetitions.Rn.3:0containn – 1.

4.5.2.2 Non-RegisterMode ExtensionWord

The extensionword fornon-registermodes isshown inFigure4-26and describedinTable4-12.An example isshown inFigure4-28. Figure4-26.ExtensionWord forNon-RegisterModes

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 00 ZC # A/L Rsvd (n-1)/Rn Op-code Rsrc Ad B/W As Rdst XORX.A R9,R8 0 0 0 1 1 0 0 0 0 0 0 14(XOR) 9 0 1 0 8(R8) XORX instruction Source R9 0: Use Carry 1: Repetition count in bits 3:0 01:Address word Destination register mode Source register mode Destination R8 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions Table4-12.DescriptionofExtensionWord BitsforNon-RegisterModes Bit Description 15:11 Extensionword op-code.Op-codes 1800h to1FFFh areextensionwords. SourceBits The fourMSBs ofthe20-bitsource.Dependingon thesourceaddressingmode, thesefourMSBs may belongtoan 19:16 immediateoperand,an index,ortoan absoluteaddress. A/L Data lengthextension.TogetherwiththeB/W bitsofthefollowingMSP430 instruction,theAL bitdefinestheused datalengthoftheinstruction. A/L B/W Comment 0 0 Reserved 0 1 20-bitaddressword 1 0 16-bitword 1 1 8-bitbyte 5:4 Reserved DestinationThe fourMSBs ofthe20-bitdestination.Dependingon thedestinationaddressingmode, thesefourMSBs may Bits19:16 belongtoan indexortoan absoluteaddress. NOTE: B/W and A/L bitsettingsforSWPBX and SXTX A/L B/W 0 0 SWPBX.A, SXTX.A 0 1 N/A 1 0 SWPB.W, SXTX.W 1 1 N/A Figure4-27.Example forExtended Registeror RegisterInstruction 165SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 1 1 Source 19:16 A/L Rsvd Destination 19:16 Op-code Rsrc Ad B/W As Rdst XORX.A #12345h,□45678h(R15) 0 0 0 1 1 1 0 0 4 14 (XOR) 0 (PC) 1 1 3 15 (R15) 18xx extension word 12345h @PC+ X(Rn) Source 15:0 Destination 15:0 Immediate operand LSBs: 2345h Index destination LSBs: 5678h 01: Address word ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com Figure4-28.Example forExtended Immediate or Indexed Instruction

4.5.2.3 Extended Double-Operand (FormatI)Instructions

All12 double-operandinstructionshave extendedversionsas listedinTable4-13. Table4-13.Extended Double-Operand Instructions StatusBits(1) Mnemonic Operands Operation V N Z C src,dst src→ dst – – – –MOVX(.B,.A) src,dst src+ dst→ dst * * * *ADDX(.B,.A) src,dst src+ dst+ C → dst * * * *ADDCX(.B,.A) src,dst dst+ .not.src+ 1 → dst * * * *SUBX(.B,.A) src,dst dst+ .not.src+ C → dst * * * *SUBCX(.B,.A) src,dst dst– src * * * *CMPX(.B,.A) src,dst src+ dst+ C → dst(decimal) * * * *DADDX(.B,.A) src,dst src.and.dst 0 * * ZBITX(.B,.A) src,dst src.or.dst→ dst – – – –BISX(.B,.A) src,dst src.xor.dst→ dst * * * ZXORX(.B,.A) src,dst src.and.dst→ dst 0 * * ZANDX(.B,.A) (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset.

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15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 19:16 Operand LSBs 15:0 Address Address+2 15 14 13 12 1 1 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 A/L n-1/Rn Op-code B/W dst

0 ZC # 0 0

src.15:0 src.19:16 0 0 src Ad As 0 0 0 1 1 A/L Op-code B/W dst dst.15:0 0 0 src Ad 0 0 0 1 1 A/L dst.19:16 Op-code B/W dst src.15:0 0 0 src Ad 0 0 0 0 dst.19:160 0 0 0 As src.19:16 As dst.15:0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions The fourpossibleaddressingcombinationsfortheextensionword forFormatIinstructionsareshown in Figure4-29. Figure4-29.Extended Format IInstructionFormats Ifthe20-bitaddressofa sourceordestinationoperandislocatedinmemory, notina CPU register,then two words areused forthisoperandas shown inFigure4-30. Figure4-30.20-BitAddresses inMemory 167SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

15 14 13 12 1 1 10 9 8 7 6 5 4 3 0 0 0 0 1 1 0 A/L n-1/Rn Op-code B/W dst dst.15:0 0 0 0 0 0 0 dst.19:160 0 0 0 0 0 0 0 0 0 1 x x 1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com

4.5.2.4 Extended Single-Operand(FormatII)Instructions

ExtendedMSP430X FormatIIinstructionsarelistedinTable4-14. Table4-14.Extended Single-OperandInstructions StatusBits(1) Mnemonic Operands Operation n V N Z C dst Callindirecttosubroutine(20-bitaddress) – – – –CALLA #n,Rdst Pop n 20-bitregistersfromstack 1 to16 – – – –POPM.A #n,Rdst Pop n 16-bitregistersfromstack 1 to16 – – – –POPM.W #n,Rsrc Push n 20-bitregisterstostack 1 to16 – – – –PUSHM.A #n,Rsrc Push n 16-bitregisterstostack 1 to16 – – – –PUSHM.W src Push 8-,16-,or20-bitsourcetostack – – – –PUSHX(.B,.A) #n,Rdst RotaterightRdstn bitsthroughcarry(16-,20-bitregister) 1 to4 0 * * *RRCM(.A) #n,Rdst RotaterightRdstn bitsunsigned(16-,20-bitregister) 1 to4 0 * * *RRUM(.A) #n,Rdst RotaterightRdstn bitsarithmetically(16-,20-bitregister) 1 to4 0 * * *RRAM(.A) #n,Rdst RotateleftRdstn bitsarithmetically(16-,20-bitregister) 1 to4 * * * *RLAM(.A) dst Rotaterightdstthroughcarry(8-,16-,20-bitdata) 1 0 * * *RRCX(.B,.A) Rdst Rotaterightdstunsigned(8-,16-,20-bit) 1 0 * * *RRUX(.B,.A) dst Rotaterightdstarithmetically 1 0 * * *RRAX(.B,.A) dst Exchange lowbytewithhighbyte 1 – – – –SWPBX(.A) Rdst Bit7→ bit8...bit19 1 0 * * ZSXTX(.A) dst Bit7→ bit8...MSB 1 0 * * ZSXTX(.A) (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset. The threepossibleaddressingmode combinationsforFormatIIinstructionsareshown inFigure4-31. Figure4-31.Extended Format IIInstructionFormat

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Op-code #imm/ix/abs19:16 index15:0 #imm15:0 / index15:0 / &abs15:0 15 12 11 8 7 4 3 0 C Rsrc Op-code 0(PC) C #imm/abs19:16 Op-code 0(PC) C Rsrc Op-code 0(PC) #imm15:0 / &abs15:0 index15:0 15 12 1 1 10 9 4 3 0 C n-1 Op-code Rdst 15 8 7 4 3 0 Op-code n-1 Rdst - n+1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions 4.5.2.4.1Extended Format IIInstructionFormat Exceptions ExceptionsfortheFormatIIinstructionformatsareshown inFigure4-32throughFigure4-35. Figure4-32.PUSHM and POPM InstructionFormat Figure4-33.RRCM, RRAM, RRUM, and RLAM InstructionFormat Figure4-34.BRA InstructionFormat Figure4-35.CALLA InstructionFormat 169SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.5.2.5 Extended Emulated Instructions

The extendedinstructionstogetherwiththeconstantgeneratorformtheextendedemulatedinstructions. Table4-15liststheemulatedinstructions. Table4-15.Extended Emulated Instructions Instruction Explanation Emulation Add carrytodstADCX(.B,.A)dst ADDCX(.B,.A)#0,dst BranchindirectdstBRAdst MOVAdst,PC ReturnfromsubroutineRETA MOVA@SP+,PC ClearRdstCLRARdst MOV#0,Rdst CleardstCLRX(.B,.A)dst MOVX(.B,.A)#0,dst Add carrytodstdecimallyDADCX(.B,.A)dst DADDX(.B,.A)#0,dst Decrement dstby 1DECX(.B,.A)dst SUBX(.B,.A)#1,dst Decrement Rdstby 2DECDARdst SUBA#2,Rdst Decrement dstby 2DECDX(.B,.A)dst SUBX(.B,.A)#2,dst Incrementdstby 1INCX(.B,.A)dst ADDX(.B,.A)#1,dst IncrementRdstby 2INCDARdst ADDA#2,Rdst Incrementdstby 2INCDX(.B,.A)dst ADDX(.B,.A)#2,dst InvertdstINVX(.B,.A)dst XORX(.B,.A)#-1,dst ShiftleftdstarithmeticallyRLAX(.B,.A)dst ADDX(.B,.A)dst,dst ShiftleftdstlogicallythroughcarryRLCX(.B,.A)dst ADDCX(.B,.A)dst,dst SubtractcarryfromdstSBCX(.B,.A)dst SUBCX(.B,.A)#0,dst TestRdst(comparewith0)TSTARdst CMPA#0,Rdst Testdst(comparewith0)TSTX(.B,.A)dst CMPX(.B,.A)#0,dst Pop todstPOPXdst MOVX(.B,.A)@SP+,dst

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions

4.5.2.6 MSP430X Address Instructions

MSP430X addressinstructionsareinstructionsthatsupport20-bitoperandsbuthave restricted addressingmodes. The addressingmodes arerestrictedtotheRegistermode and theImmediatemode, exceptfortheMOVA instructionas listedinTable4-16.Restrictingtheaddressingmodes removes the need fortheadditionalextension-wordop-codeimprovingcode densityand executiontime.Address instructionsshouldbe used any timean MSP430X instructionisneeded withthecorrespondingrestricted addressingmode. Table4-16.Address Instructions,Operate on 20-BitRegisterData StatusBits(1) Mnemonic Operands Operation V N Z C Add sourcetodestinationregister * * * *ADDA Rsrc,Rdst #imm20,Rdst Move sourcetodestination – – – –MOVA Rsrc,Rdst #imm20,Rdst z16(Rsrc),Rdst EDE,Rdst &abs20,Rdst @Rsrc,Rdst @Rsrc+,Rdst Rsrc,z16(Rdst) Rsrc,&abs20 Compare sourcetodestinationregister * * * *CMPA Rsrc,Rdst #imm20,Rdst Subtractsourcefromdestinationregister * * * *SUBA Rsrc,Rdst #imm20,Rdst (1) *= Statusbitisaffected. – = Statusbitisnotaffected. 0 = Statusbitiscleared. 1 = Statusbitisset. 171SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.5.2.7 MSP430X InstructionExecution

The number ofCPU clockcyclesrequiredforan MSP430X instructiondepends on theinstructionformat and theaddressingmodes used,nottheinstructionitself.The number ofclockcyclesreferstoMCLK. 4.5.2.7.1MSP430X Format II(Single-Operand)InstructionCycles and Lengths Table4-17liststhelengthand theCPU cyclesforalladdressingmodes oftheMSP430X extendedsingle- operandinstructions. Table4-17.MSP430X Format IIInstructionCycles and Length ExecutionCycles,Length ofInstruction(Words) Instruction Rn @Rn @Rn+ #N X(Rn) EDE & EDE CALLA 5,1 6,1 6,1 5,2 5(1),2 7,2 7,2 (1) Add one cyclewhen Rn = SP

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MSP430 and MSP430X Instructions 4.5.2.7.2MSP430X Format I(Double-Operand)InstructionCycles and Lengths Table4-18liststhelengthand CPU cyclesforalladdressingmodes oftheMSP430X extendedFormatI instructions. Table4-18.MSP430X Format IInstructionCycles and Length Length ofAddressing Mode No. ofCycles Instruction Examples Rn Rm (1) 2 2 2 BITX.BR5,R8 PC 4 4 2 ADDXR9,PC x(Rm) 5(2) 7(3) 3 ANDX.AR5,4(R6) EDE 5(2) 7(3) 3 XORXR8,EDE &EDE 5(2) 7(3) 3 BITX.WR5,&EDE @Rn Rm 3 4 2 BITX@R5,R8 PC 5 6 2 ADDX@R9,PC x(Rm) 6(2) 9(3) 3 ANDX.A@R5,4(R6) EDE 6(2) 9(3) 3 XORX@R8,EDE &EDE 6(2) 9(3) 3 BITX.B@R5,&EDE @Rn+ Rm 3 4 2 BITX@R5+,R8 PC 5 6 2 ADDX.A@R9+,PC x(Rm) 6(2) 9(3) 3 ANDX@R5+,4(R6) EDE 6(2) 9(3) 3 XORX.B@R8+,EDE &EDE 6(2) 9(3) 3 BITX@R5+,&EDE #N Rm 3 3 3 BITX#20,R8 PC (4) 4 4 3 ADDX.A#FE000h,PC EDE 6(2) 8(3) 4 XORX#A5A5h,EDE &EDE 6(2) 8(3) 4 BITX.B#12,&EDE x(Rn) Rm 4 5 3 BITX2(R5),R8 PC (4) 6 7 3 SUBX.A2(R6),PC TONI 7(2) 10(3) 4 ANDX4(R7),4(R6) x(Rm) 7(2) 10(3) 4 XORX.B2(R6),EDE &TONI 7(2) 10(3) 4 BITX8(SP),&EDE EDE Rm 4 5 3 BITX.BEDE,R8 PC (4) 6 7 3 ADDX.AEDE,PC TONI 7(2) 10(3) 4 ANDXEDE,4(R6) x(Rm) 7(2) 10(3) 4 ANDXEDE,TONI &TONI 7(2) 10(3) 4 BITXEDE,&TONI &EDE Rm 4 5 3 BITX&EDE,R8 PC (4) 6 7 3 ADDX.A&EDE,PC TONI 7(2) 10(3) 4 ANDX.B&EDE,4(R6) x(Rm) 7(2) 10(3) 4 XORX&EDE,TONI &TONI 7(2) 10(3) 4 BITX&EDE,&TONI (1) Repeat instructionsrequiren + 1 cycles,where n isthenumber oftimestheinstructionisexecuted. (2) Reduce thecyclecountby one forMOV, BIT,and CMP instructions. (3) Reduce thecyclecountby two forMOV, BIT,and CMP instructions. (4) Reduce thecyclecountby one forMOV, ADD, and SUB instructions. 173SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MSP430 and MSP430X Instructions www.ti.com 4.5.2.7.3MSP430X Address InstructionCycles and Lengths Table4-19liststhelengthand theCPU cyclesforalladdressingmodes oftheMSP430X address instructions. Table4-19.Address InstructionCycles and Length ExecutionTime Length ofInstructionAddressing Mode (MCLK Cycles) (Words) ExampleCMPA CMPAMOVASource Destination ADDA MOVA ADDABRA SUBA SUBA Rn Rn 1 1 1 1 CMPAR5,R8 PC 3 3 1 1 SUBAR9,PC x(Rm) 4 – 2 – MOVAR5,4(R6) EDE 4 – 2 – MOVAR8,EDE &EDE 4 – 2 – MOVAR5,&EDE @Rn Rm 3 – 1 – MOVA@R5,R8 PC 5 – 1 – MOVA@R9,PC @Rn+ Rm 3 – 1 – MOVA@R5+,R8 PC 5 – 1 – MOVA@R9+,PC #N Rm 2 3 2 2 CMPA#20,R8 PC 3 3 2 2 SUBA#FE000h,PC x(Rn) Rm 4 – 2 – MOVA2(R5),R8 PC 6 – 2 – MOVA2(R6),PC EDE Rm 4 – 2 – MOVAEDE,R8 PC 6 – 2 – MOVAEDE,PC &EDE Rm 4 – 2 – MOVA&EDE,R8 PC 6 – 2 – MOVA&EDE,PC

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4.6 InstructionSet Description

Table4-20shows allavailableinstructions: Table4-20.InstructionMap ofMSP430X 000 040 080 0C0 100 140 180 1C0 200 240 280 2C0 300 340 380 3C0 0xxx MOVA, CMPA, ADDA, SUBA, RRCM, RRAM, RLAM, RRUM RRC. SWP RRA. PUS PUS CALL10xx RRC RRA SXT CALL RETIB B B H H.B A 14xx PUSHM.A, POPM.A, PUSHM.W, POPM.W 18xx Extensionword forFormatIand FormatIIinstructions1Cxx 20xx JNE, JNZ 24xx JEQ, JZ 28xx JNC 2Cxx JC 30xx JN 34xx JGE 38xx JL 3Cxx JMP 4xxx MOV, MOV.B 5xxx ADD, ADD.B 6xxx ADDC, ADDC.B 7xxx SUBC, SUBC.B 8xxx SUB, SUB.B 9xxx CMP, CMP.B Axxx DADD, DADD.B Bxxx BIT,BIT.B Cxxx BIC,BIC.B Dxxx BIS,BIS.B Exxx XOR, XOR.B Fxxx AND, AND.B 175SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.1 Extended InstructionBinaryDescriptions

DetailedMSP430X instructionbinarydescriptionsareshown inthefollowingtables. Instruction Instructionsrcor data.19:16 dstGroup IdentifierInstruction 15 12 11 8 7 4 3 0 MOVA 0 0 0 0 src 0 0 0 0 dst MOVA@Rsrc,Rdst 0 0 0 0 src 0 0 0 1 dst MOVA@Rsrc+,Rdst 0 0 0 0 &abs.19:16 0 0 1 0 dst MOVA&abs20,Rdst &abs.15:0 0 0 0 0 src 0 0 1 1 dst MOVAx(Rsrc),Rdst x.15:0 ±15-bitindexx 0 0 0 0 src 0 1 1 0 &abs.19:16 MOVARsrc,&abs20 &abs.15:0 0 0 0 0 src 0 1 1 1 dst MOVARsrc,X(Rdst) x.15:0 ±15-bitindexx 0 0 0 0 imm.19:16 1 0 0 0 dst MOVA#imm20,Rdst imm.15:0 CMPA 0 0 0 0 imm.19:16 1 0 0 1 dst CMPA#imm20,Rdst imm.15:0 ADDA 0 0 0 0 imm.19:16 1 0 1 0 dst ADDA#imm20,Rdst imm.15:0 SUBA 0 0 0 0 imm.19:16 1 0 1 1 dst SUBA#imm20,Rdst imm.15:0 MOVA 0 0 0 0 src 1 1 0 0 dst MOVARsrc,Rdst CMPA 0 0 0 0 src 1 1 0 1 dst CMPARsrc,Rdst ADDA 0 0 0 0 src 1 1 1 0 dst ADDARsrc,Rdst SUBA 0 0 0 0 src 1 1 1 1 dst SUBARsrc,Rdst Instruction InstructionBitLoc. Inst.ID dstGroup IdentifierInstruction 15 12 11 10 9 8 7 4 3 0 RRCM.A 0 0 0 0 n – 1 0 0 0 1 0 0 dst RRCM.A#n,Rdst RRAM.A 0 0 0 0 n – 1 0 1 0 1 0 0 dst RRAM.A#n,Rdst RLAM.A 0 0 0 0 n – 1 1 0 0 1 0 0 dst RLAM.A#n,Rdst RRUM.A 0 0 0 0 n – 1 1 1 0 1 0 0 dst RRUM.A#n,Rdst RRCM.W 0 0 0 0 n – 1 0 0 0 1 0 1 dst RRCM.W#n,Rdst RRAM.W 0 0 0 0 n – 1 0 1 0 1 0 1 dst RRAM.W#n,Rdst RLAM.W 0 0 0 0 n – 1 1 0 0 1 0 1 dst RLAM.W#n,Rdst RRUM.W 0 0 0 0 n – 1 1 1 0 1 0 1 dst RRUM.W#n,Rdst

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription InstructionIdentifier dst Instruction 15 12 11 8 7 6 5 4 3 0 RETI 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 CALLA 0 0 0 1 0 0 1 1 0 1 0 0 dst CALLARdst 0 0 0 1 0 0 1 1 0 1 0 1 dst CALLAx(Rdst) x.15:0 0 0 0 1 0 0 1 1 0 1 1 0 dst CALLA@Rdst 0 0 0 1 0 0 1 1 0 1 1 1 dst CALLA@Rdst+ 0 0 0 1 0 0 1 1 1 0 0 0 &abs.19:16 CALLA&abs20 &abs.15:0 0 0 0 1 0 0 1 1 1 0 0 1 x.19:16 CALLAEDE x.15:0 CALLAx(PC) 0 0 0 1 0 0 1 1 1 0 1 1 imm.19:16 CALLA#imm20 imm.15:0 Reserved 0 0 0 1 0 0 1 1 1 0 1 0 x x x x Reserved 0 0 0 1 0 0 1 1 1 1 x x x x x x PUSHM.A 0 0 0 1 0 1 0 0 n – 1 dst PUSHM.A#n,Rdst PUSHM.W 0 0 0 1 0 1 0 1 n – 1 dst PUSHM.W#n,Rdst POPM.A 0 0 0 1 0 1 1 0 n – 1 dst– n + 1 POPM.A#n,Rdst POPM.W 0 0 0 1 0 1 1 1 n – 1 dst– n + 1 POPM.W#n,Rdst 177SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.2 MSP430 Instructions

The MSP430 instructionsarelistedand describedon thefollowingpages.

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4.6.2.1 ADC

*ADC[.W] Add carrytodestination *ADC.B Add carrytodestination Syntax ADCdstor ADC.Wdst ADC.Bdst Operation dst+ C → dst ADDC#0,dstEmulation ADDC.B#0,dst Description The carrybit(C)isadded tothedestinationoperand.The previouscontentsofthe destinationarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Setifdstwas incrementedfrom0FFFFh to0000,resetotherwise Setifdstwas incrementedfrom0FFh to00,resetotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 16-bitcounterpointedtoby R13 isadded toa 32-bitcounterpointedtoby R12. ADD @R13,0(R12);AddLSDs ADC 2(R12) ;AddcarrytoMSD Example The 8-bitcounterpointedtoby R13 isadded toa 16-bitcounterpointedtoby R12. ADD.B@R13,0(R12);AddLSDs ADC.B1(R12) ;AddcarrytoMSD 179SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.2.2 ADD

ADD[.W] Add sourceword todestinationword ADD.B Add sourcebytetodestinationbyte Syntax ADDsrc,dstor ADD.Wsrc,dst ADD.Bsrc,dst Operation src+ dst→ dst Description The sourceoperandisadded tothedestinationoperand.The previouscontentofthe destinationislost. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Ten isadded tothe16-bitcounterCNTR locatedinlower64 K. ADD.W#10,&CNTR ;Add10to16-bitcounter Example A tableword pointedtoby R5 (20-bitaddressinR5) isadded toR6. The jump tolabel TONI isperformedon a carry. ADD.W@R5,R6 ;AddtablewordtoR6.R6.19:16=0 JC TONI ;Jumpifcarry ... ;Nocarry Example A tablebytepointedtoby R5 (20-bitaddress)isadded toR6. The jump tolabelTONI is performedifno carryoccurs.The tablepointerisauto-incrementedby 1.R6.19:8= 0 ADD.B@R5+,R6;AddbytetoR6.R5+1.R6:000xxh JNC TONI ;Jumpifnocarry ... ;Carryoccurred

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4.6.2.3 ADDC

ADDC[.W] Add sourceword and carrytodestinationword ADDC.B Add sourcebyteand carrytodestinationbyte Syntax ADDCsrc,dstor ADDC.Wsrc,dst ADDC.Bsrc,dst Operation src+ dst+ C → dst Description The sourceoperandand thecarrybitC areadded tothedestinationoperand.The previouscontentofthedestinationislost. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Constantvalue15 and thecarryofthepreviousinstructionareadded tothe16-bit counterCNTR locatedinlower64 K. ADDC.W#15,&CNTR ;Add15+Cto16-bitCNTR Example A tableword pointedtoby R5 (20-bitaddress)and thecarryC areadded toR6. The jump tolabelTONI isperformedon a carry.R6.19:16= 0 ADDC.W@R5,R6 ;Addtableword+CtoR6 JC TONI ;Jumpifcarry ... ;Nocarry Example A tablebytepointedtoby R5 (20-bitaddress)and thecarrybitC areadded toR6. The jump tolabelTONI isperformedifno carryoccurs.The tablepointerisauto-incremented by 1.R6.19:8= 0 ADDC.B@R5+,R6;Addtablebyte+CtoR6.R5+1 JNC TONI ;Jumpifnocarry ... ;Carryoccurred 181SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.2.4 AND

AND[.W] LogicalAND ofsourceword withdestinationword AND.B LogicalAND ofsourcebytewithdestinationbyte Syntax ANDsrc,dstor AND.Wsrc,dst AND.Bsrc,dst Operation src.and.dst→ dst Description The sourceoperandand thedestinationoperandarelogicallyANDed. The resultis placedintothedestination.The sourceoperandisnotaffected. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setiftheresultisnotzero,resetotherwise.C = (.not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The bitssetinR5 (16-bitdata)areused as a mask (AA55h)fortheword TOM locatedin thelower64 K.Iftheresultiszero,a branchistakentolabelTONI. R5.19:16= 0 MOV #AA55h,R5;Load16-bitmasktoR5 AND R5,&TOM ;TOM.and.R5->TOM JZ TONI ;Jumpifresult0 ... ;Result>0 orshorter: AND #AA55h,&TOM;TOM.and.AA55h->TOM JZ TONI ;Jumpifresult0 Example A tablebytepointedtoby R5 (20-bitaddress)islogicallyANDed withR6. R5 is incrementedby 1 afterthefetchingofthebyte.R6.19:8= 0 AND.B@R5+,R6;ANDtablebytewithR6.R5+1

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4.6.2.5 BIC

BIC[.W] Clearbitssetinsourceword indestinationword BIC.B Clearbitssetinsourcebyteindestinationbyte Syntax BICsrc,dstor BIC.Wsrc,dst BIC.Bsrc,dst Operation (.not.src).and.dst→ dst Description The invertedsourceoperandand thedestinationoperandarelogicallyANDed. The resultisplacedintothedestination.The sourceoperandisnotaffected. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The bits15:14ofR5 (16-bitdata)arecleared.R5.19:16= 0 BIC #0C000h,R5;ClearR5.19:14bits Example A tableword pointedtoby R5 (20-bitaddress)isused toclearbitsinR7. R7.19:16= 0 BIC.W@R5,R7 ;ClearbitsinR7setin@R5 Example A tablebytepointedtoby R5 (20-bitaddress)isused toclearbitsinPort1. BIC.B@R5,&P1OUT;ClearI/OportP1bitssetin@R5 183SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.2.6 BIS

BIS[.W] Setbitssetinsourceword indestinationword BIS.B Setbitssetinsourcebyteindestinationbyte Syntax BISsrc,dstor BIS.Wsrc,dst BIS.Bsrc,dst Operation src.or.dst→ dst Description The sourceoperandand thedestinationoperandarelogicallyORed. The resultisplaced intothedestination.The sourceoperandisnotaffected. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Bits15 and 13 ofR5 (16-bitdata)aresettoone.R5.19:16= 0 BIS #A000h,R5;SetR5bits Example A tableword pointedtoby R5 (20-bitaddress)isused tosetbitsinR7. R7.19:16= 0 BIS.W@R5,R7 ;SetbitsinR7 Example A tablebytepointedtoby R5 (20-bitaddress)isused tosetbitsinPort1.R5 is incrementedby 1 afterwards. BIS.B@R5+,&P1OUT;SetI/OportP1bits.R5+1

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4.6.2.7 BIT

BIT[.W] Testbitssetinsourceword indestinationword BIT.B Testbitssetinsourcebyteindestinationbyte Syntax BITsrc,dstor BIT.Wsrc,dst BIT.Bsrc,dst Operation src.and.dst Description The sourceoperandand thedestinationoperandarelogicallyANDed. The resultaffects onlythestatusbitsinSR. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setiftheresultisnotzero,resetotherwise.C = (.not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Testifone (orboth)ofbits15 and 14 ofR5 (16-bitdata)isset.Jump tolabelTONI ifthis isthecase.R5.19:16arenotaffected. BIT #C000h,R5;TestR5.15:14bits JNZ TONI ;AtleastonebitissetinR5 ... ;Bothbitsarereset Example A tableword pointedtoby R5 (20-bitaddress)isused totestbitsinR7. Jump tolabel TONI ifatleastone bitisset.R7.19:16arenotaffected. BIT.W@R5,R7 ;TestbitsinR7 JC TONI ;Atleastonebitisset ... ;Botharereset Example A tablebytepointedtoby R5 (20-bitaddress)isused totestbitsinoutputPort1.Jump tolabelTONI ifno bitisset.The nexttablebyteisaddressed. BIT.B@R5+,&P1OUT;TestI/OportP1bits.R5+1 JNC TONI ;Nocorrespondingbitisset ... ;Atleastonebitisset 185SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.2.8 BR, BRANCH

*BR, Branchtodestinationinlower64K addressspace BRANCH BRdstSyntax Operation dst→ PC MOVdst,PCEmulation Description An unconditionalbranchistakentoan addressanywhere inthelower64K address space.Allsourceaddressingmodes can be used.The branchinstructionisa word instruction. StatusBits Statusbitsarenotaffected. Example Examples foralladdressingmodes aregiven. BR #EXEC;BranchtolabelEXECordirectbranch(forexample#0A4h) ;CoreinstructionMOV@PC+,PC BR EXEC ;BranchtotheaddresscontainedinEXEC ;CoreinstructionMOVX(PC),PC ;Indirectaddress BR &EXEC;Branchtotheaddresscontainedinabsolute ;addressEXEC ;CoreinstructionMOVX(0),PC ;Indirectaddress BR R5 ;BranchtotheaddresscontainedinR5 ;CoreinstructionMOVR5,PC ;IndirectR5 BR @R5 ;Branchtotheaddresscontainedintheword ;pointedtobyR5. ;CoreinstructionMOV@R5,PC ;Indirect,indirectR5 BR @R5+ ;Branchtotheaddresscontainedinthewordpointed ;tobyR5andincrementpointerinR5afterwards. ;Thenexttime-S/WflowusesR5pointer-itcan ;alterprogramexecutionduetoaccessto ;nextaddressinatablepointedtobyR5 ;CoreinstructionMOV@R5,PC ;Indirect,indirectR5withautoincrement BR X(R5);Branchtotheaddresscontainedintheaddress ;pointedtobyR5+X(forexampletablewithaddress ;startingatX).Xcanbeanaddressoralabel ;CoreinstructionMOVX(R5),PC ;Indirect,indirectR5+X

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4.6.2.9 CALL

CALL Calla subroutineinlower64 K CALLdstSyntax Operation dst→ tmp 16-bitdstisevaluatedand stored SP – 2 → SP PC → @SP updatedPC withreturnaddresstoTOS tmp → PC saved 16-bitdsttoPC Description A subroutinecallismade froman addressinthelower64 K toa subroutineaddressin thelower64 K.Allseven sourceaddressingmodes can be used.The callinstructionisa word instruction.The returnismade withtheRET instruction. StatusBits Statusbitsarenotaffected. PC.19:16cleared(addressinlower64 K) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Examples Examples foralladdressingmodes aregiven. ImmediateMode: Calla subroutineatlabelEXEC (lower64 K) orcalldirectlytoaddress. CALL#EXEC ;StartaddressEXEC CALL#0AA04h ;Startaddress0AA04h SymbolicMode: Calla subroutineatthe16-bitaddresscontainedinaddressEXEC. EXEC islocatedattheaddress(PC + X) where X iswithinPC ± 32 K. CALLEXEC ;Startaddressat@EXEC.z16(PC) AbsoluteMode: Calla subroutineatthe16-bitaddresscontainedinabsoluteaddress EXEC inthelower64 K. CALL&EXEC ;Startaddressat@EXEC Registermode: Calla subroutineatthe16-bitaddresscontainedinregisterR5.15:0. CALLR5 ;StartaddressatR5 IndirectMode: Calla subroutineatthe16-bitaddresscontainedintheword pointedtoby registerR5 (20-bitaddress). CALL@R5 ;Startaddressat@R5 187SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.10CLR *CLR[.W] Cleardestination *CLR.B Cleardestination Syntax CLRdstor CLR.Wdst CLR.Bdst Operation 0 → dst MOV#0,dstEmulation MOV.B#0,dst Description The destinationoperandiscleared. StatusBits Statusbitsarenotaffected. Example RAM word TONI iscleared. CLR TONI ;0->TONI Example RegisterR5 iscleared. CLR R5 Example RAM byteTONI iscleared. CLR.BTONI ;0->TONI

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.11CLRC *CLRC Clearcarrybit CLRCSyntax Operation 0 → C BIC#1,SREmulation Description The carrybit(C)iscleared.The clearcarryinstructionisa word instruction. StatusBits N: Not affected Z: Not affected C: Cleared V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 16-bitdecimalcounterpointedtoby R13 isadded toa 32-bitcounterpointedtoby R12. CLRC ;C=0:definesstart DADD@R13,0(R12);add16-bitcountertolowwordof32-bitcounter DADC2(R12) ;addcarrytohighwordof32-bitcounter 189SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.12CLRN *CLRN Clearnegativebit CLRNSyntax Operation 0 → N or (.NOT.src.AND. dst→ dst) BIC#4,SREmulation Description The constant04h isinverted(0FFFBh)and islogicallyANDed withthedestination operand.The resultisplacedintothedestination.The clearnegativebitinstructionisa word instruction. StatusBits N: Resetto0 Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The negativebitintheSR iscleared.Thisavoidsspecialtreatmentwithnegative numbers ofthesubroutinecalled. CLRN CALLSUBR SUBR JN SUBRET;Ifinputisnegative:donothingandreturn SUBRETRET

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.13CLRZ *CLRZ Clearzerobit CLRZSyntax Operation 0 → Z or (.NOT.src.AND. dst→ dst) BIC#2,SREmulation Description The constant02h isinverted(0FFFDh) and logicallyANDed withthedestination operand.The resultisplacedintothedestination.The clearzerobitinstructionisa word instruction. StatusBits N: Not affected Z: Resetto0 C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The zerobitintheSR iscleared. CLRZ Indirect,Auto-Incrementmode: Calla subroutineatthe16-bitaddresscontainedinthe word pointedtoby registerR5 (20-bitaddress)and incrementthe16-bitaddressinR5 afterwardsby 2.The nexttimethesoftwareuses R5 as a pointer,itcan alterthe programexecutiondue toaccesstothenextword addressinthetablepointedtoby R5. CALL@R5+ ;Startaddressat@R5.R5+2 Indexedmode: Calla subroutineatthe16-bitaddresscontainedinthe20-bitaddress pointedtoby register(R5 + X);forexample,a tablewithaddressesstartingatX.The addressiswithinthelower64 KB. X iswithin±32 KB. CALLX(R5) ;Startaddressat@(R5+X).z16(R5) 191SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.14CMP CMP[.W] Compare sourceword and destinationword CMP.B Compare sourcebyteand destinationbyte Syntax CMPsrc,dstor CMP.Wsrc,dst CMP.Bsrc,dst Operation (.not.src)+ 1 + dst or dst– src BIC#2,SREmulation Description The sourceoperandissubtractedfromthedestinationoperand.Thisismade by adding the1s complement ofthesource+ 1 tothedestination.The resultaffectsonlythestatus bitsinSR. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src= dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow). Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Compare word EDE witha 16-bitconstant1800h.Jump tolabelTONI ifEDE equalsthe constant.The addressofEDE iswithinPC + 32 K. CMP #01800h,EDE;ComparewordEDEwith1800h JEQ TONI ;EDEcontains1800h ... ;Notequal Example A tableword pointedtoby (R5 + 10)iscompared withR7. Jump tolabelTONI ifR7 containsa lower,signed16-bitnumber.R7.19:16isnotcleared.The addressofthe sourceoperandisa 20-bitaddressinfullmemory range. CMP.W10(R5),R7;Comparetwosignednumbers JL TONI ;R7<10(R5) ... ;R7>=10(R5) Example A tablebytepointedtoby R5 (20-bitaddress)iscompared tothevalueinoutputPort1. Jump tolabelTONI ifvaluesareequal.The nexttablebyteisaddressed. CMP.B@R5+,&P1OUT ;CompareP1bitswithtable.R5+1 JEQ TONI ;Equalcontents ... ;Notequal

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.15DADC *DADC[.W] Add carrydecimallytodestination *DADC.B Add carrydecimallytodestination Syntax DADCdstor DADC.Wdst DADC.Bdst Operation dst+ C → dst(decimally) DADD#0,dstEmulation DADD.B#0,dst Description The carrybit(C)isadded decimallytothedestination. StatusBits N: SetifMSB is1 Z: Setifdstis0,resetotherwise C: Setifdestinationincrementsfrom9999 to0000,resetotherwise Setifdestinationincrementsfrom99 to00,resetotherwise V: Undefined Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The four-digitdecimalnumber containedinR5 isadded toan eight-digitdecimalnumber pointedtoby R8. CLRC ;Resetcarry ;nextinstruction'sstartconditionisdefined DADDR5,0(R8);AddLSDs+C DADC2(R8) ;AddcarrytoMSD Example The two-digitdecimalnumber containedinR5 isadded toa four-digitdecimalnumber pointedtoby R8. CLRC ;Resetcarry ;nextinstruction'sstartconditionisdefined DADD.BR5,0(R8);AddLSDs+C DADC 1(R8) ;AddcarrytoMSDs 193SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.16DADD *DADD[.W] Add sourceword and carrydecimallytodestinationword *DADD.B Add sourcebyteand carrydecimallytodestinationbyte Syntax DADDsrc,dstor DADD.Wsrc,dst DADD.Bsrc,dst Operation src+ dst+ C → dst(decimally) Description The sourceoperandand thedestinationoperandaretreatedas two (.B)orfour(.W) binarycoded decimals(BCD) withpositivesigns.The sourceoperandand thecarrybitC areadded decimallytothedestinationoperand.The sourceoperandisnotaffected.The previouscontentofthedestinationislost.The resultisnotdefinedfornon-BCD numbers. StatusBits N: SetifMSB ofresultis1 (word> 7999h,byte> 79h),resetifMSB is0 Z: Setifresultiszero,resetotherwise C: SetiftheBCD resultistoolarge(word> 9999h,byte> 99h),resetotherwise V: Undefined Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Decimal10 isadded tothe16-bitBCD counterDECCNTR. DADD#10h,&DECCNTR;Add10to4-digitBCDcounter Example The eight-digitBCD number containedin16-bitRAM addressesBCD and BCD+2 is added decimallytoan eight-digitBCD number containedinR4 and R5 (BCD+2 and R5 containtheMSDs). The carryC isadded,and cleared. CLRC ;Clearcarry DADD.W&BCD,R4 ;AddLSDs.R4.19:16=0 DADD.W&BCD+2,R5;AddMSDswithcarry.R5.19:16=0 JC OVERFLOW;Result>9999,9999:gotoerrorroutine ... ;Resultok Example The two-digitBCD number containedinword BCD (16-bitaddress)isadded decimallyto a two-digitBCD number containedinR4. The carryC isadded,also.R4.19:8= 0 CLRC ;Clearcarry DADD.B&BCD,R4 ;AddBCDtoR4decimally. R4:0,00ddh

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.17DEC *DEC[.W] Decrement destination *DEC.B Decrement destination Syntax DECdstor DEC.Wdst DEC.Bdst Operation dst– 1 → dst SUB#1,dstEmulation SUB.B#1,dst Description The destinationoperandisdecrementedby one.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained1,resetotherwise C: Resetifdstcontained0,setotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset. Setifinitialvalueofdestinationwas 08000h,otherwisereset. Setifinitialvalueofdestinationwas 080h,otherwisereset. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R10 isdecrementedby 1. DEC R10 ;DecrementR10 ;Moveablockof255bytesfrommemorylocationstartingwithEDEto ;memorylocationstartingwithTONI.Tablesshouldnotoverlap:startof ;destinationaddressTONImustnotbewithintherangeEDEtoEDE+0FEh MOV #EDE,R6 MOV #255,R10 L$1 MOV.B@R6+,TONI-EDE-1(R6) DEC R10 JNZ L$1 Do nottransfertablesusingtheroutineabove withtheoverlapshown inFigure4-36. Figure4-36.Decrement Overlap 195SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.18DECD *DECD[.W] Double-decrementdestination *DECD.B Double-decrementdestination Syntax DECDdstor DECD.Wdst DECD.Bdst Operation dst– 2 → dst SUB#2,dstEmulation SUB.B#2,dst Description The destinationoperandisdecrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained2,resetotherwise C: Resetifdstcontained0 or1,setotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset Setifinitialvalueofdestinationwas 08001 or08000h,otherwisereset Setifinitialvalueofdestinationwas 081 or080h,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R10 isdecrementedby 2. DECD R10 ;DecrementR10bytwo ;Moveablockof255bytesfrommemorylocationstartingwithEDEto ;memorylocationstartingwithTONI. ;Tablesshouldnotoverlap:startofdestinationaddressTONImustnot ;bewithintherangeEDEtoEDE+0FEh MOV #EDE,R6 MOV #255,R10 L$1 MOV.B@R6+,TONI-EDE-2(R6) DECD R10 JNZ L$1 Example Memory atlocationLEO isdecrementedby two. DECD.BLEO ;DecrementMEM(LEO) Decrement statusbyteSTATUS by two DECD.BSTATUS

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.19DINT *DINT Disable(general)interrupts DINTSyntax Operation 0 → GIE or BIC#8,SREmulation Description Allinterruptsaredisabled. The constant08h isinvertedand logicallyANDed withtheSR. The resultisplacedinto theSR. StatusBits Statusbitsarenotaffected. Mode Bits GIE isreset.OSCOFF and CPUOFF arenotaffected. Example The generalinterruptenable(GIE)bitintheSR isclearedtoallowa nondisruptedmove ofa 32-bitcounter.Thisensuresthatthecounterisnotmodifiedduringthemove by any interrupt. DINT ;AllinterrupteventsusingtheGIEbitaredisabled NOP MOV COUNTHI,R5;Copycounter MOV COUNTLO,R6 EINT ;AllinterrupteventsusingtheGIEbitareenabled NOTE: Disableinterrupt Ifany code sequence needs tobe protectedfrominterruption,DINT shouldbe executedat leastone instructionbeforethebeginningoftheuninterruptiblesequence,oritshouldbe followedby a NOP instruction. NOTE: Enable and DisableInterrupt Due tothepipelinedCPU architecture,theinstructionfollowingtheenableinterrupt instruction(EINT)isalwaysexecuted,even ifan interruptservicerequestispendingwhen theinterruptsareenabled. Iftheenableinterruptinstruction(EINT)isimmediatelyfollowedby a disableinterrupt instruction(DINT),a pendinginterruptmightnotbe serviced.FurtherinstructionsafterDINT mightexecuteincorrectlyand resultinunexpectedCPU execution.Itisrecommended to alwaysinsertatleastone instructionbetween EINT and DINT.Note thatany alternative instructionuse thatsetsand immediatelyclearstheCPU statusregisterGIE bitmust be consideredinthesame fashion. 197SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.20EINT *EINT Enable(general)interrupts EINTSyntax Operation 1 → GIE or BIS#8,SREmulation Description Allinterruptsareenabled. The constant#08h and theSR arelogicallyORed. The resultisplacedintotheSR. StatusBits Statusbitsarenotaffected. Mode Bits GIE isset.OSCOFF and CPUOFF arenotaffected. Example The generalinterruptenable(GIE)bitintheSR isset. PUSH.B&P1IN BIC.B@SP,&P1IFG;Resetonlyacceptedflags EINT ;Presetport1interruptflagsstoredonstack ;otherinterruptsareallowed BIT#Mask,@SP JEQMaskOK ;Flagsarepresentidenticallytomask:jump MaskOKBIC#Mask,@SP INCDSP ;Housekeeping:inversetoPUSHinstruction ;atthestartofinterruptsubroutine.Corrects ;thestackpointer. RETI NOTE: Enable and DisableInterrupt Due tothepipelinedCPU architecture,theinstructionfollowingtheenableinterrupt instruction(EINT)isalwaysexecuted,even ifan interruptservicerequestispendingwhen theinterruptsareenabled. Iftheenableinterruptinstruction(EINT)isimmediatelyfollowedby a disableinterrupt instruction(DINT),a pendinginterruptmightnotbe serviced.FurtherinstructionsafterDINT mightexecuteincorrectlyand resultinunexpectedCPU execution.Itisrecommended to alwaysinsertatleastone instructionbetween EINT and DINT.Note thatany alternative instructionuse thatsetsand immediatelyclearstheCPU statusregisterGIE bitmust be consideredinthesame fashion.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.21INC *INC[.W] Incrementdestination *INC.B Incrementdestination Syntax INCdstor INC.Wdst INC.Bdst Operation dst+ 1 → dst ADD#1,dstEmulation Description The destinationoperandisincrementedby one.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise C: Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise V: Setifdstcontained07FFFh, resetotherwise Setifdstcontained07Fh,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The statusbyte,STATUS, ofa processisincremented.When itisequalto11,a branch toOVFL istaken. INC.BSTATUS CMP.B#11,STATUS JEQ OVFL 199SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.22INCD *INCD[.W] Double-incrementdestination *INCD.B Double-incrementdestination Syntax INCDdstor INCD.Wdst INCD.Bdst Operation dst+ 2 → dst ADD#2,dstEmulation Description The destinationoperandisincrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFEh, resetotherwise Setifdstcontained0FEh, resetotherwise C: Setifdstcontained0FFFEh or0FFFFh, resetotherwise Setifdstcontained0FEh or0FFh,resetotherwise V: Setifdstcontained07FFEh or07FFFh, resetotherwise Setifdstcontained07Eh or07Fh,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The itemon thetopofthestack(TOS) isremoved withoutusinga register. PUSHR5 ;R5istheresultofacalculation,whichisstored ;inthesystemstack INCDSP ;RemoveTOSbydouble-incrementfromstack ;DonotuseINCD.B,SPisaword-alignedregister RET Example The byteon thetopofthestackisincrementedby two. INCD.B0(SP);ByteonTOSisincrementbytwo

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.23INV *INV[.W] Invertdestination *INV.B Invertdestination Syntax INVdstor INV.Wdst INV.Bdst Operation .not.dst→ dst XOR#0FFFFh,dstEmulation XOR.B#0FFh,dst Description The destinationoperandisinverted.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise C: Setifresultisnotzero,resetotherwise(= .NOT. Zero) V: Setifinitialdestinationoperandwas negative,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example ContentofR5 isnegated(2scomplement). MOV #00AEh,R5; R5=000AEh INV R5 ;InvertR5, R5=0FF51h INC R5 ;R5isnownegated,R5=0FF52h Example Contentofmemory byteLEO isnegated. MOV.B#0AEh,LEO; MEM(LEO)=0AEh INV.BLEO ;InvertLEO, MEM(LEO)=051h INC.BLEO ;MEM(LEO)isnegated,MEM(LEO)=052h 201SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.24JC, JHS JC Jump ifcarry JHS Jump ifhigherorsame (unsigned) JClabelSyntax JHSlabel Operation IfC = 1:PC + (2× Offset)→ PC IfC = 0:executethefollowinginstruction Description The carrybitC intheSR istested.Ifitisset,thesigned10-bitword offsetcontainedin theinstructionismultipliedby two,signextended,and added tothe20-bitPC. This means a jump intherange–511 to+512 words relativetothePC inthefullmemory range.IfC isreset,theinstructionafterthejump isexecuted. JC isused forthetestofthecarrybitC. JHS isused forthecomparisonofunsignednumbers. StatusBits Statusbitsarenotaffected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The stateoftheport1 pinP1IN.1bitdefinestheprogramflow. BIT.B#2,&P1IN ;Port1,bit1set?Bit->C JC Label1 ;Yes,proceedatLabel1 ... ;No,continue Example IfR5 ≥ R6 (unsigned),theprogramcontinuesatLabel2. CMP R6,R5 ;IsR5>=R6?InfotoC JHS Label2 ;Yes,C=1 ... ;No,R5<R6.Continue Example IfR5 ≥ 12345h (unsignedoperands),theprogramcontinuesatLabel2. CMPA#12345h,R5;IsR5>=12345h?InfotoC JHS Label2 ;Yes,12344h<R5<=F,FFFFh.C=1 ... ;No,R5<12345h.Continue

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.25JEQ, JZ JEQ Jump ifequal JZ Jump ifzero JEQlabelSyntax JZlabel Operation IfZ = 1:PC + (2× Offset)→ PC IfZ = 0:executefollowinginstruction Description The zerobitZ intheSR istested.Ifitisset,thesigned10-bitword offsetcontainedin theinstructionismultipliedby two,signextended,and added tothe20-bitPC. This means a jump intherange–511 to+512 words relativetothePC inthefullmemory range.IfZ isreset,theinstructionafterthejump isexecuted. JZ isused forthetestofthezerobitZ. JEQ isused forthecomparisonofoperands. StatusBits Statusbitsarenotaffected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The stateoftheP2IN.0bitdefinestheprogramflow. BIT.B#1,&P2IN ;Port2,bit0reset? JZ Label1 ;Yes,proceedatLabel1 ... ;No,set,continue Example IfR5 = 15000h (20-bitdata),theprogramcontinuesatLabel2. CMPA#15000h,R5;IsR5=15000h?InfotoSR JEQ Label2 ;Yes,R5=15000h.Z=1 ... ;No,R5notequal15000h.Continue Example R7 (20-bitcounter)isincremented.Ifitscontentiszero,theprogramcontinuesat Label4. ADDA#1,R7 ;IncrementR7 JZ Label4 ;Zeroreached:GotoLabel4 203SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.26JGE JGE Jump ifgreaterorequal(signed) JGElabelSyntax Operation If(N .xor.V) = 0:PC + (2× Offset)→ PC If(N .xor.V) = 1:executefollowinginstruction Description The negativebitN and theoverflowbitV intheSR aretested.Ifbothbitsaresetorboth arereset,thesigned10-bitword offsetcontainedintheinstructionismultipliedby two, signextended,and added tothe20-bitPC. Thismeans a jump intherange-511to+512 words relativetothePC infullMemory range.Ifonlyone bitisset,theinstructionafter thejump isexecuted. JGE isused forthecomparisonofsignedoperands:alsoforincorrectresultsdue to overflow,thedecisionmade by theJGE instructioniscorrect. Note thatJGE emulatesthenonimplementedJP (jumpifpositive)instructionifused after theinstructionsAND, BIT,RRA, SXTX, and TST. These instructionscleartheV bit. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example IfbyteEDE (lower64 K) containspositivedata,go toLabel1.Softwarecan runinthefull memory range. TST.B&EDE ;IsEDEpositive?V<-0 JGE Label1 ;Yes,JGEemulatesJP ... ;No,80h<=EDE<=FFh Example IfthecontentofR6 isgreaterthanorequaltothememory pointedtoby R7, theprogram continuesa Label5.Signeddata.Data and programinfullmemory range. CMP @R7,R6 ;IsR6>=@R7? JGE Label5 ;Yes,gotoLabel5 ... ;No,continuehere Example IfR5 ≥ 12345h (signedoperands),theprogramcontinuesatLabel2.Program infull memory range. CMPA#12345h,R5;IsR5>=12345h? JGE Label2 ;Yes,12344h<R5<=7FFFFh

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.27JL JL Jump ifless(signed) JLlabelSyntax Operation If(N .xor.V) = 1:PC + (2× Offset)→ PC If(N .xor.V) = 0:executefollowinginstruction Description The negativebitN and theoverflowbitV intheSR aretested.Ifonlyone isset,the signed10-bitword offsetcontainedintheinstructionismultipliedby two,signextended, and added tothe20-bitPC. Thismeans a jump intherange–511 to+512 words relative tothePC infullmemory range.IfbothbitsN and V aresetorbotharereset,the instructionafterthejump isexecuted. JL isused forthecomparisonofsignedoperands:alsoforincorrectresultsdue to overflow,thedecisionmade by theJL instructioniscorrect. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example IfbyteEDE containsa smaller,signedoperandthanbyteTONI, continueatLabel1.The addressEDE iswithinPC ± 32 K. CMP.B&TONI,EDE;IsEDE<TONI JL Label1 ;Yes ... ;No,TONI<=EDE Example IfthesignedcontentofR6 islessthanthememory pointedtoby R7 (20-bitaddress),the programcontinuesatLabel5.Data and programinfullmemory range. CMP @R7,R6 ;IsR6<@R7? JL Label5 ;Yes,gotoLabel5 ... ;No,continuehere Example IfR5 < 12345h (signedoperands),theprogramcontinuesatLabel2.Data and program infullmemory range. CMPA#12345h,R5;IsR5<12345h? JL Label2 ;Yes,80000h=<R5<12345h ... ;No,12344h<R5<=7FFFFh 205SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.28JMP JMP Jump unconditionally JMPlabelSyntax Operation PC + (2× Offset)→ PC Description The signed10-bitword offsetcontainedintheinstructionismultipliedby two,sign extended,and added tothe20-bitPC. Thismeans an unconditionaljump intherange –511 to+512 words relativetothePC inthefullmemory. The JMP instructionmay be used as a BR orBRA instructionwithinitslimitedrangerelativetothePC. StatusBits Statusbitsarenotaffected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The byteSTATUS issetto10.Then a jump tolabelMAINLOOP ismade. Data inlower 64 K,programinfullmemory range. MOV.B#10,&STATUS;SetSTATUSto10 JMP MAINLOOP;Gotomainloop Example The interruptvectorTAIV ofTimer_A3 isreadand used fortheprogramflow.Program in fullmemory range,butinterrupthandlersalwaysstartsinlower64 K. ADD &TAIV,PC;AddTimer_AinterruptvectortoPC RETI ;NoTimer_Ainterruptpending JMP IHCCR1 ;Timerblock1causedinterrupt JMP IHCCR2 ;Timerblock2causedinterrupt RETI ;Nolegalinterrupt,return

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.29JN JN Jump ifnegative JNlabelSyntax Operation IfN = 1:PC + (2× Offset)→ PC IfN = 0:executefollowinginstruction Description The negativebitN intheSR istested.Ifitisset,thesigned10-bitword offsetcontained intheinstructionismultipliedby two,signextended,and added tothe20-bitprogram PC. Thismeans a jump intherange-511to+512 words relativetothePC inthefull memory range.IfN isreset,theinstructionafterthejump isexecuted. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The byteCOUNT istested.Ifitisnegative,programexecutioncontinuesatLabel0.Data inlower64 K,programinfullmemory range. TST.B&COUNT;IsbyteCOUNTnegative? JN Label0;Yes,proceedatLabel0 ... ;COUNT>=0 Example R6 issubtractedfromR5. Iftheresultisnegative,programcontinuesatLabel2.Program infullmemory range. SUB R6,R5 ;R5-R6->R5 JN Label2;R5isnegative:R6>R5(N=1) Example R7 (20-bitcounter)isdecremented.Ifitscontentisbelowzero,theprogramcontinuesat Label4.Program infullmemory range. SUBA#1,R7 ;DecrementR7 JN Label4;R7<0:GotoLabel4 207SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.30JNC, JLO JNC Jump ifno carry JLO Jump iflower(unsigned) JNClabelSyntax JLOlabel Operation IfC = 0:PC + (2× Offset)→ PC IfC = 1:executefollowinginstruction Description The carrybitC intheSR istested.Ifitisreset,thesigned10-bitword offsetcontainedin theinstructionismultipliedby two,signextended,and added tothe20-bitPC. This means a jump intherange–511 to+512 words relativetothePC inthefullmemory range.IfC isset,theinstructionafterthejump isexecuted. JNC isused forthetestofthecarrybitC. JLO isused forthecomparisonofunsignednumbers. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example IfbyteEDE < 15,theprogramcontinuesatLabel2.Unsigneddata.Data inlower64 K, programinfullmemory range. CMP.B#15,&EDE ;IsEDE<15?InfotoC JLO Label2 ;Yes,EDE<15.C=0 ... ;No,EDE>=15.Continue Example The word TONI isadded toR5. Ifno carryoccurs,continueatLabel0.The addressof TONI iswithinPC ± 32 K. ADD TONI,R5;TONI+R5->R5.Carry->C JNC Label0 ;Nocarry ... ;Carry=1:continuehere

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.31JNZ, JNE JNZ Jump ifnotzero JNE Jump ifnotequal JNZlabelSyntax JNElabel Operation IfZ = 0:PC + (2× Offset)→ PC IfZ = 1:executefollowinginstruction Description The zerobitZ intheSR istested.Ifitisreset,thesigned10-bitword offsetcontainedin theinstructionismultipliedby two,signextended,and added tothe20-bitPC. This means a jump intherange–511 to+512 words relativetothePC inthefullmemory range.IfZ isset,theinstructionafterthejump isexecuted. JNZ isused forthetestofthezerobitZ. JNE isused forthecomparisonofoperands. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The byteSTATUS istested.Ifitisnotzero,theprogramcontinuesatLabel3.The addressofSTATUS iswithinPC ± 32 K. TST.BSTATUS ;IsSTATUS=0? JNZ Label3 ;No,proceedatLabel3 ... ;Yes,continuehere Example Ifword EDE ≠ 1500,theprogramcontinuesatLabel2.Data inlower64 K,programinfull memory range. CMP #1500,&EDE ;IsEDE=1500?InfotoSR JNE Label2 ;No,EDEnotequal1500. ... ;Yes,R5=1500.Continue Example R7 (20-bitcounter)isdecremented.Ifitscontentisnotzero,theprogramcontinuesat Label4.Program infullmemory range. SUBA #1,R7 ;DecrementR7 JNZ Label4 ;Zeronotreached:GotoLabel4 209SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.32MOV MOV[.W] Move sourceword todestinationword MOV.B Move sourcebytetodestinationbyte Syntax MOVsrc,dstor MOV.Wsrc,dst MOV.Bsrc,dst Operation src→ dst Description The sourceoperandiscopiedtothedestination.The sourceoperandisnotaffected. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Move a 16-bitconstant1800h toabsoluteaddress-wordEDE (lower64 K) MOV #01800h,&EDE ;Move1800htoEDE Example The contentsoftableEDE (worddata,16-bitaddresses)arecopiedtotableTOM. The lengthofthetablesis030h words.Bothtablesresideinthelower64 K. MOV #EDE,R10 ;Preparepointer(16-bitaddress) LoopMOV @R10+,TOM-EDE-2(R10);R10pointstobothtables. ;R10+2 CMP #EDE+60h,R10;Endoftablereached? JLO Loop ;Notyet ... ;Copycompleted Example The contentsoftableEDE (bytedata,16-bitaddresses)arecopiedtotableTOM. The lengthofthetablesis020h bytes.Bothtablesmay resideinfullmemory range,butmust be withinR10 ± 32 K. MOVA#EDE,R10 ;Preparepointer(20-bit) MOV #20h,R9 ;Preparecounter LoopMOV.B@R10+,TOM-EDE-1(R10);R10pointstobothtables. ;R10+1 DEC R9 ;Decrementcounter JNZ Loop ;Notyetdone ... ;Copycompleted

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.33NOP *NOP No operation NOPSyntax Operation None MOV#0,R3Emulation Description No operationisperformed.The instructionmay be used fortheeliminationofinstructions duringthesoftwarecheckorfordefinedwaitingtimes. StatusBits Statusbitsarenotaffected. 211SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.34POP *POP[.W] Pop word fromstacktodestination *POP.B Pop bytefromstacktodestination POPdstSyntax POP.Bdst Operation @SP → temp SP + 2 → SP temp → dst Emulation MOV@SP+,dstor MOV.W@SP+,dst MOV.B@SP+,dst Description The stacklocationpointedtoby theSP (TOS) ismoved tothedestination.The SP is incrementedby two afterwards. StatusBits Statusbitsarenotaffected. Example The contentsofR7 and theSR arerestoredfromthestack. POP R7 ;RestoreR7 POP SR ;Restorestatusregister Example The contentsofRAM byteLEO isrestoredfromthestack. POP.BLEO ;ThelowbyteofthestackismovedtoLEO. Example The contentsofR7 isrestoredfromthestack. POP.BR7 ;ThelowbyteofthestackismovedtoR7, ;thehighbyteofR7is00h Example The contentsofthememory pointedtoby R7 and theSR arerestoredfromthestack. POP.B0(R7);Thelowbyteofthestackismovedtothe ;thebytewhichispointedtobyR7 :Example:R7=203h ; Mem(R7)=lowbyteofsystemstack :Example:R7=20Ah ; Mem(R7)=lowbyteofsystemstack POP SR ;LastwordonstackmovedtotheSR NOTE: System stackpointer The systemSP isalwaysincrementedby two,independentofthebytesuffix.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.35PUSH PUSH[.W] Save a word on thestack PUSH.B Save a byteon thestack Syntax PUSHdstor PUSH.Wdst PUSH.Bdst Operation SP – 2 → SP dst→ @SP Description The 20-bitSP SP isdecrementedby two.The operandisthencopiedtotheRAM word addressedby theSP. A pushed byteisstoredinthelowbyte;thehighbyteisnot affected. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Save thetwo 16-bitregistersR9 and R10 on thestack PUSH R9 ;SaveR9andR10XXXXh PUSH R10 ;YYYYh Example Save thetwo bytesEDE and TONI on thestack.The addressesEDE and TONI are withinPC ± 32 K. PUSH.BEDE ;SaveEDExxXXh PUSH.BTONI ;SaveTONIxxYYh 213SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.36RET *RET Returnfromsubroutine RETSyntax Operation @SP →PC.15:0 Saved PC toPC.15:0. PC.19:16← 0 SP + 2 → SP Description The 16-bitreturnaddress(lower64 K),pushed ontothestackby a CALL instructionis restoredtothePC. The programcontinuesattheaddressfollowingthesubroutinecall. The fourMSBs ofthePC.19:16arecleared. StatusBits Statusbitsarenotaffected. PC.19:16:Cleared Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Calla subroutineSUBR inthelower64 K and returntotheaddressinthelower64 K aftertheCALL. CALL#SUBR;CallsubroutinestartingatSUBR ... ;ReturnbyRETtohere SUBRPUSHR14 ;SaveR14(16bitdata) ... ;Subroutinecode POP R14 ;RestoreR14 RET ;Returntolower64K Figure4-37.Stack Aftera RET Instruction

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.37RETI RETI Returnfrominterrupt RETISyntax Operation @SP → SR.15:0 Restoresaved SR withPC.19:16 SP + 2 → SP @SP → PC.15:0 Restoresaved PC.15:0 SP + 2 → SP Housekeeping Description The SR isrestoredtothevalueatthebeginningoftheinterruptserviceroutine.This includesthefourMSBs ofthePC.19:16.The SP isincrementedby two afterward. The 20-bitPC isrestoredfromPC.19:16(fromsame stacklocationas thestatusbits) and PC.15:0.The 20-bitPC isrestoredtothevalueatthebeginningoftheinterrupt serviceroutine.The programcontinuesattheaddressfollowingthelastexecuted instructionwhen theinterruptwas granted.The SP isincrementedby two afterward. StatusBits N: Restoredfromstack C: Restoredfromstack Z: Restoredfromstack V: Restoredfromstack Mode Bits OSCOFF, CPUOFF, and GIE arerestoredfromstack. Example Interrupthandlerinthelower64 K.A 20-bitreturnaddressisstoredon thestack. INTRPTPUSHM.A#2,R14;SaveR14andR13(20-bitdata) ... ;Interrupthandlercode POPM.A#2,R14;RestoreR13andR14(20-bitdata) RETI ;Returnto20-bitaddressinfullmemoryrange 215SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C Byte Word ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.38RLA *RLA[.W] Rotateleftarithmetically *RLA.B Rotateleftarithmetically Syntax RLAdstor RLA.Wdst RLA.Bdst Operation C ← MSB ← MSB-1 ....LSB+1 ← LSB ← 0 ADDdst,dstEmulation ADD.Bdst,dst Description The destinationoperandisshiftedleftone positionas shown inFigure4-38.The MSB is shiftedintothecarrybit(C)and theLSB isfilledwith0.The RLA instructionactsas a signedmultiplicationby 2. An overflowoccursifdst≥ 04000h and dst< 0C000h beforeoperationisperformed;the resulthas changed sign. Figure4-38.DestinationOperand — ArithmeticShiftLeft An overflowoccursifdst≥ 040h and dst< 0C0h beforetheoperationisperformed;the resulthas changed sign. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Loaded fromtheMSB V: Setifan arithmeticoverflowoccurs;theinitialvalueis04000h ≤ dst< 0C000h, resetotherwise Setifan arithmeticoverflowoccurs;theinitialvalueis040h ≤ dst< 0C0h, reset otherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R7 ismultipliedby 2. RLA R7 ;ShiftleftR7(x2) Example The lowbyteofR7 ismultipliedby 4. RLA.BR7 ;ShiftleftlowbyteofR7(x2) RLA.BR7 ;ShiftleftlowbyteofR7(x4) NOTE: RLA substitution The assemblerdoes notrecognizetheinstructions: RLA@R5+ RLA.B@R5+ RLA(.B)@R5 They must be substitutedby: ADD@R5+,-2(R5)ADD.B@R5+,-1(R5)ADD(.B)@R5

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C Byte Word ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.39RLC *RLC[.W] Rotateleftthroughcarry *RLC.B Rotateleftthroughcarry Syntax RLCdstor RLC.Wdst RLC.Bdst Operation C ← MSB ← MSB-1 ....LSB+1 ← LSB ← C ADDCdst,dstEmulation Description The destinationoperandisshiftedleftone positionas shown inFigure4-39.The carrybit (C)isshiftedintotheLSB, and theMSB isshiftedintothecarrybit(C). Figure4-39.DestinationOperand — CarryLeftShift StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Loaded fromtheMSB V: Setifan arithmeticoverflowoccurs;theinitialvalueis04000h ≤ dst< 0C000h, resetotherwise Setifan arithmeticoverflowoccurs;theinitialvalueis040h ≤ dst< 0C0h, reset otherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R5 isshiftedleftone position. RLC R5 ;(R5x2)+C->R5 Example The inputP1IN.1informationisshiftedintotheLSB ofR5. BIT.B#2,&P1IN ;Information->Carry RLC R5 ;Carry=P0in.1->LSBofR5 Example The MEM(LEO) contentisshiftedleftone position. RLC.BLEO ;Mem(LEO)x2+C->Mem(LEO) NOTE: RLA substitution The assemblerdoes notrecognizetheinstructions: RLC@R5+ RLC.B@R5+ RLC(.B)@R5 They must be substitutedby: ADDC@R5+,-2(R5)ADDC.B@R5+,-1(R5)ADDC(.B)@R5 217SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C 19 0 MSB0 0 0 0 0 0 0 715 0 0 0 0 0 LSB C 19 0 MSB0 0 0 0 LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.40RRA RRA[.W] Rotaterightarithmeticallydestinationword RRA.B Rotaterightarithmeticallydestinationbyte Syntax RRA.Bdstor RRA.Wdst Operation MSB → MSB → MSB –1 → ...LSB+1 → LSB → C Description The destinationoperandisshiftedrightarithmeticallyby one bitpositionas shown in Figure4-40.The MSB retainsitsvalue(sign).RRA operatesequaltoa signeddivision by 2.The MSB isretainedand shiftedintotheMSB –1.The LSB+1 isshiftedintothe LSB. The previousLSB isshiftedintothecarrybitC. StatusBits N: Setifresultisnegative(MSB = 1),resetotherwise(MSB = 0) Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The signed16-bitnumber inR5 isshiftedarithmeticallyrightone position. RRA R5 ;R5/2->R5 Example The signedRAM byteEDE isshiftedarithmeticallyrightone position. RRA.BEDE ;EDE/2->EDE Figure4-40.RotateRightArithmeticallyRRA.B and RRA.W

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C 19 0 MSB0 0 0 0 0 0 0 715 0 0 0 0 0 LSB C 19 0 MSB0 0 0 0 LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.41RRC RRC[.W] Rotaterightthroughcarrydestinationword RRC.B Rotaterightthroughcarrydestinationbyte Syntax RRCdstor RRC.Wdst RRC.Bdst Operation C → MSB → MSB –1 → ...LSB+1 → LSB → C Description The destinationoperandisshiftedrightby one bitpositionas shown inFigure4-41.The carrybitC isshiftedintotheMSB and theLSB isshiftedintothecarrybitC. StatusBits N: Setifresultisnegative(MSB = 1),resetotherwise(MSB = 0) Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM word EDE isshiftedrightone bitposition.The MSB isloadedwith1. SETC ;PreparecarryforMSB RRC EDE ;EDE=EDE>>1+8000h Figure4-41.RotateRightThrough CarryRRC.B and RRC.W 219SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.42SBC *SBC[.W] Subtractborrow(.NOT.carry)fromdestination *SBC.B Subtractborrow(.NOT.carry)fromdestination Syntax SBCdstor SBC.Wdst SBC.Bdst Operation dst+ 0FFFFh + C → dst dst+ 0FFh + C → dst SUBC#0,dstEmulation SUBC.B#0,dst Description The carrybit(C)isadded tothedestinationoperandminus one.The previouscontents ofthedestinationarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise Setto1 ifno borrow,resetifborrow V: Setifan arithmeticoverflowoccurs,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 16-bitcounterpointedtoby R13 issubtractedfroma 32-bitcounterpointedtoby R12. SUB @R13,0(R12);SubtractLSDs SBC 2(R12) ;SubtractcarryfromMSD Example The 8-bitcounterpointedtoby R13 issubtractedfroma 16-bitcounterpointedtoby R12. SUB.B@R13,0(R12);SubtractLSDs SBC.B1(R12) ;SubtractcarryfromMSD NOTE: Borrow implementation The borrowistreatedas a .NOT. carry: Borrow CarryBit Yes 0 No 1

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.43SETC *SETC Setcarrybit SETCSyntax Operation 1 → C BIS#1,SREmulation Description The carrybit(C)isset. StatusBits N: Not affected Z: Not affected C: Set V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Emulationofthedecimalsubtraction: SubtractR5 fromR6 decimally. Assume thatR5 = 03987h and R6 = 04137h. DSUBADD #06666h,R5;MovecontentR5from0-9to6-0Fh ;R5=03987h+06666h=09FEDh INV R5 ;Invertthis(resultbackto0-9) ;R5=.NOT.R5=06012h SETC ;Preparecarry=1 DADDR5,R6 ;Emulatesubtractionbyadditionof: ;(010000h-R5-1) ;R6=R6+R5+1 ;R6=0150h 221SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.44SETN *SETN Setnegativebit SETNSyntax Operation 1 → N BIS#4,SREmulation Description The negativebit(N)isset. StatusBits N: Set Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.45SETZ *SETZ Setzerobit SETZSyntax Operation 1 → N BIS#2,SREmulation Description The zerobit(Z)isset. StatusBits N: Not affected Z: Set C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. 223SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.46SUB SUB[.W] Subtractsourceword fromdestinationword SUB.B Subtractsourcebytefromdestinationbyte Syntax SUBsrc,dstor SUB.Wsrc,dst SUB.Bsrc,dst Operation (.not.src)+ 1 + dst→ dst or dst– src→ dst Description The sourceoperandissubtractedfromthedestinationoperand.Thisismade by adding the1s complement ofthesource+ 1 tothedestination.The sourceoperandisnot affected,theresultiswrittentothedestinationoperand. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src≤ dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example A 16-bitconstant7654h issubtractedfromRAM word EDE. SUB #7654h,&EDE ;Subtract7654hfromEDE Example A tableword pointedtoby R5 (20-bitaddress)issubtractedfromR7. Afterwards,ifR7 containszero,jump tolabelTONI. R5 isthenauto-incrementedby 2.R7.19:16= 0. SUB @R5+,R7 ;SubtracttablenumberfromR7.R5+2 JZ TONI ;R7=@R5(beforesubtraction) ... ;R7<>@R5(beforesubtraction) Example ByteCNT issubtractedfrombyteR12 pointsto.The addressofCNT iswithinPC ± 32K. The addressR12 pointstoisinfullmemory range. SUB.BCNT,0(R12);SubtractCNTfrom@R12

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.47SUBC SUBC[.W] Subtractsourceword withcarryfromdestinationword SUBC.B Subtractsourcebytewithcarryfromdestinationbyte Syntax SUBCsrc,dstor SUBC.Wsrc,dst SUBC.Bsrc,dst Operation (.not.src)+ C + dst→ dst or dst– (src– 1)+ C → dst Description The sourceoperandissubtractedfromthedestinationoperand.Thisisdone by adding the1s complement ofthesource+ carrytothedestination.The sourceoperandisnot affected,theresultiswrittentothedestinationoperand.Used for32,48,and 64-bit operands. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example A 16-bitconstant7654h issubtractedfromR5 withthecarryfromtheprevious instruction.R5.19:16= 0 SUBC.W#7654h,R5;Subtract7654h+CfromR5 Example A 48-bitnumber (3words)pointedtoby R5 (20-bitaddress)issubtractedfroma 48-bit counterinRAM, pointedtoby R7. R5 pointstothenext48-bitnumber afterwards.The addressR7 pointstoisinfullmemory range. SUB @R5+,0(R7);SubtractLSBs.R5+2 SUBC @R5+,2(R7);SubtractMIDswithC.R5+2 SUBC @R5+,4(R7);SubtractMSBswithC.R5+2 Example ByteCNT issubtractedfromthebyte,R12 pointsto.The carryofthepreviousinstruction isused.The addressofCNT isinlower64 K. SUBC.B&CNT,0(R12);SubtractbyteCNTfrom@R12 225SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

x 0... 15 8 7 0 15 8 7 0 Low Byte Low ByteHigh Byte High Byte Before SWPB After SWPB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.48SWPB SWPB Swap bytes SWPBdstSyntax Operation dst.15:8↔ dst.7:0 Description The highand thelowbyteoftheoperandareexchanged.PC.19:16bitsareclearedin registermode. StatusBits Statusbitsarenotaffected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Exchange thebytesofRAM word EDE (lower64 K) MOV #1234h,&EDE ;1234h->EDE SWPB&EDE ;3412h->EDE Figure4-42.Swap Bytes inMemory Figure4-43.Swap Bytes ina Register

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.49SXT SXT Extendsign SXTdstSyntax Operation dst.7→ dst.15:8,dst.7→ dst.19:8(registermode) Description Registermode: thesignofthelowbyteoftheoperandisextendedintothebits Rdst.19:8. Rdst.7= 0:Rdst.19:8= 000h afterwards Rdst.7= 1:Rdst.19:8= FFFh afterwards Othermodes: thesignofthelowbyteoftheoperandisextendedintothehighbyte. dst.7= 0:highbyte= 00h afterwards dst.7= 1:highbyte= FFh afterwards StatusBits N: Setifresultisnegative,resetotherwise Z: Setifresultiszero,resetotherwise C: Setifresultisnotzero,resetotherwise(C = .not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The signed8-bitdatainEDE (lower64 K) issignextendedand added tothe16-bit signeddatainR7. MOV.B&EDE,R5;EDE->R5.00XXh SXT R5 ;SignextendlowbytetoR5.19:8 ADD R5,R7 ;Addsigned16-bitvalues Example The signed8-bitdatainEDE (PC +32 K) issignextendedand added tothe20-bitdata inR7. MOV.BEDE,R5 ;EDE->R5.00XXh SXT R5 ;SignextendlowbytetoR5.19:8 ADDAR5,R7 ;Addsigned20-bitvalues 227SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.2.50TST *TST[.W] Testdestination *TST.B Testdestination Syntax TSTdstor TST.Wdst TST.Bdst Operation dst+ 0FFFFh + 1 dst+ 0FFh + 1 CMP#0,dstEmulation CMP.B#0,dst Description The destinationoperandiscompared withzero.The statusbitsaresetaccordingtothe result.The destinationisnotaffected. StatusBits N: Setifdestinationisnegative,resetifpositive Z: Setifdestinationcontainszero,resetotherwise C: Set V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R7 istested.Ifitisnegative,continueatR7NEG; ifitispositivebutnotzero,continueat R7POS. TST R7 ;TestR7 JN R7NEG;R7isnegative JZ R7ZERO;R7iszero Example The lowbyteofR7 istested.Ifitisnegative,continueatR7NEG; ifitispositivebutnot zero,continueatR7POS. TST.BR7 ;TestlowbyteofR7 JN R7NEG;LowbyteofR7isnegative JZ R7ZERO;LowbyteofR7iszero

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.2.51XOR XOR[.W] ExclusiveOR sourceword withdestinationword XOR.B ExclusiveOR sourcebytewithdestinationbyte Syntax XORsrc,dstor XOR.Wsrc,dst XOR.Bsrc,dst Operation src.xor.dst→ dst Description The sourceand destinationoperandsareexclusivelyORed. The resultisplacedintothe destination.The sourceoperandisnotaffected.The previouscontentofthedestination islost. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifresultisnotzero,resetotherwise(C = .not.Z) V: Setifbothoperandsarenegativebeforeexecution,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Togglebitsinword CNTR (16-bitdata)withinformation(bit= 1)inaddress-wordTONI. Bothoperandsarelocatedinlower64 K. XOR &TONI,&CNTR ;TogglebitsinCNTR Example A tableword pointedtoby R5 (20-bitaddress)isused totogglebitsinR6. R6.19:16= 0. XOR @R5,R6 ;TogglebitsinR6 Example ResettozerothosebitsinthelowbyteofR7 thataredifferentfromthebitsinbyteEDE. R7.19:8= 0.The addressofEDE iswithinPC ± 32 K. XOR.BEDE,R7 ;Setdifferentbitsto1inR7. INV.BR7 ;InvertlowbyteofR7,highbyteis0h 229SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.3 Extended Instructions

The extendedMSP430X instructionsgivetheMSP430X CPU fullaccesstoits20-bitaddressspace. MSP430X instructionsrequirean additionalword ofop-codecalledtheextensionword.Alladdresses, indexes,and immediatenumbers have 20-bitvalueswhen precededby theextensionword.The MSP430X extendedinstructionsarelistedand describedinthefollowingpages.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription

4.6.3.1 ADCX

*ADCX.A Add carrytodestinationaddress-word *ADCX.[W] Add carrytodestinationword *ADCX.B Add carrytodestinationbyte ADCX.AdstSyntax ADCXdstor ADCX.Wdst ADCX.Bdst Operation dst+ C → dst ADDCX.A#0,dstEmulation ADDCX#0,dst ADDCX.B#0,dst Description The carrybit(C)isadded tothedestinationoperand.The previouscontentsofthe destinationarelost. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 40-bitcounter,pointedtoby R12 and R13, isincremented. INCX.A@R12 ;Incrementlower20bits ADCX.A@R13 ;Addcarrytoupper20bits 231SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.3.2 ADDX

ADDX.A Add sourceaddress-wordtodestinationaddress-word ADDX.[W] Add sourceword todestinationword ADDX.B Add sourcebytetodestinationbyte ADDX.Asrc,dstSyntax ADDXsrc,dstor ADDX.Wsrc,dst ADDX.Bsrc,dst Operation src+ dst→ dst Description The sourceoperandisadded tothedestinationoperand.The previouscontentsofthe destinationarelost.Bothoperandscan be locatedinthefulladdressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Ten isadded tothe20-bitpointerCNTR locatedintwo words CNTR (LSBs)and CNTR+2 (MSBs). ADDX.A#10,CNTR;Add10to20-bitpointer Example A tableword (16-bit)pointedtoby R5 (20-bitaddress)isadded toR6. The jump tolabel TONI isperformedon a carry. ADDX.W@R5,R6;AddtablewordtoR6 JC TONI ;Jumpifcarry ... ;Nocarry Example A tablebytepointedtoby R5 (20-bitaddress)isadded toR6. The jump tolabelTONI is performedifno carryoccurs.The tablepointerisauto-incrementedby 1. ADDX.B@R5+,R6;AddtablebytetoR6.R5+1.R6:000xxh JNC TONI ;Jumpifnocarry ... ;Carryoccurred Note:Use ADDA forthefollowingtwo casesforbettercode densityand execution. ADDX.ARsrc,Rdst ADDX.A#imm20,Rdst

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription

4.6.3.3 ADDCX

ADDCX.A Add sourceaddress-wordand carrytodestinationaddress-word ADDCX.[W] Add sourceword and carrytodestinationword ADDCX.B Add sourcebyteand carrytodestinationbyte ADDCX.Asrc,dstSyntax ADDCXsrc,dstor ADDCX.Wsrc,dst ADDCX.Bsrc,dst Operation src+ dst+ C → dst Description The sourceoperandand thecarrybitC areadded tothedestinationoperand.The previouscontentsofthedestinationarelost.Bothoperandsmay be locatedinthefull addressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Constant15 and thecarryofthepreviousinstructionareadded tothe20-bitcounter CNTR locatedintwo words. ADDCX.A#15,&CNTR;Add15+Cto20-bitCNTR Example A tableword pointedtoby R5 (20-bitaddress)and thecarryC areadded toR6. The jump tolabelTONI isperformedon a carry. ADDCX.W@R5,R6;Addtableword+CtoR6 JC TONI ;Jumpifcarry ... ;Nocarry Example A tablebytepointedtoby R5 (20-bitaddress)and thecarrybitC areadded toR6. The jump tolabelTONI isperformedifno carryoccurs.The tablepointerisauto-incremented by 1. ADDCX.B@R5+,R6;Addtablebyte+CtoR6.R5+1 JNC TONI ;Jumpifnocarry ... ;Carryoccurred 233SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.3.4 ANDX

ANDX.A LogicalAND ofsourceaddress-wordwithdestinationaddress-word ANDX.[W] LogicalAND ofsourceword withdestinationword ANDX.B LogicalAND ofsourcebytewithdestinationbyte ANDX.Asrc,dstSyntax ANDXsrc,dstor ANDX.Wsrc,dst ANDX.Bsrc,dst Operation src.and.dst→ dst Description The sourceoperandand thedestinationoperandarelogicallyANDed. The resultis placedintothedestination.The sourceoperandisnotaffected.Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setiftheresultisnotzero,resetotherwise.C = (.not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The bitssetinR5 (20-bitdata)areused as a mask (AAA55h) fortheaddress-wordTOM locatedintwo words.Iftheresultiszero,a branchistakentolabelTONI. MOVA #AAA55h,R5;Load20-bitmasktoR5 ANDX.AR5,TOM ;TOM.and.R5->TOM JZ TONI ;Jumpifresult0 ... ;Result>0 orshorter: ANDX.A#AAA55h,TOM;TOM.and.AAA55h->TOM JZ TONI ;Jumpifresult0 Example A tablebytepointedtoby R5 (20-bitaddress)islogicallyANDed withR6. R6.19:8= 0. The tablepointerisauto-incrementedby 1. ANDX.B@R5+,R6 ;ANDtablebytewithR6.R5+1

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription

4.6.3.5 BICX

BICX.A Clearbitssetinsourceaddress-wordindestinationaddress-word BICX.[W] Clearbitssetinsourceword indestinationword BICX.B Clearbitssetinsourcebyteindestinationbyte BICX.Asrc,dstSyntax BICXsrc,dstor BICX.Wsrc,dst BICX.Bsrc,dst Operation (.not.src).and.dst→ dst Description The invertedsourceoperandand thedestinationoperandarelogicallyANDed. The resultisplacedintothedestination.The sourceoperandisnotaffected.Bothoperands may be locatedinthefulladdressspace. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The bits19:15ofR5 (20-bitdata)arecleared. BICX.A#0F8000h,R5;ClearR5.19:15bits Example A tableword pointedtoby R5 (20-bitaddress)isused toclearbitsinR7. R7.19:16= 0. BICX.W@R5,R7 ;ClearbitsinR7 Example A tablebytepointedtoby R5 (20-bitaddress)isused toclearbitsinoutputPort1. BICX.B@R5,&P1OUT ;ClearI/OportP1bits 235SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.3.6 BISX

BISX.A Setbitssetinsourceaddress-wordindestinationaddress-word BISX.[W] Setbitssetinsourceword indestinationword BISX.B Setbitssetinsourcebyteindestinationbyte BISX.Asrc,dstSyntax BISXsrc,dstor BISX.Wsrc,dst BISX.Bsrc,dst Operation src.or.dst→ dst Description The sourceoperandand thedestinationoperandarelogicallyORed. The resultisplaced intothedestination.The sourceoperandisnotaffected.Bothoperandsmay be located inthefulladdressspace. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Bits16 and 15 ofR5 (20-bitdata)aresettoone. BISX.A#018000h,R5;SetR5.16:15bits Example A tableword pointedtoby R5 (20-bitaddress)isused tosetbitsinR7. BISX.W@R5,R7 ;SetbitsinR7 Example A tablebytepointedtoby R5 (20-bitaddress)isused tosetbitsinoutputPort1. BISX.B@R5,&P1OUT ;SetI/OportP1bits

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription

4.6.3.7 BITX

BITX.A Testbitssetinsourceaddress-wordindestinationaddress-word BITX.[W] Testbitssetinsourceword indestinationword BITX.B Testbitssetinsourcebyteindestinationbyte BITX.Asrc,dstSyntax BITXsrc,dstor BITX.Wsrc,dst BITX.Bsrc,dst Operation src.and.dst→ dst Description The sourceoperandand thedestinationoperandarelogicallyANDed. The resultaffects onlythestatusbits.Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setiftheresultisnotzero,resetotherwise.C = (.not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Testifbit16 or15 ofR5 (20-bitdata)isset.Jump tolabelTONI ifso. BITX.A#018000h,R5;TestR5.16:15bits JNZ TONI ;Atleastonebitisset ... ;Botharereset Example A tableword pointedtoby R5 (20-bitaddress)isused totestbitsinR7. Jump tolabel TONI ifatleastone bitisset. BITX.W@R5,R7 ;TestbitsinR7:C=.not.Z JC TONI ;Atleastoneisset ... ;Botharereset Example A tablebytepointedtoby R5 (20-bitaddress)isused totestbitsininputPort1.Jump to labelTONI ifno bitisset.The nexttablebyteisaddressed. BITX.B@R5+,&P1IN ;TestinputP1bits.R5+1 JNC TONI ;Nocorrespondinginputbitisset ... ;Atleastonebitisset 237SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.3.8 CLRX

*CLRX.A Cleardestinationaddress-word *CLRX.[W] Cleardestinationword *CLRX.B Cleardestinationbyte CLRX.AdstSyntax CLRXdstor CLRX.Wdst CLRX.Bdst Operation 0 → dst MOVX.A#0,dstEmulation MOVX#0,dst MOVX.B#0,dst Description The destinationoperandiscleared. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM address-wordTONI iscleared. CLRX.ATONI;0->TONI

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription

4.6.3.9 CMPX

CMPX.A Compare sourceaddress-wordand destinationaddress-word CMPX.[W] Compare sourceword and destinationword CMPX.B Compare sourcebyteand destinationbyte CMPX.Asrc,dstSyntax CMPXsrc,dstor CMPX.Wsrc,dst CMPX.Bsrc,dst Operation (.not.src)+ 1 + dst or dst– src Description The sourceoperandissubtractedfromthedestinationoperandby addingthe1s complement ofthesource+ 1 tothedestination.The resultaffectsonlythestatusbits. Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src≤ dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Compare EDE witha 20-bitconstant18000h.Jump tolabelTONI ifEDE equalsthe constant. CMPX.A#018000h,EDE;CompareEDEwith18000h JEQ TONI ;EDEcontains18000h ... ;Notequal Example A tableword pointedtoby R5 (20-bitaddress)iscompared withR7. Jump tolabelTONI ifR7 containsa lower,signed,16-bitnumber. CMPX.W@R5,R7 ;Comparetwosignednumbers JL TONI ;R7<@R5 ... ;R7>=@R5 Example A tablebytepointedtoby R5 (20-bitaddress)iscompared totheinputinI/OPort1. Jump tolabelTONI ifthevaluesareequal.The nexttablebyteisaddressed. CMPX.B@R5+,&P1IN ;CompareP1bitswithtable.R5+1 JEQ TONI ;Equalcontents ... ;Notequal Note:Use CMPA forthefollowingtwo casesforbetterdensityand execution. CMPA Rsrc,Rdst CMPA #imm20,Rdst 239SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.10DADCX *DADCX.A Add carrydecimallytodestinationaddress-word *DADCX.[W] Add carrydecimallytodestinationword *DADCX.B Add carrydecimallytodestinationbyte DADCX.AdstSyntax DADCXdstor DADCX.Wdst DADCX.Bdst Operation dst+ C → dst(decimally) DADDX.A#0,dstEmulation DADDX#0,dst DADDX.B#0,dst Description The carrybit(C)isadded decimallytothedestination. StatusBits N: SetifMSB ofresultis1 (address-word> 79999h,word > 7999h,byte> 79h),reset ifMSB is0 Z: Setifresultiszero,resetotherwise C: SetiftheBCD resultistoolarge(address-word> 99999h,word > 9999h,byte> 99h),resetotherwise V: Undefined Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 40-bitcounter,pointedtoby R12 and R13, isincrementeddecimally. DADDX.A#1,0(R12);Incrementlower20bits DADCX.A0(R13) ;Addcarrytoupper20bits

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.11DADDX DADDX.A Add sourceaddress-wordand carrydecimallytodestinationaddress-word DADDX.[W] Add sourceword and carrydecimallytodestinationword DADDX.B Add sourcebyteand carrydecimallytodestinationbyte DADDX.Asrc,dstSyntax DADDXsrc,dstor DADDX.Wsrc,dst DADDX.Bsrc,dst Operation src+ dst+ C → dst(decimally) Description The sourceoperandand thedestinationoperandaretreatedas two (.B),four(.W),or five(.A)binarycoded decimals(BCD) withpositivesigns.The sourceoperandand the carrybitC areadded decimallytothedestinationoperand.The sourceoperandisnot affected.The previouscontentsofthedestinationarelost.The resultisnotdefinedfor non-BCD numbers.Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: SetifMSB ofresultis1 (address-word> 79999h,word > 7999h,byte> 79h),reset ifMSB is0. Z: Setifresultiszero,resetotherwise C: SetiftheBCD resultistoolarge(address-word> 99999h,word > 9999h,byte> 99h),resetotherwise V: Undefined Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Decimal10 isadded tothe20-bitBCD counterDECCNTR locatedintwo words. DADDX.A#10h,&DECCNTR;Add10to20-bitBCDcounter Example The eight-digitBCD number containedin20-bitaddressesBCD and BCD+2 isadded decimallytoan eight-digitBCD number containedinR4 and R5 (BCD+2 and R5 contain theMSDs). CLRC ;Clearcarry DADDX.WBCD,R4 ;AddLSDs DADDX.WBCD+2,R5 ;AddMSDswithcarry JC OVERFLOW ;Result>99999999:gotoerrorroutine ... ; Resultok Example The two-digitBCD number containedin20-bitaddressBCD isadded decimallytoa two- digitBCD number containedinR4. CLRC ;Clearcarry DADDX.BBCD,R4 ;AddBCDtoR4decimally. ;R4:000ddh 241SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.12DECX *DECX.A Decrement destinationaddress-word *DECX.[W] Decrement destinationword *DECX.B Decrement destinationbyte DECX.AdstSyntax DECXdstor DECX.Wdst DECX.Bdst Operation dst– 1 → dst SUBX.A#1,dstEmulation SUBX#1,dst SUBX.B#1,dst Description The destinationoperandisdecrementedby one.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained1,resetotherwise C: Resetifdstcontained0,setotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM address-wordTONI isdecrementedby one. DECX.ATONI ;DecrementTONI

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.13DECDX *DECDX.A Double-decrementdestinationaddress-word *DECDX.[W] Double-decrementdestinationword *DECDX.B Double-decrementdestinationbyte DECDX.AdstSyntax DECDXdstor DECDX.Wdst DECDX.Bdst Operation dst– 2 → dst SUBX.A#2,dstEmulation SUBX#2,dst SUBX.B#2,dst Description The destinationoperandisdecrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained2,resetotherwise C: Resetifdstcontained0 or1,setotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM address-wordTONI isdecrementedby two. DECDX.ATONI ;DecrementTONI 243SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.14INCX *INCX.A Incrementdestinationaddress-word *INCX.[W] Incrementdestinationword *INCX.B Incrementdestinationbyte INCX.AdstSyntax INCXdstor INCX.Wdst INCX.Bdst Operation dst+ 1 → dst ADDX.A#1,dstEmulation ADDX#1,dst ADDX.B#1,dst Description The destinationoperandisincrementedby one.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFFFh, resetotherwise Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise C: Setifdstcontained0FFFFFh, resetotherwise Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise V: Setifdstcontained07FFFh, resetotherwise Setifdstcontained07FFFh, resetotherwise Setifdstcontained07Fh,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM address-wordTONIisincrementedby one. INCX.ATONI ;IncrementTONI(20-bits)

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.15INCDX *INCDX.A Double-incrementdestinationaddress-word *INCDX.[W] Double-incrementdestinationword *INCDX.B Double-incrementdestinationbyte INCDX.AdstSyntax INCDXdstor INCDX.Wdst INCDX.Bdst Operation dst+ 2 → dst ADDX.A#2,dstEmulation ADDX#2,dst ADDX.B#2,dst Description The destinationoperandisincrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFFEh, resetotherwise Setifdstcontained0FFFEh, resetotherwise Setifdstcontained0FEh, resetotherwise C: Setifdstcontained0FFFFEh or0FFFFFh, resetotherwise Setifdstcontained0FFFEh or0FFFFh, resetotherwise Setifdstcontained0FEh or0FFh,resetotherwise V: Setifdstcontained07FFFEh or07FFFFh, resetotherwise Setifdstcontained07FFEh or07FFFh, resetotherwise Setifdstcontained07Eh or07Fh,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM byteLEO isincrementedby two;PC pointstouppermemory. INCDX.BLEO ;IncrementLEObytwo 245SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.16INVX *INVX.A Invertdestination *INVX.[W] Invertdestination *INVX.B Invertdestination INVX.AdstSyntax INVXdstor INVX.Wdst INVX.Bdst Operation .NOT.dst→ dst XORX.A#0FFFFFh,dstEmulation XORX#0FFFFh,dst XORX.B#0FFh,dst Description The destinationoperandisinverted.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifdstcontained0FFFFFh, resetotherwise Setifdstcontained0FFFFh, resetotherwise Setifdstcontained0FFh,resetotherwise C: Setifresultisnotzero,resetotherwise(= .NOT. Zero) V: Setifinitialdestinationoperandwas negative,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example 20-bitcontentofR5 isnegated(2scomplement). INVX.AR5 ;InvertR5 INCX.AR5 ;R5isnownegated Example Contentofmemory byteLEO isnegated.PC ispointingtouppermemory. INVX.BLEO ;InvertLEO INCX.BLEO ;MEM(LEO)isnegated

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.17MOVX MOVX.A Move sourceaddress-wordtodestinationaddress-word MOVX.[W] Move sourceword todestinationword MOVX.B Move sourcebytetodestinationbyte MOVX.Asrc,dstSyntax MOVXsrc,dstor MOVX.Wsrc,dst MOVX.Bsrc,dst Operation src→ dst Description The sourceoperandiscopiedtothedestination.The sourceoperandisnotaffected. Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Move a 20-bitconstant18000h toabsoluteaddress-wordEDE MOVX.A#018000h,&EDE ;Move18000htoEDE Example The contentsoftableEDE (worddata,20-bitaddresses)arecopiedtotableTOM. The lengthofthetableis030h words. MOVA #EDE,R10 ;Preparepointer(20-bitaddress) LoopMOVX.W@R10+,TOM-EDE-2(R10);R10pointstobothtables. ;R10+2 CMPA #EDE+60h,R10;Endoftablereached? JLO Loop ;Notyet ... ;Copycompleted Example The contentsoftableEDE (bytedata,20-bitaddresses)arecopiedtotableTOM. The lengthofthetableis020h bytes. MOVA #EDE,R10 ;Preparepointer(20-bit) MOV #20h,R9 ;Preparecounter LoopMOVX.W@R10+,TOM-EDE-2(R10);R10pointstobothtables. ;R10+1 DEC R9 ;Decrementcounter JNZ Loop ;Notyetdone ... ;Copycompleted Ten ofthe28 possibleaddressingcombinationsoftheMOVX.A instructioncan use the MOVA instruction.Thissavestwo bytesand code cycles.Examples fortheaddressing combinationsare: MOVX.ARsrc,Rdst MOVARsrc,Rdst;Reg/Reg MOVX.A#imm20,RdstMOVA#imm20,Rdst;Immediate/Reg MOVX.A&abs20,RdstMOVA&abs20,Rdst;Absolute/Reg MOVX.A@Rsrc,RdstMOVA@Rsrc,Rdst;Indirect/Reg MOVX.A@Rsrc+,RdstMOVA@Rsrc+,Rdst;Indirect,Auto/Reg MOVX.ARsrc,&abs20 MOVARsrc,&abs20 ;Reg/Absolute 247SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com The nextfourreplacementsarepossibleonlyif16-bitindexesaresufficientforthe addressing: MOVX.Az20(Rsrc),RdstMOVAz16(Rsrc),Rdst;Indexed/Reg MOVX.ARsrc,z20(Rdst)MOVARsrc,z16(Rdst);Reg/Indexed MOVX.Asymb20,RdstMOVAsymb16,Rdst;Symbolic/Reg MOVX.ARsrc,symb20MOVARsrc,symb16;Reg/Symbolic

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.18POPM POPM.A Restoren CPU registers(20-bitdata)fromthestack POPM.[W] Restoren CPU registers(16-bitdata)fromthestack POPM.A#n,RdstSyntax 1 ≤ n ≤ 16 POPM.W#n,Rdstor POPM#n,Rdst 1 ≤ n ≤ 16 Operation POPM.A: RestoretheregistervaluesfromstacktothespecifiedCPU registers.The SP isincrementedby fourforeach registerrestoredfromstack.The 20-bitvaluesfrom stack(twowords perregister)arerestoredtotheregisters. POPM.W: Restorethe16-bitregistervaluesfromstacktothespecifiedCPU registers. The SP isincrementedby two foreach registerrestoredfromstack.The 16-bitvalues fromstack(oneword perregister)arerestoredtotheCPU registers. Note :Thisinstructiondoes notuse theextensionword. Description POPM.A: The CPU registerspushed on thestackaremoved totheextendedCPU registers,startingwiththeCPU register(Rdst– n + 1).The SP isincrementedby (n× 4)aftertheoperation. POPM.W: The 16-bitregisterspushed on thestackaremoved back totheCPU registers,startingwithCPU register(Rdst– n + 1).The SP isincrementedby (n× 2) aftertheinstruction.The MSBs (Rdst.19:16)oftherestoredCPU registersarecleared. StatusBits Statusbitsarenotaffected,exceptSR isincludedintheoperation. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Restorethe20-bitregistersR9, R10, R11, R12, R13 fromthestack POPM.A#5,R13;RestoreR9,R10,R11,R12,R13 Example Restorethe16-bitregistersR9, R10, R11, R12, R13 fromthestack. POPM.W#5,R13;RestoreR9,R10,R11,R12,R13 249SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.19PUSHM PUSHM.A Save n CPU registers(20-bitdata)on thestack PUSHM.[W] Save n CPU registers(16-bitwords)on thestack PUSHM.A#n,RdstSyntax 1 ≤ n ≤ 16 PUSHM.W#n,Rdstor PUSHM#n,Rdst 1 ≤ n ≤ 16 Operation PUSHM.A: Save the20-bitCPU registervalueson thestack.The SP isdecremented by fourforeach registerstoredon thestack.The MSBs arestoredfirst(higher address). PUSHM.W: Save the16-bitCPU registervalueson thestack.The SP isdecremented by two foreach registerstoredon thestack. Description PUSHM.A: The n CPU registers,startingwithRdstbackwards,arestoredon thestack. The SP isdecrementedby (n× 4)aftertheoperation.The data(Rn.19:0)ofthepushed CPU registersisnotaffected. PUSHM.W: The n registers,startingwithRdstbackwards,arestoredon thestack.The SP isdecrementedby (n× 2)aftertheoperation.The data(Rn.19:0)ofthepushed CPU registersisnotaffected. Note :Thisinstructiondoes notuse theextensionword. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Save thefive20-bitregistersR9, R10, R11, R12, R13 on thestack PUSHM.A#5,R13;SaveR13,R12,R11,R10,R9 Example Save thefive16-bitregistersR9, R10, R11, R12, R13 on thestack PUSHM.W#5,R13;SaveR13,R12,R11,R10,R9

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.20POPX *POPX.A Restoresingleaddress-wordfromthestack *POPX.[W] Restoresingleword fromthestack *POPX.B Restoresinglebytefromthestack POPX.AdstSyntax POPXdstor POPX.Wdst POPX.Bdst Operation Restorethe8-,16-,20-bitvaluefromthestacktothedestination.20-bitaddressesare possible.The SP isincrementedby two (byteand word operands)and by four (address-wordoperand). MOVX(.B,.A)@SP+,dstEmulation Description The itemon TOS iswrittentothedestinationoperand.Registermode, Indexedmode, Symbolicmode, and Absolutemode arepossible.The SP isincrementedby two or four. Note:theSP isincrementedby two alsoforbyteoperations. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Writethe16-bitvalueon TOS tothe20-bitaddress&EDE POPX.W&EDE ;WritewordtoaddressEDE Example Writethe20-bitvalueon TOS toR9 POPX.AR9 ;Writeaddress-wordtoR9 251SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.21PUSHX PUSHX.A Save singleaddress-wordtothestack PUSHX.[W] Save singleword tothestack PUSHX.B Save singlebytetothestack PUSHX.AsrcSyntax PUSHXsrcor PUSHX.Wsrc PUSHX.Bsrc Operation Save the8-,16-,20-bitvalueofthesourceoperandon theTOS. 20-bitaddressesare possible.The SP isdecrementedby two (byteand word operands)orby four(address- word operand)beforethewriteoperation. Description The SP isdecrementedby two (byteand word operands)orby four(address-word operand).Then thesourceoperandiswrittentotheTOS. Allseven addressingmodes arepossibleforthesourceoperand. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Save thebyteatthe20-bitaddress&EDE on thestack PUSHX.B&EDE ;SavebyteataddressEDE Example Save the20-bitvalueinR9 on thestack. PUSHX.AR9 ;Saveaddress-wordinR9

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C 19 0 MSB0000 LSB C 19 0 MSB LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.22RLAM RLAM.A Rotateleftarithmeticallythe20-bitCPU registercontent RLAM.[W] Rotateleftarithmeticallythe16-bitCPU registercontent RLAM.A#n,RdstSyntax 1 ≤ n ≤ 4 RLAM.W#n,Rdstor RLAM#n,Rdst 1 ≤ n ≤ 4 Operation C ← MSB ← MSB-1 ....LSB+1 ← LSB ← 0 Description The destinationoperandisshiftedarithmeticallyleftone,two,three,orfourpositionsas shown inFigure4-44.RLAM worksas a multiplication(signedand unsigned)with2,4, 8,or16.The word instructionRLAM.W clearsthebitsRdst.19:16. Note :Thisinstructiondoes notuse theextensionword. StatusBits N: Setifresultisnegative .A:Rdst.19= 1,resetifRdst.19= 0 .W:Rdst.15= 1,resetifRdst.15= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheMSB (n= 1),MSB-1 (n= 2),MSB-2 (n= 3),MSB-3 (n= 4) V: Undefined Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitoperandinR5 isshiftedleftby threepositions.Itoperatesequaltoan arithmeticmultiplicationby 8. RLAM.A#3,R5;R5=R5x8 Figure4-44.RotateLeftArithmetically— RLAM[.W] and RLAM.A 253SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.23RLAX *RLAX.A Rotateleftarithmeticallyaddress-word *RLAX.[W] Rotateleftarithmeticallyword *RLAX.B Rotateleftarithmeticallybyte RLAX.AdstSyntax RLAXdstor RLAX.Wdst RLAX.Bdst Operation C ← MSB ← MSB-1 ....LSB+1 ← LSB ← 0 ADDX.Adst,dstEmulation ADDXdst,dst ADDX.Bdst,dst Description The destinationoperandisshiftedleftone positionas shown inFigure4-45.The MSB isshiftedintothecarrybit(C)and theLSB isfilledwith0.The RLAX instructionactsas a signedmultiplicationby 2. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Loaded fromtheMSB V: Setifan arithmeticoverflowoccurs:theinitialvalueis040000h ≤ dst< 0C0000h; resetotherwise Setifan arithmeticoverflowoccurs:theinitialvalueis04000h ≤ dst< 0C000h; resetotherwise Setifan arithmeticoverflowoccurs:theinitialvalueis040h ≤ dst< 0C0h; reset otherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR7 ismultipliedby 2 RLAX.AR7 ;ShiftleftR7(20-bit) Figure4-45.DestinationOperand-ArithmeticShiftLeft

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.24RLCX *RLCX.A Rotateleftthroughcarryaddress-word *RLCX.[W] Rotateleftthroughcarryword *RLCX.B Rotateleftthroughcarrybyte RLCX.AdstSyntax RLCXdstor RLCX.Wdst RLCX.Bdst Operation C ← MSB ← MSB-1 ....LSB+1 ← LSB ← C ADDCX.Adst,dstEmulation ADDCXdst,dst ADDCX.Bdst,dst Description The destinationoperandisshiftedleftone positionas shown inFigure4-46.The carry bit(C)isshiftedintotheLSB and theMSB isshiftedintothecarrybit(C). StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Loaded fromtheMSB V: Setifan arithmeticoverflowoccurs:theinitialvalueis040000h ≤ dst< 0C0000h; resetotherwise Setifan arithmeticoverflowoccurs:theinitialvalueis04000h ≤ dst< 0C000h; resetotherwise Setifan arithmeticoverflowoccurs:theinitialvalueis040h ≤ dst< 0C0h; reset otherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR5 isshiftedleftone position. RLCX.AR5 ;(R5x2)+C->R5 Example The RAM byteLEO isshiftedleftone position.PC ispointingtouppermemory. RLCX.BLEO ;RAM(LEO)x2+C->RAM(LEO) Figure4-46.DestinationOperand-CarryLeftShift 255SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C 19 0 MSB0000 LSB C 19 0 MSB LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.25RRAM RRAM.A Rotaterightarithmeticallythe20-bitCPU registercontent RRAM.[W] Rotaterightarithmeticallythe16-bitCPU registercontent RRAM.A#n,RdstSyntax 1 ≤ n ≤ 4 RRAM.W#n,Rdstor RRAM#n,Rdst 1 ≤ n ≤ 4 Operation MSB → MSB → MSB –1 ...LSB+1 → LSB → C Description The destinationoperandisshiftedrightarithmeticallyby one,two,three,orfourbit positionsas shown inFigure4-47.The MSB retainsitsvalue(sign).RRAM operates equaltoa signeddivisionby 2,4,8,or16.The MSB isretainedand shiftedintoMSB-1. The LSB+1 isshiftedintotheLSB, and theLSB isshiftedintothecarrybitC. The word instructionRRAM.W clearsthebitsRdst.19:16. Note :Thisinstructiondoes notuse theextensionword. StatusBits N: Setifresultisnegative .A:Rdst.19= 1,resetifRdst.19= 0 .W:Rdst.15= 1,resetifRdst.15= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB (n= 1),LSB+1 (n= 2),LSB+2 (n= 3),orLSB+3 (n= 4) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The signed20-bitnumber inR5 isshiftedarithmeticallyrighttwo positions. RRAM.A#2,R5 ;R5/4->R5 PUSHM.A#1,R15 ;SaveextendedR15onstack RRAM.A#1,R15 ;R15y0.5->R15 ADDX.A@SP+,R15;R15y0.5+R15=1.5yR15->R15 RRAM.A#1,R15 ;(1.5yR15)y0.5=0.75yR15->R15 Figure4-47.RotateRightArithmeticallyRRAM[.W] and RRAM.A

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.26RRAX RRAX.A Rotaterightarithmeticallythe20-bitoperand RRAX.[W] Rotaterightarithmeticallythe16-bitoperand RRAX.B Rotaterightarithmeticallythe8-bitoperand RRAX.ARdstSyntax RRAX.WRdst RRAXRdst RRAX.BRdst RRAX.Adst RRAXdstor RRAX.Wdst RRAX.Bdst Operation MSB → MSB → MSB –1 ...LSB+1 → LSB → C Description Registermode forthedestination:thedestinationoperandisshiftedrightby one bit positionas shown inFigure4-48.The MSB retainsitsvalue(sign).The word instruction RRAX.W clearsthebitsRdst.19:16,thebyteinstructionRRAX.B clearsthebits Rdst.19:8.The MSB retainsitsvalue(sign),theLSB isshiftedintothecarrybit.RRAX hereoperatesequaltoa signeddivisionby 2. Allothermodes forthedestination:thedestinationoperandisshiftedrightarithmetically by one bitpositionas shown inFigure4-49.The MSB retainsitsvalue(sign),theLSB isshiftedintothecarrybit.RRAX hereoperatesequaltoa signeddivisionby 2.All addressingmodes, withtheexceptionoftheImmediatemode, arepossibleinthefull memory. StatusBits N: Setifresultisnegative,resetifpositive .A:dst.19= 1,resetifdst.19= 0 .W:dst.15= 1,resetifdst.15= 0 .B:dst.7= 1,resetifdst.7= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The signed20-bitnumber inR5 isshiftedarithmeticallyrightfourpositions. RPT #4 RRAX.AR5 ;R5/16->R5 Example The signed8-bitvalueinEDE ismultipliedby 0.5. 257SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C MSB LSB C 15 0 MSB LSB C 19 0 MSB LSB 31 20 0 0 C MSB LSB C 15 0 MSB LSB C 19 0 MSB LSB 819 0 0 19 16 0000 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com RRAX.B&EDE ;EDE/2->EDE Figure4-48.RotateRightArithmeticallyRRAX(.B,.A)– RegisterMode Figure4-49.RotateRightArithmeticallyRRAX(.B,.A)– Non-RegisterMode

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.27RRCM RRCM.A Rotaterightthroughcarrythe20-bitCPU registercontent RRCM.[W] Rotaterightthroughcarrythe16-bitCPU registercontent RRCM.A#n,RdstSyntax 1 ≤ n ≤ 4 RRCM.W#n,Rdstor RRCM#n,Rdst 1 ≤ n ≤ 4 Operation C → MSB → MSB –1 ...LSB+1 → LSB → C Description The destinationoperandisshiftedrightby one,two,three,orfourbitpositionsas shown inFigure4-50.The carrybitC isshiftedintotheMSB, theLSB isshiftedintothe carrybit.The word instructionRRCM.W clearsthebitsRdst.19:16. Note :Thisinstructiondoes notuse theextensionword. StatusBits N: Setifresultisnegative .A:Rdst.19= 1,resetifRdst.19= 0 .W:Rdst.15= 1,resetifRdst.15= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB (n= 1),LSB+1 (n= 2),LSB+2 (n= 3),orLSB+3 (n= 4) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. 259SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C 19 0 MSB0 LSB C 19 0 MSB LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com Example The address-wordinR5 isshiftedrightby threepositions.The MSB –2 isloadedwith1. SETC ;PreparecarryforMSB-2 RRCM.A#3,R5 ;R5=R5»3+20000h Example The word inR6 isshiftedrightby two positions.The MSB isloadedwiththeLSB. The MSB –1 isloadedwiththecontentsofthecarryflag. RRCM.W#2,R6 ;R6=R6»2.R6.19:16=0 Figure4-50.RotateRightThrough CarryRRCM[.W] and RRCM.A

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.28RRCX RRCX.A Rotaterightthroughcarrythe20-bitoperand RRCX.[W] Rotaterightthroughcarrythe16-bitoperand RRCX.B Rotaterightthroughcarrythe8-bitoperand RRCX.ARdstSyntax RRCX.WRdst RRCXRdst RRCX.BRdst RRCX.Adst RRCXdstor RRCX.Wdst RRCX.Bdst Operation C → MSB → MSB –1 ...LSB+1 → LSB → C Description Registermode forthedestination:thedestinationoperandisshiftedrightby one bit positionas shown inFigure4-51.The word instructionRRCX.W clearsthebits Rdst.19:16,thebyteinstructionRRCX.B clearsthebitsRdst.19:8.The carrybitC is shiftedintotheMSB, theLSB isshiftedintothecarrybit. Allothermodes forthedestination:thedestinationoperandisshiftedrightby one bit positionas shown inFigure4-52.The carrybitC isshiftedintotheMSB, theLSB is shiftedintothecarrybit.Alladdressingmodes, withtheexceptionoftheImmediate mode, arepossibleinthefullmemory. StatusBits N: Setifresultisnegative .A:dst.19= 1,resetifdst.19= 0 .W:dst.15= 1,resetifdst.15= 0 .B:dst.7= 1,resetifdst.7= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitoperandataddressEDE isshiftedrightby one position.The MSB isloaded with1. SETC ;PreparecarryforMSB RRCX.AEDE ;EDE=EDE»1+80000h Example The word inR6 isshiftedrightby 12 positions. 261SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C MSB LSB C 15 0 MSB LSB C 19 0 MSB LSB 31 20 0 0 C 19 0 LSB C 19 0 MSB LSB C 15 0 MSB LSB 19 16 0 0 0 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com RPT #12 RRCX.WR6 ;R6=R6»12.R6.19:16=0 Figure4-51.RotateRightThrough CarryRRCX(.B,.A)– RegisterMode Figure4-52.RotateRightThrough CarryRRCX(.B,.A)– Non-RegisterMode

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C 19 0 MSB0000 LSB C 19 0 MSB LSB ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.29RRUM RRUM.A Rotaterightthroughcarrythe20-bitCPU registercontent RRUM.[W] Rotaterightthroughcarrythe16-bitCPU registercontent RRUM.A#n,RdstSyntax 1 ≤ n ≤ 4 RRUM.W#n,Rdstor RRUM#n,Rdst 1 ≤ n ≤ 4 Operation 0 → MSB → MSB –1 ...LSB+1 → LSB → C Description The destinationoperandisshiftedrightby one,two,three,orfourbitpositionsas shown inFigure4-53.ZeroisshiftedintotheMSB, theLSB isshiftedintothecarrybit. RRUM workslikean unsigneddivisionby 2,4,8,or16.The word instructionRRUM.W clearsthebitsRdst.19:16. Note :Thisinstructiondoes notuse theextensionword. StatusBits N: Setifresultisnegative .A:Rdst.19= 1,resetifRdst.19= 0 .W:Rdst.15= 1,resetifRdst.15= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB (n= 1),LSB+1 (n= 2),LSB+2 (n= 3),orLSB+3 (n= 4) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The unsignedaddress-wordinR5 isdividedby 16. RRUM.A#4,R5 ;R5=R5»4.R5/16 Example The word inR6 isshiftedrightby one bit.The MSB R6.15 isloadedwith0. RRUM.W#1,R6 ;R6=R6/2.R6.19:15=0 Figure4-53.RotateRightUnsigned RRUM[.W] and RRUM.A 263SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

C 19 0 LSB C 19 0 MSB LSB C 15 0 MSB LSB 19 16 0 0 0 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.30RRUX RRUX.A Shiftrightunsignedthe20-bitCPU registercontent RRUX.[W] Shiftrightunsignedthe16-bitCPU registercontent RRUX.B Shiftrightunsignedthe8-bitCPU registercontent RRUX.ARdstSyntax RRUX.WRdst RRUXRdst RRUX.BRdst Operation C=0 → MSB → MSB –1 ...LSB+1 → LSB → C Description RRUX isvalidforregistermode only:thedestinationoperandisshiftedrightby one bit positionas shown inFigure4-54.The word instructionRRUX.W clearsthebits theMSB, theLSB isshiftedintothecarrybit. StatusBits N: Setifresultisnegative .A:dst.19= 1,resetifdst.19= 0 .W:dst.15= 1,resetifdst.15= 0 .B:dst.7= 1,resetifdst.7= 0 Z: Setifresultiszero,resetotherwise C: Loaded fromtheLSB V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The word inR6 isshiftedrightby 12 positions. RPT #12 RRUX.WR6 ;R6=R6»12.R6.19:16=0 Figure4-54.RotateRightUnsigned RRUX(.B,.A)– RegisterMode

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.31SBCX *SBCX.A Subtractborrow(.NOT.carry)fromdestinationaddress-word *SBCX.[W] Subtractborrow(.NOT.carry)fromdestinationword *SBCX.B Subtractborrow(.NOT.carry)fromdestinationbyte SBCX.AdstSyntax SBCXdstor SBCX.Wdst SBCX.Bdst Operation dst+ 0FFFFFh + C → dst dst+ 0FFFFh + C → dst dst+ 0FFh + C → dst SBCX.A#0,dstEmulation SBCX#0,dst SBCX.B#0,dst Description The carrybit(C)isadded tothedestinationoperandminus one.The previouscontents ofthedestinationarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB oftheresult,resetotherwise Setto1 ifno borrow,resetifborrow V: Setifan arithmeticoverflowoccurs,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 8-bitcounterpointedtoby R13 issubtractedfroma 16-bitcounterpointedtoby R12. SUBX.B@R13,0(R12);SubtractLSDs SBCX.B1(R12) ;SubtractcarryfromMSD NOTE: Borrow implementation The borrowistreatedas a .NOT. carry: Borrow CarryBit Yes 0 No 1 265SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.32SUBX SUBX.A Subtractsourceaddress-wordfromdestinationaddress-word SUBX.[W] Subtractsourceword fromdestinationword SUBX.B Subtractsourcebytefromdestinationbyte SUBX.Asrc,dstSyntax SUBXsrc,dstor SUBX.Wsrc,dst SUBX.Bsrc,dst Operation (.not.src)+ 1 + dst→ dst or dst– src→ dst Description The sourceoperandissubtractedfromthedestinationoperand.Thisisdone by adding the1s complement ofthesource+ 1 tothedestination.The sourceoperandisnot affected.The resultiswrittentothedestinationoperand.Bothoperandsmay be located inthefulladdressspace. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src≤ dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example A 20-bitconstant87654h issubtractedfromEDE (LSBs)and EDE+2 (MSBs). SUBX.A#87654h,EDE;Subtract87654hfromEDE+2|EDE Example A tableword pointedtoby R5 (20-bitaddress)issubtractedfromR7. Jump tolabel TONI ifR7 containszeroaftertheinstruction.R5 isauto-incrementedby two.R7.19:16= SUBX.W@R5+,R7 ;SubtracttablenumberfromR7.R5+2 JZ TONI ;R7=@R5(beforesubtraction) ... ;R7<>@R5(beforesubtraction) Example ByteCNT issubtractedfromthebyteR12 pointstointhefulladdressspace.Addressof CNT iswithinPC ± 512 K. SUBX.BCNT,0(R12);SubtractCNTfrom@R12 Note:Use SUBA forthefollowingtwo casesforbetterdensityand execution. SUBX.ARsrc,Rdst SUBX.A#imm20,Rdst

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.33SUBCX SUBCX.A Subtractsourceaddress-wordwithcarryfromdestinationaddress-word SUBCX.[W] Subtractsourceword withcarryfromdestinationword SUBCX.B Subtractsourcebytewithcarryfromdestinationbyte SUBCX.Asrc,dstSyntax SUBCXsrc,dstor SUBCX.Wsrc,dst SUBCX.Bsrc,dst Operation (.not.src)+ C + dst→ dst or dst– (src– 1)+ C → dst Description The sourceoperandissubtractedfromthedestinationoperand.Thisismade by adding the1s complement ofthesource+ carrytothedestination.The sourceoperandisnot affected,theresultiswrittentothedestinationoperand.Bothoperandsmay be located inthefulladdressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesourceoperand froma negativedestinationoperanddeliversa positiveresult,resetotherwise(no overflow). Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example A 20-bitconstant87654h issubtractedfromR5 withthecarryfromtheprevious instruction. SUBCX.A#87654h,R5;Subtract87654h+CfromR5 Example A 48-bitnumber (3words)pointedtoby R5 (20-bitaddress)issubtractedfroma 48-bit counterinRAM, pointedtoby R7. R5 auto-incrementstopointtothenext48-bitnumber. SUBX.W@R5+,0(R7);SubtractLSBs.R5+2 SUBCX.W@R5+,2(R7);SubtractMIDswithC.R5+2 SUBCX.W@R5+,4(R7);SubtractMSBswithC.R5+2 Example ByteCNT issubtractedfromthebyteR12 pointsto.The carryofthepreviousinstruction isused.20-bitaddresses. SUBCX.B&CNT,0(R12);SubtractbyteCNTfrom@R12 267SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Before SWPBX.A After SWPBX.A X 19 16 31 20 X 15 8 7 0 High ByteLow Byte0 19 1631 20 X 15 8 7 0 15 8 7 0 Low Byte Low ByteHigh Byte High Byte Before SWPBX.A After SWPBX.A X X ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.34SWPBX SWPBX.A Swap bytesoflowerword SWPBX.[W] Swap bytesofword SWPBX.AdstSyntax SWPBXdstor SWPBX.Wdst Operation dst.15:8↔ dst.7:0 Description Registermode: Rn.15:8areswapped withRn.7:0.When the.Aextensionisused, Othermodes: When the.Aextensionisused,bits31:20ofthedestinationaddressare cleared,bits19:16areleftunchanged,and bits15:8areswapped withbits7:0.When the.W extensionisused,bits15:8areswapped withbits7:0oftheaddressedword. StatusBits Statusbitsarenotaffected. Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Exchange thebytesofRAM address-wordEDE MOVX.A#23456h,&EDE ;23456h->EDE SWPBX.AEDE ;25634h->EDE Example Exchange thebytesofR5 MOVA #23456h,R5;23456h->R5 SWPBX.WR5 ;05634h->R5 Figure4-55.Swap Bytes SWPBX.A RegisterMode Figure4-56.Swap Bytes SWPBX.A InMemory

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X ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription Figure4-57.Swap Bytes SWPBX[.W] RegisterMode Figure4-58.Swap Bytes SWPBX[.W] InMemory 269SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

S 15 8 7 6 019 16 S 19 16 SXTX[.W] Rdst SXTX[.W] dst 15 8 7 6 019 162031 19 16 15 8 7 6 019 16 S 19 16 SXTX.A Rdst SXTX.A dst ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.35SXTX SXTX.A Extendsignoflowerbytetoaddress-word SXTX.[W] Extendsignoflowerbytetoword SXTX.AdstSyntax SXTXdstor SXTX.Wdst Operation dst.7→ dst.15:8,Rdst.7→ Rdst.19:8(Registermode) Description Registermode: The signofthelowbyteoftheoperand(Rdst.7)isextendedintothebits Rdst.19:8. Othermodes: SXTX.A: thesignofthelowbyteoftheoperand(dst.7)isextendedinto dst.19:8.The bitsdst.31:20arecleared. SXTX[.W]:thesignofthelowbyteoftheoperand(dst.7)isextendedintodst.15:8. StatusBits N: Setifresultisnegative,resetotherwise Z: Setifresultiszero,resetotherwise C: Setifresultisnotzero,resetotherwise(C = .not.Z) V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The signed8-bitdatainEDE.7:0issignextendedto20 bits:EDE.19:8.Bits31:20 locatedinEDE+2 arecleared. SXTX.A&EDE ;SignextendedEDE->EDE+2/EDE Figure4-59.Sign Extend SXTX.A Figure4-60.Sign Extend SXTX[.W]

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.3.36TSTX *TSTX.A Testdestinationaddress-word *TSTX.[W] Testdestinationword *TSTX.B Testdestinationbyte TSTX.AdstSyntax TSTXdstor TSTX.Wdst TSTX.Bdst Operation dst+ 0FFFFFh + 1 dst+ 0FFFFh + 1 dst+ 0FFh + 1 CMPX.A#0,dstEmulation CMPX#0,dst CMPX.B#0,dst Description The destinationoperandiscompared withzero.The statusbitsaresetaccordingtothe result.The destinationisnotaffected. StatusBits N: Setifdestinationisnegative,resetifpositive Z: Setifdestinationcontainszero,resetotherwise C: Set V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example RAM byteLEO istested;PC ispointingtouppermemory. Ifitisnegative,continueat LEONEG; ifitispositivebutnotzero,continueatLEOPOS. TSTX.BLEO ;TestLEO JN LEONEG ;LEOisnegative JZ LEOZERO;LEOiszero 271SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.3.37XORX XORX.A ExclusiveOR sourceaddress-wordwithdestinationaddress-word XORX.[W] ExclusiveOR sourceword withdestinationword XORX.B ExclusiveOR sourcebytewithdestinationbyte XORX.Asrc,dstSyntax XORXsrc,dstor XORX.Wsrc,dst XORX.Bsrc,dst Operation src.xor.dst→ dst Description The sourceand destinationoperandsareexclusivelyORed. The resultisplacedinto thedestination.The sourceoperandisnotaffected.The previouscontentsofthe destinationarelost.Bothoperandsmay be locatedinthefulladdressspace. StatusBits N: Setifresultisnegative(MSB = 1),resetifpositive(MSB = 0) Z: Setifresultiszero,resetotherwise C: Setifresultisnotzero,resetotherwise(carry= .not.Zero) V: Setifbothoperandsarenegative(beforeexecution),resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Togglebitsinaddress-wordCNTR (20-bitdata)withinformationinaddress-wordTONI (20-bitaddress) XORX.ATONI,&CNTR ;TogglebitsinCNTR Example A tableword pointedtoby R5 (20-bitaddress)isused totogglebitsinR6. XORX.W@R5,R6 ;TogglebitsinR6.R6.19:16=0 Example ResettozerothosebitsinthelowbyteofR7 thataredifferentfromthebitsinbyteEDE (20-bitaddress) XORX.BEDE,R7 ;Setdifferentbitsto1inR7 INV.BR7 ;InvertlowbyteofR7.R7.19:8=0.

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4.6.4 Address Instructions

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.4.1 ADDA

ADDA Add 20-bitsourcetoa 20-bitdestinationregister ADDARsrc,RdstSyntax ADDA#imm20,Rdst Operation src+ Rdst→ Rdst Description The 20-bitsourceoperandisadded tothe20-bitdestinationCPU register.The previous contentsofthedestinationarelost.The sourceoperandisnotaffected. StatusBits N: Setifresultisnegative(Rdst.19= 1),resetifpositive(Rdst.19= 0) Z: Setifresultiszero,resetotherwise C: Setifthereisa carryfromthe20-bitresult,resetotherwise V: Setiftheresultoftwo positiveoperandsisnegative,oriftheresultoftwo negative numbers ispositive,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example R5 isincreasedby 0A4320h.The jump toTONI isperformedifa carryoccurs. ADDA#0A4320h,R5;AddA4320hto20-bitR5 JC TONI ;Jumponcarry ... ;Nocarryoccurred

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4.6.4.2 BRA

*BRA Branchtodestination BRAdstSyntax Operation dst→ PC MOVAdst,PCEmulation Description An unconditionalbranchistakentoa 20-bitaddressanywhere inthefulladdress space.Allseven sourceaddressingmodes can be used.The branchinstructionisan address-wordinstruction.Ifthedestinationaddressiscontainedina memory location X,itiscontainedintwo ascendingwords:X (LSBs)and (X + 2)(MSBs). StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Examples Examples foralladdressingmodes aregiven. Immediatemode: BranchtolabelEDE locatedanywhere inthe20-bitaddressspace or branchdirectlytoaddress. BRA #EDE ;MOVA#imm20,PC BRA #01AA04h Symbolicmode: Branchtothe20-bitaddresscontainedinaddressesEXEC (LSBs)and EXEC+2 (MSBs).EXEC islocatedattheaddress(PC + X) where X iswithin+32 K. Indirectaddressing. BRA EXEC ;MOVAz16(PC),PC Note:Ifthe16-bitindexisnotsufficient,a 20-bitindexmay be used withthefollowing instruction. MOVX.AEXEC,PC;1Mbyterangewith20-bitindex Absolutemode: Branchtothe20-bitaddresscontainedinabsoluteaddressesEXEC (LSBs)and EXEC+2 (MSBs).Indirectaddressing. BRA &EXEC ;MOVA&abs20,PC Registermode: Branchtothe20-bitaddresscontainedinregisterR5. IndirectR5. BRA R5 ;MOVAR5,PC Indirectmode: Branchtothe20-bitaddresscontainedintheword pointedtoby register R5 (LSBs).The MSBs have theaddress(R5 + 2).Indirect,indirectR5. BRA @R5 ;MOVA@R5,PC 275SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com Indirect,Auto-Incrementmode: Branchtothe20-bitaddresscontainedinthewords pointedtoby registerR5 and incrementtheaddressinR5 afterwardsby 4.The next timethesoftwareflowuses R5 as a pointer,itcan altertheprogramexecutiondue to accesstothenextaddressinthetablepointedtoby R5. Indirect,indirectR5. BRA @R5+ ;MOVA@R5+,PC.R5+4 Indexedmode: Branchtothe20-bitaddresscontainedintheaddresspointedtoby register(R5 + X) (forexample,a tablewithaddressesstartingatX).(R5 + X) pointsto theLSBs, (R5 + X + 2)pointstotheMSBs oftheaddress.X iswithinR5 + 32 K. Indirect,indirect(R5 + X). BRA X(R5) ;MOVAz16(R5),PC Note:Ifthe16-bitindexisnotsufficient,a 20-bitindexX may be used withthefollowing instruction: MOVX.AX(R5),PC;1Mbyterangewith20-bitindex

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4.6.4.3 CALLA

Operation dst→ tmp 20-bitdstisevaluatedand stored SP – 2 → SP PC.19:16→ @SP updatedPC withreturnaddresstoTOS (MSBs) SP – 2 → SP PC.15:0→ @SP updatedPC toTOS (LSBs) tmp → PC saved 20-bitdsttoPC Description A subroutinecallismade toa 20-bitaddressanywhere inthefulladdressspace.All seven sourceaddressingmodes can be used.The callinstructionisan address-word instruction.Ifthedestinationaddressiscontainedina memory locationX,itis containedintwo ascendingwords,X (LSBs)and (X + 2)(MSBs).Two words on the stackareneeded forthereturnaddress.The returnismade withtheinstructionRETA. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Examples Examples foralladdressingmodes aregiven. Immediatemode: Calla subroutineatlabelEXEC orcalldirectlyan address. CALLA#EXEC ;StartaddressEXEC CALLA#01AA04h;Startaddress01AA04h Symbolicmode: Calla subroutineatthe20-bitaddresscontainedinaddressesEXEC (LSBs)and EXEC+2 (MSBs).EXEC islocatedattheaddress(PC + X) where X is within+32 K.Indirectaddressing. CALLAEXEC ;Startaddressat@EXEC.z16(PC) Absolutemode: Calla subroutineatthe20-bitaddresscontainedinabsoluteaddresses EXEC (LSBs)and EXEC+2 (MSBs).Indirectaddressing. CALLA&EXEC ;Startaddressat@EXEC Registermode: Calla subroutineatthe20-bitaddresscontainedinregisterR5. Indirect R5. CALLAR5 ;Startaddressat@R5 Indirectmode: Calla subroutineatthe20-bitaddresscontainedintheword pointedto by registerR5 (LSBs).The MSBs have theaddress(R5 + 2).Indirect,indirectR5. CALLA@R5 ;Startaddressat@R5 277SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com Indirect,Auto-Incrementmode: Calla subroutineatthe20-bitaddresscontainedinthe words pointedtoby registerR5 and incrementthe20-bitaddressinR5 afterwardsby 4. The nexttimethesoftwareflowuses R5 as a pointer,itcan altertheprogramexecution due toaccesstothenextword addressinthetablepointedtoby R5. Indirect,indirect R5. CALLA@R5+ ;Startaddressat@R5.R5+4 Indexedmode: Calla subroutineatthe20-bitaddresscontainedintheaddresspointed toby register(R5 + X);forexample,a tablewithaddressesstartingatX.(R5 + X) pointstotheLSBs, (R5 + X + 2)pointstotheMSBs oftheword address.X iswithinR5 + 32 K.Indirect,indirect(R5 + X). CALLAX(R5) ;Startaddressat@(R5+X).z16(R5)

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4.6.4.4 CLRA

*CLRA Clear20-bitdestinationregister CLRARdstSyntax Operation 0 → Rdst MOVA#0,RdstEmulation Description The destinationregisteriscleared. StatusBits Statusbitsarenotaffected. Example The 20-bitvalueinR10 iscleared. CLRAR10 ;0->R10 279SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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4.6.4.5 CMPA

CMPA Compare the20-bitsourcewitha 20-bitdestinationregister CMPARsrc,RdstSyntax CMPA#imm20,Rdst Operation (.not.src)+ 1 + Rdst or Rdst– src Description The 20-bitsourceoperandissubtractedfromthe20-bitdestinationCPU register.This ismade by addingthe1s complement ofthesource+ 1 tothedestinationregister.The resultaffectsonlythestatusbits. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src≤ dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB, resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesource operandfroma negativedestinationoperanddeliversa positiveresult,reset otherwise(nooverflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example A 20-bitimmediateoperandand R6 arecompared.Iftheyareequal,theprogram continuesatlabelEQUAL. CMPA#12345h,R6;CompareR6with12345h JEQ EQUAL ;R6=12345h ... ;Notequal Example The 20-bitvaluesinR5 and R6 arecompared.IfR5 isgreaterthan(signed)orequalto R6, theprogramcontinuesatlabelGRE. CMPAR6,R5 ;CompareR6withR5(R5-R6) JGE GRE ;R5>=R6 ... ;R5<R6

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4.6.4.6 DECDA

*DECDA Double-decrement20-bitdestinationregister DECDARdstSyntax Operation Rdst– 2 → Rdst SUBA#2,RdstEmulation Description The destinationregisterisdecrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: SetifRdstcontained2,resetotherwise C: ResetifRdstcontained0 or1,setotherwise V: Setifan arithmeticoverflowoccurs,otherwisereset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR5 isdecrementedby 2. DECDAR5 ;DecrementR5bytwo 281SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com

4.6.4.7 INCDA

*INCDA Double-increment20-bitdestinationregister INCDARdstSyntax Operation Rdst+ 2 → Rdst ADDA#2,RdstEmulation Description The destinationregisterisincrementedby two.The originalcontentsarelost. StatusBits N: Setifresultisnegative,resetifpositive Z: SetifRdstcontained0FFFFEh, resetotherwise SetifRdstcontained0FFFEh, resetotherwise SetifRdstcontained0FEh, resetotherwise C: SetifRdstcontained0FFFFEh or0FFFFFh, resetotherwise SetifRdstcontained0FFFEh or0FFFFh, resetotherwise SetifRdstcontained0FEh or0FFh,resetotherwise V: SetifRdstcontained07FFFEh or07FFFFh, resetotherwise SetifRdstcontained07FFEh or07FFFh, resetotherwise SetifRdstcontained07Eh or07Fh,resetotherwise Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR5 isincrementedby two. INCDAR5 ;IncrementR5bytwo

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4.6.4.8 MOVA

MOVA Move the20-bitsourcetothe20-bitdestination MOVARsrc,RdstSyntax MOVA#imm20,Rdst MOVAz16(Rsrc),Rdst MOVAEDE,Rdst MOVA&abs20,Rdst MOVA@Rsrc,Rdst MOVA@Rsrc+,Rdst MOVARsrc,z16(Rdst) MOVARsrc,&abs20 Operation src→ Rdst Rsrc→ dst Description The 20-bitsourceoperandismoved tothe20-bitdestination.The sourceoperandisnot affected.The previouscontentofthedestinationislost. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Examples Copy 20-bitvalueinR9 toR8 MOVAR9,R8 ;R9->R8 Write20-bitimmediatevalue12345h toR12 MOVA#12345h,R12;12345h->R12 Copy 20-bitvalueaddressedby (R9 + 100h)toR8. Sourceoperandinaddresses(R9 + 100h)LSBs and (R9 + 102h)MSBs. MOVA100h(R9),R8;Index:+32K.2wordstransferred Move 20-bitvaluein20-bitabsoluteaddressesEDE (LSBs)and EDE+2 (MSBs) toR12 MOVA&EDE,R12 ;&EDE->R12.2wordstransferred Move 20-bitvaluein20-bitaddressesEDE (LSBs)and EDE+2 (MSBs) toR12. PC index± 32 K. MOVAEDE,R12 ;EDE->R12.2wordstransferred Copy 20-bitvalueR9 pointsto(20bitaddress)toR8. Sourceoperandinaddresses @R9 LSBs and @(R9 + 2)MSBs. MOVA@R9,R8 ;@R9->R8.2wordstransferred 283SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com Copy 20-bitvalueR9 pointsto(20bitaddress)toR8. R9 isincrementedby four afterwards.Sourceoperandinaddresses@R9 LSBs and @(R9 + 2)MSBs. MOVA@R9+,R8 ;@R9->R8.R9+4.2wordstransferred. Copy 20-bitvalueinR8 todestinationaddressedby (R9 + 100h).Destinationoperand inaddresses@(R9 + 100h)LSBs and @(R9 + 102h)MSBs. MOVAR8,100h(R9);Index:+-32K.2wordstransferred Move 20-bitvalueinR13 to20-bitabsoluteaddressesEDE (LSBs)and EDE+2 (MSBs) MOVAR13,&EDE ;R13->EDE.2wordstransferred Move 20-bitvalueinR13 to20-bitaddressesEDE (LSBs)and EDE+2 (MSBs).PC index± 32 K. MOVAR13,EDE ;R13->EDE.2wordstransferred

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4.6.4.9 RETA

*RETA Returnfromsubroutine RETASyntax Operation @SP → PC.15:0LSBs (15:0)ofsaved PC toPC.15:0 SP + 2 → SP @SP → PC.19:16MSBs (19:16)ofsaved PC toPC.19:16 SP + 2 → SP MOVA@SP+,PCEmulation Description The 20-bitreturnaddressinformation,pushed ontothestackby a CALLA instruction,is restoredtothePC. The programcontinuesattheaddressfollowingthesubroutinecall. The SR bitsSR.11:0arenotaffected.Thisallowsthetransferofinformationwiththese bits. StatusBits N: Not affected Z: Not affected C: Not affected V: Not affected Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example Calla subroutineSUBR fromanywhere inthe20-bitaddressspace and returntothe addressaftertheCALLA CALLA#SUBR ;CallsubroutinestartingatSUBR ... ;ReturnbyRETAtohere SUBRPUSHM.A#2,R14;SaveR14andR13(20bitdata) ... ;Subroutinecode POPM.A#2,R14;RestoreR13andR14(20bitdata) RETA ;Return(tofulladdressspace) 285SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. InstructionSetDescription www.ti.com 4.6.4.10SUBA SUBA Subtract20-bitsourcefrom20-bitdestinationregister SUBARsrc,RdstSyntax SUBA#imm20,Rdst Operation (.not.src)+ 1 + Rdst→ Rdst or Rdst– src→ Rdst Description The 20-bitsourceoperandissubtractedfromthe20-bitdestinationregister.Thisis made by addingthe1s complement ofthesource+ 1 tothedestination.The resultis writtentothedestinationregister,thesourceisnotaffected. StatusBits N: Setifresultisnegative(src> dst),resetifpositive(src≤ dst) Z: Setifresultiszero(src= dst),resetotherwise(src≠ dst) C: Setifthereisa carryfromtheMSB (Rdst.19),resetotherwise V: Setifthesubtractionofa negativesourceoperandfroma positivedestination operanddeliversa negativeresult,orifthesubtractionofa positivesource operandfroma negativedestinationoperanddeliversa positiveresult,reset otherwise(nooverflow) Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR5 issubtractedfromR6. Ifa carryoccurs,theprogramcontinuesat labelTONI. SUBAR5,R6;R6-R5->R6 JC TONI ;Carryoccurred ... ;Nocarry

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com InstructionSetDescription 4.6.4.11TSTA *TSTA Test20-bitdestinationregister TSTARdstSyntax Operation dst+ 0FFFFFh + 1 dst+ 0FFFFh + 1 dst+ 0FFh + 1 CMPA#0,RdstEmulation Description The destinationregisteriscompared withzero.The statusbitsaresetaccordingtothe result.The destinationregisterisnotaffected. StatusBits N: Setifdestinationregisterisnegative,resetifpositive Z: Setifdestinationregistercontainszero,resetotherwise C: Set V: Reset Mode Bits OSCOFF, CPUOFF, and GIE arenotaffected. Example The 20-bitvalueinR7 istested.Ifitisnegative,continueatR7NEG; ifitispositivebut notzero,continueatR7POS. TSTAR7 ;TestR7 JN R7NEG ;R7isnegative JZ R7ZERO;R7iszero 287SLAU259E –May 2009–RevisedJanuary2013 CPUX SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter5 SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller Thischapterdescribestheoperationoftheflashmemory controller.

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Control Registers Address/Data Latch Timing Generator Programming Voltage Generator Flash Memory Array ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Introduction

5.1 FlashMemory Introduction

The flashmemory isbyte,word,and long-wordaddressableand programmable.The flashmemory module has an integratedcontrollerthatcontrolsprogrammingand eraseoperations.The module contains threeregisters,a timinggenerator,and a voltagegeneratortosupplyprogramand erasevoltages.The cumulativehigh-voltagetimemust notbe exceeded,and each 32-bitword can be writtennotmore than fourtimes(inbyte,word,orlongword writemodes) beforeanothererasecycle(seedevice-specificdata sheetfordetails). The flashmemory featuresinclude:

Internalprogrammingvoltagegeneration
Byte,word (2bytes),and long(4bytes)programmable
Ultralowpower operation
Segment erase,bank erase(devicespecific),and mass erase
Marginal0 and marginal1 readmodes
Each bank (devicespecific)can be erasedindividuallywhileprogramexecutioncan proceedina differentflashbank. NOTE: Bank operationsarenotsupportedon alldevices.See thedevice-specificdatasheetfor banks supportedand theirrespectivesizes. The blockdiagramoftheflashmemory and controllerisshown inFigure5-1. Figure5-1.FlashMemory Module Block Diagram 289SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Segment□126 Segment□127 Segment X ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Segmentation www.ti.com

5.2 FlashMemory Segmentation

The flashmain memory ispartitionedinto512-bytesegments.Singlebits,bytes,orwords can be written toflashmemory, buta segment isthesmallestsizeoftheflashmemory thatcan be erased. The flashmemory ispartitionedintomain and informationmemory sections.Thereisno differenceinthe operationofthemain and informationmemory sections.Code and datacan be locatedineithersection. The differencebetween thesectionsisthesegment size. Therearefourinformationmemory segments,A throughD. Each informationmemory segment contains 128 bytesand can be erasedindividually. The bootstraploader(BSL)memory consistsoffoursegments,A throughD. Each BSL memory segment contains512 bytesand can be erasedindividually. The main memory segment sizeis512 byte.See thedevice-specificdatasheetforthestartand end addressesofeach bank,when available,and forthecompletememory map ofa device. Figure5-2shows theflashsegmentationusingan example of256-KB flashthathas fourbanks of64 KB (segmentsA throughD) and informationmemory. Figure5-2.256-KB FlashMemory Segments Example

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5.2.1 Segment A

Segment A oftheinformationmemory islockedseparatelyfromallothersegments withtheLOCKA bit.If LOCKA = 1,segment A cannotbe writtenorerased,and allinformationmemory isprotectedfrombeing segment erased.IfLOCKA = 0,segment A can be erasedand writtenlikeany otherflashmemory segment. The stateoftheLOCKA bitistoggledwhen a 1 iswrittentoit.Writinga 0 toLOCKA has no effect.This allowsexistingflashprogrammingroutinestobe used unchanged. ;UnlockInfoMemory MOV #FWPW,&FCTL4 ;ClearLOCKINFO,ifset ;UnlockSegmentA BIT #LOCKA,&FCTL3 ;TestLOCKA JZ SEGA_UNLOCKED;Alreadyunlocked? MOV #FWPW+LOCKA,&FCTL3 ;No,unlockSegmentA SEGA_UNLOCKED ;Yes,continue ;SegmentAisunlocked ;LockSegmentA BIT #LOCKA,&FCTL3 ;TestLOCKA JNZ SEGA_LOCKED ;Alreadylocked? MOV #FWPW+LOCKA,&FCTL3 ;No,lockSegmentA SEGA_LOCKED ;Yes,continue ;SegmentAislocked ;LockInfoMemory MOV #FWPW+LOCKINFO,&FCTL4;SetLOCKINFO 291SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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5.3 FlashMemory Operation

The defaultmode oftheflashmemory isreadmode. Inreadmode, theflashmemory isnotbeingerased orwritten,theflashtiminggeneratorand voltagegeneratorareoff,and thememory operatesidenticallyto ROM. Read and fetchwhileerase– The flashmemory allowsexecutionofa programfromflashwhilea differentflashbank iserased.Data readsarealsopossiblefromany flashbank notbeingerased. NOTE: Read and fetchwhileerase The readand fetchwhileerasefeatureisavailableinflashmemory configurationswhere more thanone flashbank isavailable.Ifthereisone flashbank available,holdingthe completeflashprogrammemory, thereadfromtheprogrammemory and information memory and BSL memory duringtheeraseisnotprovided.Table5-1summarizeswhich flashoperationsaresupportedfordevicesthatsupportreadand fetchwhileerasing. Table5-1.Supported Simultaneous Code Executionand FlashOperations Simultaneous Code Execution FlashOperation WithinFlash WithinRAM Bank Erase Supported Supported Executedcode must notresideinthe bank tobe erased Segment Erase Not Supported Supported Byte,word,long-wordwrite Not supported Supported Flashmemory isin-systemprogrammable(ISP)withouttheneed foradditionalexternalvoltage.The CPU can programtheflashmemory. The flashmemory writeand erasemodes areselectedby theBLKWRT, WRT, MERAS, and ERASE bitsand are:

Byte,word,orlong-word(32-bit)write
Blockwrite
Segment erase
Bank erase(onlymain memory)
Mass erase(allmain memory banks)
Read duringbank erase(exceptfortheone currentlyreadfrom) Readingorwritingtoflashmemory whileitisbusy programmingorerasing(page,mass, orbank)from thesame bank isprohibited.Any flasheraseorprogrammingcan be initiatedfromwithinflashmemory or RAM.

5.3.1 ErasingFlashMemory

The logicalvalueofan erasedflashmemory bitis1.Each bitcan be programmed from1 to0 individually, buttoreprogramfrom0 to1 requiresan erasecycle.The smallestamount offlashthatcan be erasedis one segment.Therearethreeerasemodes selectedby theERASE and MERAS bitslistedinTable5-2. Table5-2.Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Bank erase(ofone bank)selectedby thedummy writeaddress(1) 1 1 Mass erase(allmemory banks areerased.Informationmemory A toD and BSL segments A toD are noterased) (1) Bank operationsarenotsupportedon alldevices.See thedevice-specificdatasheetforsupportofbank operations.

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Erase□Operation Active Erase□Time,□Current□Consumption□is□Increased Generate Programming□Voltage Remove Programming□Voltage t =□tErase Mass_erase, Segment_erase, Bank_erase ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.1.1 Erase Cycle

An erasecycleisinitiatedby a dummy writetotheaddressrangeofthesegment tobe erased.The dummy writestartstheeraseoperationand isrequiredforalleraseoperationsincludingmass erase. Figure5-3shows theerasecycletiming.The BUSY bitissetimmediatelyafterthedummy writeand remainssetthroughouttheerasecycle.BUSY, MERAS, and ERASE areautomaticallyclearedwhen the cyclecompletes.No additionaldummy writeaccessshouldbe made whilethecontrolbitsarecleared, otherwise,ACCVIFG isset.The mass erasecycletimingisnotdependenton theamount offlashmemory presenton a device.Erasecycletimesareequivalentforalldevices. Figure5-3.Erase Cycle Timing

5.3.1.2 ErasingMain Memory

The main memory consistsofone ormore banks.Each bank can be erasedindividually(bankerase).All main memory banks can be erasedinthemass erasemode.

5.3.1.3 ErasingInformationMemory or BSL FlashSegments

The informationmemory A toD and theBSL segments A toD can onlybe erasedinsegment erase mode. They arenoterasedduringa bank eraseora mass erase.Erasingisonlypossibleby firstclearing theLOCKINFO bit. 293SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Yes BUSY =□1 Disable□watchdog Setup□flash□controller□and erase□mode Dummy□write reenable watchdog ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.1.4 InitiatingErase From Flash

An erasecyclecan be initiatedfromwithinflashmemory. Duringa bank erase,code can be executed fromflashorRAM. The executedcode cannotbe locatedina bank tobe erased. Forany segment erase,theCPU ishelduntiltheerasecyclecompletesregardlessofthebank thecode residesin.Afterthesegment erasecycleends,theCPU resumes code executionwiththeinstruction followingthedummy write. When initiatingan erasecyclefromwithinflashmemory, itispossibletoerasethecode needed for executionaftertheeraseoperation.Ifthisoccurs,CPU executionisunpredictableaftertheerasecycle. The flowtoinitiatean erasefromflashisshown inFigure5-4. Figure5-4.Erase Cycle From Flash ;SegmentErasefromflash. ;AssumesProgramMemory.InformationmemoryorBSL ;requiresLOCKINFOtobeclearedaswell. ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT L1BIT#BUSY,&FCTL3 ;TestBUSY JNZL1 ;Loopwhilebusy MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+ERASE,&FCTL1 ;Enablesegmenterase CLR&0FC10h ;Dummywrite L2BIT#BUSY,&FCTL3 ;TestBUSY JNZL2 ;Loopwhilebusy MOV#FWPW+LOCK,&FCTL3 ;Done,setLOCK ... ;Re-enableWDT?

294 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

Yes BUSY =□1 Yes BUSY =□1 Disable□watchdog Setup□flash□controller□and erase□mode Dummy□write Reenable□watchdog ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.1.5 InitiatingErase From RAM

An erasecyclecan be initiatedfromRAM. Inthiscase,theCPU isnotheldand continuestoexecute code fromRAM. The mass erase(allmain memory banks)operationisinitiatedwhileexecutingfrom RAM. The BUSY bitisused todeterminetheend oftheerasecycle.Iftheflashisbusy completinga bank erase,flashaddressesofa differentbank can be used toreaddataortofetchinstructions.Whiletheflash isBUSY, startingan erasecycleora programmingcyclecausesan accessviolation,ACCIFG issetto1, and theresultoftheeraseoperationisunpredictable. The flowtoinitiatean erasefromflashfromRAM isshown inFigure5-5. Figure5-5.Erase Cycle From RAM ;segmentErasefromRAM. ;AssumesProgramMemory.InformationmemoryorBSL ;requiresLOCKINFOtobeclearedaswell. ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT L1BIT#BUSY,&FCTL3 ;TestBUSY JNZL1 ;Loopwhilebusy MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+ERASE,&FCTL1 ;Enablepageerase CLR&0FC10h ;Dummywrite L2BIT#BUSY,&FCTL3 ;TestBUSY JNZL2 ;Loopwhilebusy MOV#FWPW+LOCK,&FCTL3 ;Done,setLOCK ... ;Re-enableWDT? 295SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Programming□Operation Active Programming□Time,□V Current□Consumption□is□IncreasedCC tWrite Generate Programming□Voltage Remove Programming□Voltage ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.2 WritingFlashMemory

The writemodes, selectedby theWRT and BLKWRT bits,arelistedinTable5-3. Table5-3.WriteModes BLKWRT WRT WriteMode 0 1 Byteorword write 1 0 Long-wordwrite 1 1 Long-wordblockwrite The writemodes use a sequence ofindividualwriteinstructions.Usingthelong-wordwritemode is approximatelytwiceas fastas thebyteorword mode. Usingthelong-wordblockwritemode is approximatelyfourtimesfasterthanbyteorword mode, because thevoltagegeneratorremainson forthe completeblockwrite,and long-wordsarewritteninparallel.Any instructionthatmodifiesa destinationcan be used tomodifya flashlocationineitherbyteorword writemode, long-wordwritemode, orblocklong- word writemode. The BUSY bitissetwhilethewriteoperationisactiveand clearedwhen theoperationcompletes.Ifthe writeoperationisinitiatedfromRAM, theCPU must notaccessflashwhileBUSY issetto1.Otherwise, an accessviolationoccurs,ACCVIFG isset,and theflashwriteisunpredictable.

5.3.2.1 Byte or Word Write

A byteorword writeoperationcan be initiatedfromwithinflashmemory orfromRAM. When initiating fromwithinflashmemory, theCPU isheldwhilethewritecompletes.Afterthewritecompletes,theCPU resumes code executionwiththeinstructionfollowingthewriteaccess.The byte,word,and long-word writetimingisshown inFigure5-6.Byte,word,and long-wordwritetimesareidentical. Figure5-6.Byte,Word, and Long-Word WriteTiming When a byteorword writeisexecutedfromRAM, theCPU continuestoexecutecode fromRAM. The BUSY bitmust be zerobeforetheCPU accessesflashagain,otherwisean accessviolationoccurs, ACCVIFG isset,and thewriteresultisunpredictable. Inany writemode, theinternally-generatedprogrammingvoltageisappliedtothecomplete128-byte block.The cumulativeprogrammingtime,tCPT ,must notbe exceeded forany block.Each byte,word,or long-wordwriteadds tothecumulativeprogramtimeofa segment.Ifthemaximum cumulativeprogram timeisreachedorexceeded,thesegment must be erased.Furtherprogrammingorusingthedatareturns unpredictableresults(seethedevice-specificdatasheetforspecifications).

296 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

and set WRT = 1 Disable watchdog Set WRT = 0, LOCK = 1, reenable watchdog Write byte or word ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.2.2 InitiatingByte or Word WriteFrom Flash

The flowtoinitiatea byteorword writefromflashisshown inFigure5-7. Figure5-7.Initiatinga Byte or Word WriteFrom Flash ;Byteorwordwritefromflash. ;Assumes0x0FF1Eisalreadyerased ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+WRT,&FCTL1 ;Enablewrite MOV#0123h,&0FF1Eh ;0123h->0x0FF1E MOV#FWPW,&FCTL1 ;Done.ClearWRT MOV#FWPW+LOCK,&FCTL3 ;SetLOCK ... ;Re-enableWDT? 297SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

BUSY = 1 Yes BUSY = 1 Disable watchdog Setup flash controller and set WRT = 1 Write byte or word Set WRT = 0, LOCK = 1, Reenable watchdog ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.2.3 InitiatingByte or Word WriteFrom RAM

The flowtoinitiatea byteorword writefromRAM isshown inFigure5-8. Figure5-8.Initiatinga Byte or Word WriteFrom RAM ;ByteorwordwritefromRAM. ;Assumes0x0FF1Eisalreadyerased ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT L1BIT#BUSY,&FCTL3 ;TestBUSY JNZL1 ;Loopwhilebusy MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+WRT,&FCTL1 ;Enablewrite MOV#0123h,&0FF1Eh ;0123h->0x0FF1E L2BIT#BUSY,&FCTL3 ;TestBUSY JNZL2 ;Loopwhilebusy MOV#FWPW,&FCTL1 ;ClearWRT MOV#FWPW+LOCK,&FCTL3 ;SetLOCK ... ;Re-enableWDT?

298 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

and set BLKWRT = 1 Disable watchdog Set BLKWRT = 0, LOCK = 1, Reenable watchdog Write 4 bytes or 2 words ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.2.4 Long-Word Write

A long-wordwriteoperationcan be initiatedfromwithinflashmemory orfromRAM. The BUSY bitissetto 1 after32 bitsarewrittentotheflashcontrollerand theprogrammingcyclestarts.When initiatingfrom withinflashmemory, theCPU isheldwhilethewritecompletes.Afterthewritecompletes,theCPU resumes code executionwiththeinstructionfollowingthewriteaccess.The long-wordwritetimingis shown inFigure5-6. A long-wordconsistsoffourconsecutivebytesalignedtoat32-bitaddress(onlythelowertwo address bitsaredifferent).The bytescan be writteninany orderorany combinationofbytesand words.Ifa byte orword iswrittenmore thanonce,thelastdatawrittentothefourbytesarestoredintotheflashmemory. Ifa writetoa flashaddressoutsideofthe32-bitaddresshappens beforeallfourbytesareavailable,the datawrittenso farisdiscarded,and thelatestbyteorword writtendefinesthenew 32-bitalignedaddress. When 32 bitsareavailable,thewritecycleisexecuted.When executingfromRAM, theCPU continuesto executecode.The BUSY bitmust be zerobeforetheCPU accessesflashagain,otherwisean access violationoccurs,ACCVIFG isset,and thewriteresultisunpredictable. Inlong-wordwritemode, theinternally-generatedprogrammingvoltageisappliedtoa complete128-byte block.The cumulativeprogrammingtime,tCPT ,must notbe exceeded forany block.Each writeadds tothe cumulativeprogramtimeofa segment.Ifthemaximum cumulativeprogramtimeisreachedorexceeded, thesegment must be erased.Furtherprogrammingorusingthedatareturnsunpredictableresults. Witheach write,theamount oftimetheblockissubjectedtotheprogrammingvoltageaccumulates.Ifthe cumulativeprogrammingtimeisreachedorexceeded,theblockmust be erasedbeforefurther programmingoruse (seethedevice-specificdatasheetforspecifications).

5.3.2.5 InitiatingLong-Word WriteFrom Flash

The flowtoinitiatea long-wordwritefromflashisshown inFigure5-9. Figure5-9.InitiatingLong-Word WriteFrom Flash ;Long-wordwritefromflash. ;Assumes0x0FF1Cand0x0FF1Eisalreadyerased ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+BLKWRT,&FCTL1 ;Enable2-wordwrite MOV#0123h,&0FF1Ch ;0123h->0x0FF1C MOV#45676h,&0FF1Eh ;04567h->0x0FF1E MOV#FWPW,&FCTL1 ;Done.ClearBLKWRT MOV#FWPW+LOCK,&FCTL3 ;SetLOCK ... ;Re-enableWDT? 299SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

BUSY = 1 Yes BUSY = 1 Disable watchdog Setup flash controller and set BLKWRT = 1 Write 4 bytes or 2 words Set BLKWRT=0, LOCK = 1, Reenable watchdog ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.2.6 InitiatingLong-Word WriteFrom RAM

The flowtoinitiatea long-wordwritefromRAM isshown inFigure5-10. Figure5-10.InitiatingLong-Word Writefrom RAM ;Two16-bitwordwritesfromRAM. ;Assumes0x0FF1Cand0x0FF1Eisalreadyerased ;AssumesACCVIE=NMIIE=OFIE=0. MOV#WDTPW+WDTHOLD,&WDTCTL;DisableWDT L1BIT#BUSY,&FCTL3 ;TestBUSY JNZL1 ;Loopwhilebusy MOV#FWPW,&FCTL3 ;ClearLOCK MOV#FWPW+BLKWRT,&FCTL1 ;Enablewrite MOV#0123h,&0FF1Ch ;0123h->0x0FF1C MOV#4567h,&0FF1Eh ;4567h->0x0FF1E L2BIT#BUSY,&FCTL3 ;TestBUSY JNZL2 ;Loopwhilebusy MOV#FWPW,&FCTL1 ;ClearWRT MOV#FWPW+LOCK,&FCTL3 ;SetLOCK ... ;Re-enableWDT?

300 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

tBlock,0 Write□to□Flash;□e.g., #0123h,□&Flash MOV□#4567h,□&Flash1 MOV BLKWRT□bit tBlock,1–(N-1) tBlock,N Generate Programming□Voltage Programming□Operation Active Remove Programming□Voltage Cumulative□Programming□Time□<□t ,□V Current□Consumption□is□IncreasedCPT CC ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.2.7 Block Write

The blockwritecan be used toacceleratetheflashwriteprocesswhen many sequentialbytesorwords need tobe programmed.The flashprogrammingvoltageremainson forthedurationofwritingthe128- byterow.The cumulativeprogrammingtime,tCPT ,must notbe exceeded forany row duringa blockwrite. Onlylong-wordwritesarepossibleusingblockwritemode. A blockwritecannotbe initiatedfromwithinflashmemory. The blockwritemust be initiatedfromRAM. The BUSY bitremainssetthroughoutthedurationoftheblockwrite.The WAIT bitmust be checked between writingfourbytes,ortwo words,totheblock.When WAIT isset,thenfourbytes,ortwo 16-bit words,oftheblockcan be written.When writingsuccessiveblocks,theBLKWRT bitmust be clearedafter thecurrentblockiscompleted.BLKWRT can be setinitiatingthenextblockwriteaftertherequiredflash recoverytimegivenby tEND .BUSY isclearedfollowingeach blockwritecompletion,indicatingthenext blockcan be written.Figure5-11shows theblockwritetiming.The firstlong-wordwriterequirestBlock,0and thelastlong-writerequirestBlock,N.AllotherblocksrequiretBlock,1-(N-1). Figure5-11.Block-WriteCycle Timing 301SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

BUSY = 1 Disable watchdog Setup flash controller Set BLKWRT = WRT = 1 Write 4 bytes or 2 words No Block Border? Yes WAIT = 0? Yes BUSY = 1 Set BLKWRT=0 Yes Another Block? Set WRT = 0, LOCK = 1, Reenable WDT ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.2.8 Block WriteFlow and Example

A blockwriteflowisshown inFigure5-12and thefollowingcode example. Figure5-12.Block WriteFlow

302 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation ;Writeoneblockstartingat0F000h. ;MustbeexecutedfromRAM,AssumesFlashisalreadyerased. ;AssumesACCVIE=NMIIE=OFIE=0. MOV #32,R5 ;Useaswritecounter MOV #0F000h,R6 ;Writepointer MOV #WDTPW+WDTHOLD,&WDTCTL ;DisableWDT L1BIT #BUSY,&FCTL3 ;TestBUSY JNZ L1 ;Loopwhilebusy MOV #FWPW,&FCTL3 ;ClearLOCK MOV #FWPW+BLKWRT+WRT,&FCTL1 ;Enableblockwrite L2MOV Write_Value1,0(R6);Write1stlocation MOV Write_Value2,2(R6);Write2ndword L3BIT #WAIT,&FCTL3 ;TestWAIT JZ L3 ;LoopwhileWAIT=0 INCDR6 ;Pointtonextwords INCDR6 ;Pointtonextwords DEC R5 ;Decrementwritecounter JNZ L2 ;Endofblock? MOV #FWPW,&FCTL1 ;ClearWRT,BLKWRT L4BIT #BUSY,&FCTL3 ;TestBUSY JNZ L4 ;Loopwhilebusy MOV #FWPW+LOCK,&FCTL3 ;SetLOCK ... ;Re-enableWDTifneeded

5.3.3 FlashMemory Access During Writeor Erase

When a writeoran eraseoperationisinitiatedfromRAM whileBUSY = 1,theCPU may notwritetoany flashlocation.Otherwise,an accessviolationoccurs,ACCVIFG isset,and theresultisunpredictable. ACCVIFG isalsosetifa Flashwriteoreraseaccessisattemptedwithoutany Flashwriteorerasemode selectedfirst. When a writeoperationisinitiatedfromwithinflashmemory, theCPU continuescode executionwiththe nextinstructionfetchafterthewritecyclecompleted(BUSY = 0). The op-code3FFFh istheJMP PC instruction.ThiscausestheCPU toloopuntiltheflashoperationis finished.When theoperationisfinishedand BUSY = 0,theflashcontrollerallowstheCPU tofetchtheop- code and programexecutionresumes. The flashaccessconditionswhileBUSY = 1 arelistedinTable5-4. Table5-4.FlashAccess While FlashisBusy (BUSY = 1) FlashOperation FlashAccess WAIT Result Read 0 From theerasedbank:ACCVIFG = 0.03FFFh isthevalueread. From any otherflashlocation:ACCVIFG = 0.Validread. Write 0 ACCVIFG = 1.Writeisignored.Bank erase Instructionfetch 0 From theerasedbank:ACCVIFG = 0.CPU fetches03FFFh. Thisisthe JMP PC instruction. From any otherflashlocation:ACCVIFG = 0.Validinstructionfetch. Read 0 ACCVIFG = 0:03FFFh isthevalueread. Segment erase Write 0 ACCVIFG = 1:Writeisignored. Instructionfetch 0 ACCVIFG = 0:CPU fetches03FFFh. ThisistheJMP PC instruction. Read 0 ACCVIFG = 0:03FFFh isthevalueread. Word orbytewrite Write 0 ACCVIFG = 1:Writeisignored.orlong-wordwrite Instructionfetch 0 ACCVIFG = 0:CPU fetches03FFFh. ThisistheJMP PC instruction. Any 0 ACCVIFG = 1:LOCK = 1,blockwriteisexited. Read 1 ACCVIFG = 0:03FFFh isthevalueread. Blockwrite Write 1 ACCVIFG = 0:Validwrite Instructionfetch 1 ACCVIFG = 1:LOCK = 1,blockwriteisexited 303SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com Interruptsareautomaticallydisabledduringany flashoperation. The watchdogtimer(inwatchdogmode) shouldbe disabledbeforea flasherasecycle.A resetabortsthe eraseand theresultisunpredictable.Aftertheerasecyclehas completed,thewatchdogmay be reenabled.

5.3.4 Stopping Writeor Erase Cycle

Any writeoreraseoperationcan be stoppedbeforeitsnormalcompletionby settingtheemergency exit bitEMEX. SettingtheEMEX bitstopstheactiveoperationand resetstheflashcontroller.Allflash operationscease,theflashreturnstoreadmode, and allbitsintheFCTL1 registerarereset.The LOCK bitofFCTL3 isset.The resultoftheintendedoperationisunpredictable.

5.3.4.1 EMEX With SingleBank FlashMemory

Fordeviceswithsinglebank flashmemories,writeand eraseoperationsinitiatedfromflash,theCPU is helduntiltheflashoperationcompletes.Thereforeitisnotpossibletoperforman emergency exitby the EMEX bit.The emergency exitofwriteoreraseoperationsinitiatedfromRAM can be performedusingthe EMEX bit.The BUSY bitisused todeterminetheend oftheemergency exitcycle.The usermust ensure thatcode executiondoes notcontinueuntiltheBUSY bitisclearedby theflashcontroller.

5.3.4.2 EMEX With MultipleBank FlashMemory

Fordeviceswithmultiplebank flashmemories,writeand segment eraseoperationsinitiatedfromflash, regardlessofwhichbank thecode residesin,theCPU ishelduntiltheflashoperationcompletes. Thereforeitisnotpossibletoperforman emergency exitby theEMEX bit.Forbank erase,thereisa possibilitytoperforman EMEX ifthebank beingerasedisnotwhere thecode resides.The BUSY bitis used todeterminetheend oftheemergency exitcycle.The usermust ensurethatcode executiondoes notcontinueuntiltheBUSY bitisclearedby theflashcontroller. The emergency exitofwriteorany eraseoperationsinitiatedfromRAM can be performedusingthe EMEX bit.The BUSY bitisused todeterminetheend oftheemergency exitcycle.The usermust ensure thatcode executiondoes notcontinueuntiltheBUSY bitisclearedby theflashcontroller.

5.3.5 Checking FlashMemory

The resultofa programmingcycleoftheflashmemory can be checkedby calculatingand storinga checksum (CRC) ofpartsorthecompleteflashmemory content.The CRC module can be used forthis purpose(seethedevice-specificdatasheet).Duringtheruntimeofthesystem,theknown checksums can be recalculatedand compared withtheexpectedvaluesstoredintheflashmemory. The program checkingtheflashmemory contentisexecutedinRAM. To getan earlyindicationofweak memory cells,readingtheflashcan be done incombinationwiththe device-specificmarginalreadmodes. The marginalreadmodes arecontrolledby theFCTL4.MRG0 and FCTL4.MRG1 registerbitsifavailable(devicespecific).Duringmarginalreadmode, marginally programmed flashmemory bitlocationscan be detected.One method foridentifyingsuch memory locationswouldbe toperiodicallyperforma checksum calculationovera sectionofflashmemory (for example,a flashsegment)and repeatingthisprocedurewiththemarginalreadmode enabled.Iftheydo notmatch,itcouldindicatean insufficientlyprogrammed flashmemory location.Itispossibletorefresh theaffectedFlashmemory segment by disablingmarginalreadmode, copyingtoRAM, erasingtheflash segment,and writingback toitfromRAM. The programcheckingtheflashmemory contentsmust be executedfromRAM. Executingcode fromflash automaticallydisablesthemarginalreadmode. The marginalreadmodes arecontrolledby theMRG0 and MRG1 registerbits.SettingMRG1 isused todetectinsufficientlyprogrammed flashcellscontaininga "1" (erasedbits).SettingMRG0 isused todetectinsufficientlyprogrammed flashcellscontaininga "0" (programmed bits).Onlyone ofthesebitsshouldbe setata time.Therefore,a fullmarginalreadcheck requirestwo passesofcheckingtheflashmemory content’s integrity.Duringmarginalreadmode, the flashaccessspeed (MCLK) must be limitedto1 MHz (seethedevice-specificdatasheet).

304 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FlashMemory Operation

5.3.6 Configuringand Accessing theFlashMemory Controller

The FCTLx registersare16-bitpassword-protectedreadand writeregisters.Any readorwriteaccess must use word instructions,and writeaccessesmust includethewritepassword0A5h intheupperbyte. Any writetoany FCTLx registerwitha valueotherthan0A5h intheupperbyteisa passwordviolation, setstheKEYV flag,and triggersa PUC systemreset.Any readofany FCTLx registersreads096h inthe upperbyte. Any writetoFCTL1 duringan eraseorbyte,word,double-wordwriteoperationisan accessviolationand setsACCVIFG. WritingtoFCTL1 isallowedinblockwritemode when WAIT = 1,butwritingtoFCTL1 in blockwritemode when WAIT = 0 isan accessviolationand setsACCVIFG. Any writetoFCTL2 (thisregisteriscurrentlynotimplemented)when BUSY = 1 isan accessviolation. Any FCTLx registermay be readwhen BUSY = 1.A readdoes notcause an accessviolation.

5.3.7 FlashMemory ControllerInterrupts

The flashcontrollerhas two interruptsources,KEYV and ACCVIFG. ACCVIFG issetwhen an access violationoccurs.When theACCVIE bitisreenabledaftera flashwriteorerase,a setACCVIFG flag generatesan interruptrequest.The ACCVIE bitresidesintheSpecialFunctionRegister,SFRIE1 (seethe SYS chapterfordetails).ACCVIFG sourcestheNMI interruptvector,so itisnotnecessaryforGIE tobe setforACCVIFG torequestan interrupt.ACCVIFG may alsobe checkedby softwaretodetermineifan accessviolationoccurred.ACCVIFG must be resetby software. The passwordviolationflag,KEYV, issetwhen any oftheflashcontrolregistersarewrittenwithan incorrectpassword.When thisoccurs,a PUC isgeneratedimmediately,resettingthedevice. 305SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Px.x, etc. T SPI, CPU executes user software Commands, data, etc. Read/write flash memory MSP430 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FlashMemory Operation www.ti.com

5.3.8 Programming FlashMemory Devices

Therearethreeoptionsforprogramminga flashdevice.Alloptionssupportin-systemprogramming.

Program viaJTAG
Program viatheBSL
Program viaa custom solution

5.3.8.1 Programming FlashMemory ViaJTAG

Devicescan be programmed viatheJTAG port.The JTAG interfacerequiresfoursignals(fivesignalson 20-and 28-pindevices),ground,and optionallyVCC and RST/NMI. The JTAG portisprotectedwitha fuse.BlowingthefusecompletelydisablestheJTAG portand isnot reversible.FurtheraccesstothedeviceviaJTAG isnotpossibleFormore details,see theMSP430 Programming ViatheJTAG InterfaceUser'sGuide (SLAU320 ).

5.3.8.2 Programming FlashMemory ViaBootstrapLoader (BSL)

Everyflashdevicecontainsa BSL. The BSL enablesuserstoreadorprogramtheflashmemory orRAM usinga UART serialinterface.Access totheflashmemory viatheBSL isprotectedby a 256-bituser- definedpassword.Formore details,see theMSP430 Programming ViatheBootstrapLoaderUser's Guide (SLAU319 ).

5.3.8.3 Programming FlashMemory ViaCustom Solution

The abilityoftheMSP430 CPU towritetoitsown flashmemory allowsforin-systemand externalcustom programmingsolutionsas shown inFigure5-13.The usercan choose toprovidedatathroughany means available(forexample,UART orSPI).User-developedsoftwarecan receivethedataand programthe flashmemory. Because thistypeofsolutionisdevelopedby theuser,itcan be completelycustomizedto fittheapplicationneeds forprogramming,erasing,orupdatingtheflashmemory. Figure5-13.User-DevelopedProgramming Solution

306 FlashMemory Controller SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com FCTL Registers

5.4 FCTL Registers

The flashmemory controller(FCTL)registersarelistedinTable5-5.The base addresscan be foundin thedevice-specificdatasheet.The addressoffsetisgiveninTable5-5. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table5-5.FCTL Registers Offset Acronym RegisterName Type Access Reset Section 00h FCTL1 FlashMemory Control1 Read/write Word 9600h Section5.4.1 00h FCTL1_L Read/Write Byte 00h 01h FCTL1_H Read/Write Byte 96h 04h FCTL3 FlashMemory Control3 Read/write Word 9658h Section5.4.2 04h FCTL3_L Read/Write Byte 58h 05h FCTL3_H Read/Write Byte 96h 06h FCTL4 FlashMemory Control4 Read/write Word 9600h Section5.4.3 06h FCTL4_L Read/Write Byte 00h 07h FCTL4_H Read/Write Byte 96h 307SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. FCTL Registers www.ti.com

5.4.1 FCTL1 Register

FlashMemory Control1 Register Figure5-14.FCTL1 Register 15 14 13 12 11 10 9 8 FRPW/FWPW 7 6 5 4 3 2 1 0 BLKWRT WRT SWRT Reserved MERAS ERASE Reserved rw-0 rw-0 rw-0 r-0 r-0 rw-0 rw-0 r-0 Table5-6.FCTL1 RegisterDescription Bit Field Type Reset Description 15-8 FRPW/FWPW RW 96h FCTL password.Alwaysreadas 096h.Must be writtenas 0A5h ora PUC is generated. 7 BLKWRT RW 0h Blockwrite.BLKWRT and WRT areused togethertoselectthewritemode. The valuesshown belowareforBLKWRT-WRT. 0-0= Reserved 0-1= Byteorword write 1-0= Long-wordwrite 1-1= Long-wordblockwrite 6 WRT RW 0h Write.BLKWRT and WRT areused togethertoselectthewritemode. The valuesshown belowareforBLKWRT-WRT. 0-0= Reserved 0-1= Byteorword write 1-0= Long-wordwrite 1-1= Long-wordblockwrite 5 SWRT RW 0h Smart write.Ifthisbitisset,theprogramtimeisshortened.The programming qualityhas tobe checkedby marginalreadmodes. 4-3 Reserved R 0h Reserved.Alwaysreadsas 0. 2 MERAS Mass erase.MERAS and ERASE areused togethertoselecttheerasemode. MERAS and ERASE areautomaticallyresetwhen EMEX issetora flasherase operationhas completed. The valuesshown belowareforMERAS-ERASE. 0-0= No erase 0-1= Segment erase 1-0= Bank erase(eraseofone bank) 1-1= Mass erase(eraseallflashmemory banks) 1 ERASE Erase.MERAS and ERASE areused togethertoselecttheerasemode. MERAS and ERASE areautomaticallyresetwhen EMEX issetora flasheraseoperation has completed. The valuesshown belowareforMERAS-ERASE. 0-0= No erase 0-1= Segment erase 1-0= Bank erase(eraseofone bank) 1-1= Mass erase(eraseallflashmemory banks) 0 Reserved R 0h Reserved.Alwaysreadsas 0.

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5.4.2 FCTL3 Register

FlashMemory Control3 Register Figure5-15.FCTL3 Register 15 14 13 12 11 10 9 8 FRPW/FWPW 7 6 5 4 3 2 1 0 Reserved LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY r-0 rw-1 rw-0 rw-1 r-1 rw-0 rw-(0) rw-0 Table5-7.FCTL3 RegisterDescription Bit Field Type Reset Description 15-8 FRPW/FWPW RW 96h FCTLx password.Alwaysreadas 096h.Must be writtenas 0A5h ora PUC is generated. 7 Reserved R 0h Reserved.Alwaysreadsas 0. 6 LOCKA RW 1h Segment A lock.Writea 1 tothisbittochange itsstate.Writing0 has no effect. 0b = Segment A oftheinformationmemory isunlockedand can be writtenor erasedinsegment erasemode. 1b = Segment A oftheinformationmemory islockedand can notbe writtenor erasedinsegment erasemode. 5 EMEX RW 0h Emergency exit.Settingthisbitstopsany eraseorwriteoperation.The LOCK bit isset. 0b = No emergency exit 1b = Emergency exit 4 LOCK RW 1h Lock.Thisbitunlockstheflashmemory forwritingorerasing.The LOCK bitcan be setany timeduringa byteorword writeoreraseoperation,and theoperation completesnormally.Intheblockwritemode, iftheLOCK bitissetwhile BLKWRT = WAIT = 1,BLKWRT and WAIT areresetand themode ends normally. 0b = Unlocked 1b = Locked 3 WAIT R 1h Wait.Indicatestheflashmemory isbeingwrittento. 0b = Flashmemory isnotreadyforthenextbyteorword write. 1b = Flashmemory isreadyforthenextbyteorword write.

2 ACCVIFG RW 0h Access violationinterruptflag

0b = No interruptpending 1b = Interruptpending 1 KEYV RW 0h Flashpasswordviolation.Thisbitindicatesan incorrectFCTLx passwordwas writtentoany flashcontrolregisterand generatesa PUC when set.KEYV must be resetwithsoftware. 0b = FCTLx passwordwas writtencorrectly. 1b = FCTLx passwordwas writtenincorrectly. 0 BUSY RW 0h Busy.Thisbitindicatesiftheflashiscurrentlybusy erasingorprogramming. 0b = Not busy 1b = Busy 309SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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5.4.3 FCTL4 Register

FlashMemory Control4 Register Figure5-16.FCTL4 Register 15 14 13 12 11 10 9 8 FRPW/FWPW 7 6 5 4 3 2 1 0 LOCKINFO Reserved MRG1 MRG0 Reserved VPE rw-0 r-0 rw-0 rw-0 r-0 r-0 r-0 rw-0 Table5-8.FCTL4 RegisterDescription Bit Field Type Reset Description 15-8 FRPW/FWPW RW 96h FCTLx password.Alwaysreadsas 096h.Must be writtenas 0A5h ora PUC is generated. 7 LOCKINFO RW 0h Lock informationmemory. Ifset,theinformationmemory cannotbe erasedin segment erasemode and cannotbe writtento. 6 Reserved R 0h Reserved.Alwaysreadsas 0. 5 MRG1 RW 0h Marginalread1 mode. Thisbitenablesthemarginal1 readmode. The marginal read1 bitisvalidforreadsfromtheflashmemory only.Duringa fetchcycle,the marginalmode isturnedoffautomatically.IfbothMRG1 and MRG0 areset, MRG1 isactiveand MRG0 isignored. 0b = Marginal1 readmode isdisabled. 1b = Marginal1 readmode isenabled. 4 MRG0 RW 0h Marginalread0 mode. Thisbitenablesthemarginal0 readmode. The marginal read1 bitisvalidforreadsfromtheflashmemory only.Duringa fetchcycle,the marginalmode isturnedoffautomatically.IfbothMRG1 and MRG0 areset, MRG1 isactiveand MRG0 isignored. 0b = Marginal0 readmode isdisabled. 1b = Marginal0 readmode isenabled. 3-1 Reserved R 0h Reserved.Alwaysreadsas 0. 0 VPE RW 0h Voltagechanged duringprogramerror.Thisbitissetby hardwareand can only be clearedby software.IfDVCC changed significantlyduringprogramming,this bitissettoindicatean invalidresult.The ACCVIFG bitissetifVPE isset.

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5.4.4 SFRIE1 Register

Figure5-17.SFRIE1 Register 15 14 13 12 11 10 9 8 OTHER 7 6 5 4 3 2 1 0 ACCVIE rw-0 Table5-9.SFRIE1 RegisterDescription Bit Field Type Reset Description 15-6 These bitsmay be used by othermodules (seethedevice-specificdatasheet and theSYS chapterfordetails). 5 ACCVIE RW 0h Flashmemory accessviolationinterruptenable.ThisbitenablestheACCVIFG interrupt.Because otherbitsinSFRIE1 may be used forothermodules,itis recommended tosetorclearthisbitusingBISorBICinstructions,ratherthan MOVorCLRinstructions.See theSYS chapterformore details. 0b = Interruptnotenabled 1b = Interruptenabled 4-0 These bitsmay be used by othermodules (seethedevice-specificdatasheet and theSYS chapterfordetails). 311SLAU259E –May 2009–RevisedJanuary2013 FlashMemory Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter6 SLAU259E –May 2009–RevisedJanuary2013 RAM Controller(RAMCTL) The RAM controller(RAMCTL) allowscontroloftheoperationoftheRAM.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RAM Controller(RAMCTL) Introduction

6.1 RAM Controller(RAMCTL) Introduction

The RAMCTL providesaccesstothedifferentpower modes oftheRAM. The RAMCTL allowstheability toreducetheleakagecurrentwhiletheCPU isoff.The RAM can alsobe switchedoff.Inretentionmode, theRAM contentissaved whiletheRAM contentislostinoffmode. The RAM ispartitionedinsectors, typicallyof4KB (sector)size.See thedevice-specificdatasheetforactualblockallocationand size.Each sectoriscontrolledby theRAM controllerRAM SectorOffcontrolbit(RCRSyOFF) oftheRAMCTL Control0 register(RCCTL0).The RCCTL0 registerisprotectedwitha key.Onlyifthecorrectkey is writtenduringa word write,theRCCTL0 registercontentcan be modified.Bytewriteaccessesorwrite accesseswitha wrong key areignored.

6.2 RAMCTL Operation

Inactivemode, theRAM can be readand writtenatany time.Ifa RAM addressofa sectormust hold data,thewholesectorcannotbe switchedoff. Low-power modes Inalllow-powermodes, theCPU isswitchedoff.As soon as theCPU isswitchedoff,theRAM enters retentionmode toreducetheleakagecurrent. RAM offmode Each sectorcan be turnedoffindependentlyofeach otherby settingtherespectiveRCRSyOFF bitto 1.Readingfroma switchedoffRAM sectorreturns0 as data.Alldatapreviouslystoredintoa switched offRAM sectorislostand cannotbe read,even ifthesectoristurnedon again. Stackpointer The programstackislocatedinRAM. Sectorsholdingthestackmust notbe turnedoffifan interrupt has tobe executed,ora low-powermode isentered. USB buffermemory On deviceswithUSB, theUSB buffermemory islocatedinRAM. Sector7 isused forthispurpose. RCRS7OFF can be settoswitchoffthismemory ifitisnotrequiredforUSB operationorisnotbeing utilizedinnormaloperation. 313SLAU259E –May 2009–RevisedJanuary2013 RAM Controller(RAMCTL) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RAMCTL Registers www.ti.com

6.3 RAMCTL Registers

The RAMCTL module registerislistedinTable6-1.The base addresscan be foundinthedevice-specific datasheet.The addressoffsetisgiveninTable6-1. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table6-1.RAMCTL Registers Offset Acronym RegisterName Type Access Reset Section 00h RCCTL0 RAM ControllerControl0 Read/write Word 6900h Section6.3.1 00h RCCTL0_L Read/write Byte 00h 01h RCCTL0_H Read/write Byte 69h

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6.3.1 RCCTL0 Register

RAM ControllerControl0 Register Figure6-1.RCCTL0 Register 15 14 13 12 11 10 9 8 RCKEY rw-0 rw-1 rw-1 rw-0 rw-1 rw-0 rw-0 rw-1 7 6 5 4 3 2 1 0 RCRS7OFF RCRS6OFF RCRS5OFF RCRS4OFF RCRS3OFF RCRS2OFF RCRS1OFF RCRS0OFF rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table6-2.RCCTL0 RegisterDescription Bit Field Type Reset Description 15-8 RCKEY RW 69h RAM controllerkey.Alwaysreadas 69h.Must be writtenas 5Ah,otherwisethe RAMCTL writeisignored. 7 RCRS7OFF RW 0h RAM controllerRAM sector7 off.Settingthebitto1 turnsofftheRAM sector7. AlldataoftheRAM sector7 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 6 RCRS6OFF RW 0h RAM controllerRAM sector6 off.Settingthebitto1 turnsofftheRAM sector6. AlldataoftheRAM sector6 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 5 RCRS5OFF RW 0h RAM controllerRAM sector5 off.Settingthebitto1 turnsofftheRAM sector5. AlldataoftheRAM sector5 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 4 RCRS4OFF RW 0h RAM controllerRAM sector4 off.Settingthebitto1 turnsofftheRAM sector4. AlldataoftheRAM sector4 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 3 RCRS3OFF RW 0h RAM controllerRAM sector3 off.Settingthebitto1 turnsofftheRAM sector3. AlldataoftheRAM sector3 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 2 RCRS2OFF RW 0h RAM controllerRAM sector2 off.Settingthebitto1 turnsofftheRAM sector2. AlldataoftheRAM sector2 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 1 RCRS1OFF RW 0h RAM controllerRAM sector1 off.Settingthebitto1 turnsofftheRAM sector1. AlldataoftheRAM sector1 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 0 RCRS0OFF RW 0h RAM controllerRAM sector0 off.Settingthebitto1 turnsofftheRAM sector0. AlldataoftheRAM sector0 islost.See thedevice-specificdatasheettofindthe thenumber ofRAM sectorsavailablealongwiththeirrespectiveaddressranges and sizes. 315SLAU259E –May 2009–RevisedJanuary2013 RAM Controller(RAMCTL) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter7 SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule The directmemory access (DMA) controllermodule transfersdatafrom one addresstoanotherwithout CPU intervention.ThischapterdescribestheoperationoftheDMA controller.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DirectMemory Access (DMA) Introduction

7.1 DirectMemory Access (DMA) Introduction

The DMA controllertransfersdatafromone addresstoanother,withoutCPU intervention,acrossthe entireaddressrange.Forexample,theDMA controllercan move datafromtheADC conversionmemory toRAM. Devicesthatcontaina DMA controllermay have up toeightDMA channelsavailable.Therefore, dependingon thenumber ofDMA channelsavailable,some featuresdescribedinthischapterarenot applicabletoalldevices.See thedevice-specificdatasheetfornumber ofchannelssupported. UsingtheDMA controllercan increasethethroughputofperipheralmodules.Itcan alsoreducesystem power consumptionby allowingtheCPU toremainina low-powermode, withouthavingtoawaken to move datatoorfroma peripheral. DMA controllerfeaturesinclude:

Up toeightindependenttransferchannels
ConfigurableDMA channelpriorities
Requiresonlytwo MCLK clockcyclespertransfer
Byteorword and mixed byte/wordtransfercapability
Blocksizesup to65535 bytesorwords
Configurabletransfertriggerselections
Selectable-edgeorlevel-triggeredtransfer
Fouraddressingmodes
Single,block,orburst-blocktransfermodes The DMA controllerblockdiagramisshown inFigure7-1. 317SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

DMA Channel□n DMASRSBYTE DMAnSZ DMAnDA DMAnSA DMADSTBYTE DMASRCINCR DMADSTINCR DMADT DMAEN DMA Channel1 DMASRSBYTE DMA1SZ DMA1DA DMA1SA DMADSTBYTE DMASRCINCR DMADSTINCR DMADT DMAEN DMA Channel□0 DMASRSBYTE DMA0SZ DMA0DA DMA0SA DMADSTBYTE DMASRCINCR DMADSTINCR DMADT DMAEN Address Space NMI□Interrupt□Request JTAG Active Halt Halt□CPU ROUNDROBIN DMARMWDIS DMAnTSEL DMA0TRIG31 DMA0TRIG0 DMA0TSEL DMA0TRIG1 00000 00001 11111 DMA1TRIG31 DMA1TRIG0 DMA1TSEL DMA1TRIG1 00000 00001 11111 DMAnTRIG31 DMAnTRIG0 DMAnTRIG1 00000 00001 11111 to□USB if□available to□USB if□available DMA Priority and Control to□USB if□available ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DirectMemory Access (DMA) Introduction www.ti.com Figure7-1.DMA ControllerBlock Diagram

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Address SpaceAddress Space DMA Controller Address Space Address Space Fixed Address To Block Of AddressesFixed Address To Fixed Address Block Of Addresses To Fixed Address Block Of Addresses To Block Of Addresses DMA Controller DMA Controller DMA Controller ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DMA Operation

7.2 DMA Operation

The DMA controllerisconfiguredwithusersoftware.The setupand operationoftheDMA isdiscussedin thefollowingsections.

7.2.1 DMA Addressing Modes

The DMA controllerhas fouraddressingmodes. The addressingmode foreach DMA channelis independentlyconfigurable.Forexample,channel0 may transferbetween two fixedaddresses,while channel1 transfersbetween two blocksofaddresses.The addressingmodes areshown inFigure7-2. The addressingmodes are:

Fixedaddresstofixedaddress
Fixedaddresstoblockofaddresses
Blockofaddressestofixedaddress
Blockofaddressestoblockofaddresses The addressingmodes areconfiguredwiththeDMASRCINCR and DMADSTINCR controlbits.The DMASRCINCR bitsselectifthesourceaddressisincremented,decremented,orunchanged aftereach transfer.The DMADSTINCR bitsselectifthedestinationaddressisincremented,decremented,or unchanged aftereach transfer. Transfersmay be bytetobyte,word toword,bytetoword,orword tobyte.When transferringword to byte,onlythelowerbyteofthesource-wordtransfers.When transferringbytetoword,theupperbyteof thedestination-wordisclearedwhen thetransferoccurs. Figure7-2.DMA Addressing Modes

7.2.2 DMA TransferModes

The DMA controllerhas sixtransfermodes selectedby theDMADT bitsas listedinTable7-1.Each channelisindividuallyconfigurableforitstransfermode. Forexample,channel0 may be configuredin singletransfermode, whilechannel1 isconfiguredforburst-blocktransfermode, and channel2 operates inrepeatedblockmode. The transfermode isconfiguredindependentlyfromtheaddressingmode. Any addressingmode can be used withany transfermode. Two typesofdatacan be transferredselectableby theDMAxCTL DSTBYTE and SRCBYTE fields.The sourceand/ordestinationlocationcan be eitherbyteorword data.Itisalsopossibletotransferbyteto byte,word toword,orany combination. 319SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DMA Operation www.ti.com Table7-1.DMA TransferModes DMADT TransferMode Description 000 Singletransfer Each transferrequiresa trigger.DMAEN isautomaticallyclearedwhen DMAxSZ transfershave been made. 001 Blocktransfer A completeblockistransferredwithone trigger.DMAEN isautomaticallyclearedat theend oftheblocktransfer. 010,011 Burst-blocktransfer CPU activityisinterleavedwitha blocktransfer.DMAEN isautomaticallyclearedat theend oftheburst-blocktransfer. 100 Repeated singletransferEach transferrequiresa trigger.DMAEN remainsenabled. 101 Repeated blocktransfer A completeblockistransferredwithone trigger.DMAEN remainsenabled. 110,111 Repeated burst-block CPU activityisinterleavedwitha blocktransfer.DMAEN remainsenabled.transfer

7.2.2.1 SingleTransfer

Insingletransfermode, each byte/wordtransferrequiresa separatetrigger.The singletransferstate diagramisshown inFigure7-3. The DMAxSZ registerisused todefinethenumber oftransferstobe made. The DMADSTINCR and DMASRCINCR bitsselectifthedestinationaddressand thesourceaddressareincrementedor decrementedaftereach transfer.IfDMAxSZ = 0,no transfersoccur. The DMAxSA, DMAxDA, and DMAxSZ registersarecopiedintotemporaryregisters.The temporary valuesofDMAxSA and DMAxDA areincrementedordecrementedaftereach transfer.The DMAxSZ registerisdecrementedaftereach transfer.When theDMAxSZ registerdecrementstozero,itisreloaded fromitstemporaryregisterand thecorrespondingDMAIFG flagisset.When DMADT = {0},theDMAEN bitisclearedautomaticallywhen DMAxSZ decrementstozeroand must be setagainforanothertransfer tooccur. Inrepeatedsingletransfermode, theDMA controllerremainsenabledwithDMAEN = 1,and a transfer occurseverytimea triggeroccurs.

320 DirectMemory Access (DMA) ControllerModule SLAU259E –May 2009–RevisedJanuary2013

Wait□forTrigger Idle Hold□CPU, Transfer□one□word/byte [+Trigger AND□DMALEVEL =□0□] OR [Trigger□=□1 AND□DMALEVEL =□1] DMAABOR T=0 DMAABOR T =□1 2□x□MCLK DMAEN□=□0 Decrement□DMAxSZ Modify□T_SourceAdd Modify□T_DestAdd [ENNMI□=□1 AND□NMI□event] OR [DMALEVEL =□1 AND□Trigger□=□0] AND□DMAxSZ□=□0] OR□DMAEN□=□0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ□=□0 DMAxSZ□>□0 AND□DMAEN□=□1 DMAEN□=□0 DMAEN□=□1 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADT□=□{4} AND□DMAxSZ□=□0 AND□DMAEN□=□1 DMAEN□=□0 DMAREQ□=□0 T_Size → DMAxSZ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DMA Operation Figure7-3.DMA SingleTransferStateDiagram

7.2.2.2 Block Transfer

Inblocktransfermode, a transferofa completeblockofdataoccursafterone trigger.When DMADT = {1} ,theDMAEN bitisclearedafterthecompletionoftheblocktransferand must be setagainbeforeanother blocktransfercan be triggered.Aftera blocktransferhas been triggered,furthertriggersignalsoccurring duringtheblocktransferareignored.The blocktransferstatediagramisshown inFigure7-4. The DMAxSZ registerisused todefinethesizeoftheblock,and theDMADSTINCR and DMASRCINCR bitsselectifthedestinationaddressand thesourceaddressareincrementedordecrementedaftereach transferoftheblock.IfDMAxSZ = 0,no transfersoccur. The DMAxSA, DMAxDA, and DMAxSZ registersarecopiedintotemporaryregisters.The temporary valuesofDMAxSA and DMAxDA areincrementedordecrementedaftereach transferintheblock.The DMAxSZ registerisdecrementedaftereach transferoftheblockand shows thenumber oftransfers remainingintheblock.When theDMAxSZ registerdecrementstozero,itisreloadedfromitstemporary registerand thecorrespondingDMAIFG flagisset. 321SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Wait□forTrigger Idle Hold□CPU, Transfer□one□word/byte [+Trigger AND□DMALEVEL=□0 ] OR [Trigger=1 AND□DMALEVEL=1] DMAABORT□=□0 Decrement□DMAxSZ Modify□T_SourceAdd Modify□T_DestAdd DMAxSZ□>□0 [ENNMI□=□1 AND□NMI□event] OR [DMALEVEL =□1 AND□Trigger□=□0] [DMADT□=□{1} AND□DMAxSZ□=□0] OR DMAEN□=□0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAREQ□=□0 T_Size DMAxSZ DMAxSA T_SourceAdd DMAxDA T_DestAdd DMADT□=□{5} AND□DMAxSZ□=□0 AND□DMAEN□=□1 DMAEN□=□0 DMAEN□=□1 DMAEN□=□0 DMAREQ□=□0 T_Size DMAxSZ→ DMAABORT□=□1 2□×□MCLK DMAEN□=□0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DMA Operation www.ti.com Duringa blocktransfer,theCPU ishalteduntilthecompleteblockhas been transferred.The block transfertakes2 × MCLK × DMAxSZ clockcyclestocomplete.CPU executionresumes withitsprevious stateaftertheblocktransferiscomplete. Inrepeatedblocktransfermode, theDMAEN bitremainssetaftercompletionoftheblocktransfer.The nexttriggerafterthecompletionofa repeatedblocktransfertriggersanotherblocktransfer. Figure7-4.DMA Block TransferStateDiagram

7.2.2.3 Burst-BlockTransfer

Inburst-blockmode, transfersareblocktransferswithCPU activityinterleaved.The CPU executes two MCLK cyclesaftereveryfourbyte/wordtransfersoftheblock,resultingin20% CPU execution capacity.Aftertheburst-block,CPU executionresumes at100% capacityand theDMAEN bitiscleared. DMAEN must be setagainbeforeanotherburst-blocktransfercan be triggered.Aftera burst-block transferhas been triggered,furthertriggersignalsoccurringduringtheburst-blocktransferareignored. The burst-blocktransferstatediagramisshown inFigure7-5. The DMAxSZ registerisused todefinethesizeoftheblock,and theDMADSTINCR and DMASRCINCR bitsselectifthedestinationaddressand thesourceaddressareincrementedordecrementedaftereach transferoftheblock.IfDMAxSZ = 0,no transfersoccur.

322 DirectMemory Access (DMA) ControllerModule SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DMA Operation The DMAxSA, DMAxDA, and DMAxSZ registersarecopiedintotemporaryregisters.The temporary valuesofDMAxSA and DMAxDA areincrementedordecrementedaftereach transferintheblock.The DMAxSZ registerisdecrementedaftereach transferoftheblockand shows thenumber oftransfers remainingintheblock.When theDMAxSZ registerdecrementstozero,itisreloadedfromitstemporary registerand thecorrespondingDMAIFG flagisset. Inrepeatedburst-blockmode, theDMAEN bitremainssetaftercompletionoftheburst-blocktransferand no furthertriggersignalsarerequiredtoinitiateanotherburst-blocktransfer.Anotherburst-blocktransfer beginsimmediatelyaftercompletionofa burst-blocktransfer.Inthiscase,thetransfersmust be stopped by clearingtheDMAEN bit,orby an (non)maskableinterrupt(NMI)when ENNMI isset.Inrepeatedburst- blockmode theCPU executesat20% capacitycontinuouslyuntiltherepeatedburst-blocktransferis stopped. 323SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

2□×□MCLK Reset Wait□for□Trigger Idle Hold□CPU, T ransfer□one□word/byte Burst□State [+Trigger AND□DMALEVEL =□0□] OR [Trigger=1 AND□DMALEVEL=1] DMAABOR T=0 DMAABORT□=□1 2□×□MCLK DMAEN□=□0 Decrement□DMAxSZ Modify□T_SourceAdd Modify□T_DestAdd AND□DMAxSZ□=□□0] [ENNMI□=□1 AND□NMI□event] OR [DMALEVEL =□1 AND Trigger□=□0] AND□DMAxSZ□=□0] OR DMAEN□=□0 DMAxSZ T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd T_Size DMAxSA T_SourceAdd DMAxDA T_DestAdd DMAxSZ DMAEN□=□0 DMAEN□=□1 a□multiple□of□4□words/bytes were□transferred DMAxSZ□>□0 DMAEN□=□0 DMAREQ□=□0 T_Size DMAxSZ→ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DMA Operation www.ti.com Figure7-5.DMA Burst-BlockTransferStateDiagram

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DMA Operation

7.2.3 InitiatingDMA Transfers

Each DMA channelisindependentlyconfiguredforitstriggersourcewiththeDMAxTSEL. The DMAxTSEL bitsshouldbe modifiedonlywhen theDMACTLx DMAEN bitis0.Otherwise,unpredictable DMA triggersmay occur.Table7-2describesthetriggeroperationforeach typeofmodule.See the device-specificdatasheetforthelistoftriggersavailable,alongwiththeirrespectiveDMAxTSEL values. When selectingthetrigger,thetriggermust nothave alreadyoccurred,orthetransferdoes nottakeplace. NOTE: DMA triggerselectionand USB On devicesthatcontaina USB module,thetriggersselectionfromDMA channels0,1,or2 can be used fortheUSB timestamp eventselection(seetheUSB module descriptionfor furtherdetails).

7.2.3.1 Edge-SensitiveTriggers

When DMALEVEL = 0,edge-sensitivetriggersareused,and therisingedge ofthetriggersignalinitiates thetransfer.Insingle-transfermode, each transferrequiresitsown trigger.When usingblockorburst- blockmodes, onlyone triggerisrequiredtoinitiatetheblockorburst-blocktransfer.

7.2.3.2 Level-SensitiveTriggers

When DMALEVEL = 1,level-sensitivetriggersareused.Forproperoperation,level-sensitivetriggerscan onlybe used when externaltriggerDMAE0 isselectedas thetrigger.DMA transfersaretriggeredas long as thetriggersignalishighand theDMAEN bitremainsset. The triggersignalmust remainhighfora blockorburst-blocktransfertocomplete.Ifthetriggersignal goes lowduringa blockorburst-blocktransfer,theDMA controllerisheldinitscurrentstateuntilthe triggergoes back highoruntiltheDMA registersaremodifiedby software.IftheDMA registersarenot modifiedby software,when thetriggersignalgoes highagain,thetransferresumes fromwhere itwas when thetriggersignalwent low. When DMALEVEL = 1,transfermodes selectedwhen DMADT = {0,1,2,3}arerecommended because theDMAEN bitisautomaticallyresetaftertheconfiguredtransfer.

7.2.4 HaltingExecutingInstructionsforDMA Transfers

The DMARMWDIS bitcontrolswhen theCPU ishaltedforDMA transfers.When DMARMWDIS = 0,the CPU ishaltedimmediatelyand thetransferbeginswhen a triggerisreceived.Inthiscase,itispossible thatCPU read-modify-writeoperationscan be interruptedby a DMA transfer.When DMARMWDIS = 1, theCPU finishesthecurrentlyexecutingread-modify-writeoperationbeforetheDMA controllerhaltsthe CPU and thetransferbegins(seeTable7-2). 325SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DMA Operation www.ti.com Table7-2.DMA TriggerOperation Module Operation DMA A transferistriggeredwhen theDMAREQ bitisset.The DMAREQ bitisautomaticallyresetwhen thetransfer starts. A transferistriggeredwhen theDMAxIFG flagisset.DMA0IFG triggerschannel1,DMA1IFG triggerschannel2, and DMA2IFG triggerschannel0.None oftheDMAxIFG flagsareautomaticallyresetwhen thetransferstarts. A transferistriggeredby theexternaltriggerDMAE0. Timer_A A transferistriggeredwhen theTAxCCR0 CCIFG flagisset.The TAxCCR0 CCIFG flagisautomaticallyreset when thetransferstarts.IftheTAxCCR0 CCIE bitisset,theTAxCCR0 CCIFG flagdiesnottriggera transfer. A transferistriggeredwhen theTAxCCR2 CCIFG flagisset.The TAxCCR2 CCIFG flagisautomaticallyreset when thetransferstarts.IftheTAxCCR2 CCIE bitisset,theTAxCCR2 CCIFG flagdoes nottriggera transfer. Timer_B A transferistriggeredwhen theTBxCCR0 CCIFG flagisset.The TBxCCR0 CCIFG flagisautomaticallyreset when thetransferstarts.IftheTBxCCR0 CCIE bitisset,theTBxCCR0 CCIFG flagdoes nottriggera transfer. A transferistriggeredwhen theTBxCCR2 CCIFG flagisset.The TBxCCR2 CCIFG flagisautomaticallyreset when thetransferstarts.IftheTBxCCR2 CCIE bitisset,theTBxCCR2 CCIFG flagdoes nottriggera transfer. USCI_Ax A transferistriggeredwhen USCI_Ax receivesnew data.UCAxRXIFG isautomaticallyresetwhen thetransfer starts.IfUCAxRXIE isset,theUCAxRXIFG does nottriggera transfer. A transferistriggeredwhen USCI_Ax isreadytotransmitnew data.UCAxTXIFG isautomaticallyresetwhen the transferstarts.IfUCAxTXIE isset,theUCAxTXIFG does nottriggera transfer. USCI_Bx A transferistriggeredwhen USCI_Bx receivesnew data.UCBxRXIFG isautomaticallyresetwhen thetransfer starts.IfUCBxRXIE isset,theUCBxRXIFG does nottriggera transfer. A transferistriggeredwhen USCI_Bx isreadytotransmitnew data.UCBxTXIFG isautomaticallyresetwhen the transferstarts.IfUCBxTXIE isset,theUCBxTXIFG does nottriggera transfer. DAC12_A A transferistriggeredwhen theDAC12_xCTL0 DAC12IFG flagisset.The DAC12_xCTL0 DAC12IFG flagis automaticallyclearedwhen thetransferstarts.IftheDAC12_xCTL0 DAC12IE bitisset,theDAC12_xCTL0 DAC12IFG flagdoes nottriggera transfer. ADC12_A A transferistriggeredby an ADC12IFG flag.When single-channelconversionsareperformed,the correspondingADC12IFG isthetrigger.When sequencesareused,theADC12IFG forthelastconversioninthe sequence isthetrigger.A transferistriggeredwhen theconversioniscompletedand theADC12IFG isset. SettingtheADC12IFG withsoftwaredoes nottriggera transfer.AllADC12IFG flagsareautomaticallyreset when theassociatedADC12MEMx registerisaccessedby theDMA controller. MPY A transferistriggeredwhen thehardwaremultiplierisreadyfora new operand. Reserved No transferistriggered.

7.2.5 Stopping DMA Transfers

Therearetwo ways tostopDMA transfersinprogress:

A single,block,orburst-blocktransfermay be stoppedwithan NMI, iftheENNMI bitissetinregister DMACTL1.
A burst-blocktransfermay be stoppedby clearingtheDMAEN bit.

7.2.6 DMA Channel Priorities

The defaultDMA channelprioritiesareDMA0 throughDMA7. Iftwo orthreetriggershappen simultaneouslyorarepending,thechannelwiththehighestprioritycompletesitstransfer(single,block,or burst-blocktransfer)first,thenthesecond prioritychannel,thenthethirdprioritychannel.Transfersin progressarenothaltedifa higher-prioritychannelistriggered.The higher-prioritychannelwaitsuntilthe transferinprogresscompletesbeforestarting. The DMA channelprioritiesareconfigurablewiththeROUNDROBIN bit.When theROUNDROBIN bitis set,thechannelthatcompletesa transferbecomes thelowestpriority.The orderofthepriorityofthe channelsalwaysstaysthesame, DMA0-DMA1-DMA2, forexample,forthreechannels.When the ROUNDROBIN bitiscleared,thechannelpriorityreturnstothedefaultpriority. DMA Priority TransferOccurs New DMA Priority DMA0-DMA1-DMA2 DMA1 DMA2-DMA0-DMA1 DMA2-DMA0-DMA1 DMA2 DMA0-DMA1-DMA2 DMA0-DMA1-DMA2 DMA0 DMA1-DMA2-DMA0

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7.2.7 DMA TransferCycle Time

The DMA controllerrequiresone ortwo MCLK clockcyclestosynchronizebeforeeach singletransferor completeblockorburst-blocktransfer.Each byte/wordtransferrequirestwo MCLK cyclesafter synchronization,and one cycleofwaittimeafterthetransfer.Because theDMA controlleruses MCLK, the DMA cycletimeisdependenton theMSP430 operatingmode and clocksystemsetup. IftheMCLK sourceisactivebuttheCPU isoff,theDMA controlleruses theMCLK sourceforeach transfer,withoutreenablingtheCPU. IftheMCLK sourceisoff,theDMA controllertemporarilyrestarts MCLK, sourcedwithDCOCLK, forthesingletransferorcompleteblockorburst-blocktransfer.The CPU remainsoffand afterthetransfercompletes,MCLK isturnedoff.The maximum DMA cycletimeforall operatingmodes isshown inTable7-3. Table7-3.Maximum Single-TransferDMA Cycle Time CPU OperatingMode Clock Source Maximum DMA Cycle Time Activemode MCLK = DCOCLK 4 MCLK cycles Activemode MCLK = LFXT1CLK 4 MCLK cycles Low-power mode LPM0/1 MCLK = DCOCLK 5 MCLK cycles Low-power mode LPM3/4 MCLK = DCOCLK 5 MCLK cycles+ 5 µs(1) Low-power mode LPM0/1 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM3 MCLK = LFXT1CLK 5 MCLK cycles Low-power mode LPM4 MCLK = LFXT1CLK 5 MCLK cycles+ 5 µs(1) (1) The additional5 µs areneeded tostarttheDCOCLK. Itisthet(LPMx) parameterinthedatasheet.

7.2.8 Using DMA With System Interrupts

DMA transfersarenotinterruptibleby systeminterrupts.System interruptsremainpendinguntilthe completionofthetransfer.NMIs can interrupttheDMA controlleriftheENNMI bitisset. System interruptserviceroutinesareinterruptedby DMA transfers.Ifan interruptserviceroutineorother routinemust executewithno interruptions,theDMA controllershouldbe disabledpriortoexecutingthe routine.

7.2.9 DMA ControllerInterrupts

Each DMA channelhas itsown DMAIFG flag.Each DMAIFG flagissetinany mode when the correspondingDMAxSZ registercountstozero.IfthecorrespondingDMAIE and GIE bitsareset,an interruptrequestisgenerated. AllDMAIFG flagsareprioritized,withDMA0IFG beingthehighest,and combined tosourcea single interruptvector.The highest-priorityenabledinterruptgeneratesa number intheDMAIV register.This number can be evaluatedoradded totheprogramcounter(PC)toautomaticallyentertheappropriate softwareroutine.DisabledDMA interruptsdo notaffecttheDMAIV value. Any access,readorwrite,oftheDMAIV registerautomaticallyresetsthehighestpendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. Forexample,assume thatDMA0 has thehighestpriority.IftheDMA0IFG and DMA2IFG flagsareset when theinterruptserviceroutineaccessestheDMAIV register,DMA0IFG isresetautomatically.Afterthe RETI instructionoftheinterruptserviceroutineisexecuted,theDMA2IFG generatesanotherinterrupt. 327SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.2.9.1 DMAIV SoftwareExample

The followingsoftwareexample shows therecommended use ofDMAIV and thehandlingoverheadforan eightchannelDMA controller.The DMAIV valueisadded tothePC toautomaticallyjump tothe appropriateroutine. The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself. ;InterrupthandlerforDMAxIFG Cycles DMA_HND... ;Interruptlatency 6 ADD &DMAIV,PC;AddoffsettoJumptable3 RETI ;Vector0:Nointerrupt5 JMP DMA0_HND;Vector2:DMAchannel0 2 JMP DMA1_HND;Vector4:DMAchannel1 2 JMP DMA2_HND;Vector6:DMAchannel2 2 JMP DMA3_HND;Vector8:DMAchannel3 2 JMP DMA4_HND;Vector10:DMAchannel4 2 JMP DMA5_HND;Vector12:DMAchannel5 2 JMP DMA6_HND;Vector14:DMAchannel6 2 JMP DMA7_HND;Vector16:DMAchannel7 2 DMA7_HND ;Vector16:DMAchannel7 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA6_HND ;Vector14:DMAchannel6 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA5_HND ;Vector12:DMAchannel5 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA4_HND ;Vector10:DMAchannel4 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA3_HND ;Vector8:DMAchannel3 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA2_HND ;Vector6:DMAchannel2 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA1_HND ;Vector4:DMAchannel1 ... ;Taskstartshere RETI ;Backtomainprogram 5 DMA0_HND ;Vector2:DMAchannel0 ... ;Taskstartshere RETI ;Backtomainprogram 5

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7.2.10 Using theUSCI_B I2C Module With theDMA Controller

The USCI_B I2C module providestwo triggersourcesfortheDMA controller.The USCI_B I2C module can triggera transferwhen new I2C dataisreceivedand thewhen thetransmitdataisneeded.

7.2.11 Using ADC12 With theDMA Controller

MSP430 deviceswithan integratedDMA controllercan automaticallymove datafromany ADC12MEMx registertoanotherlocation.DMA transfersaredone withoutCPU interventionand independentlyofany low-powermodes. The DMA controllerincreasesthroughputoftheADC12 module,and enhances low- power applicationsallowingtheCPU toremainoffwhiledatatransfersoccur. DMA transferscan be triggeredfromany ADC12IFG flag.When CONSEQx = {0,2},theADC12IFG flagfor theADC12MEMx used fortheconversioncan triggera DMA transfer.When CONSEQx = {1,3},the ADC12IFG flagforthelastADC12MEMx inthesequence can triggera DMA transfer.Any ADC12IFG flag isautomaticallyclearedwhen theDMA controlleraccessesthecorrespondingADC12MEMx.

7.2.12 Using DAC12 With theDMA Controller

MSP430 deviceswithan integratedDMA controllercan automaticallymove datatotheDAC12_xDAT register.DMA transfersaredone withoutCPU interventionand independentlyofany low-powermodes. The DMA controllerincreasesthroughputtotheDAC12 module,and enhances low-powerapplications allowingtheCPU toremainoffwhiledatatransfersoccur. Applicationsrequiringperiodicwaveform generationcan benefitfromusingtheDMA controllerwiththe DAC12. Forexample,an applicationthatproducesa sinusoidalwaveform may storethesinusoidvalues ina table.The DMA controllercan continuouslyand automaticallytransferthevaluestotheDAC12 at specificintervalscreatingthesinusoidwithzeroCPU execution.The DAC12_xCTL DAC12IFG flagis automaticallyclearedwhen theDMA controlleraccessestheDAC12_xDAT register. 329SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3 DMA Registers

The DMA module registersarelistedinTable7-4.The base addressescan be foundinthedevice-specific datasheet.Each channelstartsatitsrespectivebase address.The addressoffsetsarelistedinTable7-4. Table7-4.DMA Registers Offset Acronym RegisterName Type Access Reset Section 00h DMACTL0 DMA Control0 Read/write Word 0000h Section7.3.1 02h DMACTL1 DMA Control1 Read/write Word 0000h Section7.3.2 04h DMACTL2 DMA Control2 Read/write Word 0000h Section7.3.3 06h DMACTL3 DMA Control3 Read/write Word 0000h Section7.3.4 08h DMACTL4 DMA Control4 Read/write Word 0000h Section7.3.5 0Eh DMAIV DMA InterruptVector Read only Word 0000h Section7.3.10 00h DMA0CTL DMA Channel0 Control Read/write Word 0000h Section7.3.6 02h DMA0SA DMA Channel0 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA0DA DMA Channel0 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA0SZ DMA Channel0 TransferSize Read/write Word undefined Section7.3.9 00h DMA1CTL DMA Channel1 Control Read/write Word 0000h Section7.3.6 02h DMA1SA DMA Channel1 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA1DA DMA Channel1 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA1SZ DMA Channel1 TransferSize Read/write Word undefined Section7.3.9 00h DMA2CTL DMA Channel2 Control Read/write Word 0000h Section7.3.6 02h DMA2SA DMA Channel2 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA2DA DMA Channel2 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA2SZ DMA Channel2 TransferSize Read/write Word undefined Section7.3.9 00h DMA3CTL DMA Channel3 Control Read/write Word 0000h Section7.3.6 02h DMA3SA DMA Channel3 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA3DA DMA Channel3 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA3SZ DMA Channel3 TransferSize Read/write Word undefined Section7.3.9 00h DMA4CTL DMA Channel4 Control Read/write Word 0000h Section7.3.6 02h DMA4SA DMA Channel4 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA4DA DMA Channel4 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA4SZ DMA Channel4 TransferSize Read/write Word undefined Section7.3.9 00h DMA5CTL DMA Channel5 Control Read/write Word 0000h Section7.3.6 02h DMA5SA DMA Channel5 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA5DA DMA Channel5 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA5SZ DMA Channel5 TransferSize Read/write Word undefined Section7.3.9 00h DMA6CTL DMA Channel6 Control Read/write Word 0000h Section7.3.6 02h DMA6SA DMA Channel6 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA6DA DMA Channel6 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA6SZ DMA Channel6 TransferSize Read/write Word undefined Section7.3.9

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DMA Registers Table7-4.DMA Registers(continued) Offset Acronym RegisterName Type Access Reset Section 00h DMA7CTL DMA Channel7 Control Read/write Word 0000h Section7.3.6 02h DMA7SA DMA Channel7 SourceAddress Read/write Word, undefined Section7.3.7 doubleword 06h DMA7DA DMA Channel7 DestinationAddress Read/write Word, undefined Section7.3.8 doubleword 0Ah DMA7SZ DMA Channel7 TransferSize Read/write Word undefined Section7.3.9 331SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3.1 DMACTL0 Register

Figure7-6.DMACTL0 Register 15 14 13 12 11 10 9 8 Reserved DMA1TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Reserved DMA0TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table7-5.DMACTL0 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12-8 DMA1TSEL RW 0h DMA 1 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA1TRIG0 00001b = DMA1TRIG1 00010b = DMA1TRIG2 11110b = DMA1TRIG30 11111b = DMA1TRIG31 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-0 DMA0TSEL RW 0h DMA 0 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA0TRIG0 00001b = DMA0TRIG1 00010b = DMA0TRIG2 11110b = DMA0TRIG30 11111b = DMA0TRIG31

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7.3.2 DMACTL1 Register

Figure7-7.DMACTL1 Register 15 14 13 12 11 10 9 8 Reserved DMA3TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Reserved DMA2TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table7-6.DMACTL1 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12-8 DMA3TSEL RW 0h DMA 3 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA3TRIG0 00001b = DMA3TRIG1 00010b = DMA3TRIG2 11110b = DMA3TRIG30 11111b = DMA3TRIG31 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-0 DMA2TSEL RW 0h DMA 2 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA2TRIG0 00001b = DMA2TRIG1 00010b = DMA2TRIG2 11110b = DMA2TRIG30 11111b = DMA2TRIG31 333SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3.3 DMACTL2 Register

Figure7-8.DMACTL2 Register 15 14 13 12 11 10 9 8 Reserved DMA5TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Reserved DMA4TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table7-7.DMACTL2 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12-8 DMA5TSEL RW 0h DMA 5 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA5TRIG0 00001b = DMA5TRIG1 00010b = DMA5TRIG2 11110b = DMA5TRIG30 11111b = DMA5TRIG31 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-0 DMA4TSEL RW 0h DMA 4 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA4TRIG0 00001b = DMA4TRIG1 00010b = DMA4TRIG2 11110b = DMA4TRIG30 11111b = DMA4TRIG31

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7.3.4 DMACTL3 Register

Figure7-9.DMACTL3 Register 15 14 13 12 11 10 9 8 Reserved DMA7TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Reserved DMA6TSEL r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table7-8.DMACTL3 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0. 12-8 DMA7TSEL RW 0h DMA 7 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA7TRIG0 00001b = DMA7TRIG1 00010b = DMA7TRIG2 11110b = DMA7TRIG30 11111b = DMA7TRIG31 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-0 DMA6TSEL RW 0h DMA 6 triggerselect.These bitsselecttheDMA transfertrigger.See thedevice- specificdatasheetfornumber ofchannelsand triggerassignment. 00000b = DMA6TRIG0 00001b = DMA6TRIG1 00010b = DMA6TRIG2 11110b = DMA6TRIG30 11111b = DMA6TRIG31 335SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3.5 DMACTL4 Register

Figure7-10.DMACTL4 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved DMARMWDIS ROUNDROBIN ENNMI r0 r0 r0 r0 r0 rw-(0) rw-(0) rw-(0) Table7-9.DMACTL4 RegisterDescription Bit Field Type Reset Description 15-3 Reserved R 0h Reserved.Alwaysreadsas 0. 2 DMARMWDIS RW 0h Read-modify-writedisable.When set,thisbitinhibitsany DMA transfersfrom occurringduringCPU read-modify-writeoperations. 0b = DMA transferscan occurduringread-modify-writeCPU operations. 1b = DMA transfersinhibitedduringread-modify-writeCPU operations 1 ROUNDROBIN RW 0h Round robin.Thisbitenablestheround-robinDMA channelpriorities. 1b = DMA channelprioritychanges witheach transfer. 0 ENNMI RW 0h EnableNMI. Thisbitenablestheinterruptionofa DMA transferby an NMI. When an NMI interruptsa DMA transfer,thecurrenttransferiscompletednormally, furthertransfersarestoppedand DMAABORT isset. 0b = NMI does notinterruptDMA transfer. 1b = NMI interruptsa DMA transfer.

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7.3.6 DMAxCTL Register

DMA Channelx ControlRegister Figure7-11.DMAxCTL Register 15 14 13 12 11 10 9 8 Reserved DMADT DMADSTINCR DMASRCINCR r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 DMADSTBYTE DMASRCBYTE DMALEVEL DMAEN DMAIFG DMAIE DMAABORT DMAREQ rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table7-10.DMAxCTL RegisterDescription Bit Field Type Reset Description 15 Reserved R 0h Reserved.Alwaysreadsas 0. 14-12 DMADT RW 0h DMA transfermode 000b = Singletransfer 001b = Blocktransfer 010b = Burst-blocktransfer 011b = Burst-blocktransfer 100b = Repeated singletransfer 101b = Repeated blocktransfer 110b = Repeated burst-blocktransfer 111b = Repeated burst-blocktransfer 11-10 DMADSTINCR RW 0h DMA destinationincrement.Thisbitselectsautomaticincrementingor decrementingofthedestinationaddressaftereach byteorword transfer.When DMADSTBYTE = 1,thedestinationaddressincrements/decrementsby one. When DMADSTBYTE = 0,thedestinationaddressincrements/decrementsby two.The DMAxDA iscopiedintoa temporaryregisterand thetemporaryregister isincrementedordecremented.DMAxDA isnotincrementedordecremented. 00b = Destinationaddressisunchanged. 01b = Destinationaddressisunchanged. 10b = Destinationaddressisdecremented. 11b = Destinationaddressisincremented. 9-8 DMASRCINCR RW 0h DMA sourceincrement.Thisbitselectsautomaticincrementingordecrementing ofthesourceaddressforeach byteorword transfer.When DMASRCBYTE = 1, thesourceaddressincrements/decrementsby one.When DMASRCBYTE = 0, thesourceaddressincrements/decrementsby two.The DMAxSA iscopiedintoa temporaryregisterand thetemporaryregisterisincrementedordecremented. DMAxSA isnotincrementedordecremented. 00b = Sourceaddressisunchanged. 01b = Sourceaddressisunchanged. 10b = Sourceaddressisdecremented. 11b = Sourceaddressisincremented. 7 DMADSTBYTE RW 0h DMA destinationbyte.Thisbitselectsthedestinationas a byteorword. 0b = Word 1b = Byte 6 DMASRCBYTE RW 0h DMA sourcebyte.Thisbitselectsthesourceas a byteorword. 0b = Word 1b = Byte 5 DMALEVEL RW 0h DMA level.Thisbitselectsbetween edge-sensitiveand level-sensitivetriggers. 0b = Edge sensitive(risingedge) 1b = Levelsensitive(highlevel) 337SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DMA Registers www.ti.com Table7-10.DMAxCTL RegisterDescription(continued) Bit Field Type Reset Description

4 DMAEN RW 0h DMA enable

0b = Disabled 1b = Enabled

3 DMAIFG RW 0h DMA interruptflag

0b = No interruptpending 1b = Interruptpending

2 DMAIE RW 0h DMA interruptenable

0b = Disabled 1b = Enabled 1 DMAABORT RW 0h DMA abort.Thisbitindicatesifa DMA transferwas interruptby an NMI. 0b = DMA transfernotinterrupted 1b = DMA transferinterruptedby NMI 0 DMAREQ RW 0h DMA request.Software-controlledDMA start.DMAREQ isresetautomatically. 0b = No DMA start 1b = StartDMA

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7.3.7 DMAxSA Register

DMA Channelx SourceAddressRegister Figure7-12.DMAxSA Register 31 30 29 28 27 26 25 24 Reserved r0 r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 16 Reserved DMAxSA r0 r0 r0 r0 rw rw rw rw 15 14 13 12 11 10 9 8 DMAxSA rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSA rw rw rw rw rw rw rw rw Table7-11.DMAxSA RegisterDescription Bit Field Type Reset Description 31-20 Reserved R 0h Reserved.Alwaysreadsas 0. 19-0 DMAxSA RW undefined DMA sourceaddress.The sourceaddressregisterpointstotheDMA source addressforsingletransfersorthefirstsourceaddressforblocktransfers.The sourceaddressregisterremainsunchanged duringblockand burst-block transfers.Therearetwo words fortheDMAxSA register.Bits31-20are reservedand alwaysreadas zero.Readingorwritingbits19-16requiresthe use ofextendedinstructions.When writingtoDMAxSA withword instructions, bits19-16arecleared. 339SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3.8 DMAxDA Register

DMA Channelx DestinationAddressRegister Figure7-13.DMAxDA Register 31 30 29 28 27 26 25 24 Reserved r0 r0 r0 r0 r0 r0 r0 r0 23 22 21 20 19 18 17 16 Reserved DMAxDA r0 r0 r0 r0 rw rw rw rw 15 14 13 12 11 10 9 8 DMAxDA rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxDA rw rw rw rw rw rw rw rw Table7-12.DMAxDA RegisterDescription Bit Field Type Reset Description 31-20 Reserved R 0h Reserved.Alwaysreadsas 0. 19-0 DMAxDA RW undefined DMA destinationaddress.The destinationaddressregisterpointstotheDMA destinationaddressforsingletransfersorthefirstdestinationaddressforblock transfers.The destinationaddressregisterremainsunchanged duringblockand burst-blocktransfers.Therearetwo words fortheDMAxDA register.Bits31-20 arereservedand alwaysreadas zero.Readingorwritingbits19-16requires theuse ofextendedinstructions.When writingtoDMAxDA withword instructions,bits19-16arecleared.

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7.3.9 DMAxSZ Register

DMA Channelx SizeAddressRegister Figure7-14.DMAxSZ Register 15 14 13 12 11 10 9 8 DMAxSZ rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 DMAxSZ rw rw rw rw rw rw rw rw Table7-13.DMAxSZ RegisterDescription Bit Field Type Reset Description 15-0 DMAxSZ RW undefined DMA size.The DMA sizeregisterdefinesthenumber ofbyte/worddataper blocktransfer.DMAxSZ registerdecrementswitheach word orbytetransfer. When DMAxSZ decrementsto0,itisimmediatelyand automaticallyreloaded withitspreviouslyinitializedvalue. 00000h = Transferisdisabled. 00001h = One byteorword istransferred. 00002h = Two bytesorwords aretransferred. 0FFFFh = 65535 bytesorwords aretransferred. 341SLAU259E –May 2009–RevisedJanuary2013 DirectMemory Access (DMA) ControllerModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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7.3.10 DMAIV Register

DMA InterruptVectorRegister Figure7-15.DMAIV Register 15 14 13 12 11 10 9 8 DMAIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 DMAIV Table7-14.DMAIV RegisterDescription Bit Field Type Reset Description 15-0 DMAIV R 0h DMA interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:DMA channel0;InterruptFlag:DMA0IFG; Interrupt Priority:Highest 04h = InterruptSource:DMA channel1;InterruptFlag:DMA1IFG 06h = InterruptSource:DMA channel2;InterruptFlag:DMA2IFG 08h = InterruptSource:DMA channel3;InterruptFlag:DMA3IFG 0Ah = InterruptSource:DMA channel4;InterruptFlag:DMA4IFG 0Ch = InterruptSource:DMA channel5;InterruptFlag:DMA5IFG 0Eh = InterruptSource:DMA channel6;InterruptFlag:DMA6IFG 10h = InterruptSource:DMA channel7;InterruptFlag:DMA7IFG; Interrupt Priority:Lowest

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter8 SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule ThischapterdescribestheoperationofthedigitalI/Oportsinalldevices. 343SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.1 DigitalI/OIntroduction

The digitalI/Ofeaturesinclude:

IndependentlyprogrammableindividualI/Os
Any combinationofinputoroutput
IndividuallyconfigurableP1 and P2 interrupts.Some devicesmay includeadditionalportinterrupts.
Independentinputand outputdataregisters
Individuallyconfigurablepulluporpulldownresistors Deviceswithinthefamilymay have up totwelvedigitalI/Oportsimplemented(P1 toP11 and PJ).Most portscontaineightI/Olines;however,some portsmay containless(seethedevice-specificdatasheetfor portsavailable).Each I/Olineisindividuallyconfigurableforinputoroutputdirection,and each can be individuallyreadorwritten.Each I/Olineisindividuallyconfigurableforpulluporpulldownresistors,as wellas,configurabledrivestrength,fullorreduced.PJ containsonlyfourI/Olines. PortsP1 and P2 alwayshave interruptcapability.Each interruptfortheP1 and P2 I/Olinescan be individuallyenabledand configuredtoprovidean interrupton a risingorfallingedge ofan inputsignal.All P1 I/Olinessourcea singleinterruptvectorP1IV,and allP2 I/Olinessourcea different,singleinterrupt vectorP2IV.On some devices,additionalportswithinterruptcapabilitymay be available(seethedevice- specificdatasheetfordetails)and containtheirown respectiveinterruptvectors. Individualportscan be accessedas byte-wideportsorcan be combined intoword-wideportsand accessedviaword formats.PortpairsP1 and P2,P3 and P4,P5 and P6,and so on,areassociatedwith thenames PA, PB, PC, and so on,respectively.Allportregistersarehandledinthismanner withthis naming conventionexceptfortheinterruptvectorregisters;forexample,PAIV does notexistforP1IV and P2IV. When writingtoportPA withword operations,all16 bitsarewrittentotheport.When writingtothelower byteofthePA portusingbyteoperations,theupperbyteremainsunchanged.Similarly,writingtothe upperbyteofthePA portusingbyteinstructionsleavesthelowerbyteunchanged.When writingtoa port thatcontainslessthanthemaximum number ofbitspossible,theunused bitsarea "don'tcare".PortsPB, PC, PD, PE, and PF behave similarly. ReadingofthePA portusingword operationscausesall16 bitstobe transferredtothedestination. ReadingthelowerorupperbyteofthePA port(P1 orP2) and storingtomemory usingbyteoperations causesonlythelowerorupperbytetobe transferredtothedestination,respectively.ReadingofthePA portand storingtoa general-purposeregisterusingbyteoperationscausesthebytetransferredtobe writtentotheleastsignificantbyteoftheregister.The uppersignificantbyteofthedestinationregisteris clearedautomatically.PortsPB, PC, PD, PE, and PF behave similarly.When readingfromportsthat containlessthanthemaximum bitspossible,unused bitsarereadas zeros(similarlyforportPJ).

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8.2 DigitalI/OOperation

The digitalI/Oareconfiguredwithusersoftware.The setupand operationofthedigitalI/Oarediscussed inthefollowingsections.

8.2.1 InputRegisters(PxIN)

Each bitineach PxIN registerreflectsthevalueoftheinputsignalatthecorrespondingI/Opinwhen the pinisconfiguredas I/Ofunction.These registersarereadonly.

Bit= 0:Inputislow
Bit= 1:Inputishigh NOTE: Writingtoread-onlyregistersPxIN Writingtotheseread-onlyregistersresultsinincreasedcurrentconsumptionwhilethewrite attemptisactive.

8.2.2 Output Registers(PxOUT)

Each bitineach PxOUT registeristhevaluetobe outputon thecorrespondingI/Opinwhen thepinis configuredas I/Ofunction,outputdirection.

Bit= 0:Outputislow
Bit= 1:Outputishigh Ifthepinisconfiguredas I/Ofunction,inputdirectionand thepullup/pulldownresistorareenabled;the correspondingbitinthePxOUT registerselectspulluporpulldown.
Bit= 0:Pinispulleddown
Bit= 1:Pinispulledup

8.2.3 DirectionRegisters(PxDIR)

Each bitineach PxDIR registerselectsthedirectionofthecorrespondingI/Opin,regardlessofthe selectedfunctionforthepin.PxDIR bitsforI/Opinsthatareselectedforotherfunctionsmust be setas requiredby theotherfunction.

Bit= 0:Portpinisswitchedtoinputdirection
Bit= 1:Portpinisswitchedtooutputdirection

8.2.4 Pullupor Pulldown ResistorEnable Registers(PxREN)

Each bitineach PxREN registerenablesordisablesthepullup/pulldownresistorofthecorrespondingI/O pin.The correspondingbitinthePxOUT registerselectsifthepincontainsa pulluporpulldown.

Bit= 0:Pullup/pulldownresistordisabled
Bit= 1:Pullup/pulldownresistorenabled Table8-1summarizestheusage ofPxDIR,PxREN, and PxOUT forproperI/Oconfiguration. Table8-1.I/OConfiguration PxDIR PxREN PxOUT I/OConfiguration 0 0 x Input 0 1 0 Inputwithpulldownresistor 0 1 1 Inputwithpullupresistor 1 x x Output 345SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.2.5 Output DriveStrengthRegisters(PxDS)

Each bitineach PxDS registerselectseitherfulldriveorreduceddrivestrength.Defaultisreduceddrive strength.

Bit= 0:Reduced drivestrength
Bit= 1:Fulldrivestrength NOTE: Drivestrengthand EMI AlloutputsdefaulttoreduceddrivestrengthtoreduceEMI.Usingfulldrivestrengthcan resultinincreasedEMI.

8.2.6 FunctionSelectRegisters(PxSEL)

Portpinsareoftenmultiplexedwithotherperipheralmodule functions.See thedevice-specificdatasheet todeterminepinfunctions.Each PxSEL bitisused toselectthepinfunction– I/Oportorperipheral module function.

Bit= 0:I/OFunctionisselectedforthepin
Bit= 1:Peripheralmodule functionisselectedforthepin SettingPxSEL = 1 does notautomaticallysetthepindirection.Otherperipheralmodule functionsmay requirethePxDIR bitstobe configuredaccordingtothedirectionneeded forthemodule function.See the pinschematicsinthedevice-specificdatasheet. NOTE: P1 and P2 interruptsaredisabledwhen PxSEL = 1 When any PxSEL bitisset,thecorrespondingpin’s interruptfunctionisdisabled.Therefore, signalson thesepinsdoes notgenerateP1 orP2 interrupts,regardlessofthestateofthe correspondingP1IE orP2IE bit. When a portpinisselectedas an inputtoa peripheral,theinputsignaltotheperipheralisa latched representationofthesignalatthedevicepin.WhileitscorrespondingPxSEL = 1,theinternalinputsignal followsthesignalatthepin.However,ifitsPxSEL = 0,theinputtotheperipheralmaintainsthevalueof theinputsignalatthedevicepinbeforeitscorrespondingPxSEL bitwas reset.

8.2.7 PortInterrupts

Each pininportsP1 and P2 has interruptcapability,configuredwiththePxIFG,PxIE,and PxIES registers.On some devices,additionalportshave interruptcapability(seethedevice-specificdatasheet). AllP1 interruptflagsareprioritized,withP1IFG.0beingthehighest,and combined tosourcea single interruptvector.The highestpriorityenabledinterruptgeneratesa number intheP1IV register.This number can be evaluatedoradded totheprogramcountertoautomaticallyentertheappropriatesoftware routine.DisabledP1 interruptsdo notaffecttheP1IV value.The same functionalityexistsforP2.The PxIV registersareword accessonly.Some devicesmay containadditionalportinterruptsbesidesP1 and P2. See thedevicespecificdatasheettodeterminewhichportinterruptsareavailable. Each PxIFG bitistheinterruptflagforitscorrespondingI/Opinand issetwhen theselectedinputsignal edge occursatthepin.AllPxIFG interruptflagsrequestan interruptwhen theircorrespondingPxIE bit and theGIE bitareset.Softwarecan alsoseteach PxIFG flag,providinga way togeneratea software- initiatedinterrupt.

Bit= 0:No interruptispending
Bit= 1:An interruptispending Onlytransitions,notstaticlevels,cause interrupts.Ifany PxIFG flagbecomes setduringa Px interrupt serviceroutine,orissetaftertheRETI instructionofa Px interruptserviceroutineisexecuted,theset PxIFG flaggeneratesanotherinterrupt.Thisensuresthateach transitionisacknowledged.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DigitalI/OOperation NOTE: PxIFG flagswhen changing PxOUT, PxDIR, or PxREN WritingtoP1OUT, P1DIR, P1REN, P2OUT, P2DIR, orP2REN can resultinsettingthe correspondingP1IFG orP2IFG flags. Any access(readorwrite)oftheP1IV registerautomaticallyresetsthehighestpendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. Forexample,assume thatP1IFG.0has thehighestpriority.IftheP1IFG.0and P1IFG.2flagsaresetwhen theinterruptserviceroutineaccessestheP1IV register,P1IFG.0isresetautomatically.AftertheRETI instructionoftheinterruptserviceroutineisexecuted,theP1IFG.2generatesanotherinterrupt. PortP2 interruptsbehave similarly,and sourcea separatesingleinterruptvectorand utilizetheP2IV register. PortInterruptSoftwareExample The followingsoftwareexample shows therecommended use ofP1IV and thehandlingoverhead.The P1IV valueisadded tothePC toautomaticallyjump totheappropriateroutine.The P2IV issimilar. The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself. ;InterrupthandlerforP1 Cycles P1_HND... ;Interruptlatency 6 ADD &P1IV,PC;AddoffsettoJumptable3 RETI ;Vector0:Nointerrupt5 JMP P1_0_HND;Vector2:Port1bit0 2 JMP P1_1_HND;Vector4:Port1bit1 2 JMP P1_2_HND;Vector6:Port1bit2 2 JMP P1_3_HND;Vector8:Port1bit3 2 JMP P1_4_HND;Vector10:Port1bit4 2 JMP P1_5_HND;Vector12:Port1bit5 2 JMP P1_6_HND;Vector14:Port1bit6 2 JMP P1_7_HND;Vector16:Port1bit7 2 P1_7_HND ;Vector16:Port1bit7 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_6_HND ;Vector14:Port1bit6 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_5_HND ;Vector12:Port1bit5 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_4_HND ;Vector10:Port1bit4 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_3_HND ;Vector8:Port1bit3 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_2_HND ;Vector6:Port1bit2 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_1_HND ;Vector4:Port1bit1 ... ;Taskstartshere RETI ;Backtomainprogram 5 P1_0_HND ;Vector2:Port1bit0 ... ;Taskstartshere RETI ;Backtomainprogram 5 347SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. I/OConfigurationand LPMx.5 Low-Power Modes www.ti.com InterruptEdge SelectRegisters(PxIES) Each PxIES bitselectstheinterruptedge forthecorrespondingI/Opin.

Bit= 0:RespectivePxIFG flagissetwitha low-to-hightransition
Bit= 1:RespectivePxIFG flagissetwitha high-to-lowtransition NOTE: WritingtoPxIES WritingtoP1IES orP2IES foreach correspondingI/Ocan resultinsettingthecorresponding interruptflags. PxIES PxIN PxIFG 0 → 1 0 May be set 0 → 1 1 Unchanged 1 → 0 0 Unchanged 1 → 0 1 May be set InterruptEnable Registers(PxIE) Each PxIE bitenablestheassociatedPxIFG interruptflag.
Bit= 0:The interruptisdisabled
Bit= 1:The interruptisenabled

8.2.8 ConfiguringUnused PortPins

Unused I/Opinsshouldbe configuredas I/Ofunction,outputdirection,and leftunconnectedon thePC board,topreventa floatinginputand reducepower consumption.The valueofthePxOUT bitisdon't care,because thepinisunconnected.Alternatively,theintegratedpullup/pulldownresistorcan be enabled by settingthePxREN bitoftheunused pintopreventthefloatinginput.See theSYS chapterfor terminationofunused pins. NOTE: ConfiguringportJ and shared JTAG pins: ApplicationshouldensurethatportPJ isconfiguredproperlytopreventa floatinginput. Because portPJ issharedwiththeJTAG function,floatinginputsmay notbe noticedwhen inan emulationenvironment.PortJ isinitializedtohigh-impedanceinputsby default. 8.3 I/OConfigurationand LPMx.5 Low-Power Modes NOTE: The LPMx.5 low-powermodes may notbe availableon alldevices.The LPM4.5 power mode allowsforlowestpower consumptionand no clocksareavailable.The LPM3.5 power mode allowsforRTC mode operationatthelowestpower consumptionavailable.See theSYS chapterfordetails;alsosee thedevice-specificdatasheetforLPMx.5 low-powermodes that areavailable.WithrespecttothedigitalI/O,thissectionisapplicableforbothLPM3.5 and LPM4.5. The regulatorofthePower Management Module (PMM) isdisabledupon enteringLPMx.5 (LPM3.5 or LPM4.5),whichcausesallI/Oregisterconfigurationstobe lost.Because theI/Oregisterconfigurations arelost,theconfigurationofI/Opinsmust be handleddifferentlytoensurethatallpinsintheapplication behave ina controlledmanner upon enteringand exitingLPMx.5.ProperlysettingtheI/Opinsiscriticalto achievingthelowestpossiblepower consumptioninLPMx.5,as wellas preventingany possible uncontrolledinputoroutputI/Ostateintheapplication.The applicationhas completecontroloftheI/Opin conditionspreventingthepossibilityofunwanted spuriousactivityupon entryand exitfromLPMx.5.The detailedflowforenteringand exitingLPMx.5 withrespecttotheI/Ooperationisas follows:

348 DigitalI/OModule SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com I/OConfigurationand LPMx.5 Low-Power Modes 1. SetallI/OstogeneralpurposeI/Osand configureas needed.Each I/Ocan be settoinputhigh impedance,inputwithpulldown,inputwithpullup,outputhigh(loworhighdrivestrength),oroutputlow (loworhighdrivestrength).Itiscriticalthatno inputsareleftfloatingintheapplication,otherwise excesscurrentmay be drawn inLPMx.5.ConfiguringtheI/Ointhismanner ensuresthateach pinisin a safeconditionpriortoenteringLPMx.5. Optionally,configureinputinterruptpinsforwake-up fromLPMx.5.To wake thedevicefromLPMx.5,a general-purposeI/Oportmust containan inputportwithinterruptcapability.Not alldevicesinclude wakeup fromLPMx.5 viaI/O,and notallinputswithinterruptcapabilityofferwakeup fromLPMx.5.See thedevice-specificdatasheetforavailability.To configurea porttowake up thedevice,itshouldbe configuredproperlypriortoenteringLPMx.5.Each portshouldbe configuredas general-purposeinput. Pulldownsorpullupscan be appliedifrequired.SettingthePxIES bitofthecorrespondingregister determinestheedge transitionthatwakes thedevice.Lastly,thePxIE fortheportmust be enabled,as wellas thegeneralinterruptenable. NOTE: Itisnotpossibletowakeup fromLPMx.5 ifitsrespectiveinterruptflagisalreadyasserted.It isrecommended thattherespectiveflagbe clearedpriortoenteringLPMx.5.Itisalso recommended thatGIE = 1 be setpriortoentryintoLPMx.5.Any pendingflagsinthiscase couldthenbe servicedpriortoLPMx.5 entry. Althoughitisrecommended tosetGIE = 1 priortoenteringLPMx.5,itisnotrequired.Device wakeup fromLPMx.5 withan enabledwakeup functionwillstillcause thedevicetowake up fromLPMx.5 even withGIE = 0.IfGIE = 0 priortoLPMx.5,additionalcaremay be required. ShouldtherespectiveinterrupteventshouldoccurduringLPMx.5 entry,thedevicemay not recognizethisorany futureinterruptwakeup eventon thisfunction. 2. EnterLPMx.5 withLPMx.5 entrysequence,enablegeneralinterruptsforwake-up: MOV.B#PMMPW_H,&PMMCTL0_H ;OpenPMMregistersforwrite BIS.B#PMMREGOFF,&PMMCTL0_L ; BIS#GIE+CPUOFF+OSCOFF+SCG1+SCG0,SR;EnterLPMx.5whenPMMREGOFFisset 3. Upon entryintoLPMx.5,LOCKLPM5 residinginPM5CTL0 ofthePMM module issetautomatically. The I/Opinstatesareheldand lockedbased on thesettingspriortoLPMx.5 entry.Note thatonlythe pinconditionsareretained.Allotherportconfigurationregistersettingssuch as PxDIR,PxREN, PxOUT, PxDS, PxIES,and PxIE contentsarelost. 4. An LPMx.5 wakeup event(forexample,an edge on a configuredwakeup inputpin)startstheBOR entrysequence togetherwiththeregulator.Allperipheralregistersaresettotheirdefaultconditions. Upon exitfromLPMx.5,theI/OpinsremainlockedwhileLOCKLPM5 remainsset.KeepingtheI/O pinslockedensuresthatallpinconditionsremainstableupon enteringtheactivemode regardlessof thedefaultI/Oregistersettings. 5. Once inactivemode, theI/Oconfigurationand I/Ointerruptconfigurationthatwas notretainedduring LPMx.5 shouldbe restoredtothevaluespriortoenteringLPMx.5.Itisrecommended toreconfigure thePxIES and PxIE totheirprevioussettingstopreventa falseportinterruptfromoccurring.The LOCKLPM5 bitcan thenbe cleared,whichreleasestheI/Opinconditionsand I/Ointerrupt configuration.Any changes totheportconfigurationregisterswhileLOCKLPM5 isset,have no effect on theI/Opins. 6. AfterenablingtheI/Ointerrupts,theI/Ointerruptthatcaused thewakeup can be servicedindicatedby thePxIFG flags.These flagscan be used directly,orthecorrespondingPxIV registermay be used. Note thatthePxIFG flagcannotbe cleareduntiltheLOCKLPM5 bithas been cleared. NOTE: Itispossiblethatmultipleeventsoccurredon variousports.Inthesecases,multiplePxIFG flagswillbe set,and itcannotbe determinedwhichporthas caused theI/Owakeup. 349SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.4 DigitalI/ORegisters

The digitalI/OregistersarelistedinTable8-2.The base addressescan be foundinthedevice-specific datasheet.Each portgroupingbeginsatitsbase address.The addressoffsetsaregiveninTable8-2. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table8-2.DigitalI/ORegisters Offset Acronym RegisterName Type Access Reset Section 0Eh P1IV Port1 InterruptVector Read only Word 0000h Section8.4.1 0Eh P1IV_L Read only Byte 00h 0Fh P1IV_H Read only Byte 00h 1Eh P2IV Port2 InterruptVector Read only Word 0000h Section8.4.2 1Eh P2IV_L Read only Byte 00h 1Fh P2IV_H Read only Byte 00h 00h P1IN or Port1 Input Read only Byte Section8.4.9 PAIN_L 02h P1OUT or Port1 Output Read/write Byte undefined Section8.4.10 PAOUT_L 04h P1DIR or Port1 Direction Read/write Byte 00h Section8.4.11 PADIR_L 06h P1REN or Port1 ResistorEnable Read/write Byte 00h Section8.4.12 PAREN_L 08h P1DS or Port1 DriveStrength Read/write Byte 00h Section8.4.13 PADS_L 0Ah P1SEL or Port1 PortSelect Read/write Byte 00h Section8.4.14 PASEL_L 18h P1IES or Port1 InterruptEdge Select Read/write Byte undefined Section8.4.3 PAIES_L 1Ah P1IE or Port1 InterruptEnable Read/write Byte 00h Section8.4.4 PAIE_L 1Ch P1IFG or Port1 InterruptFlag Read/write Byte 00h Section8.4.5 PAIFG_L 01h P2IN or Port2 Input Read only Byte Section8.4.9 PAIN_H 03h P2OUT or Port2 Output Read/write Byte undefined Section8.4.10 PAOUT_H 05h P2DIR or Port2 Direction Read/write Byte 00h Section8.4.11 PADIR_H 07h P2REN or Port2 ResistorEnable Read/write Byte 00h Section8.4.12 PAREN_H 09h P2DS or Port2 DriveStrength Read/write Byte 00h Section8.4.13 PADS_H 0Bh P2SEL or Port2 PortSelect Read/write Byte 00h Section8.4.14 PASEL_H 19h P2IES or Port2 InterruptEdge Select Read/write Byte undefined Section8.4.6 PAIES_H 1Bh P2IE or Port2 InterruptEnable Read/write Byte 00h Section8.4.7 PAIE_H 1Dh P2IFG or Port2 InterruptFlag Read/write Byte 00h Section8.4.8 PAIFG_H 00h P3IN or Port3 Input Read only Byte Section8.4.9 PBIN_L 02h P3OUT or Port3 Output Read/write Byte undefined Section8.4.10 PBOUT_L

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DigitalI/ORegisters Table8-2.DigitalI/ORegisters(continued) Offset Acronym RegisterName Type Access Reset Section 04h P3DIR or Port3 Direction Read/write Byte 00h Section8.4.11 PBDIR_L 06h P3REN or Port3 ResistorEnable Read/write Byte 00h Section8.4.12 PBREN_L 08h P3DS or Port3 DriveStrength Read/write Byte 00h Section8.4.13 PBDS_L 0Ah P3SEL or Port3 PortSelect Read/write Byte 00h Section8.4.14 PBSEL_L 01h P4IN or Port4 Input Read only Byte Section8.4.9 PBIN_H 03h P4OUT or Port4 Output Read/write Byte undefined Section8.4.10 PBOUT_H 05h P4DIR or Port4 Direction Read/write Byte 00h Section8.4.11 PBDIR_H 07h P4REN or Port4 ResistorEnable Read/write Byte 00h Section8.4.12 PBREN_H 09h P4DS or Port4 DriveStrength Read/write Byte 00h Section8.4.13 PBDS_H 0Bh P4SEL or Port4 PortSelect Read/write Byte 00h Section8.4.14 PBSEL_H 00h P5IN or Port5 Input Read only Byte Section8.4.9 PCIN_L 02h P5OUT or Port5 Output Read/write Byte undefined Section8.4.10 PCOUT_L 04h P5DIR or Port5 Direction Read/write Byte 00h Section8.4.11 PCDIR_L 06h P5REN or Port5 ResistorEnable Read/write Byte 00h Section8.4.12 PCREN_L 08h P5DS or Port5 DriveStrength Read/write Byte 00h Section8.4.13 PCDS_L 0Ah P5SEL or Port5 PortSelect Read/write Byte 00h Section8.4.14 PCSEL_L 01h P6IN or Port6 Input Read only Byte Section8.4.9 PCIN_H 03h P6OUT or Port6 Output Read/write Byte undefined Section8.4.10 PCOUT_H 05h P6DIR or Port6 Direction Read/write Byte 00h Section8.4.11 PCDIR_H 07h P6REN or Port6 ResistorEnable Read/write Byte 00h Section8.4.12 PCREN_H 09h P6DS or Port6 DriveStrength Read/write Byte 00h Section8.4.13 PCDS_H 0Bh P6SEL or Port6 PortSelect Read/write Byte 00h Section8.4.14 PCSEL_H 00h P7IN or Port7 Input Read only Byte Section8.4.9 PDIN_L 02h P7OUT or Port7 Output Read/write Byte undefined Section8.4.10 PDOUT_L 04h P7DIR or Port7 Direction Read/write Byte 00h Section8.4.11 PDDIR_L 06h P7REN or Port7 ResistorEnable Read/write Byte 00h Section8.4.12 PDREN_L 08h P7DS or Port7 DriveStrength Read/write Byte 00h Section8.4.13 PDDS_L 0Ah P7SEL or Port7 PortSelect Read/write Byte 00h Section8.4.14 PDSEL_L 351SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DigitalI/ORegisters www.ti.com Table8-2.DigitalI/ORegisters(continued) Offset Acronym RegisterName Type Access Reset Section 01h P8IN or Port8 Input Read only Byte Section8.4.9 PDIN_H 03h P8OUT or Port8 Output Read/write Byte undefined Section8.4.10 PDOUT_H 05h P8DIR or Port8 Direction Read/write Byte 00h Section8.4.11 PDDIR_H 07h P8REN or Port8 ResistorEnable Read/write Byte 00h Section8.4.12 PDREN_H 09h P8DS or Port8 DriveStrength Read/write Byte 00h Section8.4.13 PDDS_H 0Bh P8SEL or Port8 PortSelect Read/write Byte 00h Section8.4.14 PDSEL_H 00h P9IN or Port9 Input Read only Byte Section8.4.9 PEIN_L 02h P9OUT or Port9 Output Read/write Byte undefined Section8.4.10 PEOUT_L 04h P9DIR or Port9 Direction Read/write Byte 00h Section8.4.11 PEDIR_L 06h P9REN or Port9 ResistorEnable Read/write Byte 00h Section8.4.12 PEREN_L 08h P9DS or Port9 DriveStrength Read/write Byte 00h Section8.4.13 PEDS_L 0Ah P9SEL or Port9 PortSelect Read/write Byte 00h Section8.4.14 PESEL_L 01h P10IN or Port10 Input Read only Byte Section8.4.9 PEIN_H 03h P10OUT or Port10 Output Read/write Byte undefined Section8.4.10 PEOUT_H 05h P10DIR or Port10 Direction Read/write Byte 00h Section8.4.11 PEDIR_H 07h P10REN or Port10 ResistorEnable Read/write Byte 00h Section8.4.12 PEREN_H 09h P10DS or Port10 DriveStrength Read/write Byte 00h Section8.4.13 PEDS_H 0Bh P10SEL or Port10 PortSelect Read/write Byte 00h Section8.4.14 PESEL_H 00h P11IN or Port11 Input Read only Byte Section8.4.9 PFIN_L 02h P11OUT or Port11 Output Read/write Byte undefined Section8.4.10 PFOUT_L 04h P11DIR or Port11 Direction Read/write Byte 00h Section8.4.11 PFDIR_L 06h P11REN or Port11 ResistorEnable Read/write Byte 00h Section8.4.12 PFREN_L 08h P11DS or Port11 DriveStrength Read/write Byte 00h Section8.4.13 PFDS_L 0Ah P11SEL or Port11 PortSelect Read/write Byte 00h Section8.4.14 PFSEL_L 00h PAIN PortA Input Read only Word 00h PAIN_L Read only Byte 01h PAIN_H Read only Byte 02h PAOUT PortA Output Read/write Word undefined 02h PAOUT_L Read/write Byte undefined 03h PAOUT_H Read/write Byte undefined 04h PADIR PortA Direction Read/write Word 0000h

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DigitalI/ORegisters Table8-2.DigitalI/ORegisters(continued) Offset Acronym RegisterName Type Access Reset Section 04h PADIR_L Read/write Byte 00h 05h PADIR_H Read/write Byte 00h 06h PAREN PortA ResistorEnable Read/write Word 0000h 06h PAREN_L Read/write Byte 00h 07h PAREN_H Read/write Byte 00h 08h PADS PortA DriveStrength Read/write Word 0000h 08h PADS_L Read/write Byte 00h 09h PADS_H Read/write Byte 00h 0Ah PASEL PortA PortSelect Read/write Word 0000h 0Ah PASEL_L Read/write Byte 00h 0Bh PASEL_H Read/write Byte 00h 18h PAIES PortA InterruptEdge Select Read/write Word undefined 18h PAIES_L Read/write Byte undefined 19h PAIES_H Read/write Byte undefined 1Ah PAIE PortA InterruptEnable Read/write Word 0000h 1Ah PAIE_L Read/write Byte 00h 1Bh PAIE_H Read/write Byte 00h 1Ch PAIFG PortA InterruptFlag Read/write Word 0000h 1Ch PAIFG_L Read/write Byte 00h 1Dh PAIFG_H Read/write Byte 00h 00h PBIN PortB Input Read only Word 00h PBIN_L Read only Byte 01h PBIN_H Read only Byte 02h PBOUT PortB Output Read/write Word undefined 02h PBOUT_L Read/write Byte undefined 03h PBOUT_H Read/write Byte undefined 04h PBDIR PortB Direction Read/write Word 0000h 04h PBDIR_L Read/write Byte 00h 05h PBDIR_H Read/write Byte 00h 06h PBREN PortB ResistorEnable Read/write Word 0000h 06h PBREN_L Read/write Byte 00h 07h PBREN_H Read/write Byte 00h 08h PBDS PortB DriveStrength Read/write Word 0000h 08h PBDS_L Read/write Byte 00h 09h PBDS_H Read/write Byte 00h 0Ah PBSEL PortB PortSelect Read/write Word 0000h 0Ah PBSEL_L Read/write Byte 00h 0Bh PBSEL_H Read/write Byte 00h 00h PCIN PortC Input Read only Word 00h PCIN_L Read only Byte 01h PCIN_H Read only Byte 02h PCOUT PortC Output Read/write Word undefined 02h PCOUT_L Read/write Byte undefined 03h PCOUT_H Read/write Byte undefined 04h PCDIR PortC Direction Read/write Word 0000h 04h PCDIR_L Read/write Byte 00h 05h PCDIR_H Read/write Byte 00h 353SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. DigitalI/ORegisters www.ti.com Table8-2.DigitalI/ORegisters(continued) Offset Acronym RegisterName Type Access Reset Section 06h PCREN PortC ResistorEnable Read/write Word 0000h 06h PCREN_L Read/write Byte 00h 07h PCREN_H Read/write Byte 00h 08h PCDS PortC DriveStrength Read/write Word 0000h 08h PCDS_L Read/write Byte 00h 09h PCDS_H Read/write Byte 00h 0Ah PCSEL PortC PortSelect Read/write Word 0000h 0Ah PCSEL_L Read/write Byte 00h 0Bh PCSEL_H Read/write Byte 00h 00h PDIN PortD Input Read only Word 00h PDIN_L Read only Byte 01h PDIN_H Read only Byte 02h PDOUT PortD Output Read/write Word undefined 02h PDOUT_L Read/write Byte undefined 03h PDOUT_H Read/write Byte undefined 04h PDDIR PortD Direction Read/write Word 0000h 04h PDDIR_L Read/write Byte 00h 05h PDDIR_H Read/write Byte 00h 06h PDREN PortD ResistorEnable Read/write Word 0000h 06h PDREN_L Read/write Byte 00h 07h PDREN_H Read/write Byte 00h 08h PDDS PortD DriveStrength Read/write Word 0000h 08h PDDS_L Read/write Byte 00h 09h PDDS_H Read/write Byte 00h 0Ah PDSEL PortD PortSelect Read/write Word 0000h 0Ah PDSEL_L Read/write Byte 00h 0Bh PDSEL_H Read/write Byte 00h 00h PEIN PortE Input Read only Word 00h PEIN_L Read only Byte 01h PEIN_H Read only Byte 02h PEOUT PortE Output Read/write Word undefined 02h PEOUT_L Read/write Byte undefined 03h PEOUT_H Read/write Byte undefined 04h PEDIR PortE Direction Read/write Word 0000h 04h PEDIR_L Read/write Byte 00h 05h PEDIR_H Read/write Byte 00h 06h PEREN PortE ResistorEnable Read/write Word 0000h 06h PEREN_L Read/write Byte 00h 07h PEREN_H Read/write Byte 00h 08h PEDS PortE DriveStrength Read/write Word 0000h 08h PEDS_L Read/write Byte 00h 09h PEDS_H Read/write Byte 00h 0Ah PESEL PortE PortSelect Read/write Word 0000h 0Ah PESEL_L Read/write Byte 00h 0Bh PESEL_H Read/write Byte 00h 00h PFIN PortF Input Read only Word 00h PFIN_L Read only Byte

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com DigitalI/ORegisters Table8-2.DigitalI/ORegisters(continued) Offset Acronym RegisterName Type Access Reset Section 01h PFIN_H Read only Byte 02h PFOUT PortF Output Read/write Word undefined 02h PFOUT_L Read/write Byte undefined 03h PFOUT_H Read/write Byte undefined 04h PFDIR PortF Direction Read/write Word 0000h 04h PFDIR_L Read/write Byte 00h 05h PFDIR_H Read/write Byte 00h 06h PFREN PortF ResistorEnable Read/write Word 0000h 06h PFREN_L Read/write Byte 00h 07h PFREN_H Read/write Byte 00h 08h PFDS PortF DriveStrength Read/write Word 0000h 08h PFDS_L Read/write Byte 00h 09h PFDS_H Read/write Byte 00h 0Ah PFSEL PortF PortSelect Read/write Word 0000h 0Ah PFSEL_L Read/write Byte 00h 0Bh PFSEL_H Read/write Byte 00h 00h PJIN PortJ Input Read only Word 00h PJIN_L Read only Byte 01h PJIN_H Read only Byte 02h PJOUT PortJ Output Read/write Word undefined 02h PJOUT_L Read/write Byte undefined 03h PJOUT_H Read/write Byte undefined 04h PJDIR PortJ Direction Read/write Word 0000h 04h PJDIR_L Read/write Byte 00h 05h PJDIR_H Read/write Byte 00h 06h PJREN PortJ ResistorEnable Read/write Word 0000h 06h PJREN_L Read/write Byte 00h 07h PJREN_H Read/write Byte 00h 08h PJDS PortJ DriveStrength Read/write Word 0000h 08h PJDS_L Read/write Byte 00h 09h PJDS_H Read/write Byte 00h 355SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.4.1 P1IV Register

Port1 InterruptVectorRegister Figure8-1.P1IV Register 15 14 13 12 11 10 9 8 P1IV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 P1IV r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table8-3.P1IV RegisterDescription Bit Field Type Reset Description 15-0 P1IV R 0h Port1 interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Port1.0interrupt;InterruptFlag:P1IFG.0;Interrupt Priority:Highest 04h = InterruptSource:Port1.1interrupt;InterruptFlag:P1IFG.1 06h = InterruptSource:Port1.2interrupt;InterruptFlag:P1IFG.2 08h = InterruptSource:Port1.3interrupt;InterruptFlag:P1IFG.3 0Ah = InterruptSource:Port1.4interrupt;InterruptFlag:P1IFG.4 0Ch = InterruptSource:Port1.5interrupt;InterruptFlag:P1IFG.5 0Eh = InterruptSource:Port1.6interrupt;InterruptFlag:P1IFG.6 10h = InterruptSource:Port1.7interrupt;InterruptFlag:P1IFG.7;Interrupt Priority:Lowest

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8.4.2 P2IV Register

Port2 InterruptVectorRegister Figure8-2.P2IV Register 15 14 13 12 11 10 9 8 P2IV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 P2IV r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table8-4.P2IV RegisterDescription Bit Field Type Reset Description 15-0 P2IV R 0h Port2 interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Port2.0interrupt;InterruptFlag:P2IFG.0;Interrupt Priority:Highest 04h = InterruptSource:Port2.1interrupt;InterruptFlag:P2IFG.1 06h = InterruptSource:Port2.2interrupt;InterruptFlag:P2IFG.2 08h = InterruptSource:Port2.3interrupt;InterruptFlag:P2IFG.3 0Ah = InterruptSource:Port2.4interrupt;InterruptFlag:P2IFG.4 0Ch = InterruptSource:Port2.5interrupt;InterruptFlag:P2IFG.5 0Eh = InterruptSource:Port2.6interrupt;InterruptFlag:P2IFG.6 10h = InterruptSource:Port2.7interrupt;InterruptFlag:P2IFG.7;Interrupt Priority:Lowest 357SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.4.3 P1IES Register

Port1 InterruptEdge SelectRegister Figure8-3.P1IES Register 7 6 5 4 3 2 1 0 P1IES rw rw rw rw rw rw rw rw Table8-5.P1IES RegisterDescription Bit Field Type Reset Description 7-0 P1IES RW undefined Port1 interruptedge select 0b = P1IFG flagissetwitha low-to-hightransition. 1b = P1IFG flagissetwitha high-to-lowtransition.

8.4.4 P1IE Register

Port1 InterruptEnableRegister Figure8-4.P1IE Register 7 6 5 4 3 2 1 0 P1IE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-6.P1IE RegisterDescription Bit Field Type Reset Description 7-0 P1IE RW 0h Port1 interruptenable 0b = Correspondingportinterruptdisabled 1b = Correspondingportinterruptenabled

8.4.5 P1IFG Register

Port1 InterruptFlagRegister Figure8-5.P1IFG Register 7 6 5 4 3 2 1 0 P1IFG rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-7.P1IFG RegisterDescription Bit Field Type Reset Description 7-0 P1IFG RW 0h Port1 interruptflag 0b = No interruptispending 1b = Interruptispending

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8.4.6 P2IES Register

Port2 InterruptEdge SelectRegister Figure8-6.P2IES Register 7 6 5 4 3 2 1 0 P2IES rw rw rw rw rw rw rw rw Table8-8.P2IES RegisterDescription Bit Field Type Reset Description 7-0 P2IES RW undefined Port2 interruptedge select 0b = P2IFG flagissetwitha low-to-hightransition. 1b = P2IFG flagissetwitha high-to-lowtransition.

8.4.7 P2IE Register

Port2 InterruptEnableRegister Figure8-7.P2IE Register 7 6 5 4 3 2 1 0 P2IE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-9.P2IE RegisterDescription Bit Field Type Reset Description 7-0 P2IE RW 0h Port2 interruptenable 0b = Correspondingportinterruptdisabled 1b = Correspondingportinterruptenabled

8.4.8 P2IFG Register

Port2 InterruptFlagRegister Figure8-8.P2IFG Register 7 6 5 4 3 2 1 0 P2IFG rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-10.P2IFG RegisterDescription Bit Field Type Reset Description 7-0 P2IFG RW 0h Port2 interruptflag 0b = No interruptispending 1b = Interruptispending 359SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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8.4.9 PxIN Register

Figure8-9.PxIN Register 7 6 5 4 3 2 1 0 PxIN r r r r r r r r Table8-11.PxIN RegisterDescription Bit Field Type Reset Description 7-0 PxIN R undefined Portx input.Read only.

8.4.10 PxOUT Register

Figure8-10.PxOUT Register 7 6 5 4 3 2 1 0 PxOUT rw rw rw rw rw rw rw rw Table8-12.PxOUT RegisterDescription Bit Field Type Reset Description 7-0 PxOUT RW undefined Portx output When I/Oconfiguredtooutputmode: 0b = Outputislow 1b = Outputishigh When I/Oconfiguredtoinputmode and pullups/pulldownsenabled: 0b = Pulldownselected 1b = Pullupselected

8.4.11 PxDIR Register

Figure8-11.PxDIR Register 7 6 5 4 3 2 1 0 PxDIR rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-13.PxDIR RegisterDescription Bit Field Type Reset Description 7-0 PxDIR RW 0h Portx direction 0b = Portconfiguredas input 1b = Portconfiguredas output

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8.4.12 PxREN Register

Portx Pullup/PulldownResistorEnableRegisters Figure8-12.PxREN Register 7 6 5 4 3 2 1 0 PxREN rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-14.PxREN RegisterDescription Bit Field Type Reset Description 7-0 PxREN RW 0h Portx pullup/pulldownresistorenable.When respectiveportisconfiguredas input,settingthisbitwillenablethepulluporpulldown.See Table8-1 0b = Pulluporpulldowndisabled. 1b = Pulluporpulldownenabled.

8.4.13 PxDS Register

Portx DriveStrengthRegister Figure8-13.PxDS Register 7 6 5 4 3 2 1 0 PxDS rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-15.PxDS RegisterDescription Bit Field Type Reset Description 7-0 PxDS RW 0h Portx drivestrength 0b = Reduced outputdrivestrength 1b = Fulloutputdrivestrength

8.4.14 PxSEL Register

Figure8-14.PxSEL Register 7 6 5 4 3 2 1 0 PxSEL rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table8-16.PxSEL RegisterDescription Bit Field Type Reset Description 7-0 PxSEL RW 0h Portx functionselection 0b = I/Ofunctionisselected 1b = Peripheralmodule functionisselected 361SLAU259E –May 2009–RevisedJanuary2013 DigitalI/OModule SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter9 SLAU259E –May 2009–RevisedJanuary2013 PortMapping Controller The portmapping controllerallowsa flexiblemapping of digitalfunctionsto portpins.This chapter describestheportmapping controller.

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9.1 PortMapping ControllerIntroduction

The portmapping controllerallowstheflexibleand reconfigurablemapping ofdigitalfunctionstoportpins. The portmapping controllerfeaturesare:

Configurationprotectedby writeaccesskey.
Defaultmapping providedforeach portpin(device-dependent,thedevicepinoutinthedevice-specific datasheet).
Mapping can be reconfiguredduringruntime.
Each outputsignalcan be mapped toseveraloutputpins.

9.2 PortMapping ControllerOperation

The portmapping isconfiguredwithusersoftware.The setupisdiscussedinthefollowingsections.

9.2.1 Access

To enablewriteaccesstoany oftheportmapping controllerregisters,thecorrectkey must be writteninto thePMAPKEYID register.The PMAPKEYID registeralwaysreads096A5h.Writingthekey 02D52h grants writeaccesstoallportmapping controllerregisters.Read accessisalwayspossible. Ifan invalidkey iswrittenwhilewriteaccessisgranted,any furtherwriteaccessesareprevented.Itis recommended thattheapplicationcompletesmapping configurationby writingan invalidkey. Thereisa timeoutcounterimplementedthatisincrementedwitheach (assembler)instruction,and when it countsto32,thewriteaccessislockedagain.Any accesstotheportmapping controllerregistersresets thecounter.Interruptsshouldbe disabledduringtheconfigurationprocessortheapplicationshouldtake precautionsthattheexecutionofan interruptserviceroutinedoes notaccidentallycause a permanent lockoftheportmapping registers;forexample,by usingthereconfigurationcapability(seeSection9.2.2). The accessstatusisreflectedinthePMAPLOCK bit. By default,theportmapping controllerallowsonlyone configurationafterPUC. A second attemptto enablewriteaccessby writingthecorrectkey isignored,and theregistersremainlocked.A PUC is requiredtodisablethepermanentlockagain.Ifitisnecessarytoreconfigurethemapping duringruntime, thePMAPRECFG bitmust be setduringthefirstwriteaccesstimeslot.IfPMAPRECFG isclearedduring laterconfigurationsessions,no more configurationsessionsarepossible.

9.2.2 Mapping

Foreach portpin,Px.y,on portsprovidingthemapping functionality,a mapping register,PxMAPy, is available.Settingthisregistertoa certainvaluemaps a module'sinputand outputsignalstothe respectiveportpinPx.y.The portpinitselfisswitchedfroma generalpurposeI/Ototheselected peripheral/secondaryfunctionby settingthecorrespondingPxSEL.y bitto1.Iftheinputortheoutput functionofthemodule isused,itistypicallydefinedby thesettingthePxDIR.ybit.IfPxDIR.y= 0,thepin isan input,ifPxDIR.y= 1,thepinisan output.Therearealsoperipherals(forexample,theUSCI module) thatcontrolthedirectionoreven otherfunctionsofthepin(forexample,open drain),and theseoptions aredocumented inthemapping table. Withtheportmapping functionalitytheoutputofa module can be mapped tomultiplepins.Alsotheinput ofa module can receiveinputsfrommultiplepins.When mapping multipleinputsontoone function,care needs tobe takenbecause theinputsignalsarelogicallyORed togetherwithoutapplyingany priority; therefore,a logicone on any oftheinputsresultsina logicone atthemodule.IfthePxSEL.y bitis0,the correspondinginputsignalisa logiczero. The mapping isdevice-dependent;see thedevice-specificdatasheetforavailablefunctionsand specific values.The use ofmapping mnemonics toabstracttheunderlyingPxMAPy valuesisrecommended to allowsimpleportabilitybetween differentdevices.Table9-1shows some examplesformapping mnemonics ofsome common peripherals. Allmappable portpinsprovidethefunctionPM_ANALOG (0FFh).Settingtheportmapping register PxMAPy toPM_ANALOG togetherwithPxSEL.y = 1 disablestheoutputdriverand theinputSchmitt- trigger,topreventparasiticcrosscurrentswhen applyinganalogsignals. 363SLAU259E –May 2009–RevisedJanuary2013 PortMapping Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PortMapping ControllerOperation www.ti.com Table9-1.Examples forPortMapping Mnemonics and Functions InputPin Function Output Pin FunctionPxMAPy Mnemonic With PxSEL.y = 1 and PxDIR.y = 0 With PxSEL.y = 1 and PxDIR.y = 1 PM_NONE None DVSS PM_ACLK None ACLK PM_MCLK None MCLK PM_SMCLK None SMCLK PM_TA0CLK Timer_A0 clockinput DVSS PM_TA0CCR0A Timer_A0 CCR0 captureinputCCI0A TA0 CCR0 compare outputOut0 PM_TA0CCR1A Timer_A0 CCR1 captureinputCCI1A TA0 CCR1 compare outputOut1 PM_TA0CCR2A Timer_A0 CCR2 captureinputCCI2A TA0 CCR2 compare outputOut2 PM_TA0CCR3A Timer_A0 CCR3 captureinputCCI3A TA0 CCR3 compare outputOut3 PM_TA0CCR4A Timer_A0 CCR4 captureinputCCI4A TA0 CCR4 compare outputOut4 PM_TA1CLK Timer_A1 clockinput DVSS PM_TA1CCR0A Timer_A1 CCR0 captureinputCCI0A TA1 CCR0 compare outputOut0 PM_TA1CCR1A Timer_A1 CCR1 captureinputCCI1A TA1 CCR1 compare outputOut1 PM_TA1CCR2A Timer_A1 CCR2 captureinputCCI2A TA1 CCR2 compare outputOut2 PM_TBCLK Timer_B clockinput DVSS PM_TBOUTH Timer_B outputshighimpedance DVSS PM_TBCCR0A Timer_B CCR0 captureinputCCI0A TB CCR0 compare outputOut0 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR1A Timer_B CCR1 captureinputCCI1A TB CCR1 compare outputOut1 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR2A Timer_B CCR2 captureinputCCI2A TB CCR2 compare outputOut2 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR3A Timer_B CCR3 captureinputCCI3A TB CCR3 compare outputOut3 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR4A Timer_B CCR4 captureinputCCI4A TB CCR4 compare outputOut4 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR5A Timer_B CCR5 captureinputCCI3A TB CCR5 compare outputOut5 [directioncontrolledby Timer_B (TBOUTH)] PM_TBCCR6A Timer_B CCR6 captureinputCCI4A TB CCR6 compare outputOut6 [directioncontrolledby Timer_B (TBOUTH)] PM_UCA0RXD USCI_A0 UART RXD (directioncontrolledby USCI -input) PM_UCA0SOMI USCI_A0 SPI slaveoutmasterin(directioncontrolledby USCI) PM_UCA0TXD USCI_A0 UART TXD (directioncontrolledby USCI -output) PM_UCA0SIMO USCI_A0 SPI slaveinmasterout(directioncontrolledby USCI) PM_UCA0CLK USCI_A0 clockinput/output(directioncontrolledby USCI) PM_UCA0STE USCI_A0 SPI slavetransmitenable(directioncontrolledby USCI) PM_UCB0SOMI USCI_B0 SPI slaveoutmasterin(directioncontrolledby USCI) PM_UCB0SCL USCI_B0 I2C clock(opendrainand directioncontrolledby USCI PM_UCB0SIMO USCI_B0 SPI slaveinmasterout(directioncontrolledby USCI) PM_UCB0SDA USCI_B0 I2C data(opendrainand directioncontrolledby USCI) PM_UCB0CLK USCI_B0 clockinput/output(directioncontrolledby USCI) PM_UCB0STE USCI_B0 SPI slavetransmitenable(directioncontrolledby USCI) PM_ANALOG Disablestheoutputdriverand theinputSchmitt-triggertopreventparasiticcrosscurrentswhen applying analogsignals

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9.3 PortMapping ControllerRegisters

The controlregisterfortheportmapping controllerarelistedinTable9-2.The mapping registersarelisted inTable9-3.The mapping registerscan alsobe accessedas words,as shown inTable9-4. Table9-2.PortMapping ControlRegisters Offset Acronym RegisterName Type Reset 00h PMAPKEYID Portmapping key register Read/write ResetwithPUC 02h PMAPCTL Portmapping controlregister Read/write ResetwithPUC Table9-3.PortMapping RegistersforPortPx – Byte Access Offset Acronym RegisterName Type Reset 00h PxMAP0 PortPx.0mapping register Read/write Devicedependent 01h PxMAP1 PortPx.1mapping register Read/write Devicedependent 02h PxMAP2 PortPx.2mapping register Read/write Devicedependent 03h PxMAP3 PortPx.3mapping register Read/write Devicedependent 04h PxMAP4 PortPx.4mapping register Read/write Devicedependent 05h PxMAP5 PortPx.5mapping register Read/write Devicedependent 06h PxMAP6 PortPx.6mapping register Read/write Devicedependent 07h PxMAP7 PortPx.7mapping register Read/write Devicedependent Table9-4.PortMapping RegistersforPortPx – Word Access Offset Acronym RegisterName Type Reset 00h PxMAP01 PortPx.0/PortPx.1mapping register Read/write Devicedependent 02h PxMAP23 PortPx.2/PortPx.3mapping register Read/write Devicedependent 04h PxMAP45 PortPx.4/PortPx.5mapping register Read/write Devicedependent 06h PxMAP67 PortPx.6/PortPx.7mapping register Read/write Devicedependent 365SLAU259E –May 2009–RevisedJanuary2013 PortMapping Controller SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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9.3.1 PMAPKEYID Register

Figure9-1.PMAPKEYID Register 15 14 13 12 11 10 9 8 PMAPKEYx 7 6 5 4 3 2 1 0 PMAPKEYx Table9-5.PMAPKEYID RegisterDescription Bit Field Type Reset Description 15-0 PMAPKEYx RW 96A5h Portwriteaccesskey.Alwaysreads096A5h.Must be written02D52h forwrite accesstotheportmapping registers.

9.3.2 PMAPCTL Register

PortMapping ControlRegister Figure9-2.PMAPCTL Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved PMAPRECFG PMAPLOCKED r0 r0 r0 r0 r0 r0 rw-0 r-1 Table9-6.PMAPCTL RegisterDescription Bit Field Type Reset Description 15-2 Reserved R 0h Reserved.Alwaysreadsas 0.

1 PMAPRECFG RW 0h Portmapping reconfigurationcontrolbit

0b = Configurationallowedonlyonce 1b = Allowreconfigurationofportmapping 0 PMAPLOCKED R 1h Portmapping lockbit.Read only 0b = Access tomapping registersisgranted 1b = Access tomapping registersislocked

9.3.3 PxMAPy Register

PortPx.yMapping Register Figure9-3.PxMAPy Register 7 6 5 4 3 2 1 0 PMAPx rw-0(1) rw-0(1) rw-0(1) rw-0(1) rw-0(1) rw-0(1) rw-0(1) rw-0(1) (1) Ifnotallbitsarerequiredtodecode allprovidedfunctions,theunused bitsarer0. Table9-7.PxMAPy RegisterDescription Bit Field Type Reset Description 7-0 PMAPx RW 0h Selectssecondaryportfunction.Settingsaredevice-dependent;see thedevice- specificdatasheet.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter10 SLAU259E –May 2009–RevisedJanuary2013 CyclicRedundancy Check (CRC) Module The cyclicredundancycheck (CRC) module providesa signaturefora givendatasequence.Thischapter describestheoperationand use oftheCRC module. NOTE: The CRC module on theCC430F613x, CC430F612x, and CC430F513x devicesdoes not supportthebit-wisereversefeaturedescribedinthismodule description.Registers CRCDIRB and CRCRESR, alongwiththeirrespectivefunctionality,arenotavailable. 367SLAU259E –May 2009–RevisedJanuary2013 CyclicRedundancy Check (CRC) Module SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Q D Q D Q D Q D Q D Q D Q D Q D Q D Q D Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Shift Clock ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CyclicRedundancy Check (CRC) Module Introduction www.ti.com

10.1 CyclicRedundancy Check (CRC) Module Introduction

The CRC module producesa signaturefora givensequence ofdatavalues.The signatureisgenerated througha feedbackpathfromdatabits0,4,11,and 15 (seeFigure10-1).The CRC signatureisbased on thepolynomialgivenintheCRC-CCITT-BR polynomial(seeEquation10). Figure10-1.LFSR ImplementationofCRC-CCITT Standard,Bit0 istheMSB oftheResult Identicalinputdatasequencesresultinidenticalsignatureswhen theCRC isinitializedwitha fixedseed value,whereas differentsequencesofinputdata,ingeneral,resultindifferentsignatures.

10.2 CRC Standard and BitOrder

The definitionsofthevariousCRC standardswere done intheeraofmain framecomputers,and by conventionbit0 was treatedas theMSB. Today,as inmost microcontrollerssuch as theMSP430, bit0 normallydenotestheLSB. InFigure10-1,thebitconventionshown isas givenintheoriginalstandards i.e.bit0 istheMSB. The factthatbit0 istreatedforsome as LSB, and forothersas MSB, continuesto cause confusion.The CRC16 module thereforeprovidesa bitreversedregisterpairforCRC16 operations tosupportbothconventions.

368 CyclicRedundancy Check (CRC) Module SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com CRC Checksum Generation

10.3 CRC Checksum Generation

The CRC generatorisfirstinitializedby writinga 16-bitword (seed)totheCRC Initializationand Result (CRCINIRES) register.Any datathatshouldbe includedintotheCRC calculationmust be writtentothe CRC Data Input(CRCDI orCRCDIRB) registerinthesame orderthattheoriginalCRC signaturewas calculated.The actualsignaturecan be readfromtheCRCINIRES registertocompare thecomputed checksum withtheexpectedchecksum. Signaturegenerationdescribesa method on how theresultofa signatureoperationcan be calculated. The calculatedsignature,whichiscomputed by an externaltool,iscalledchecksum inthefollowingtext. The checksum isstoredintheproduct'smemory and isused tocheckthecorrectnessoftheCRC operationresult.

10.3.1 CRC Implementation

To allowparallelprocessingoftheCRC, thelinearfeedbackshiftregister(LFSR) functionalityis implementedwithan XOR tree.Thisimplementationshows theidenticalbehavioras theLFSR approach after8 bitsofdataareshiftedinwhen theLSB is'shifted'infirst.The generationofa signaturecalculation has tobe startedby writinga seed totheCRCINIRES registertoinitializetheregister.Softwareor hardware(forexample,DMA) can transferdatatotheCRCDI orCRCDIRB register(forexample,from memory).The valueinCRCDI orCRCDIRB isthenincludedintothesignature,and theresultisavailable inthesignatureresultregistersatthenextreadaccess(CRCINIRES and CRCRESR). The signaturecan be generatedusingword orbytedata. Ifa word dataisprocessed,thelowerbyteattheeven addressisused atthefirstclock(MCLK) cycle. Duringthesecond clockcycle,thehigherbyteisprocessed.Thus,ittakestwo clockcyclestoprocess word data,whileittakesonlyone clock(MCLK) cycletoprocessbytedata. Data byteswrittentoCRCDIRB inword mode orthedatabyteinbytemode arebit-wisereversedbefore theCRC engineadds them tothesignature.The bitsamong each bytearereversed.Data byteswrittento CRCDI inword mode orthedatabyteinbytemode arenotbitreversedbeforeuse by theCRC engine. IftheCheck Sum itself(withreversedbitorder)isincludedintotheCRC operation(asdatawrittento CRCDI orCRCDIRB), theresultintheCRCINIRES and CRCRESR registersmust be zero. 369SLAU259E –May 2009–RevisedJanuary2013 CyclicRedundancy Check (CRC) Module SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

CRC Data In Register CRCDI Data In 8-bit or 16-bit Byte MUX CRC Initialization and Result Register CRCINIRES 8 16 Write to CRCINIRES ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CRC Checksum Generation www.ti.com Figure10-2.ImplementationofCRC-CCITT Using theCRCDI and CRCINIRES Registers

10.3.2 Assembler Examples

10.3.2.1GeneralAssembler Example Thisexample demonstratestheoperationoftheon-chipCRC: ... PUSHR4 ;Saveregisters PUSHR5 MOV #StartAddress,R4;StartAddress<EndAddress MOV #EndAddress,R5 MOV &INIT,&CRCINIRES;INITtoCRCINIRES L1MOV @R4+,&CRCDI ;ItemtoDataInregister CMP R5,R4 ;Endaddressreached? JLO L1 ;No MOV &Check_Sum,&CRCDI;Yes,Includechecksum TST &CRCINIRES;Result=0? JNZ CRC_ERROR ;No,CRCRES<>0:error ... ;Yes,CRCRES=0: ;informationok. POP R5 ;Restoreregisters POP R4

370 CyclicRedundancy Check (CRC) Module SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com CRC Checksum Generation 10.3.2.2ReferenceData Sequence The detailsoftheimplementedCRC algorithmisshown by thefollowingdatasequencesusingword or byteaccessesand theCRC data-inas wellas theCRC data-inreversebyteregisters: ... mov #0FFFFh,&CRCINIRES;initializeCRC mov.b#00031h,&CRCDI_L;"1" mov.b#00032h,&CRCDI_L;"2" mov.b#00033h,&CRCDI_L;"3" mov.b#00034h,&CRCDI_L;"4" mov.b#00035h,&CRCDI_L;"5" mov.b#00036h,&CRCDI_L;"6" mov.b#00037h,&CRCDI_L;"7" mov.b#00038h,&CRCDI_L;"8" mov.b#00039h,&CRCDI_L;"9" cmp #089F6h,&CRCINIRES;compareresult ;CRCRESRcontains06F91h jeq &Success ;noerror br &Error ;toerrorhandler mov #0FFFFh,&CRCINIRES;initializeCRC cmp #089F6h,&CRCINIRES;compareresult ;CRCRESRcontains06F91h jeq &Success ;noerror br &Error ;toerrorhandler ... mov #0FFFFh,&CRCINIRES;initializeCRC mov.b#00031h,&CRCDIRB_L;"1" mov.b#00032h,&CRCDIRB_L;"2" mov.b#00033h,&CRCDIRB_L;"3" mov.b#00034h,&CRCDIRB_L;"4" mov.b#00035h,&CRCDIRB_L;"5" mov.b#00036h,&CRCDIRB_L;"6" mov.b#00037h,&CRCDIRB_L;"7" mov.b#00038h,&CRCDIRB_L;"8" mov.b#00039h,&CRCDIRB_L;"9" cmp #029B1h,&CRCINIRES;compareresult ;CRCRESRcontains08D94h jeq &Success ;noerror br &Error ;toerrorhandler ... mov #0FFFFh,&CRCINIRES;initializeCRC mov.b#039h,&CRCDIRB_L;"9" cmp #029B1h,&CRCINIRES;compareresult ;CRCRESRcontains08D94h jeq &Success ;noerror br &Error ;toerrorhandler 371SLAU259E –May 2009–RevisedJanuary2013 CyclicRedundancy Check (CRC) Module SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CRC Registers www.ti.com

10.4 CRC Registers

The CRC module registersarelistedinTable10-1.The base addresscan be foundinthedevice-specific datasheet.The addressoffsetisgiveninTable10-1. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table10-1.CRC Registers Offset Acronym RegisterName Type Access Reset Section 0000h CRCDI CRC Data In Read/write Word 0000h Section10.4.1 0000h CRCDI_L Read/write Byte 00h 0001h CRCDI_H Read/write Byte 00h 0002h CRCDIRB CRC Data InReverseByte(1) Read/write Word 0000h Section10.4.2 0002h CRCDIRB_L Read/write Byte 00h 0003h CRCDIRB_H Read/write Byte 00h 0004h CRCINIRES CRC Initializationand Result Read/write Word FFFFh Section10.4.3 0004h CRCINIRES_L Read/write Byte FFh 0005h CRCINIRES_H Read/write Byte FFh 0006h CRCRESR CRC ResultReverse(1) Read only Word FFFFh Section10.4.4 0006h CRCRESR_L Read/write Byte FFh 0007h CRCRESR_H Read/write Byte FFh (1) Not availableon MSP430F543x and MSP430F541x non-A versions.

372 CyclicRedundancy Check (CRC) Module SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com CRC Registers

10.4.1 CRCDI Register

Figure10-3.CRCDI Register 15 14 13 12 11 10 9 8 CRCDI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CRCDI rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table10-2.CRCDI RegisterDescription Bit Field Type Reset Description 15-0 CRCDI RW 0h CRC datain.Data writtentotheCRCDI registerisincludedtothepresent signatureintheCRCINIRES registeraccordingtotheCRC-CCITT standard.

10.4.2 CRCDIRB Register

CRC Data InReverseRegister Figure10-4.CRCDIRB Register 15 14 13 12 11 10 9 8 CRCDIRB rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CRCDIRB rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table10-3.CRCDIRB RegisterDescription Bit Field Type Reset Description 15-0 CRCDIRB RW 0h CRC datainreversebyte.Data writtentotheCRCDIRB registerisincludedto thepresentsignatureintheCRCINIRES and CRCRESR registersaccordingto theCRC-CCITT standard.ReadingtheregisterreturnstheregisterCRCDI content. 373SLAU259E –May 2009–RevisedJanuary2013 CyclicRedundancy Check (CRC) Module SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. CRC Registers www.ti.com

10.4.3 CRCINIRES Register

CRC Initializationand ResultRegister Figure10-5.CRCINIRES Register 15 14 13 12 11 10 9 8 CRCINIRES rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 7 6 5 4 3 2 1 0 CRCINIRES rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 rw-1 Table10-4.CRCINIRES RegisterDescription Bit Field Type Reset Description 15-0 CRCINIRES RW FFFFh CRC initializationand result.ThisregisterholdsthecurrentCRC result (accordingtotheCRC-CCITT standard).Writingtothisregisterinitializesthe CRC calculationwiththevaluewrittentoit.The valuejustwrittencan be read fromCRCINIRES register.

10.4.4 CRCRESR Register

Figure10-6.CRCRESR Register 15 14 13 12 11 10 9 8 CRCRESR r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 7 6 5 4 3 2 1 0 CRCRESR r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1 Table10-5.CRCRESR RegisterDescription Bit Field Type Reset Description 15-0 CRCRESR R FFFFh CRC reverseresult.ThisregisterholdsthecurrentCRC result(accordingtothe CRC-CCITT standard).The orderofbitsisreversed(forexample, CRCINIRES[15] = CRCRESR[0]) compared totheorderofbitsinthe CRCINIRES register(seeexample code).

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter11 SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator The AES acceleratormodule performsAES128 encryptionor decryptionin hardware.This chapter describestheAES accelerator. 375SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES AcceleratorIntroduction www.ti.com

11.1 AES AcceleratorIntroduction

The AES acceleratormodule performsencryptionand decryptionof128-bitdatawith128-bitkeys accordingtotheadvanced encryptionstandard(AES) (FIPSPUB 197)inhardware. The AES acceleratorfeaturesare:

Encryptionand decryptionaccordingtoAES FIPS PUB 197 with128-bitkey
On-the-flykey expansionforencryptionand decryption
Off-linekey generationfordecryption
Byteand word accesstokey,input,and outputdata
AES readyinterruptflag The AES acceleratorblockdiagramisshown inFigure11-1. Figure11-1.AES AcceleratorBlock Diagram

376 AES Accelerator SLAU259E –May 2009–RevisedJanuary2013

in[3] in[2] in[1] in[0] in[7] in[6] in[5] in[4] in[11] in[10] in[9] in[8] in[15] in[14] in[13] in[12] s[3,0] s[2,0] s[1,0] s[0,0] s[3,1] s[2,1] s[1,1] s[0,1] s[3,2] s[2,2] s[1,2] s[0,2] s[3,3] s[2,3] s[1,3] s[0,3] Input bytes State array Output bytes out[3] out[2] out[1] out[0] out[7] out[6] out[5] out[4] out[11] out[10] out[9] out[8] out[15] out[14] out[13] out[12] ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AES AcceleratorOperation

11.2 AES AcceleratorOperation

The AES acceleratorisconfiguredwithusersoftware.The setupand operationisdiscussedinthe followingsections. Internally,theAES algorithm’s operationsareperformedon a two-dimensionalarrayofbytescalledthe State.ForAES-128,theStateconsistsoffourrows ofbytes,each containingfourbytes.The inputis assignedtotheStatearrayas illustratedinFigure11-2,within[0]beingthefirstdatabytewrittenintothe AES acceleratordatainputregister,AESADIN. The encryptordecryptoperationsarethenconductedon theStatearray,afterwhichitsfinalvaluescan be readfromtheoutputwithout[0]beingthefirstdatabyte readfromtheAES acceleratordataoutputregister,AESADOUT. Figure11-2.AES StateArrayInputand Output The module allowsword and byteaccesstoalldataregisters,AESAKEY, AESADIN, and AESADOUT. Word and byteaccessshouldnotbe mixed whilereadingfromorwritingintoone oftheregisters. However,itispossibletowriteone oftheregistersusingbyteaccessand anotherusingword access. NOTE: Access Restrictions WhiletheAES acceleratorisbusy (AESBUSY = 1),AESADOUT alwaysreadsas zero,the AESDOUTCNTx counter,theAESDOUTRD flag,and theAESDINWR flagarereset,any attempttochange AESOPx, AESDINWR, orAESKEYWR isignored,and writingto AESAKEY orAESADIN abortsthecurrentoperation,thecompletemodule isreset(except forAESRDYIE and AESOPx), and theAES errorflagAESERRFG isset. AESADIN and AESAKEY arewrite-onlyregistersand alwaysreadas zero. WritingdataintoAESADIN influencesthecontentofthecorrespondingoutputdata;for example,writingin[0]altersout[0],writingin[1]altersout[1],etc.,butinterleafedoperationis possible;forexample,firstreadingout[0],thenwritingin[0],and continuingwithreading out[1],writingin[1],etc. NOTE: When usinga code debugger,theAES module does notstopitsoperationwhen program code ishaltedorsinglestepped. 377SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

(AESADIN) Ciphertext (AESADOUT) Cipher Key (AESAKEY) Encryption Process Cipher Initial RoundInitial Key Round 1Round Key 1 Round 2Round Key 2 Round 9Round Key 9 Final RoundRound Key 10 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES AcceleratorOperation www.ti.com

11.2.1 Encryption

Figure11-3shows theencryptionprocesswiththecipherbeinga seriesoftransformationsthatconverts theplaintextwrittenintotheAESADIN registertoa ciphertextthatcan be readfromtheAESADOUT registerusingthecipherkey providedviatheAESAKEY register. Figure11-3.AES-128 EncryptionProcess The stepstoperformencryptionare: 1. SetAESOPx = 00 toselectencryption.ChangingtheAESOPx bitsclearstheAESKEYWR flag,and a new key must be loadedinthenextstep. 2. Load the128-bitkey intoAESAKEY orsettheAESKEYWR flagby software,ifthekey froma previous operationshouldbe used.When all16 bytesarewritten,theAESKEYWR flagindicatescompletion. Ifa key was loadedpreviouslywithoutchangingAESOPx, theAESKEYWR flagisclearedwiththefirst writeaccesstoAESAKEY. Loadingthekey mistbe completedbeforethenextstepisperformed. 3. Load 128-bitdataintoAESADIN, orsettheAESDINWR flagby softwareiftheoutputdatafroma previousoperationshouldbe encrypted.When all16 bytesarewritten,theAESDINWR flagindicates completion.The module startsencryptingthepresenteddatawhen AESDINWR = 1. 4. WhiletheAES module isperformingencryption,theAESBUSY bitis1.The encryptiontakes 167 MCLK clockcycles.Afteritscompletion,theAESRDYIFG isset,and theresultcan be readfrom AESADOUT. When all16 bytesareread,theAESDOUTRD flagindicatescompletion. The AESRDYIFG flagisclearedwhen readingAESADOUT orwritingtoAESAKEY orAESADIN. 5. Ifadditionaldatashouldbe encryptedwiththesame key loadedinstep2,new datacan be writteninto AESADIN aftertheresultsoftheoperationon thepreviousdatawere readfromAESADOUT. When an additional16 databytesarewritten,themodule automaticallystartstheencryptionusingthekey loadedinstep2. When usingtheoutputfeedback(OFB) cipherblockchainingmode, settingtheAESDINWR flagis sufficienttotriggerthenextencryption,and themodule startstheencryptionautomaticallyusingthe outputdatafromthepreviousencryptionas inputdata.

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Decryption Process – Inverse CipherDecrypt Key Generation Cipher Key (AESAKEY) Initial Key Round Key 1 Round Key 2 Round Key 9 Round Key 10 Inverse Cipher Plaintext (AESADOUT) Ciphertext (AESADIN) Inverse Initial RoundInitial Key Inverse Round 1Round Key 1 Inverse Round 2Round Key 2 Inverse Round 9Round Key 9 Inverse Final RoundRound Key 10 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AES AcceleratorOperation

11.2.2 Decryption

Figure11-4shows thedecryptionprocesswiththeinversecipherbeinga seriesoftransformationsthat converttheciphertextwrittenintotheAESADIN registertoa plaintextthatcan be readfromthe AESADOUT registerusingthecipherkey providedviatheAESAKEY register. Figure11-4.AES-128 DecryptionProcess using AESOPx = 01 The stepstoperformdecryptionare: 1. SetAESOPx = 01 toselectdecryptionusingthesame key used forencryption.SetAESOPx = 11 if thefirst-roundkey requiredfordecryption(roundkey 10)isalreadygeneratedand isloadedinstep2. ChangingtheAESOPx bitsclearstheAESKEYWR flag,and a new key must be loadedinstep2. 2. Load the128-bitkey intoAESAKEY, orsettheAESKEYWR flagby software,ifthekey froma previousoperationshouldbe used.When all16 bytesarewritten,theAESKEYWR flagindicates completion. Ifa key was loadedpreviouslywithoutchangingAESOPx, theAESKEYWR flagisclearedwiththefirst writeaccesstoAESAKEY. Loadingthekey must be completedbeforethenextstepisperformed. 3. Load 128-bitdataintoAESADIN orsettheAESDINWR flagby softwareiftheoutputdatafroma previousoperationshouldbe decrypted.When all16 bytesarewritten,theAESDINWR flagindicates completion.The module startsdecryptingthepresenteddataas soon as AESDINWR = 1. 4. WhiletheAES module isperformingdecryption,theAESBUSY bitis1.The decryptiontakes 214 MCLK clockcycleswithAESOPx = 01 and 167 MCLK clockcycleswithAESOPx = 11.Afterits completion,theAESRDYIFG isset,and theresultcan be readfromAESADOUT. When all16 bytes arereadtheAESDOUTRD flagindicatescompletion. The AESRDYIFG flagisclearedwhen readingAESADOUT orwritingtoAESAKEY orAESADIN. 5. Ifadditionaldatashouldbe decryptedwiththesame key loadedinstep2,new datacan be writteninto AESADIN aftertheresultsoftheoperationon thepreviousdatawere readfromAESADOUT. When additional16 databytesarewritten,themodule automaticallystartsthedecryptionusingthekey loadedinstep2. 379SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Decryption Process – Inverse Cipher (AESOPx = 11) Decrypt Key Generation (AESOPx = 10) Cipher Key (AESAKEY) Initial Key Round Key 1 Round Key 2 Round Key 9 Round Key 10 Inverse Cipher Plaintext (AESADOUT) Ciphertext (AESADIN) Inverse Initial RoundInitial Key Inverse Round 1Round Key 1 Inverse Round 2Round Key 2 Inverse Round 9Round Key 9 Inverse Final RoundRound Key 10 Pregenerated Key (AESAKEY) Pregenerated Key (AESADOUT) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES AcceleratorOperation www.ti.com

11.2.3 DecryptionKey Generation

Figure11-5shows thedecryptionprocesswitha pregenerateddecryptionkey.Inthiscase,thedecryption key iscalculatedfirstwithAESOPx = 10,thentheprecalculatedkey can be used togetherwiththe decryptionoperationAESOPx = 11. Figure11-5.AES-128 DecryptionProcess using AESOPx = 10 and 11 To generatethedecryptionkey independentfromtheactualdecryption,thefollowingstepsarerequired: 1. SetAESOPx = 10 toselectdecryptionkey generation.ChangingtheAESOPx bitsclearsthe AESKEYWR flag,and a new key must be loadedinstep2. 2. Load the128-bitkey intoAESAKEY, orsettheAESKEYWR flagby softwareifthekey froma previous operationshouldbe used.When all16 bytesarewritten,theAESKEYWR flagindicatescompletion. The generationofthefirstroundkey requiredfordecryptionisstartedimmediately. 3. WhiletheAES module isperformingthekey generation,theAESBUSY bitis1.Ittakes52 CPU clock cyclestocompletethekey generation.Afteritscompletion,theAESRDYIFG isset,and theresultcan be readfromAESADOUT. When all16 bytesareread,theAESDOUTRD flagindicatescompletion. The AESRDYIFG flagisclearedwhen readingAESADOUT orwritingtoAESAKEY orAESADIN. 4. Ifdatashouldbe decryptedwiththegeneratedkey,AESOPx must be setto11.Then thegenerated key must be loadedor,ifitwas justgeneratedwithAESOPx = 10,itissufficienttosetthe AESKEYWR flagby softwaretoindicatethatthekey isalreadyvalid.Afterward,thestepsdescribedin Section11.2.2toloadthedata,etc.,must be followed.

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11.2.4 Using theAES AcceleratorWith Low-Power Modes

The AES acceleratormodule providesautomaticclockactivationforMCLK foruse withlow-powermodes. When theAES acceleratorisbusy,itautomaticallyactivatesMCLK, regardlessofthecontrol-bitsettings fortheclocksource.The clockremainsactiveuntiltheAES acceleratorcompletesitsoperation.

11.2.5 AES AcceleratorInterrupts

The AESRDYIFG interruptflagissetwhen theAES module completestheselectedoperationon the provideddata.An interruptrequestisgeneratedifAESRDYIE and GIE arealsoset.AESRDYIFG is automaticallyresetiftheAES interruptisserviced,ifAESADOUT isread,orifAESADIN orAESAKEY are written.AESRDYIFG isresetaftera PUC orwithAESSWRST = 1.AESRDYIE isresetaftera PUC butis notresetby AESSWRST = 1.

11.2.6 ImplementingBlock CipherModes

Allblockciphermodes can be implementedusingtheAES acceleratortogetherwithsoftware.A separate applicationreportdescribestheblockciphermodes togetherwiththeirimplementationinsoftware. 381SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES_ACCEL Registers www.ti.com

11.3 AES_ACCEL Registers

The AES AcceleratorregistersarelistedinTable11-1. Table11-1.AES_ACCEL Registers Offset Acronym RegisterName Type Access Reset Section 000h AESACTL0 AES acceleratorcontrolregister0 Read/write Word 00h Section11.3.1 002h AESACTL1 AES acceleratorcontrolregister1 Read/write Word 00h Section11.3.2 004h AESASTAT AES acceleratorstatusregister Read only Word 00h Section11.3.3 006h AESAKEY AES acceleratorkey register Read/write Word 00h Section11.3.4 008h AESADIN AES acceleratordatainregister Read/write Word 00h Section11.3.5 00Ah AESADOUT AES acceleratordataoutregister Read/write Word 00h Section11.3.6 00Ch AESAXDIN AES acceleratorXORed datain Read/write Word 00h Section11.3.7 register 00Eh AESAXIN AES acceleratorXORed datain Read/write Word 00h Section11.3.8 register(notrigger)

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11.3.1 AESACTL0 Register

AES acceleratorcontrolregister0 AESACTL0 isshown inFigure11-6and describedinTable11-2. Figure11-6.AESACTL0 Register 15 14 13 12 11 10 9 8 AESCMEN Reserved AESRDYIE AESERRFG Reserved AESRDYIFG rw-0 r0 r0 rw-0 rw-0 r0 r0 rw-0 7 6 5 4 3 2 1 0 AESSWRST AESCMx Reserved AESKLx AESOPx rw-0 r0 r0 r0 rw-0 rw-0 rw-0 rw-0 Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. Table11-2.AESACTL0 RegisterDescription Bit Field Type Reset Description

15 AESCMEN RW 0h AESCMEN enablesthesupportoftheciphermodesECB, CBC, OFB and CFB

togetherwiththeDMA. Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. 0 = No DMA triggersaregenerated 1 = DMA ciphermodesupportoperationisenabledand thecorrespondingDMA triggersaregenerated. 14-13 Reserved R 0h Reserved 12 AESRDYIE RW 0h AES readyinterruptenable.AESRDYIE isnotresetby AESSWRST = 1. 0 = Interruptdisabled 1 = Interruptenabled 11 AESERRFG RW 0h AES errorflag.AESAKEY orAESADIN were writtenwhilean AES operationwas inprogress.The bitmust be clearedby software. 0 = No error 1 = Erroroccurred 10-9 Reserved R 0h Reserved 8 AESRDYIFG RW 0h AES readyinterruptflag.Setwhen theselectedAES operationwas completed and theresultcan be readfromAESADOUT. Automaticallyclearedwhen AESADOUT isreadorAESAKEY orAESADIN iswritten. 0 = No interruptpending 1 = Interruptpending 7 AESSWRST RW 0h AES softwarereset.ImmediatelyresetsthecompleteAES acceleratormodule even when busy exceptfortheAESRDYIE, theAESKLx and theAESOPx bits.It alsoclearsthe(internal)statememory. The AESSWRST bitisautomaticallyresetand isalwaysreadas zero. 0 = No reset 1 = ResetAES acceleratormodule 6-5 AESCMx R 0h AES ciphermode select.These bitsareignoredforAESCMEN=0. Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. 00 = ECB 01 = CBC 10 = OFB 11 = CFB

4 Reserved R 0h Reserved

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES_ACCEL Registers www.ti.com Table11-2.AESACTL0 RegisterDescription(continued) Bit Field Type Reset Description 3-2 AESKLx RW 0h AES key length.These bitsdefinewhichofthe3 AES standardsisperformed. The AESKLx bitsarenotresetby AESSWRST = 1. Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. 00 = AES128. The keysizeis128 bit. 01 = AES192. The keysizeis192 bit. 10 = AES256. The keysizeis256 bit. 11 = Reserved 1-0 AESOPx RW 0h AES operation.The AESOPx bitsarenotresetby AESSWRST = 1. Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. 00 = Encryption 01 = Decryption.The providedkey isthesame key used forencryption. 10 = Generatefirstroundkey requiredfordecryption. 11 = Decryption.The providedkey isthefirstroundkey requiredfordecryption.

11.3.2 AESACTL1 Register

AES AcceleratorControlRegister1 AESACTL1 isshown inFigure11-7and describedinTable11-3. Figure11-7.AESACTL1 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 AESBLKCNTx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0. Table11-3.AESACTL1 RegisterDescription Bit Field Type Reset Description 15-8 Reserved R 0 Reserved.Alwaysreads0. 7-0 AESBLKCNTx RW 0 CipherBlockCounter.Number ofblockstobe encryptedordecryptedwithblock ciphermodes enabled(AESCMEN=1). IgnoredifAESCMEN=0. The blockcounterdecrementswitheach performedencryptionordecryption. Writesareignoredwhen AESCMEN = 1 and AESBLKCNTx > 0.

384 AES Accelerator SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AES_ACCEL Registers

11.3.3 AESASTAT Register

AES AcceleratorStatusRegister AESASTAT isshown inFigure11-8and describedinTable11-4. Figure11-8.AESASTAT Register 15 14 13 12 11 10 9 8 AESDOUTCNTx AESDINCNTx r-0 r-0 r-0 r-0 r-0 r-0 r-0 r-0 7 6 5 4 3 2 1 0 AESKEYCNTx AESDOUTRD AESDINWR AEKEYWR AESBUSY r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 r-0 Table11-4.AESASTAT RegisterDescription Bit Field Type Reset Description 15-12 AESDOUTCNTx R 0h BytesreadviaAESADOUT. Resetwhen AESDOUTRD isreset. IfAESDOUTCNTx = 0 and AESDOUTRD = 0,no byteswere read. IfAESDOUTCNTx = 0 and AESDOUTRD = 1,allbyteswere read. 11-8 AESDINCNTx R 0h ByteswrittenviaAESADIN, AESAXDIN orAESAXIN. Resetwhen AESDINWR is reset. IfAESDINCNTx = 0 and AESDINWR = 0,no byteswere written. IfAESDINCNTx = 0 and AESDINWR = 1,allbyteswere written. 7-4 AESKEYCNTx R 0h ByteswrittenviaAESAKEY forAESKLx=00, words writtenviaAESAKEY if AESKLx=01,10,11.Resetwhen AESKEYWR isreset. IfAESKEYCNTx = 0 and AESKEYWR = 0,no byteswere written. IfAESKEYCNTx = 0 and AESKEYWR = 1,allbyteswere written. 3 AESDOUTRD R 0h All16 bytesreadfromAESADOUT. AESDOUTRD isresetby PUC, AESSWRST, an errorcondition,changing AESOPx, changingAESKLx, when theAES acceleratorisbusy,and when the outputdataisreadagain. 0 = Not allbytesread 1 = Allbytesread 2 AESDINWR RW 0h All16 byteswrittentoAESADIN, AESAXDIN orAESAXIN. Thisbitcan be modifiedby softwareonlyifAESCMEN=0. Changingitsstateby softwarealso resetstheAESDINCNTx bits. AESDINWR isresetby PUC, AESSWRST, an errorcondition,changing AESOPx, changingAESKLx, thestartto(over)writethedata,and when theAES acceleratorisbusy.Because itisresetwhen AESOPx orAESKLx ischanged it can be setby softwareagaintoindicatethatthecurrentdataisstillvalid. 0 = Not allbyteswritten 1 = Allbyteswritten 1 AESKEYWR RW 0h All16 byteswrittentoAESAKEY. Thisbitcan be modifiedby softwarebutit must notbe resetby software(1→0)ifAESCMEN=1. Changingitsstateby softwarealsoresetstheAESKEYCNTx bits. AESKEYWR isresetby PUC, AESSWRST, an errorcondition,changing AESOPx, changingAESKLx, and thestartto(over)writea new key.Because itis resetwhen AESOPx ischanged itcan be setby softwareagaintoindicatethat theloadedkey isstillvalid. 0 = Not allbyteswritten 1 = Allbyteswritten

0 AESBUSY R 0h AES acceleratormodule busy;encryption,decryption,orkey generationin

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES_ACCEL Registers www.ti.com

11.3.4 AESAKEY Register

AES AcceleratorKey Register AESAKEY isshown inFigure11-9and describedinTable11-5. Figure11-9.AESAKEY Register 15 14 13 12 11 10 9 8 AESKEY1x (KeyByten+1) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 1 0 AESKEY0x (KeyByten) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 Table11-5.AESAKEY RegisterDescription Bit Field Type Reset Description 15-8 AESKEY1x W 0 AES key byten+1 when AESAKEY iswrittenas word. Do notuse thesebitsforbyteaccess. Do notmix word and byteaccess. Alwaysreadsas zero. The key isresetby PUC orby AESSWRST = 1. 7-0 AESKEY0x W 0 AES key byten when AESAKEY iswrittenas word. AES nextkey bytewhen AESAKEY_L iswrittenas byte. Do notmix word and byteaccess. Alwaysreadsas zero. The key isresetby PUC orby AESSWRST = 1.

386 AES Accelerator SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com AES_ACCEL Registers

11.3.5 AESADIN Register

AES AcceleratorData InRegister AESADIN isshown inFigure11-10and describedinTable11-6. Figure11-10.AESADIN Register 15 14 13 12 11 10 9 8 AESDIN1x (DINByten+1) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 1 0 AESDIN0x (DINByten) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 Table11-6.AESADIN RegisterDescription Bit Field Type Reset Description 15-8 AESDIN1x W 0 AES datainbyten+1 when AESADIN iswrittenas word. Do notuse thesebitsforbyteaccess. Do notmix word and byteaccess. Alwaysreadsas zero. 7-0 AESDIN0x W 0 AES datainbyten when AESADIN iswrittenas word. AES nextdatainbytewhen AESADIN_L iswrittenas byte. Do notmix word and byteaccess. Alwaysreadsas zero.

11.3.6 AESADOUT Register

AES AcceleratorData Out Register AESADOUT isshown inFigure11-11and describedinTable11-7. Figure11-11.AESADOUT Register 15 14 13 12 11 10 9 8 AESDOUT1x (DOUT Byten+1) 7 6 5 4 3 2 1 0 AESDOUT0x (DOUT Byten) Table11-7.AESADOUT RegisterDescription Bit Field Type Reset Description 15-8 AESDOUT1x R 0 AES dataoutbyten+1 when AESADOUT isreadas word. Do notuse thesebitsforbyteaccess. Do notmix word and byteaccess. 7-0 AESDOUT0x R 0 AES dataoutbyten when AESADOUT isreadas word. AES nextdataoutbytewhen AESADOUT_L isreadas byte. Do notmix word and byteaccess. 387SLAU259E –May 2009–RevisedJanuary2013 AES Accelerator SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. AES_ACCEL Registers www.ti.com

11.3.7 AESAXDIN Register

AES acceleratorXORed datainregister AESAXDIN isshown inFigure11-12and describedinTable11-8. Figure11-12.AESAXDIN Register 15 14 13 12 11 10 9 8 AESXDIN1x (XDIN Byten+1) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 1 0 AESXDIN0x (XDIN Byten) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 Table11-8.AESAXDIN RegisterDescription Bit Field Type Reset Description 15-8 AESXDIN1x W 0 AES datainbyten+1 when AESAXDIN iswrittenas word. Do notuse thesebitsforbyteaccess. Do notmix word and byteaccess. Alwaysreadsas zero. 7-0 AESXDIN0x W 0 AES datainbyten when AESAXDIN iswrittenas word. AES nextdatainbytewhen AESAXDIN_L iswrittenas byte. Do notmix word and byteaccess. Alwaysreadsas zero.

11.3.8 AESAXIN Register

AES acceleratorXORed datainregister(notrigger) AESAXIN isshown inFigure11-13and describedinTable11-9. Figure11-13.AESAXIN Register 15 14 13 12 11 10 9 8 AESXIN1x (DINByten+1) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 7 6 5 4 3 2 1 0 AESXIN0x (DINByten) w-0 w-0 w-0 w-0 w-0 w-0 w-0 w-0 Table11-9.AESAXIN RegisterDescription Bit Field Type Reset Description 15-8 AESXIN1x W 0 AES datainbyten+1 when AESAXIN iswrittenas word. Do notuse thesebitsforbyteaccess. Do notmix word and byteaccess. Alwaysreadsas zero. 7-0 AESXIN0x W 0 AES datainbyten when AESAXIN iswrittenas word. AES nextdatainbytewhen AESAXIN_L iswrittenas byte. Do notmix word and byteaccess. Alwaysreadsas zero.

388 AES Accelerator SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter12 SLAU259E –May 2009–RevisedJanuary2013 Watchdog Timer (WDT_A) The watchdog timerisa 32-bittimerthatcan be used as a watchdog oras an intervaltimer.Thischapter describesthewatchdogtimer.The enhanced watchdogtimer,WDT_A, isimplementedinalldevices. 389SLAU259E –May 2009–RevisedJanuary2013 Watchdog Timer(WDT_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. WDT_A Introduction www.ti.com

12.1 WDT_A Introduction

The primaryfunctionofthewatchdogtimer(WDT_A) module istoperforma controlledsystemrestart aftera softwareproblemoccurs.Iftheselectedtimeintervalexpires,a systemresetisgenerated.Ifthe watchdogfunctionisnotneeded inan application,themodule can be configuredas an intervaltimerand can generateinterruptsatselectedtimeintervals. Featuresofthewatchdogtimermodule include:

Eightsoftware-selectabletimeintervals
Watchdog mode
Intervalmode
Password-protectedaccesstoWatchdog TimerControl(WDTCTL) register
Selectableclocksource
Can be stoppedtoconservepower
Clockfail-safefeature The watchdogtimerblockdiagramisshown inFigure12-1. NOTE: Watchdog timerpowers up active. Aftera PUC, theWDT_A module isautomaticallyconfiguredinthewatchdogmode withan initial~32-ms resetintervalusingtheSMCLK. The usermust setuporhalttheWDT_A prior totheexpirationoftheinitialresetinterval.

390 Watchdog Timer(WDT_A) SLAU259E –May 2009–RevisedJanuary2013

Write□Enable Low□Byte R / W MDB LSB MSB WDTCTL (Asyn) Int. Flag Pulse Generator VLOCLK Clock Request Logic X_CLK□request SMCLK□request ACLK□request VLOCLK□request Q13 Q15 Q19 Q23 Q27 Q31 X_CLK 16-bit Counter CLK 32Bit□WDT□extension ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com WDT_A Introduction Figure12-1.Watchdog Timer Block Diagram 391SLAU259E –May 2009–RevisedJanuary2013 Watchdog Timer(WDT_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. WDT_A Operation www.ti.com

12.2 WDT_A Operation

The watchdogtimermodule can be configuredas eithera watchdogorintervaltimerwiththeWDTCTL register.WDTCTL isa 16-bitpassword-protectedread/writeregister.Any readorwriteaccessmust use word instructionsand writeaccessesmust includethewritepassword05Ah intheupperbyte.Any writeto WDTCTL withany valueotherthan05Ah intheupperbyteisa passwordviolationand triggersa PUC systemreset,regardlessoftimermode. Any readofWDTCTL reads069h intheupperbyte.Bytereads on WDTCTL highorlowpartresultinthevalueofthelowbyte.Writingbytewidetoupperorlowerparts ofWDTCTL resultsina PUC.

12.2.1 Watchdog Timer Counter (WDTCNT)

The WDTCNT isa 32-bitup counterthatisnotdirectlyaccessibleby software.The WDTCNT iscontrolled and itstimeintervalsareselectedthroughtheWatchdog TimerControl(WDTCTL) register.The WDTCNT can be sourcedfromSMCLK, ACLK, VLOCLK, orX_CLK on some devices.The clocksourceisselected withtheWDTSSEL bits.The timerintervalisselectedwiththeWDTIS bits.

12.2.2 Watchdog Mode

Aftera PUC condition,theWDT module isconfiguredinthewatchdogmode withan initial~32-ms reset intervalusingtheSMCLK. The usermust setup,halt,orclearthewatchdogtimerpriortotheexpirationof theinitialresetintervaloranotherPUC isgenerated.When thewatchdogtimerisconfiguredtooperatein watchdogmode, eitherwritingtoWDTCTL withan incorrectpassword,orexpirationoftheselectedtime intervaltriggersa PUC. A PUC resetsthewatchdogtimertoitsdefaultcondition.

12.2.3 IntervalTimer Mode

SettingtheWDTTMSEL bitto1 selectstheintervaltimermode. Thismode can be used toprovide periodicinterrupts.Inintervaltimermode, theWDTIFG flagissetattheexpirationoftheselectedtime interval.A PUC isnotgeneratedinintervaltimermode atexpirationoftheselectedtimerinterval,and the WDTIFG enablebitWDTIE remainsunchanged. When theWDTIE bitand theGIE bitareset,theWDTIFG flagrequestsan interrupt.The WDTIFG interruptflagisautomaticallyresetwhen itsinterruptrequestisserviced,oritmay be resetby software. The interruptvectoraddressinintervaltimermode isdifferentfromthatinwatchdogmode. NOTE: Modifyingthewatchdog timer The watchdogtimerintervalshouldbe changed togetherwithWDTCNTCL = 1 ina single instructiontoavoidan unexpectedimmediatePUC orinterrupt.The watchdogtimershould be haltedbeforechangingtheclocksourcetoavoida possibleincorrectinterval.

12.2.4 Watchdog Timer Interrupts

The watchdogtimeruses two bitsintheSFRs forinterruptcontrol:

WDT interruptflag,WDTIFG, locatedinSFRIFG1.0
WDT interruptenable,WDTIE, locatedinSFRIE1.0 When usingthewatchdogtimerinthewatchdogmode, theWDTIFG flagsourcesa resetvector interrupt.TheWDTIFG willselfclearupon a watchdogtimeoutevent.The SYSRSTIV can be readto determineiftheresetwas caused by a watchdogtimeoutevent. When usingthewatchdogtimerinintervaltimermode, theWDTIFG flagissetaftertheselectedtime intervaland requestsa watchdogtimerintervaltimerinterruptiftheWDTIE and theGIE bitsareset.The intervaltimerinterruptvectorisdifferentfromtheresetvectorused inwatchdogmode. Inintervaltimer mode, theWDTIFG flagisresetautomaticallywhen theinterruptisserviced,orcan be resetwith software.

392 Watchdog Timer(WDT_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com WDT_A Operation

12.2.5 Clock Fail-SafeFeature

The WDT_A providesa fail-safeclockingfeature,ensuringtheclocktotheWDT_A cannotbe disabled whileinwatchdogmode. Thismeans thatthelow-powermodes may be affectedby thechoiceforthe WDT_A clock. IfSMCLK orACLK failsas theWDT_A clocksource,VLOCLK isautomaticallyselectedas theWDT_A clocksource. When theWDT_A module isused inintervaltimermode, thereisno fail-safefeaturewithinWDT_A for theclocksource.

12.2.6 OperationinLow-Power Modes

The deviceshave severallow-powermodes. Differentclocksignalsareavailableindifferentlow-power modes. The requirementsoftheapplicationand thetypeofclockingthatisused determinehow the WDT_A shouldbe configured.Forexample,theWDT_A shouldnotbe configuredinwatchdogmode with a clocksourcethatisoriginallysourcedfromDCO, XT1 inhigh-frequencymode, orXT2 viaSMCLK or ACLK, iftheuserwantstouse low-powermode 3.Inthiscase,SMCLK orACLK wouldremainenabled, increasingthecurrentconsumptionofLPM3. When thewatchdogtimerisnotrequired,theWDTHOLD bit can be used toholdtheWDTCNT, reducingpower consumption.

12.2.7 SoftwareExamples

Any writeoperationtoWDTCTL must be a word operationwith05Ah (WDTPW) intheupperbyte: ;Periodicallyclearanactivewatchdog MOV#WDTPW+WDTIS2+WDTIS1+WDTCNTCL,&WDTCTL ;Changewatchdogtimerinterval MOV#WDTPW+WDTCNTCL+SSEL,&WDTCTL ;Stopthewatchdog MOV#WDTPW+WDTHOLD,&WDTCTL ;ChangeWDTtointervaltimermode,clock/8192interval MOV#WDTPW+WDTCNTCL+WDTTMSEL+WDTIS2+WDTIS0,&WDTCTL 393SLAU259E –May 2009–RevisedJanuary2013 Watchdog Timer(WDT_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. WDT_A Registers www.ti.com

12.3 WDT_A Registers

The watchdogtimermodule registersarelistedinTable12-1.The base addressforthewatchdogtimer module registersand specialfunctionregisters(SFRs)can be foundindevice-specificdatasheets.The addressoffsetisgiveninTable12-1. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table12-1.WDT_A Registers Offset Acronym RegisterName Type Access Reset Section 0Ch WDTCTL Watchdog TimerControl Read/write Word 6904h Section12.3.1 0Ch WDTCTL_L Read/write Byte 04h 0Dh WDTCTL_H Read/write Byte 69h

394 Watchdog Timer(WDT_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com WDT_A Registers

12.3.1 WDTCTL Register

Watchdog TimerControlRegister Figure12-2.WDTCTL Register 15 14 13 12 11 10 9 8 WDTPW 7 6 5 4 3 2 1 0 WDTHOLD WDTSSEL WDTTMSEL WDTCNTCL WDTIS rw-0 rw-0 rw-0 rw-0 r0(w) rw-1 rw-0 rw-0 Table12-2.WDTCTL RegisterDescription Bit Field Type Reset Description 15-8 WDTPW RW 69h Watchdog timerpassword.Alwaysreadas 069h.Must be writtenas 5Ah;ifany othervalueiswritten,a PUC isgenerated. 7 WDTHOLD RW 0h Watchdog timerhold.Thisbitstopsthewatchdogtimer.SettingWDTHOLD = 1 when theWDT isnotinuse conservespower. 0b = Watchdog timerisnotstopped. 1b = Watchdog timerisstopped. 6-5 WDTSSEL RW 0h Watchdog timerclocksourceselect 00b = SMCLK 01b = ACLK 10b = VLOCLK 11b = X_CLK; VLOCLK indevicesthatdo notsupportX_CLK

4 WDTTMSEL RW 0h Watchdog timermode select

0b = Watchdog mode 1b = Intervaltimermode 3 WDTCNTCL RW 0h Watchdog timercounterclear.SettingWDTCNTCL = 1 clearsthecountvalueto 0000h.WDTCNTCL isautomaticallyreset. 0b = No action 1b = WDTCNT = 0000h 2-0 WDTIS RW 4h Watchdog timerintervalselect.These bitsselectthewatchdogtimerintervalto settheWDTIFG flagand/orgeneratea PUC. 000b = Watchdog clocksource/(2^31)(18h:12m:16sat32.768kHz) 001b = Watchdog clocksource/(2^27)(01h:08m:16sat32.768kHz) 010b = Watchdog clocksource/(2^23)(00h:04m:16sat32.768kHz) 011b = Watchdog clocksource/(2^19)(00h:00m:16sat32.768kHz) 100b = Watchdog clocksource/(2^15)(1s at32.768kHz) 101b = Watchdog clocksource/(2^13)(250ms at32.768kHz) 110b = Watchdog clocksource/(2^9)(15.625ms at32.768kHz) 111b = Watchdog clocksource/(2^6)(1.95ms at32.768kHz) 395SLAU259E –May 2009–RevisedJanuary2013 Watchdog Timer(WDT_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter13 SLAU259E –May 2009–RevisedJanuary2013 Timer_A Timer_A isa 16-bittimer/counterwithmultiplecapture/compareregisters.There can be multipleTimer_A modules on a givendevice(seethedevice-specificdatasheet).Thischapterdescribestheoperationand use oftheTimer_A module.

396 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Introduction

13.1 Timer_A Introduction

Timer_A isa 16-bittimer/counterwithup toseven capture/compareregisters.Timer_A can support multiplecapture/compares,PWM outputs,and intervaltiming.Timer_A alsohas extensiveinterrupt capabilities.Interruptsmay be generatedfromthecounteron overflowconditionsand fromeach ofthe capture/compareregisters. Timer_A featuresinclude:

Asynchronous16-bittimer/counterwithfouroperatingmodes
Selectableand configurableclocksource
Up toseven configurablecapture/compareregisters
Configurableoutputswithpulsewidthmodulation(PWM) capability
Asynchronousinputand outputlatching
InterruptvectorregisterforfastdecodingofallTimer_A interrupts The blockdiagramofTimer_A isshown inFigure13-1. NOTE: Use oftheword count Count isused throughoutthischapter.Itmeans thecountermust be intheprocessof countingfortheactiontotakeplace.Ifa particularvalueisdirectlywrittentothecounter,an associatedactiondoes nottakeplace. NOTE: Nomenclature Theremay be multipleinstantiationsofTimer_A on a givendevice.The prefixTAx isused, where x isa greaterthanequaltozeroindicatingtheTimer_A instantiation.Fordeviceswith one instantiation,x = 0.The suffixn,where n = 0 to6,representsthespecific capture/compareregistersassociatedwiththeTimer_A instantiation. 397SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

/1/2/4/8 Count Mode T16-bit imer TAxR RC Set TAxCTL TAIFG 15 0 TASSEL MCID Clear Timer Clock EQU0 Timer Clock Timer Clock TAxCCR6 SCCI Y A EN CCR1 POR TACLR CCR0 Timer Block Set TAxCCR6 CCIFG CAP CCR2 CCR3 ACLK SMCLK TAxCLK INCLK IDEX Divider /1.../8 CCR4 CCR5 2 2 3 2 2 2 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Introduction www.ti.com Figure13-1.Timer_A Block Diagram

398 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation

13.2 Timer_A Operation

The Timer_A module isconfiguredwithusersoftware.The setupand operationofTimer_A arediscussed inthefollowingsections. 13.2.1 16-BitTimer Counter The 16-bittimer/counterregister,TAxR, incrementsordecrements(dependingon mode ofoperation)with each risingedge oftheclocksignal.TAxR can be readorwrittenwithsoftware.Additionally,thetimercan generatean interruptwhen itoverflows. TAxR may be clearedby settingtheTACLR bit.SettingTACLR alsoclearstheclockdividerand count directionforup/down mode. NOTE: ModifyingTimer_A registers Itisrecommended tostopthetimerbeforemodifyingitsoperation(withexceptionofthe interruptenable,interruptflag,and TACLR) toavoiderrantoperatingconditions. When thetimerclockisasynchronoustotheCPU clock,any readfromTAxR shouldoccur whilethetimerisnotoperatingortheresultsmay be unpredictable.Alternatively,thetimer may be readmultipletimeswhileoperating,and a majorityvotetakeninsoftwareto determinethecorrectreading.Any writetoTAxR takeseffectimmediately. 13.2.1.1Clock Source Selectand Divider The timerclockcan be sourcedfromACLK, SMCLK, orexternallyviaTAxCLK orINCLK. The clock sourceisselectedwiththeTASSEL bits.The selectedclocksourcemay be passed directlytothetimeror dividedby 2,4,or8,usingtheID bits.The selectedclocksourcecan be furtherdividedby 2,3,4,5,6,7, or8 usingtheTAIDEX bits.The timerclockdividerlogicisresetwhen TACLR isset. NOTE: Timer_A dividers AfterprogrammingID orTAIDEX bits,settheTACLR bit.ThisclearsthecontentsofTAxR and resetstheclockdividerlogictoa definedstate.The clockdividersareimplementedas down counters.Therefore,when theTACLR bitiscleared,thetimerclockimmediately beginsclockingatthefirstrisingedge oftheTimer_A clocksourceselectedwiththe TASSEL bitsand continuesclockingatthedividersettingssetby theID and TAIDEX bits.

13.2.2 StartingtheTimer

The timermay be startedorrestartedinthefollowingways:

The timercountswhen MC > {0 }and theclocksourceisactive.
When thetimermode iseitherup orup/down,thetimermay be stoppedby writing0 toTAxCCR0. The timermay thenbe restartedby writinga nonzerovaluetoTAxCCR0. Inthisscenario,thetimerstarts incrementingintheup directionfromzero. 399SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Timer□Clock Timer Set TAxCTL TAIFG Set TAxCCR0□CCIFG 1h CCR0-1 CCR0 0h T AxCCR0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Operation www.ti.com

13.2.3 Timer Mode Control

The timerhas fourmodes ofoperation:stop,up,continuous,and up/down (seeTable13-1).The operatingmode isselectedwiththeMC bits. Table13-1.Timer Modes MC Mode Description 00 Stop The timerishalted.

01 Up The timerrepeatedlycountsfromzerotothevalueofTAxCCR0

10 Continuous The timerrepeatedlycountsfromzeroto0FFFFh. 11 Up/down The timerrepeatedlycountsfromzeroup tothevalueofTAxCCR0 and back down tozero. 13.2.3.1Up Mode The up mode isused ifthetimerperiodmust be differentfrom0FFFFh counts.The timerrepeatedly countsup tothevalueofcompare registerTAxCCR0, whichdefinestheperiod(seeFigure13-2).The number oftimercountsintheperiodisTAxCCR0 + 1.When thetimervalueequalsTAxCCR0, thetimer restartscountingfromzero.Ifup mode isselectedwhen thetimervalueisgreaterthanTAxCCR0, the timerimmediatelyrestartscountingfromzero. Figure13-2.Up Mode The TAxCCR0 CCIFG interruptflagissetwhen thetimercountstotheTAxCCR0 value.The TAIFG interruptflagissetwhen thetimercountsfromTAxCCR0 tozero.Figure13-3shows theflagsetcycle. Figure13-3.Up Mode FlagSetting 13.2.3.1.1Changing PeriodRegisterTAxCCR0 When changingTAxCCR0 whilethetimerisrunning,ifthenew periodisgreaterthanorequaltotheold periodorgreaterthanthecurrentcountvalue,thetimercountsup tothenew period.Ifthenew periodis lessthanthecurrentcountvalue,thetimerrollstozero.However,one additionalcountmay occurbefore thecounterrollstozero.

400 Timer_A SLAU259E –May 2009–RevisedJanuary2013

T AxCCR0b T AxCCR0c T AxCCR0d t0 t0 T AxCCR1a T AxCCR1b T AxCCR1c T AxCCR1d t1 t1 FFFEh FFFFh 0h Timer□Clock Timer Set TAxCTL TAIFG 1h FFFEh FFFFh 0h 0FFFFh ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation 13.2.3.2Continuous Mode Inthecontinuousmode, thetimerrepeatedlycountsup to0FFFFh and restartsfromzeroas shown in Figure13-4.The capture/compareregisterTAxCCR0 worksthesame way as theothercapture/compare registers. Figure13-4.Continuous Mode The TAIFG interruptflagissetwhen thetimercountsfrom0FFFFh tozero.Figure13-5shows theflagset cycle. Figure13-5.Continuous Mode FlagSetting 13.2.3.3Use ofContinuous Mode The continuousmode can be used togenerateindependenttimeintervalsand outputfrequencies.Each timean intervaliscompleted,an interruptisgenerated.The nexttimeintervalisadded totheTAxCCRn registerintheinterruptserviceroutine.Figure13-6shows two separatetimeintervals,t0 and t1,being added tothecapture/compareregisters.Inthisusage,thetimeintervaliscontrolledby hardware,not software,withoutimpactfrominterruptlatency.Up ton (wheren = 0 to6),independenttimeintervalsor outputfrequenciescan be generatedusingcapture/compareregisters. Figure13-6.Continuous Mode Time Intervals 401SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Timer□Clock Timer Set TAxCTL TAIFG Set TAxCCR0□CCIFG CCR0-2 1h 0h Up/Down T AxCCR0 0FFFFh ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Operation www.ti.com Time intervalscan be producedwithothermodes as well,where TAxCCR0 isused as theperiodregister. Theirhandlingismore complexsincethesum oftheoldTAxCCRn dataand thenew periodcan be higher thantheTAxCCR0 value.When thepreviousTAxCCRn valueplustx isgreaterthantheTAxCCR0 data, theTAxCCR0 valuemust be subtractedtoobtainthecorrecttimeinterval. 13.2.3.4Up/Down Mode The up/down mode isused ifthetimerperiodmust be differentfrom0FFFFh counts,and ifsymmetrical pulsegenerationisneeded.The timerrepeatedlycountsup tothevalueofcompare registerTAxCCR0 and back down tozero(seeFigure13-7).The periodistwicethevalueinTAxCCR0. Figure13-7.Up/Down Mode The countdirectionislatched.Thisallowsthetimertobe stoppedand thenrestartedinthesame direction itwas countingbeforeitwas stopped.Ifthisisnotdesired,theTACLR bitmust be settoclearthe direction.The TACLR bitalsoclearstheTAxR valueand thetimerclockdivider. Inup/down mode, theTAxCCR0 CCIFG interruptflagand theTAIFG interruptflagaresetonlyonce duringa period,separatedby one-halfthetimerperiod.The TAxCCR0 CCIFG interruptflagissetwhen thetimercountsfromTAxCCR0-1 toTAxCCR0, and TAIFG issetwhen thetimercompletescounting down from0001h to0000h.Figure13-8shows theflagsetcycle. Figure13-8.Up/Down Mode FlagSetting 13.2.3.4.1Changing PeriodRegisterTAxCCR0 When changingTAxCCR0 whilethetimerisrunningand countinginthedown direction,thetimer continuesitsdescentuntilitreacheszero.The new periodtakeseffectafterthecountercountsdown to zero. When thetimeriscountingintheup direction,and thenew periodisgreaterthanorequaltotheold periodorgreaterthanthecurrentcountvalue,thetimercountsup tothenew periodbeforecounting down. When thetimeriscountingintheup directionand thenew periodislessthanthecurrentcountvalue,the timerbeginscountingdown. However,one additionalcountmay occurbeforethecounterbeginscounting down.

402 Timer_A SLAU259E –May 2009–RevisedJanuary2013

Output□Mode□2: Toggle/Reset Output□Mode□6: Toggle/Set TAxCCR0 TAxCCR1 EQU1 TAIFG Interrupt□EventsEQU1 EQU0 EQU1 EQU1 EQU0 TAxCCR2 EQU2 EQU2 EQU2 EQU2 Dead Time ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation 13.2.3.5Use ofUp/Down Mode The up/down mode supportsapplicationsthatrequiredead timesbetween outputsignals(seesection Timer_A OutputUnit).Forexample,toavoidoverloadconditions,two outputsdrivingan H-bridgemust neverbe ina highstatesimultaneously.Intheexample shown inFigure13-9,thetdead is: tdead = ttimer× (TAxCCR1 – TAxCCR2) Where: tdead = Time duringwhichbothoutputsneed tobe inactive ttimer= Cycletimeofthetimerclock TAxCCRn = Contentofcapture/compareregistern The TAxCCRn registersarenotbuffered.They updateimmediatelywhen writtento.Therefore,any requireddead timeisnotmaintainedautomatically. Figure13-9.Output UnitinUp/Down Mode

13.2.4 Capture/Compare Blocks

Up toseven identicalcapture/compareblocks,TAxCCRn (wheren = 0 to7),arepresentinTimer_A.Any oftheblocksmay be used tocapturethetimerdataortogeneratetimeintervals. 13.2.4.1Capture Mode The capturemode isselectedwhen CAP = 1.Capturemode isused torecordtimeevents.Itcan be used forspeed computationsortimemeasurements.The captureinputsCCIxA and CCIxB areconnectedto externalpinsorinternalsignalsand areselectedwiththeCCIS bits.The CM bitsselectthecaptureedge oftheinputsignalas rising,falling,orboth.A captureoccurson theselectededge oftheinputsignal.Ifa captureoccurs:

The timervalueiscopiedintotheTAxCCRn register.
The interruptflagCCIFG isset. The inputsignallevelcan be readatany timeviatheCCI bit.Devicesmay have differentsignals connectedtoCCIxA and CCIxB.See thedevice-specificdatasheetfortheconnectionsofthesesignals. The capturesignalcan be asynchronoustothetimerclockand cause a racecondition.SettingtheSCS bitsynchronizesthecapturewiththenexttimerclock.SettingtheSCS bittosynchronizethecapture signalwiththetimerclockisrecommended (seeFigure13-10). 403SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

COV□=□1 Taken Capture Taken No Capture Taken Read Taken Capture Clear□Bit□COV in□Register TAxCCTLn Idle Idle Capture Capture□Read□and□No□Capture Capture Capture□ReadCapture Set TAxCCRn□CCIFG Capture CCI Timer Timer□Clock n–2 n–1 n n+1 n+2 n+3 n+4 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Operation www.ti.com Figure13-10.Capture Signal(SCS = 1) NOTE: Changing Capture Inputs Changingcaptureinputswhileincapturemode may cause unintendedcaptureevents.To avoidthisscenario,captureinputsshouldonlybe changed when capturemode isdisabled (CM = {0}orCAP = 0). Overflowlogicisprovidedineach capture/compareregistertoindicateifa second capturewas performed beforethevaluefromthefirstcapturewas read.BitCOV issetwhen thisoccursas shown inFigure13- 11.COV must be resetwithsoftware. Figure13-11.Capture Cycle

404 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation 13.2.4.1.1Capture Initiatedby Software Capturescan be initiatedby software.The CMx bitscan be setforcaptureon bothedges.Softwarethen setsCCIS1 = 1 and togglesbitCCIS0 toswitchthecapturesignalbetween VCC and GND, initiatinga captureeach timeCCIS0 changes state: MOV#CAP+SCS+CCIS1+CM_3,&TA0CCTL1;SetupTA0CCTL1,synch.capturemode ;Eventtriggeronbothedgesofcaptureinput. XOR#CCIS0,&TA0CCTL1 ;TA0CCR1=TA0R NOTE: Capture Initiatedby Software Ingeneral,changingcaptureinputswhileincapturemode may cause unintendedcapture events.Forthisscenario,switchingthecaptureinputbetween VCC and GND, disablingthe capturemode isnotrequired. 13.2.4.2Compare Mode The compare mode isselectedwhen CAP = 0.The compare mode isused togeneratePWM output signalsorinterruptsatspecifictimeintervals.When TAxR countstothevalueina TAxCCRn, where n representsthespecificcapture/compareregister.

InterruptflagCCIFG isset.
InternalsignalEQUn = 1.
EQUn affectstheoutputaccordingtotheoutputmode.
The inputsignalCCI islatchedintoSCCI.

13.2.5 Output Unit

Each capture/compareblockcontainsan outputunit.The outputunitisused togenerateoutputsignals, such as PWM signals.Each outputunithas eightoperatingmodes thatgeneratesignalsbased on the EQU0 and EQUn signals. 13.2.5.1Output Modes The outputmodes aredefinedby theOUTMOD bitsand aredescribedinTable13-2.The OUTn signalis changed withtherisingedge ofthetimerclockforallmodes exceptmode 0.Outputmodes 2,3,6,and 7 arenotusefulforoutputunit0 because EQUn = EQU0. Table13-2.Output Modes OUTMODx Mode Description 000 Output The outputsignalOUTn isdefinedby theOUT bit.The OUTn signalupdatesimmediately when OUT isupdated. 001 Set The outputissetwhen thetimercountstotheTAxCCRn value.Itremainssetuntila reset ofthetimer,oruntilanotheroutputmode isselectedand affectstheoutput. 010 Toggle/Reset The outputistoggledwhen thetimercountstotheTAxCCRn value.Itisresetwhen the timercountstotheTAxCCR0 value. 011 Set/Reset The outputissetwhen thetimercountstotheTAxCCRn value.Itisresetwhen thetimer countstotheTAxCCR0 value. 100 Toggle The outputistoggledwhen thetimercountstotheTAxCCRn value.The outputperiodis doublethetimerperiod. 101 Reset The outputisresetwhen thetimercountstotheTAxCCRn value.Itremainsresetuntil anotheroutputmode isselectedand affectstheoutput. 110 Toggle/Set The outputistoggledwhen thetimercountstotheTAxCCRn value.Itissetwhen thetimer countstotheTAxCCR0 value. 111 Reset/Set The outputisresetwhen thetimercountstotheTAxCCRn value.Itissetwhen thetimer countstotheTAxCCR0 value. 405SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

406 Timer_A SLAU259E –May 2009–RevisedJanuary2013

Output□Mode□1:□Set Output□Mode□2: Toggle/Reset Output□Mode□3:□Set/Reset Output□Mode□4: Toggle Output□Mode□5:□Reset Output□Mode□6: oggle/SetT Output□Mode□7:□Reset/Set TAxCCR0 TAxCCR1 EQU1 TAIFG EQU1 EQU0 Interrupt□EventsEQU0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation 13.2.5.1.2Output Example – Timer inContinuous Mode The OUTn signalischanged when thetimerreachestheTAxCCRn and TAxCCR0 values,dependingon theoutputmode. An example isshown inFigure13-13usingTAxCCR0 and TAxCCR1. Figure13-13.Output Example – Timer inContinuous Mode 407SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Output□Mode□1:□Set Output□Mode□2: Toggle/Reset Output□Mode□3:□Set/Reset Output□Mode□4: Toggle Output□Mode□5:□Reset Output□Mode□6: Toggle/Set Output□Mode□7:□Reset/Set TAxCCR0 TAxCCR2 EQU2 TAIFG Interrupt□EventsEQU2 EQU0 EQU2 EQU2 EQU0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Operation www.ti.com 13.2.5.1.3Output Example – Timer inUp/Down Mode The OUTn signalchanges when thetimerequalsTAxCCRn ineithercountdirectionand when thetimer equalsTAxCCR0, dependingon theoutputmode. An example isshown inFigure13-14usingTAxCCR0 and TAxCCR2. Figure13-14.Output Example – Timer inUp/Down Mode NOTE: Switchingbetween outputmodes When switchingbetween outputmodes, one oftheOUTMOD bitsshouldremainsetduring thetransition,unlessswitchingtomode 0.Otherwise,outputglitchingcan occur,because a NOR gatedecodes outputmode 0.A safemethod forswitchingbetween outputmodes isto use outputmode 7 as a transitionstate: BIS#OUTMOD_7,&TA0CCTL1;Setoutputmode=7 BIC#OUTMOD,&TA0CCTL1;Clearunwantedbits

408 Timer_A SLAU259E –May 2009–RevisedJanuary2013

D Set Q IRQ, Interrupt Service Requested Reset Timer Clock POR CAP EQU0 Capture IRACC, Interrupt Request Accepted CCIE ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Operation

13.2.6 Timer_A Interrupts

Two interruptvectorsareassociatedwiththe16-bitTimer_A module:

TAxCCR0 interruptvectorforTAxCCR0 CCIFG
TAxIV interruptvectorforallotherCCIFG flagsand TAIFG Incapturemode, any CCIFG flagissetwhen a timervalueiscapturedintheassociatedTAxCCRn register.Incompare mode, any CCIFG flagissetifTAxR countstotheassociatedTAxCCRn value. Softwaremay alsosetorclearany CCIFG flag.AllCCIFG flagsrequestan interruptwhen their correspondingCCIE bitand theGIE bitareset. 13.2.6.1TAxCCR0 Interrupt The TAxCCR0 CCIFG flaghas thehighestTimer_A interruptpriorityand has a dedicatedinterruptvector as shown inFigure13-15.The TAxCCR0 CCIFG flagisautomaticallyresetwhen theTAxCCR0 interrupt requestisserviced. Figure13-15.Capture/Compare TAxCCR0 InterruptFlag 13.2.6.2TAxIV,InterruptVectorGenerator The TAxCCRy CCIFG flagsand TAIFG flagsareprioritizedand combined tosourcea singleinterrupt vector.The interruptvectorregisterTAxIV isused todeterminewhichflagrequestedan interrupt. The highest-priorityenabledinterruptgeneratesa number intheTAxIV register(seeregisterdescription). Thisnumber can be evaluatedoradded totheprogramcountertoautomaticallyentertheappropriate softwareroutine.DisabledTimer_A interruptsdo notaffecttheTAxIV value. Any access,readorwrite,oftheTAxIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. Forexample,iftheTAxCCR1 and TAxCCR2 CCIFG flagsaresetwhen theinterruptserviceroutine accessestheTAxIV register,TAxCCR1 CCIFG isresetautomatically.AftertheRETI instructionofthe interruptserviceroutineisexecuted,theTAxCCR2 CCIFG flaggeneratesanotherinterrupt. 409SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Operation www.ti.com 13.2.6.2.1TAxIV SoftwareExample The followingsoftwareexample shows therecommended use ofTAxIV and thehandlingoverhead.The TAxIV valueisadded tothePC toautomaticallyjump totheappropriateroutine.The example assumes a singleinstantiationofthelargesttimerconfigurationavailable. The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself.The latenciesare:

Capture/compareblockTA0CCR0: 11 cycles
Capture/compareblocksTA0CCR1, TA0CCR2, TA0CCR3, TA0CCR4, TA0CCR5, TA0CCR6: 16 cycles
TimeroverflowTA0IFG: 14 cycles ;InterrupthandlerforTA0CCR0CCIFG. Cycles CCIFG_0_HND ; ... ;StartofhandlerInterruptlatency6 RETI 5 ;InterrupthandlerforTA0IFG,TA0CCR1throughTA0CCR6CCIFG. TA0_HND... ;Interruptlatency 6 ADD &TA0IV,PC;AddoffsettoJumptable3 RETI ;Vector0:Nointerrupt5 JMP CCIFG_1_HND;Vector2:TA0CCR1 2 JMP CCIFG_2_HND;Vector4:TA0CCR2 2 JMP CCIFG_3_HND;Vector6:TA0CCR3 2 JMP CCIFG_4_HND;Vector8:TA0CCR4 2 JMP CCIFG_5_HND;Vector10:TA0CCR5 2 JMP CCIFG_6_HND;Vector12:TA0CCR6 2 TA0IFG_HND ;Vector14:TA0IFGFlag ... ;Taskstartshere RETI 5 CCIFG_6_HND ;Vector12:TA0CCR6 ... ;Taskstartshere RETI ;Backtomainprogram 5 CCIFG_5_HND ;Vector10:TA0CCR5 ... ;Taskstartshere RETI ;Backtomainprogram 5 CCIFG_4_HND ;Vector8:TA0CCR4 ... ;Taskstartshere RETI ;Backtomainprogram 5 CCIFG_3_HND ;Vector6:TA0CCR3 ... ;Taskstartshere RETI ;Backtomainprogram 5 CCIFG_2_HND ;Vector4:TA0CCR2 ... ;Taskstartshere RETI ;Backtomainprogram 5 CCIFG_1_HND ;Vector2:TA0CCR1 ... ;Taskstartshere RETI ;Backtomainprogram 5

410 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Registers

13.3 Timer_A Registers

Timer_A registersarelistedinTable13-3forthelargestconfigurationavailable.The base addresscan be foundinthedevice-specificdatasheet. Table13-3.Timer_A Registers Offset Acronym RegisterName Type Access Reset Section 00h TAxCTL Timer_AxControl Read/write Word 0000h Section13.3.1 02h TAxCCTL0 Timer_AxCapture/CompareControl0 Read/write Word 0000h Section13.3.3 04h TAxCCTL1 Timer_AxCapture/CompareControl1 Read/write Word 0000h Section13.3.3 06h TAxCCTL2 Timer_AxCapture/CompareControl2 Read/write Word 0000h Section13.3.3 08h TAxCCTL3 Timer_AxCapture/CompareControl3 Read/write Word 0000h Section13.3.3 0Ah TAxCCTL4 Timer_AxCapture/CompareControl4 Read/write Word 0000h Section13.3.3 0Ch TAxCCTL5 Timer_AxCapture/CompareControl5 Read/write Word 0000h Section13.3.3 0Eh TAxCCTL6 Timer_AxCapture/CompareControl6 Read/write Word 0000h Section13.3.3 10h TAxR Timer_AxCounter Read/write Word 0000h Section13.3.2 12h TAxCCR0 Timer_AxCapture/Compare0 Read/write Word 0000h Section13.3.4 14h TAxCCR1 Timer_AxCapture/Compare1 Read/write Word 0000h Section13.3.4 16h TAxCCR2 Timer_AxCapture/Compare2 Read/write Word 0000h Section13.3.4 18h TAxCCR3 Timer_AxCapture/Compare3 Read/write Word 0000h Section13.3.4 1Ah TAxCCR4 Timer_AxCapture/Compare4 Read/write Word 0000h Section13.3.4 1Ch TAxCCR5 Timer_AxCapture/Compare5 Read/write Word 0000h Section13.3.4 1Eh TAxCCR6 Timer_AxCapture/Compare6 Read/write Word 0000h Section13.3.4 2Eh TAxIV Timer_AxInterruptVector Read only Word 0000h Section13.3.5 20h TAxEX0 Timer_AxExpansion0 Read/write Word 0000h Section13.3.6 411SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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13.3.1 TAxCTL Register

Timer_AxControlRegister Figure13-16.TAxCTL Register 15 14 13 12 11 10 9 8 Reserved TASSEL rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ID MC Reserved TACLR TAIE TAIFG rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) w-(0) rw-(0) rw-(0) Table13-4.TAxCTL RegisterDescription Bit Field Type Reset Description 15-10 Reserved RW 0h Reserved 9-8 TASSEL RW 0h Timer_A clocksourceselect 00b = TAxCLK 01b = ACLK 10b = SMCLK 11b = INCLK 7-6 ID RW 0h Inputdivider.These bitsalongwiththeTAIDEX bitsselectthedividerforthe inputclock. 00b = /1 01b = /2 10b = /4 11b = /8 5-4 MC RW 0h Mode control.SettingMCx = 00h when Timer_A isnotinuse conservespower. 00b = Stopmode: Timerishalted 01b = Up mode: Timercountsup toTAxCCR0 10b = Continuousmode: Timercountsup to0FFFFh 11b = Up/down mode: Timercountsup toTAxCCR0 thendown to0000h

3 Reserved RW 0h Reserved

2 TACLR RW 0h Timer_A clear.SettingthisbitresetsTAxR, thetimerclockdividerlogic,and the countdirection.The TACLR bitisautomaticallyresetand isalwaysreadas zero. 1 TAIE RW 0h Timer_A interruptenable.ThisbitenablestheTAIFG interruptrequest. 0b = Interruptdisabled 1b = Interruptenabled

0 TAIFG RW 0h Timer_A interruptflag

0b = No interruptpending 1b = Interruptpending

412 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Registers

13.3.2 TAxR Register

Timer_AxCounterRegister Figure13-17.TAxR Register 15 14 13 12 11 10 9 8 TAxR rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 TAxR rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table13-5.TAxR RegisterDescription Bit Field Type Reset Description 15-0 TAxR RW 0h Timer_A register.The TAxR registeristhecountofTimer_A. 413SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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13.3.3 TAxCCTLn Register

Timer_AxCapture/CompareControln Register Figure13-18.TAxCCTLn Register 15 14 13 12 11 10 9 8 CM CCIS SCS SCCI Reserved CAP rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-(0) r-(0) rw-(0) 7 6 5 4 3 2 1 0 OUTMOD CCIE CCI OUT COV CCIFG rw-(0) rw-(0) rw-(0) rw-(0) r rw-(0) rw-(0) rw-(0) Table13-6.TAxCCTLn RegisterDescription Bit Field Type Reset Description 15-14 CM RW 0h Capturemode 00b = No capture 01b = Captureon risingedge 10b = Captureon fallingedge 11b = Captureon bothrisingand fallingedges 13-12 CCIS RW 0h Capture/compareinputselect.These bitsselecttheTAxCCR0 inputsignal.See thedevice-specificdatasheetforspecificsignalconnections. 00b = CCIxA 01b = CCIxB 10b = GND 11b = VCC 11 SCS RW 0h Synchronizecapturesource.Thisbitisused tosynchronizethecaptureinput signalwiththetimerclock. 0b = Asynchronouscapture 1b = Synchronouscapture 10 SCCI RW 0h Synchronizedcapture/compareinput.The selectedCCI inputsignalislatched withtheEQUx signaland can be readviathisbit. 9 Reserved R 0h Reserved.Reads as 0.

8 CAP RW 0h Capturemode

0b = Compare mode 1b = Capturemode 7-5 OUTMOD RW 0h Outputmode. Modes 2,3,6,and 7 arenotusefulforTAxCCR0 because EQUx = EQU0. 000b = OUT bitvalue 001b = Set 010b = Toggle/reset 011b = Set/reset 100b = Toggle 101b = Reset 110b = Toggle/set 111b = Reset/set 4 CCIE RW 0h Capture/compareinterruptenable.Thisbitenablestheinterruptrequestofthe correspondingCCIFG flag. 0b = Interruptdisabled 1b = Interruptenabled 3 CCI R 0h Capture/compareinput.The selectedinputsignalcan be readby thisbit. 2 OUT RW 0h Output.Foroutputmode 0,thisbitdirectlycontrolsthestateoftheoutput. 0b = Outputlow 1b = Outputhigh

414 Timer_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Timer_A Registers Table13-6.TAxCCTLn RegisterDescription(continued) Bit Field Type Reset Description 1 COV RW 0h Captureoverflow.Thisbitindicatesa captureoverflowoccurred.COV must be resetwithsoftware. 0b = No captureoverflowoccurred 1b = Captureoverflowoccurred

0 CCIFG RW 0h Capture/compareinterruptflag

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Timer_A Registers www.ti.com

13.3.4 TAxCCRn Register

Timer_A Capture/Comparen Register Figure13-19.TAxCCRn Register 15 14 13 12 11 10 9 8 TAxCCRn rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 TAxCCRn rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table13-7.TAxCCRn RegisterDescription Bit Field Type Reset Description 15-0 TAxCCR0 RW 0h Compare mode: TAxCCRn holdsthedataforthecomparisontothetimervalue intheTimer_A Register,TAR. Capturemode: The Timer_A Register,TAR, iscopiedintotheTAxCCRn register when a captureisperformed.

13.3.5 TAxIV Register

Timer_AxInterruptVectorRegister Figure13-20.TAxIV Register 15 14 13 12 11 10 9 8 TAIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 TAIV r0 r0 r0 r0 r-(0) r-(0) r-(0) r0 Table13-8.TAxIV RegisterDescription Bit Field Type Reset Description 15-0 TAIV R 0h Timer_A interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Capture/compare1;InterruptFlag:TAxCCR1 CCIFG; InterruptPriority:Highest 04h = InterruptSource:Capture/compare2;InterruptFlag:TAxCCR2 CCIFG 06h = InterruptSource:Capture/compare3;InterruptFlag:TAxCCR3 CCIFG 08h = InterruptSource:Capture/compare4;InterruptFlag:TAxCCR4 CCIFG 0Ah = InterruptSource:Capture/compare5;InterruptFlag:TAxCCR5 CCIFG 0Ch = InterruptSource:Capture/compare6;InterruptFlag:TAxCCR6 CCIFG 0Eh = InterruptSource:Timeroverflow;InterruptFlag:TAxCTL TAIFG; Interrupt Priority:Lowest

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13.3.6 TAxEX0 Register

Timer_AxExpansion0 Register Figure13-21.TAxEX0 Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved TAIDEX (1) r0 r0 r0 r0 r0 rw-(0) rw-(0) rw-(0) (1) AfterprogrammingTAIDEX bitsand configurationofthetimer,setTACLR bittoensureproperresetofthetimerdividerlogic. Table13-9.TAxEX0 RegisterDescription Bit Field Type Reset Description 15-3 Reserved R 0h Reserved.Reads as 0. 2-0 TAIDEX RW 0h Inputdividerexpansion.These bitsalongwiththeID bitsselectthedividerfor theinputclock. 000b = Divideby 1 001b = Divideby 2 010b = Divideby 3 011b = Divideby 4 100b = Divideby 5 101b = Divideby 6 110b = Divideby 7 111b = Divideby 8 417SLAU259E –May 2009–RevisedJanuary2013 Timer_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter14 SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock (RTC) Overview

14.1 RTC Overview

Table14-1.RTC Overview RTC_A RTC_D Feature LPM3.5, Calendarand Counter Mode CalendarMode Yes Yes CounterMode Yes Yes Programmable Alarms Yes Yes Password ProtectedCalendarRegisters No No InputClocks ALCK, SMCLK 32-kHzcrystaloscillator LPM3.5 Support No Yes OffsetCalibrationRegister Yes Yes TemperatureCompensationRegister No No -2.035ppm× 63 ≈ -128ppm -2.17ppm× 59 ≈ -128ppmFrequencyAdjustmentRange +4.069ppm × 63 ≈ +256 ppm +4.34ppm × 59 ≈ +256 ppm FrequencyAdjustmentSteps -2.035ppm, +4.069pmm -2.17ppm, +4.34pmm Withsoftware,manipulatingoffset Withsoftware,manipulatingoffsetTemperatureCompensation calibrationvalue calibrationvalue Calibrationand CompensationPeriod 64 min 60 min IntegratedforCalendarModeBCD toBinaryConversion IntegratedforCalendarMode plusseparateconversionregisters

418 Real-TimeClock(RTC) Overview SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter15 SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock (RTC_A) The Real-TimeClock(RTC_A) module providesclockcounterswitha calendar,a flexibleprogrammable alarm,and calibration.ThischapterdescribestheRTC_A module. 419SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.1 RTC_A Introduction

The RTC_A module providesa real-timeclockand calendarfunctionthatcan alsobe configuredas a general-purposecounter. RTC_A featuresinclude:

Configurableforreal-timeclockwithcalendarfunctionorgeneral-purposecounter
Providesseconds,minutes,hours,day ofweek,day ofmonth,month,and yearinreal-timeclockwith calendarfunction
Interruptcapability
SelectableBCD orbinaryformatinreal-timeclockmode
Programmable alarmsinreal-timeclockmode
Calibrationlogicfortimeoffsetcorrectioninreal-timeclockmode The RTC_A blockdiagramisshown inFigure15-1. NOTE: Real-timeclockinitialization Most RTC_A module registershave no initialcondition.These registersmust be configured by usersoftwarebeforeuse.

420 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

RTCMONRTCYEARLRTCYEARH RTCDAY RTCTEV 8-bit□overflow/minute□changed RTCSSEL

2 RTCBCD

RTCAHOURRTCADAYRTCADOW RTCAMIN Set_RTCTEVIFG Set_RTCAIFG EN EN EN RTCHOLD RT1PS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RT1SSEL RT1PSDIV Set_RT1PSIFG EN RT1IP RT1PSHOLD RT0PS RT0SSEL 3RT0PSDIV Set_RT0PSIFG EN 110 101 100 011 010 001 000 RT0IP SMCLK ACLK RT0PSHOLD Keepout Logic Set_RTCRDYIFG Calibration Logic EN RTCCALS RTCCAL RTCMODE 111110101100011010001000 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 111 111110101100011010001000 16-bit□overflow/hour□changed 24-bit□overflow/midnight 32-bit□overflow/noon RTCNT3/ RTCHOUR RTCNT2/ RTCMIN RTCNT1/ RTCSEC 110 101 100 011 010 001 000 111 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_A Introduction Figure15-1.RTC_A 421SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.2 RTC_A Operation

The RTC_A module can be configuredas a real-timeclockwithcalendarfunction(calendarmode) oras a 32-bitgeneralpurposecounter(countermode) withtheRTCMODE bit.

15.2.1 Counter Mode

Countermode isselectedwhen RTCMODE isreset.Inthismode, a 32-bitcounterisprovidedthatis directlyaccessibleby software.Switchingfromcalendarmode tocountermode resetsthecountvalue (RTCNT1, RTCNT2, RTCNT3, RTCNT4), as wellas theprescalecounters(RT0PS, RT1PS). The clocktoincrementthecountercan be sourcedfromACLK, SMCLK, orprescaledversionsofACLK or SMCLK. PrescaledversionsofACLK orSMCLK aresourcedfromtheprescaledividers(RT0PS and RT1PS). RT0PS and RT1PS output/2,/4,/8,16,/32,/64,/128,and /256versionsofACLK and SMCLK, respectively.The outputofRT0PS can be cascadedwithRT1PS. The cascadedoutputcan be used as a clocksourceinputtothe32-bitcounter. Fourindividual8-bitcountersarecascadedtoprovidethe32-bitcounter.Thisprovides8-bit,16-bit,24-bit, or32-bitoverflowintervalsofthecounterclock.The RTCTEV bitsselecttherespectivetriggerevent.An RTCTEV eventcan triggeran interruptby settingtheRTCTEVIE bit.Each counter,RTCNT1 through RTCNT4, isindividuallyaccessibleand may be writtento. RT0PS and RT1PS can be configuredas two 8-bitcountersorcascadedintoa single16-bitcounter. RT0PS and RT1PS can be haltedon an individualbasisby settingtheirrespectiveRT0PSHOLD and RT1PSHOLD bits.When RT0PS iscascadedwithRT1PS, settingRT0PSHOLD causesbothRT0PS and RT1PS tobe halted.The 32-bitcountercan be haltedseveralways dependingon theconfiguration.Ifthe 32-bitcounterissourceddirectlyfromACLK orSMCLK, itcan be haltedby settingRTCHOLD. Ifitis sourcedfromtheoutputofRT1PS, itcan be haltedby settingRT1PSHOLD orRTCHOLD. Finally,ifitis sourcedfromthecascadedoutputsofRT0PS and RT1PS, itcan be haltedby settingRT0PSHOLD, RT1PSHOLD, orRTCHOLD. NOTE: Accessing theRTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, RT1PS registers When thecounterclockisasynchronoustotheCPU clock,any readfromany RTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, orRT1PS registershouldoccurwhilethecounteris notoperating.Otherwise,theresultsmay be unpredictable.Alternatively,thecountermay be readmultipletimeswhileoperating,and a majorityvotetakeninsoftwaretodeterminethe correctreading.Any writetotheseregisterstakeseffectimmediately.

15.2.2 CalendarMode

Calendarmode isselectedwhen RTCMODE isset.Incalendarmode, theRTC_A module provides seconds,minutes,hours,day ofweek,day ofmonth,month,and yearinselectableBCD orhexadecimal format.The calendarincludesa leap-yearalgorithmthatconsidersallyearsevenlydivisibleby fouras leapyears.Thisalgorithmisaccuratefromtheyear1901 through2099.

15.2.2.1 Real-TimeClock and PrescaleDividers

The prescaledividers,RT0PS and RT1PS, areautomaticallyconfiguredtoprovidea 1-sclockintervalfor theRTC_A. RT0PS issourcedfromACLK. ACLK must be setto32768 Hz (nominal)forproperRTC_A calendaroperation.RT1PS iscascadedwiththeoutputACLK/256 ofRT0PS. The RTC_A issourcedwith the/128outputofRT1PS, therebyprovidingtherequired1-sinterval.Switchingfromcountertocalendar mode clearstheseconds,minutes,hours,day-of-week,and yearcountsand setsday-of-monthand month countsto1.Inaddition,RT0PS and RT1PS arecleared. When RTCBCD = 1,BCD formatisselectedforthecalendarregisters.The formatmust be selected beforethetimeisset.ChangingthestateofRTCBCD clearstheseconds,minutes,hours,day-of-week, and yearcountsand setsday-of-monthand month countsto1.Inaddition,RT0PS and RT1PS are cleared.

422 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_A Operation Incalendarmode, theRT0SSEL, RT1SSEL, RT0PSDIV, RT1PSDIV, RT0PSHOLD, RT1PSHOLD, and RTCSSEL bitsaredon'tcare.SettingRTCHOLD haltsthereal-timecountersand prescalecounters, RT0PS and RT1PS.

15.2.2.2 Real-TimeClock Alarm Function

The RTC_A module providesfora flexiblealarmsystem.Thereisa singleuser-programmablealarmthat can be programmed based on thesettingscontainedinthealarmregistersforminutes,hours,day of week,and day ofmonth.The user-programmablealarmfunctionisonlyavailableinthecalendarmode of operation. Each alarmregistercontainsan alarmenable(AE)bitthatcan be used toenabletherespectivealarm register.By settingAE bitsofthevariousalarmregisters,a varietyofalarmeventscan be generated.

Example 1:A userwishestosetan alarmeveryhourat15 minutespastthehour;thatis,at00:15:00, 01:15:00,02:15:00,and so on.Thisispossibleby settingRTCAMIN to15.By settingtheAE bitofthe RTCAMIN and clearingallotherAE bitsofthealarmregisters,thealarmisenabled.When enabled, theAF issetwhen thecounttransitionsfrom00:14:59to00:15:00,01:14:59to01:15:00,02:14:59to 02:15:00,etc.
Example 2:A userwishestosetan alarmeveryday at04:00:00.Thisispossibleby setting RTCAHOUR to4.By settingtheAE bitoftheRTCHOUR and clearingallotherAE bitsofthealarm registers,thealarmisenabled.When enabled,theAF issetwhen thecounttransitionsfrom03:59:59 to04:00:00.
Example 3:A userwishestosetan alarmfor06:30:00.RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsofRTCAHOUR and RTCAMIN, thealarmisenabled.Once enabled,theAF issetwhen thethetimecounttransitionsfrom06:29:59to06:30:00.Inthiscase,the alarmeventoccurseveryday at06:30:00.
Example 4:A userwishestosetan alarmeveryTuesday at06:30:00.RTCADOW wouldbe setto2, RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsof RTCADOW, RTCAHOUR and RTCAMIN, thealarmisenabled.Once enabled,theAF issetwhen the thetimecounttransitionsfrom06:29:59to06:30:00and theRTCDOW transitionsfrom1 to2.
Example 5:A userwishestosetan alarmthefifthday ofeach month at06:30:00.RTCADAY wouldbe setto5,RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsof RTCADAY, RTCAHOUR and RTCAMIN, thealarmisenabled.Once enabled,theAF issetwhen the thetimecounttransitionsfrom06:29:59to06:30:00and theRTCDAY equals5. NOTE: Invalidalarm settings Invalidalarmsettingsarenotcheckedviahardware.Itistheuser'sresponsibilitytoensure thatvalidalarmsettingsareentered. NOTE: Invalidtimeand datevalues Writingofinvaliddateand/ortimeinformationordatavaluesoutsidethelegalranges specifiedintheRTCSEC, RTCMIN, RTCHOUR, RTCDAY, RTCDOW, RTCYEARH, RTCYEARL, RTCAMIN, RTCAHOUR, RTCADAY, and RTCADOW registerscan resultin unpredictablebehavior. NOTE: Settingthealarm To preventpotentialerroneousalarmconditionsfromoccurring,thealarmsshouldbe disabledby clearingtheRTCAIE, RTCAIFG, and AE bitspriortowritingnew timevaluesto theRTC timeregisters.

15.2.2.3 Reading or WritingReal-TimeClock RegistersinCalendarMode

Because thesystemclockmay be asynchronoustotheRTC_A clocksource,specialcaremust be taken when accessingthereal-timeclockregisters. 423SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_A Operation www.ti.com Incalendarmode, thereal-timeclockregistersareupdatedonce persecond.To preventreadingany real- timeclockregisteratthetimeofan update,whichcouldresultinan invalidtimebeingread,a keepout window isprovided.The keepoutwindow iscenteredapproximately-128/32768s aroundtheupdate transition.The read-onlyRTCRDY bitisresetduringthekeepoutwindow periodand setoutsidethe keepoutthewindow period.Any readoftheclockregisterswhileRTCRDY isresetisconsideredtobe potentiallyinvalid,and thetimereadshouldbe ignored. An easy way tosafelyreadthereal-timeclockregistersistouse theRTCRDYIFG interruptflag.Setting RTCRDYIE enablestheRTCRDYIFG interrupt.Once enabled,an interruptisgeneratedbased on the risingedge oftheRTCRDY bit,causingtheRTCRDYIFG tobe set.Atthispoint,theapplicationhas nearlya completesecond tosafelyreadany orallofthereal-timeclockregisters.Thissynchronization processpreventsreadingthetimevalueduringtransition.The RTCRDYIFG flagisresetautomatically when theinterruptisserviced,orcan be resetwithsoftware. Incountermode, theRTCRDY bitremainsreset.RTCRDYIE isa don'tcareand RTCRDYIFG remains reset. NOTE: Reading or writingreal-timeclockregisters When thecounterclockisasynchronoustotheCPU clock,any readfromany RTCSEC, RTCMIN, RTCHOUR, RTCDOW, RTCDAY, RTCMON, RTCYEARL, orRTCYEARH register whiletheRTCRDY isresetmay resultininvaliddatabeingread.To safelyreadthecounting registers,eitherpollingoftheRTCRDY bitorthesynchronizationprocedurepreviously describedcan be used.Alternatively,thecounterregistercan be readmultipletimeswhile operating,and a majorityvotetakeninsoftwaretodeterminethecorrectreading.Reading theRT0PS and RT1PS can onlybe handledby readingtheregistersmultipletimesand a majorityvotetakeninsoftwaretodeterminethecorrectreadingorby haltingthecounters. Any writetoany countingregistertakeseffectimmediately.However,theclockisstopped duringthewrite.Inaddition,RT0PS and RT1PS registersarereset.Thiscouldresultin losingup to1 s duringa write.Writingofdataoutsidethelegalrangesorinvalidtimestamp combinationsresultsinunpredictablebehavior.

15.2.3 Real-TimeClock Interrupts

The RTC_A module has fiveinterruptsourcesavailable,each withindependentenablesand flags.

15.2.3.1 Real-TimeClock InterruptsinCalendarMode

Incalendarmode, fivesourcesforinterruptsareavailable,namely RT0PSIFG, RT1PSIFG, RTCRDYIFG, RTCTEVIFG, and RTCAIFG. These flagsareprioritizedand combined tosourcea singleinterruptvector. The interruptvectorregister(RTCIV)isused todeterminewhichflagrequestedan interrupt. The highest-priorityenabledinterruptgeneratesa number intheRTCIV register(seeregisterdescription). Thisnumber can be evaluatedoradded totheprogramcounter(PC)toautomaticallyenterthe appropriatesoftwareroutine.DisabledRTC interruptsdo notaffecttheRTCIV value. Any access,readorwrite,oftheRTCIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. Inaddition,allflagscan be clearedviasoftware. The user-programmablealarmeventsourcesthereal-timeclockinterrupt,RTCAIFG. SettingRTCAIE enablestheinterrupt.Inadditiontotheuser-programmablealarm,theRTC_A module providesforan intervalalarmthatsourcesreal-timeclockinterrupt,RTCTEVIFG. The intervalalarmcan be selectedto cause an alarmeventwhen RTCMIN changed orRTCHOUR changed,everyday atmidnight(00:00:00) oreveryday atnoon (12:00:00).The eventisselectablewiththeRTCTEV bits.SettingtheRTCTEVIE bit enablestheinterrupt. The RTCRDY bitsourcesthereal-timeclockinterrupt,RTCRDYIFG, and isusefulinsynchronizingthe readoftimeregisterswiththesystemclock.SettingtheRTCRDYIE bitenablestheinterrupt.

424 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_A Operation RT0PSIFG can be used togenerateinterruptintervalsselectableby theRT0IP bits.Incalendarmode, RT0PS issourcedwithACLK at32768 Hz,so intervalsof16384 Hz,8192 Hz,4096 Hz,2048 Hz, 1024 Hz,512 Hz,256 Hz,or128 Hz arepossible.SettingtheRT0PSIE bitenablestheinterrupt. RT1PSIFG can generateinterruptintervalsselectableby theRT1IP bits.Incalendarmode, RT1PS is sourcedwiththeoutputofRT0PS, whichis128 Hz (32768/256Hz).Therefore,intervalsof64 Hz,32 Hz, 16 Hz,8 Hz,4 Hz,2 Hz,1 Hz,or0.5Hz arepossible.SettingtheRT1PSIE bitenablestheinterrupt. 15.2.3.2Real-TimeClock InterruptsinCounter Mode Incountermode, threeinterruptsourcesareavailable:RT0PSIFG, RT1PSIFG, and RTCTEVIFG. RTCAIFG and RTCRDYIFG arecleared.RTCRDYIE and RTCAIE aredon'tcare. RT0PSIFG can be used togenerateinterruptintervalsselectableby theRT0IP bits.Incountermode, RT0PS issourcedwithACLK orSMCLK, so divideratiosof/2,/4,/8,/16,/32,/64,/128,and /256ofthe respectiveclocksourcearepossible.SettingtheRT0PSIE bitenablestheinterrupt. RT1PSIFG can be used togenerateinterruptintervalsselectableby theRT1IP bits.Incountermode, RT1PS issourcedwithACLK, SMCLK, ortheoutputofRT0PS, so divideratiosof/2,/4,/8,/16,/32,/64, /128,and /256oftherespectiveclocksourcearepossible.SettingtheRT1PSIE bitenablestheinterrupt. The RTC_A module providesforan intervaltimerthatsourcesreal-timeclockinterrupt,RTCTEVIFG. The intervaltimercan be selectedtocause an interrupteventwhen an 8-bit,16-bit,24-bit,or32-bitoverflow occurswithinthe32-bitcounter.The eventisselectablewiththeRTCTEV bits.SettingtheRTCTEVIE bit enablestheinterrupt. 15.2.3.2.1RTCIV SoftwareExample The followingsoftwareexample shows therecommended use ofRTCIV and thehandlingoverhead.The RTCIV valueisadded tothePC toautomaticallyjump totheappropriateroutine. The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself. ;InterrupthandlerforRTCinterruptflags. Cycles RTC_HND ;Interruptlatency 6 ADD&RTCIV,PC;AddoffsettoJumptable3 RETI ;Vector0:Nointerrupt5 JMPRTCRDYIFG_HND;Vector2:RTCRDYIFG2 JMPRTCTEVIFG_HND;Vector4:RTCTEVIFG2 JMPRTCAIFG ;Vector6:RTCAIFG 5 JMPRT0PSIFG;Vector8:RT0PSIFG 5 JMPRT1PSIFG;VectorA:RT1PSIFG 5 RETI ;VectorC:Reserved 5 RTCRDYIFG_HND ;Vector2:RTCRDYIFGFlag to ;Taskstartshere RETI 5 RTCTEVIFG_HND ;Vector4:RTCTEVIFG to ;Taskstartshere RETI ;Backtomainprogram 5 RTCAIFG_HND ;Vector6:RTCAIFG to ;Taskstartshere RT0PSIFG_HND ;Vector8:RT0PSIFG to ;Taskstartshere RT1PSIFG_HND ;VectorA:RT1PSIFG to ;Taskstartshere 425SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.2.4 Real-TimeClock Calibration

The RTC_A module has calibrationlogicthatallowsforadjustingthecrystalfrequencyinapproximately +4-ppm or–2-ppm steps,allowingforhighertimekeepingaccuracyfromstandardcrystals.TheRTCCAL bitsareused toadjustthefrequency.When RTCCALS isset,each RTCCAL LSB causesa ≈ +4-ppm adjustment.When RTCCALS iscleared,each RTCCAL LSB causesa ≈ –2-ppm adjustment.Calibrationis availableonlyincalendarmode. Incountermode (RTCMODE = 0),thecalibrationlogicisdisabled. Calibrationisaccomplishedby periodicallyadjustingtheRT1PS counterbased on theRTCCALS and RTCCALx settings.Incalendarmode, theRT0PS dividesthenominial37268-Hz low-frequency(LF) crystalclockinputby 256.A 64-minuteperiodhas 32768 cycles/sec× 60 sec/min× 64 min = 125829120 cycles.Thereforea –2-ppm reductioninfrequency(down calibration)approximatelyequatestoaddingan additional256 cyclesevery125829120 cycles(256/125829120= 2.035ppm).Thisisaccomplishedby holdingtheRT1PS counterforone additionalclockoftheRT0PS outputwithina 64-minuteperiod. Similary,a +4-ppm increaseinfrequency(upcalibration)approximatelyequatestoremoving512 cycles every125829120 cycle(512/125829120= 4.069ppm).Thisisaccomplishedby incrementingtheRT1PS counterfortwo additionalclocksoftheRT0PS outputwithina 64-minuteperiod.Each RTCCALx calibrationbitcauseseither256 LF crystalclockcyclestobe added every64 minutesor512 LF crystal clockcyclestobe subtractedevery64 minutes,givinga frequencyadjustmentofapproximately–2 ppm or +4 ppm, respectively. To calibratethefrequency,theRTCCLK outputsignalisavailableata pin.The RTCCALF bitscan be used toselectthefrequencyrateoftheRTCCLK outputsignal,eitherno signal,512 Hz,256 Hz,or1 Hz. The basicflowtocalibratethefrequencyisas follows: 1. ConfiguretheRTCCLK pin. 2. Measure theRTCCLK outputsignalwithan appropriateresolutionfrequencycounter;thatis,withinthe resolutionrequired. 3. Compute theabsoluteerrorinppm: AbsoluteError(ppm)= |106 × (fMEASURED – fRTCCLK )/fRTCCLK |,where fRTCCLK istheexpectedfrequencyof512 Hz,256 Hz,or1 Hz. 4. Adjustthefrequency,by performingthefollowing: (a)Ifthefrequencyistoolow,setRTCALS = 1 and applytheappropriateRTCCALx bits,where RTCCALx = (AbsoluteError)/4.069,roundedtothenearestinteger. (b)Ifthefrequencyistoohigh,clearRTCALS = 0 and applytheappropriateRTCCALx bits,where RTCCALx = (AbsoluteError)/2.035,roundedtothenearestinteger. Forexample,assume thatRTCCLK isoutputata frequencyof512 Hz.The measured RTCCLK is RTCCALS wouldbe set,and RTCCAL wouldbe setto16 (66.8/4.069).Similarly,assume thatthe measured RTCCLK is512.0125Hz.The frequencyerrorisapproximately24.4ppm high.To decreasethe frequencyby 24.4ppm, RTCCALS wouldbe cleared,and RTCCAL wouldbe setto12 (24.4/2.035). The calibrationcorrectsonlyinitialoffsetsand does notadjustfortemperatureand agingeffects.Thiscan be handledby periodicallymeasuringtemperatureand usingthecrystal'scharateristiccurvetoadjustthe ppm based on temperatureas required.Incountermode (RTCMODE = 0),thecalibrationlogicis disabled. NOTE: Minimum PossibleCalibration The minimialcalibrationpossibleis-4ppm or+8 ppm. Forexample,settingRTCCALS = 0 and RTCCAL = 0h wouldresultina -4ppm decreaseinfrequency.Similarly,setting RTCCALS = 1 and RTCCAL = 0h wouldresultina +8 ppm increaseinfrequency.

426 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_A Operation NOTE: Calibrationoutputfrequency The 512-Hz and 256-Hz outputfrequenciesobservedattheRTCCLK pinarenotaffectedby changes inthecalibrationsettingssincetheseoutputfrequenciesaregeneratedpriortothe calibrationlogic.The 1-Hz outputfrequencyisaffectedby changes inthecalibrationsettings. Because thefrequencychange issmalland infrequentovera verylongtimeinterval,itcan be difficulttoobserve. 427SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3 RTC_A Registers

The RTC_A module registersarelistedinand Table15-1.The base registerfortheRTC_A module registerscan be foundinthedevice-specificdatasheet.The addressoffsetsaregiveninTable15-1. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table15-1.RTC_A Registers Offset Acronym RegisterName Type Access Reset 00h RTCCTL01 Real-TimeClockControl0,1 Read/write Word 4000h 00h RTCCTL0 Real-TimeClockControl0 Read/write Byte 00h orRTCCTL01_L 01h RTCCTL1 Real-TimeClockControl1 Read/write Byte 40h orRTCCTL01_H 02h RTCCTL23 Real-TimeClockControl2,3 Read/write Word 0000h 02h RTCCTL2 Real-TimeClockControl2 Read/write Byte 00h orRTCCTL23_L 03h RTCCTL3 Real-TimeClockControl3 Read/write Byte 00h orRTCCTL23_H 08h RTCPS0CTL Real-TimePrescaleTimer0 Control Read/write Word 0100h 08h RTCPS0CTLL Read/write Byte 00h orRTCPS0CTL_L 09h RTCPS0CTLH Read/write Byte 01h orRTCPS0CTL_H 0Ah RTCPS1CTL Real-TimePrescaleTimer1 Control Read/write Word 0100h 0Ah RTCPS1CTLL Read/write Byte 00h orRTCPS1CTL_L 0Bh RTCPS0CTLH Read/write Byte 01h orRTCPS0CTL_H 0Ch RTCPS Real-TimePrescaleTimer0,1 Counter Read/write Word undefined 0Ch RT0PS Real-TimePrescaleTimer0 Counter Read/write Byte undefined orRTCPS_L 0Dh RT1PS Real-TimePrescaleTimer1 Counter Read/write Byte undefined orRTCPS_H 0Eh RTCIV RealTime ClockInterruptVector Read Word 0000h 0Eh RTCIV_L Read Byte 00h 0Fh RTCIV_H Read Byte 00h 10h RTCTIM0 Real-TimeClockSeconds,Minutes Read/write Word undefined orRTCNT12 Real-TimeCounter1,2 10h RTCSEC Real-TimeClockSeconds Read/write Byte undefined RTCNT1 Real-TimeCounter1 orRTCTIM0_L 11h RTCMIN Real-TimeClockMinutes Read/write Byte undefined RTCNT2 Real-TimeCounter2 orRTCTIM0_H 12h RTCTIM1 Real-TimeClockHour,Day ofWeek Read/write Word undefined orRTCNT34 Real-TimeCounter3,4 12h RTCHOUR Real-TimeClockHour Read/write Byte undefined

428 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_A Registers Table15-1.RTC_A Registers(continued) Offset Acronym RegisterName Type Access Reset RTCNT3 Real-TimeCounter3 orRTCTIM1_L 13h RTCDOW Real-TimeClockDay ofWeek Read/write Byte undefined RTCNT4 Real-TimeCounter4 orRTCTIM1_H 14h RTCDATE Real-TimeClockDate Read/write Word undefined 14h RTCDAY Real-TimeClockDay ofMonth Read/write Byte undefined orRTCDATE_L 15h RTCMON Real-TimeClockMonth Read/write Byte undefined orRTCDATE_H 16h RTCYEAR Real-TimeClockYear Read/write Word undefined 16h RTCYEARL Read/write Byte undefined orRTCYEAR_L 17h RTCYEARH Read/write Byte undefined orRTCYEAR_H 18h RTCAMINHR Real-TimeClockMinutes,Hour Alarm Read/write Word undefined 18h RTCAMIN Real-TimeClockMinutesAlarm Read/write Byte undefined orRTCAMINHR_L 19h RTCAHOUR Real-TimeClockHours Alarm Read/write Byte undefined orRTCAMINHR_H 1Ah RTCADOWDAY Real-TimeClockDay ofWeek, Day ofMonth Read/write Word undefined Alarm 1Ah RTCADOW Real-TimeClockDay ofWeek Alarm Read/write Byte undefined orRTCADOWDAY_L 1Bh RTCADAY Real-TimeClockDay ofMonth Alarm Read/write Byte undefined orRTCADOWDAY_H 429SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.1 RTCCTL0 Register

Real-TimeClockControl0 Register Figure15-2.RTCCTL0 Register 7 6 5 4 3 2 1 0 Reserved RTCTEVIE RTCAIE RTCRDYIE Reserved RTCTEVIFG RTCAIFG RTCRDYIFG r0 rw-0 rw-0 rw-0 r0 rw-(0) rw-(0) rw-(0) Table15-2.RTCCTL0 RegisterDescription Bit Field Type Reset Description 7 Reserved R 0h Reserved.Alwaysreadsas 0.

6 RTCTEVIE RW 0h Real-timeclocktimeeventinterruptenable

0b = Interruptnotenabled 1b = Interruptenabled 5 RTCAIE RW 0h Real-timeclockalarminterruptenable.Thisbitremainsclearedwhen incounter mode (RTCMODE = 0). 0b = Interruptnotenabled 1b = Interruptenabled

4 RTCRDYIE RW 0h Real-timeclockreadreadyinterruptenable

0b = Interruptnotenabled 1b = Interruptenabled 3 Reserved R 0h Reserved.Alwaysreadsas 0.

2 RTCTEVIFG RW 0h Real-timeclocktimeeventflag

0b = No timeeventoccurred. 1b = Time eventoccurred. 1 RTCAIFG RW 0h Real-timeclockalarmflag.Thisbitremainsclearedwhen incountermode (RTCMODE = 0). 0b = No timeeventoccurred. 1b = Time eventoccurred.

0 RTCRDYIFG RW 0h Real-timeclockreadreadyflag

0b = RTC cannotbe readsafely. 1b = RTC can be readsafely.

430 Real-TimeClock(RTC_A) SLAU259E –May 2009–RevisedJanuary2013

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15.3.2 RTCCTL1 Register

Real-TimeClockControlRegister1 Figure15-3.RTCCTL1 Register 7 6 5 4 3 2 1 0 RTCBCD RTCHOLD RTCMODE RTCRDY RTCSSEL RTCTEV rw-(0) rw-(1) rw-(0) r-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table15-3.RTCCTL1 RegisterDescription Bit Field Type Reset Description 7 RTCBCD RW 0h Real-timeclockBCD select.SelectsBCD countingforreal-timeclock.Appliesto calendarmode (RTCMODE = 1)only;settingisignoredincountermode. Changingthisbitclearsseconds,minutes,hours,day ofweek,and yearto0 and setsday ofmonth and month to1.The real-timeclockregistersmust be setby softwareafterwards. 0b = Binary(hexadecimal)code selected 1b = Binarycoded decimal(BCD) code selected

6 RTCHOLD RW 1h Real-timeclockhold

0b = Real-timeclock(32-bitcounterorcalendarmode) isoperational. 1b = Incountermode (RTCMODE = 0),onlythe32-bitcounterisstopped.In calendarmode (RTCMODE = 1),thecalendarisstoppedas wellas theprescale counters,RT0PS and RT1PS. RT0PSHOLD and RT1PSHOLD aredon'tcare.

5 RTCMODE RW 0h Real-timeclockmode

0b = 32-bitcountermode 1b = Calendarmode. Switchingbetween counterand calendarmode resetsthe real-timeclockcounterregisters.Switchingtocalendarmode clearsseconds, minutes,hours,day ofweek,and yearto0 and setsday ofmonth and month to 1.The real-timeclockregistersmust be setby softwareafterwards.RT0PS and RT1PS arealsocleared.

4 RTCRDY RW 0h Real-timeclockready

0b = RTC timevaluesintransition(calendarmode only) 1b = RTC timevaluessafeforreading(calendarmode only).Thisbitindicates when thereal-timeclocktimevaluesaresafeforreading(calendarmode only). Incountermode, RTCRDY signalremainscleared. 3-2 RTCSSEL RW 0h Real-timeclocksourceselect.SelectsclockinputsourcetotheRTC/32-bit counter.Incalendarmode, thesebitsaredon'tcare.The clockinputis automaticallysettotheoutputofRT1PS. 00b = ACLK 01b = SMCLK 10b = OutputfromRT1PS 11b = OutputfromRT1PS 1-0 RTCTEV RW 0h Real-timeclocktimeevent Countermode (RTCMODE = 0) 00b = 8-bitoverflow 01b = 16-bitoverflow 10b = 24-bitoverflow 11b = 32-bitoverflow Calendarmode (RTCMODE = 1) 00b = Minutechanged 01b = Hour changed 10b = Everyday atmidnight(00:00) 11b = Everyday atnoon (12:00) 431SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.3 RTCCTL2 Register

Real-TimeClockControl2 Register Figure15-4.RTCCTL2 Register 7 6 5 4 3 2 1 0 RTCCALS Reserved RTCCAL rw-(0) r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table15-4.RTCCTL2 RegisterDescription Bit Field Type Reset Description

7 RTCCALS RW 0h Real-timeclockcalibrationsign

0b = Frequencyadjusteddown 1b = Frequencyadjustedup 6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-0 RTCCAL RW 0h Real-timeclockcalibration.Each LSB representsapproximately+4ppm (RTCCALS = 1)ora –2ppm (RTCCALS = 0)adjustmentinfrequency.

15.3.4 RTCCTL3 Register

Real-TimeClockControl3 Register Figure15-5.RTCCTL3 Register 7 6 5 4 3 2 1 0 Reserved RTCCALF r0 r0 r0 r0 r0 r0 rw-(0) rw-(0) Table15-5.RTCCTL3 RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1-0 RTCCALF RW 0h Real-timeclockcalibrationfrequency.SelectsfrequencyoutputtoRTCCLK pin forcalibrationmeasurement.The correspondingportmust be configuredforthe peripheralmodule function.The RTCCLK isnotavailableincountermode and remainslow,and theRTCCALF bitsaredon'tcare. 00b = No frequencyoutputtoRTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz

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15.3.5 RTCNT1 Register

Real-TimeClockCounter1 Register– CounterMode Figure15-6.RTCNT1 Register 7 6 5 4 3 2 1 0 RTCNT1 rw rw rw rw rw rw rw rw Table15-6.RTCNT1 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT1 RW undefined The RTCNT1 registeristhecountofRTCNT1

15.3.6 RTCNT2 Register

Real-TimeClockCounter2 Register– CounterMode Figure15-7.RTCNT2 Register 7 6 5 4 3 2 1 0 RTCNT2 rw rw rw rw rw rw rw rw Table15-7.RTCNT2 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT2 RW undefined The RTCNT2 registeristhecountofRTCNT2

15.3.7 RTCNT3 Register

Real-TimeClockCounter3 Register– CounterMode Figure15-8.RTCNT3 Register 7 6 5 4 3 2 1 0 RTCNT3 rw rw rw rw rw rw rw rw Table15-8.RTCNT3 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT3 RW undefined The RTCNT3 registeristhecountofRTCNT3

15.3.8 RTCNT4 Register

Real-TimeClockCounter4 Register– CounterMode Figure15-9.RTCNT4 Register 7 6 5 4 3 2 1 0 RTCNT4 rw rw rw rw rw rw rw rw Table15-9.RTCNT4 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT4 RW undefined The RTCNT4 registeristhecountofRTCNT4. 433SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.9 RTCSEC Register– CalendarMode With Hexadecimal Format

Real-TimeClockSeconds Register– CalendarMode WithHexadecimalFormat Figure15-10.RTCSEC Register 7 6 5 4 3 2 1 0

0 Seconds

Table15-10.RTCSEC RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Always0 5-0 Seconds RW undefined Seconds (0to59)

15.3.10 RTCSEC Register– CalendarMode With BCD Format

Real-TimeClockSeconds Register– CalendarMode WithBCD Format Figure15-11.RTCSEC Register 7 6 5 4 3 2 1 0

0 Seconds – highdigit Seconds – lowdigit

Table15-11.RTCSEC RegisterDescription Bit Field Type Reset Description 7 0 R 0h Always0 6-4 Seconds – highdigit RW undefined Seconds – highdigit(0to5) 3-0 Seconds – lowdigit RW undefined Seconds – lowdigit(0to9)

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15.3.11 RTCMIN Register– CalendarMode With Hexadecimal Format

Real-TimeClockMinutesRegister– CalendarMode WithHexadecimalFormat Figure15-12.RTCMIN Register 7 6 5 4 3 2 1 0

0 Minutes

Table15-12.RTCMIN RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Always0 5-0 Minutes RW undefined Minutes(0to59)

15.3.12 RTCMIN Register– CalendarMode With BCD Format

Real-TimeClockMinutesRegister– CalendarMode WithBCD Format Figure15-13.RTCMIN Register 7 6 5 4 3 2 1 0

0 Minutes– highdigit Minutes– lowdigit

Table15-13.RTCMIN RegisterDescription Bit Field Type Reset Description 7 0 R 0h Always0 6-4 Minutes– highdigit RW undefined Minutes– highdigit(0to5) 3-0 Minutes– lowdigit RW undefined Minutes– lowdigit(0to9) 435SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.13 RTCHOUR Register– CalendarMode With Hexadecimal Format

Real-TimeClockHours Register– CalendarMode WithHexadecimalFormat Figure15-14.RTCHOUR Register 7 6 5 4 3 2 1 0

0 Hours

r-0 r-0 r-0 rw rw rw rw rw Table15-14.RTCHOUR RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Always0 4-0 Hours RW undefined Hours (0to23)

15.3.14 RTCHOUR Register– CalendarMode With BCD Format

Real-TimeClockHours Register– CalendarMode WithBCD Format Figure15-15.RTCHOUR Register 7 6 5 4 3 2 1 0

0 Hours – highdigit Hours – lowdigit

Table15-15.RTCHOUR RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Always0 5-4 Hours – highdigit RW undefined Hours – highdigit(0to2) 3-0 Hours – lowdigit RW undefined Hours – lowdigit(0to9)

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15.3.15 RTCDOW Register– CalendarMode

Real-TimeClockDay ofWeek Register– CalendarMode Figure15-16.RTCDOW Register 7 6 5 4 3 2 1 0

0 Day ofweek

r-0 r-0 r-0 r-0 r-0 rw rw rw Table15-16.RTCDOW RegisterDescription Bit Field Type Reset Description 7-3 0 R 0h Always0 2-0 Day ofweek RW undefined Day ofweek (0to6)

15.3.16 RTCDAY Register– CalendarMode With Hexadecimal Format

Real-TimeClockDay ofMonth Register– CalendarMode WithHexadecimalFormat Figure15-17.RTCDAY Register 7 6 5 4 3 2 1 0

0 Day ofmonth

r-0 r-0 r-0 rw rw rw rw rw Table15-17.RTCDAY RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Always0 4-0 Day ofmonth RW undefined Day ofmonth (1to28,29,30,31)

15.3.17 RTCDAY Register– CalendarMode With BCD Format

Real-TimeClockDay ofMonth Register– CalendarMode WithBCD Format Figure15-18.RTCDAY Register 7 6 5 4 3 2 1 0

0 Day ofmonth – highdigit Day ofmonth – lowdigit

Table15-18.RTCDAY RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h 5-4 Day ofmonth – high RW undefined Day ofmonth – highdigit(0to3) digit 3-0 Day ofmonth – low RW undefined Day ofmonth – lowdigit(0to9) digit 437SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.18 RTCMON Register– CalendarMode With Hexadecimal Format

Real-TimeClockMonth Register– CalendarMode WithHexadecimalFormat Figure15-19.RTCMON Register 7 6 5 4 3 2 1 0

0 Month

r-0 r-0 r-0 r-0 rw rw rw rw Table15-19.RTCMON RegisterDescription Bit Field Type Reset Description 7-4 0 R 0h Always0 3-0 Month RW undefined Month (1to12)

15.3.19 RTCMON Register– CalendarMode With BCD Format

Real-TimeClockMonth Register– CalendarMode WithBCD Format Figure15-20.RTCMON Register 7 6 5 4 3 2 1 0

0 Month – high Month – lowdigit

r-0 r-0 r-0 rw rw rw rw rw Table15-20.RTCMON RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Always0

4 Month – highdigit RW undefined Month – highdigit(0or1)

3-0 Month – lowdigit RW undefined Month – lowdigit(0to9)

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15.3.20 RTCYEARL Register– CalendarMode With Hexadecimal Format

Real-TimeClockYear Low-ByteRegister– CalendarMode WithHexadecimalFormat Figure15-21.RTCYEARL Register 7 6 5 4 3 2 1 0 Year – lowbyteof0 to4095 rw rw rw rw rw rw rw rw Table15-21.RTCYEARL RegisterDescription Bit Field Type Reset Description 7-0 Year RW undefined Year – lowbyteof0 to4095

15.3.21 RTCYEARL Register– CalendarMode With BCD Format

Real-TimeClockYear Low-ByteRegister– CalendarMode WithBCD Format Figure15-22.RTCYEARL Register 7 6 5 4 3 2 1 0 Decade Year – lowestdigit rw rw rw rw rw rw rw rw Table15-22.RTCYEARL RegisterDescription Bit Field Type Reset Description 7-4 Decade RW undefined Decade (0to9) 3-0 Year – lowestdigit RW undefined Year – lowestdigit(0to9) 439SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.22 RTCYEARH Register– CalendarMode With Hexadecimal Format

Real-TimeClockYear High-ByteRegister– CalendarMode WithHexadecimalFormat Figure15-23.RTCYEARH Register 7 6 5 4 3 2 1 0

0 Year – highbyteof0 to4095

r-0 r-0 r-0 r-0 rw rw rw rw Table15-23.RTCYEARH RegisterDescription Bit Field Type Reset Description 7-4 0 R 0h Always0 3-0 Year RW undefined Year – highbyteof0 to4095

15.3.23 RTCYEARH Register– CalendarMode With BCD Format

Real-TimeClockYear High-ByteRegister– CalendarMode WithBCD Format Figure15-24.RTCYEARH Register 7 6 5 4 3 2 1 0

0 Century– highdigit Century– lowdigit

Table15-24.RTCYEARH RegisterDescription Bit Field Type Reset Description 7 0 R 0h Always0 6-4 Century– highdigit RW undefined Century– highdigit(0to4) 3-0 Century– lowdigit RW undefined Century– lowdigit(0to9)

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15.3.24 RTCAMIN Register– CalendarMode With Hexadecimal Format

Real-TimeClockMinutesAlarmRegister– CalendarMode WithHexadecimalFormat Figure15-25.RTCAMIN Register 7 6 5 4 3 2 1 0 AE 0 Minutes rw r-0 rw rw rw rw rw rw Table15-25.RTCAMIN RegisterDescription Bit Field Type Reset Description

7 AE RW undefined Alarmenable

5-0 Minutes RW undefined Minutes(0to59)

15.3.25 RTCAMIN Register– CalendarMode With BCD Format

Real-TimeClockMinutesAlarmRegister– CalendarMode WithBCD Format Figure15-26.RTCAMIN Register 7 6 5 4 3 2 1 0 AE Minutes– highdigit Minutes– lowdigit rw rw rw rw rw rw rw rw Table15-26.RTCAMIN RegisterDescription Bit Field Type Reset Description

7 AE RW 0h Alarmenable

6-4 Minutes– highdigit RW undefined Minutes– highdigit(0to5) 3-0 Minutes– lowdigit RW undefined Minutes– lowdigit(0to9) 441SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.26 RTCAHOUR Register– CalendarMode With Hexadecimal Format

Real-TimeClockHours AlarmRegister– CalendarMode WithHexadecimalFormat Figure15-27.RTCAHOUR Register 7 6 5 4 3 2 1 0 AE 0 Hours rw r-0 r-0 rw rw rw rw rw Table15-27.RTCAHOUR RegisterDescription Bit Field Type Reset Description 4-0 Hours RW undefined Hours (0to23)

15.3.27 RTCAHOUR Register– CalendarMode With BCD Format

Real-TimeClockHours AlarmRegister– CalendarMode WithBCD Format Figure15-28.RTCAHOUR Register 7 6 5 4 3 2 1 0 AE 0 Hours – highdigit Hours – lowdigit rw r-0 rw rw rw rw rw rw Table15-28.RTCAHOUR RegisterDescription Bit Field Type Reset Description 5-4 Hours – highdigit RW undefined Hours – highdigit(0to2) 3-0 Hours – lowdigit RW undefined Hours – lowdigit(0to9)

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15.3.28 RTCADOW Register

Real-TimeClockDay ofWeek AlarmRegister– CalendarMode Figure15-29.RTCADOW Register 7 6 5 4 3 2 1 0 AE 0 Day ofweek rw r-0 r-0 r-0 r-0 rw rw rw Table15-29.RTCADOW RegisterDescription Bit Field Type Reset Description 2-0 Day ofweek RW undefined Day ofweek (0to6)

15.3.29 RTCADAY Register– CalendarMode With Hexadecimal Format

Real-TimeClockDay ofMonth AlarmRegister– CalendarMode WithHexadecimalFormat Figure15-30.RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day ofmonth rw r-0 r-0 rw rw rw rw rw Table15-30.RTCADAY RegisterDescription Bit Field Type Reset Description 4-0 Day ofmonth RW undefined Day ofmonth (1to28,29,30,31)

15.3.30 RTCADAY Register– CalendarMode With BCD Format

Real-TimeClockDay ofMonth AlarmRegister– CalendarMode WithBCD Format Figure15-31.RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day ofmonth – highdigit Day ofmonth – lowdigit rw r-0 rw rw rw rw rw rw Table15-31.RTCADAY RegisterDescription Bit Field Type Reset Description 5-4 Day ofmonth – high RW undefined Day ofmonth – highdigit(0to3) digit 3-0 Day ofmonth – low RW undefined Day ofmonth – lowdigit(0to9) digit 443SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock(RTC_A) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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15.3.31 RTCPS0CTL Register

Real-TimeClockPrescaleTimer0 ControlRegister Figure15-32.RTCPS0CTL Register 15 14 13 12 11 10 9 8 Reserved RT0SSEL RT0PSDIV Reserved RT0PSHOLD rw-0 rw-0 rw-0 rw-0 rw-0 r0 r0 rw-1 7 6 5 4 3 2 1 0 Reserved RT0IP RT0PSIE RT0PSIFG r0 r0 r0 rw-0 rw-0 rw-0 rw-0 rw-(0) Table15-32.RTCPS0CTL RegisterDescription Bit Field Type Reset Description 15 Reserved R 0h Reserved.Alwaysreadsas 0. 14 RT0SSEL RW 0h Prescaletimer0 clocksourceselect.SelectsclockinputsourcetotheRT0PS counter.Inreal-timeclockcalendarmode, thesebitsaredo notcare.RT0PS clockinputisautomaticallysettotheoutputofRT0PS. 0b = ACLK 1b = SMCLK 13-11 RT0PSDIV RW 0h Prescaletimer0 clockdivide.These bitscontrolthedivideratiooftheRT0PS counter.Inreal-timeclockcalendarmode, thesebitsaredon'tcareforRT0PS and RT1PS. RT0PS clockoutputisautomaticallysetto/256.RT1PS clock outputisautomaticallysetto/128. 00b = Divideby 2 01b = Divideby 4 10b = Divideby 8 11b = Divideby 16 00b = Divideby 32 01b = Divideby 64 10b = Divideby 128 11b = Divideby 256 10-9 Reserved R 0h Reserved.Alwaysreadsas 0. 8 RT0PSHOLD RW 1h Prescaletimer0 hold.Inreal-timeclockcalendarmode, thisbitisdon'tcare. RT0PS isstoppedviatheRTCHOLD bit. 0b = RT0PS operational 1b = RT0PS held 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-2 RT0IP RW 0h Prescaletimer0 interruptinterval 00b = Divideby 2 01b = Divideby 4 10b = Divideby 8 11b = Divideby 16 00b = Divideby 32 01b = Divideby 64 10b = Divideby 128 11b = Divideby 256

1 RT0PSIE RW 0h Prescaletimer0 interruptenable

0b = Interruptnotenabled 1b = Interruptenabled

0 RT0PSIFG RW 0h Prescaletimer0 interruptflag

0b = No timeeventoccurred 1b = Time eventoccurred

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15.3.32 RTCPS1CTL Register

Real-TimeClockPrescaleTimer1 ControlRegister Figure15-33.RTCPS1CTL Register 15 14 13 12 11 10 9 8 RT1SSEL RT1PSDIV Reserved RT1PSHOLD rw-0 rw-0 rw-0 rw-0 rw-0 r0 r0 rw-1 7 6 5 4 3 2 1 0 Reserved RT1IP RT1PSIE RT1PSIFG r0 r0 r0 rw-0 rw-0 rw-0 rw-0 rw-(0) Table15-33.RTCPS1CTL RegisterDescription Bit Field Type Reset Description 15-14 RT1SSEL RW 0h Prescaletimer1 clocksourceselect.SelectsclockinputsourcetotheRT1PS counter.Inreal-timeclockcalendarmode, thesebitsaredo notcare.RT1PS clockinputisautomaticallysettotheoutputofRT0PS. 00b = ACLK 01b = SMCLK 10b = OutputfromRT0PS 11b = OutputfromRT0PS 13-11 RT1PSDIV RW 0h Prescaletimer1 clockdivide.These bitscontrolthedivideratiooftheRT0PS counter.Inreal-timeclockcalendarmode, thesebitsaredon'tcareforRT0PS and RT1PS. RT0PS clockoutputisautomaticallysetto/256.RT1PS clock outputisautomaticallysetto/128. 00b = Divideby 2 01b = Divideby 4 10b = Divideby 8 11b = Divideby 16 00b = Divideby 32 01b = Divideby 64 10b = Divideby 128 11b = Divideby 256 10-9 Reserved R 0h Reserved.Alwaysreadsas 0. 8 RT1PSHOLD RW 1h Prescaletimer1 hold.Inreal-timeclockcalendarmode, thisbitisdon'tcare. RT1PS isstoppedviatheRTCHOLD bit. 0b = RT1PS operational 1b = RT1PS held 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-2 RT1IP RW 0h Prescaletimer1 interruptinterval 00b = Divideby 2 01b = Divideby 4 10b = Divideby 8 11b = Divideby 16 00b = Divideby 32 01b = Divideby 64 10b = Divideby 128 11b = Divideby 256

1 RT1PSIE RW 0h Prescaletimer1 interruptenable

0b = Interruptnotenabled 1b = Interruptenabled

0 RT1PSIFG RW 0h Prescaletimer1 interruptflag

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15.3.33 RT0PS Register

Real-TimeClockPrescaleTimer0 CounterRegister Figure15-34.RT0PS Register 7 6 5 4 3 2 1 0 RT0PS rw rw rw rw rw rw rw rw Table15-34.RT0PS RegisterDescription Bit Field Type Reset Description 7-0 RT0PS RW Undefined Prescaletimer0 countervalue

15.3.34 RT1PS Register

Real-TimeClockPrescaleTimer1 CounterRegister Figure15-35.RTPS1 Register 7 6 5 4 3 2 1 0 RT1PS rw rw rw rw rw rw rw rw Table15-35.RT1PS RegisterDescription Bit Field Type Reset Description 7-0 RT1PS RW Undefined Prescaletimer1 countervalue

15.3.35 RTCIV Register

Real-TimeClockInterruptVectorRegister Figure15-36.RTCIV Register 15 14 13 12 11 10 9 8 RTCIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 RTCIV Table15-36.RTCIV RegisterDescription Bit Field Type Reset Description 15-0 RTCIV R 0h Real-timeclockinterruptvectorvalue 00h = No interruptpending 02h = InterruptSource:RTC ready;InterruptFlag:RTCRDYIFG 04h = InterruptSource:RTC intervaltimer;InterruptFlag:RTCTEVIFG 06h = InterruptSource:RTC useralarm;InterruptFlag:RTCAIFG 08h = InterruptSource:RTC prescaler0;InterruptFlag:RT0PSIFG 0Ah = InterruptSource:RTC prescaler1;InterruptFlag:RT1PSIFG 0Ch = Reserved 0Eh = Reserved 10h = Reserved;InterruptPriority:Lowest

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter16 SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClock D (RTC_D) The real-timeclockRTC_D module providesclockcounterswithcalendarmode, a flexibleprogrammable alarm,and calibration.The RTC_D alsosupportsoperationinLPMx.5.ThischapterdescribestheRTC_D module. 447SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.1 Real-TimeClock RTC_D Introduction

The RTC_D module providesconfigurableclockcounters. RTC_D featuresinclude:

Configurableforreal-timeclockwithcalendarfunctionargeneral-purposecounter
Real-timeclockand calendarmode providingseconds,minutes,hours,day ofweek,day ofmonth, month,and year(includingleapyearcorrection)
Interruptcapability
SelectableBCD orbinaryformatinreal-timeclockand calendarmode
Programmable alarmsinreal-timeclockand calendarmode
Calibrationlogicfortimeoffsetcorrectioninreal-timeclockand calendarmode
OperationinLPMx.5 The RTC_D blockdiagramisshown inFigure16-1. NOTE: Real-timeclockinitialization Most RTC_D module registershave no initialcondition.These registersmust be configured by usersoftwarebeforeuse.

448 Real-TimeClockD (RTC_D) SLAU259E –May 2009–RevisedJanuary2013

RTCMONRTCYEARLRTCYEARH RTCDAY RTCTEV 8-bit overflow/minute changed RTCSSEL RTCAHOURRTCADAYRTCADOW RTCAMIN Set_RTCTEVIFG Set_RTCAIFG EN EN EN RTCHOLD RT1PS Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 RT1SSEL RT1PSDIV Set_RT1PSIFG EN RT1IP RT1PSHOLD RT0PS 3RT0PSDIV Set_RT0PSIFG EN 110 101 100 011 010 001 000 RT0IP from 32kHz Crystal Osc. RT0PSHOLD Keepout Logic Set_RTCRDYIFG Calibration Logic EN RTCCALS RTCCAL RTCMODE 111110101100011010001000 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 111 111110101100011010001000 16-bit overflow/hour changed 24-bit overflow/midnight 32-bit overflow/noon RTCNT3/ RTCHOUR RTCNT2/ RTCMIN RTCNT1/ RTCSEC 110 101 100 011 010 001 000 111 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Real-TimeClockRTC_D Introduction Figure16-1.RTC_D Block Diagram 449SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.2 RTC_D Operation

The RTC_D module can be configuredas a real-timeclockwithcalendarfunction(calendarmode) oras a 32-bitgeneralpruposecounter(countermode) withtheRTCMODE bit.

16.2.1 Counter Mode

Countermode isselectedwhen RTCMODE isreset.Inthismode, a 32-bitcounterisprovidedthatis directlyaccessibleby software.Switchingfromcalendarmode tocountermode does not resetthecount value(RTCNT1, RTCNT2, RTCNT3, RTCNT4) northeprescalecounters(RT0PS, RT1PS). These registersmust be configuredby usersoftwarebeforeuse. The clocktoincrementthecountercan be sourcedfromthe32kHz cyrstaloscillator,orprescaledversions ofthe32kHz cyrstaloscillatorclock.Prescaledversionsaresourcedfromtheprescaledividers(RT0PS and RT1PS). RT0PS and RT1PS can output/2,/4,/8,16,/32,/64,/128,and /256versionsofthe32kHz clock.The outputofRT0PS can be cascadedwithRT1PS. The cascadedoutputcan alsobe used as a clocksourceinputtothe32-bitcounter. Fourindividual8-bitcountersarecascadedtoprovidethe32-bitcounter.Thisprovides8-bit,16-bit,24-bit, or32-bitoverflowintervalsofthecounterclock.The RTCTEV bitsselecttherespectivetriggerevent.An RTCTEV eventcan triggeran interruptby settingtheRTCTEVIE bit.Each counter,RTCNT1 through RTCNT4, isindividuallyaccessibleand may be writtento. RT0PS and RT1PS can be configuredas two 8-bitcountersorcascadedintoa single16-bitcounter. RT0PS and RT1PS can be haltedon an individualbasisby settingtheirrespectiveRT0PSHOLD and RT1PSHOLD bits.When RT0PS iscascadedwithRT1PS, settingRT0PSHOLD causesbothRT0PS and RT1PS tobe halted.The 32-bitcountercan be haltedseveralways dependingon theconfiguration.Ifthe 32-bitcounterissourceddirectlyby the32kHz cyrstalclock,itcan be haltedby settingRTCHOLD. Ifitis sourcedfromtheoutputofRT1PS, itcan be haltedby settingRT1PSHOLD orRTCHOLD. Finally,ifitis sourcedfromthecascadedoutputsofRT0PS and RT1PS, itcan be haltedby settingRT0PSHOLD, RT1PSHOLD, orRTCHOLD. NOTE: Accessing theRTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, RT1PS registers When thecounterclockisasynchronoustotheCPU clock,any readfromany RTCNT1, RTCNT2, RTCNT3, RTCNT4, RT0PS, orRT1PS registershouldoccurwhilethecounteris notoperating.Otherwise,theresultsmay be unpredictable.Alternatively,thecountermay be readmultipletimeswhileoperating,and a majorityvotetakeninsoftwaretodeterminethe correctreading.Any writetotheseregisterstakeseffectimmediately.

16.2.2 CalendarMode

Calendarmode isselectedwhen RTCMODE isset.Incalendarmode, theRTC_D module provides seconds,minutes,hours,day ofweek,day ofmonth,month,and yearinselectableBCD orhexadecimal format.The calendarincludesa leap-yearalgorithmthatconsidersallyearsevenlydivisibleby fouras leapyears.Thisalgorithmisaccuratefromtheyear1901 through2099.Switchingfromcountermode to calendarmode does not resetthecalendarregisters(RTCSEC, RTCMIN, RTCHOUR, RTCDAY, RTCDOW, and RTCYEAR) northeprescalecounters(RT0PS, RT1PS). These registersmust be configuredby usersoftwarebeforeuse. 16.2.2.1Real-TimeClock and PrescaleDividers The prescaledividers,RT0PS and RT1PS, areautomaticallyconfiguredtoprovidea 1-sclockintervalfor theRTC_D. The low-frequencyoscillatormust be operatedat32768 Hz (nominal)forproperRTC_D operation.RT0PS issourceddirectlyfromthelow-frequencycrystaloscillator.RT1PS iscascadedwith theoutputACLK/256 ofRT0PS. The RTC_A issourcedwiththe/128outputofRT1PS, therebyproviding therequired1-sinterval.Switchingfromcountertocalendarmode clearstheseconds,minutes,hours, day-of-week,and yearcountsand setsday-of-monthand month countsto1.Inaddition,RT0PS and RT1PS arecleared.When RTCBCD = 1,BCD formatisselectedforthecalendarregisters.Setting RTCHOLD haltsthereal-timecountersand prescalecounters,RT0PS and RT1PS.

450 Real-TimeClockD (RTC_D) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_D Operation 16.2.2.2Real-TimeClock Alarm Function The RTC_D module providesfora flexiblealarmsystem.Thereisa singleuser-programmablealarmthat can be programmed based on thesettingscontainedinthealarmregistersforminutes,hours,day of week,and day ofmonth.The user-programmablealarmfunctionisonlyavailableinthecalendarmode of operation. Each alarmregistercontainsan alarmenable(AE)bitthatcan be used toenabletherespectivealarm register.By settingAE bitsofthevariousalarmregisters,a varietyofalarmeventscan be generated.

Example 1:A userwishestosetan alarmeveryhourat15 minutespastthehour,thatis,at00:15:00, 01:15:00,02:15:00,and so on.Thisispossibleby settingRTCAMIN to15.By settingtheAE bitofthe RTCAMIN and clearingallotherAE bitsofthealarmregisters,thealarmisenabled.When enabled, theRTCAIFG issetwhen thecounttransitionsfrom00:14:59to00:15:00,01:14:59to01:15:00,
Example 2:A userwishestosetan alarmeveryday at04:00:00.Thisispossibleby setting RTCAHOUR to4.By settingtheAE bitoftheRTCHOUR and clearingallotherAE bitsofthealarm registers,thealarmisenabled.When enabled,theRTCAIFG issetwhen thecounttransitionsfrom
Example 3:A userwishestosetan alarmfor06:30:00.RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsofRTCAHOUR and RTCAMIN, thealarmisenabled.Once enabled,theRTCAIFG issetwhen thetimecounttransitionsfrom06:29:59to06:30:00.Inthiscase, thealarmeventoccurseveryday at06:30:00.
Example 4:A userwishestosetan alarmeveryTuesday at06:30:00.RTCADOW wouldbe setto2, RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsof RTCADOW, RTCAHOUR, and RTCAMIN, thealarmisenabled.Once enabled,theRTCAIFG isset when thetimecounttransitionsfrom06:29:59to06:30:00and theRTCDOW transitionsfrom1 to2.
Example 5:A userwishestosetan alarmthefifthday ofeach month at06:30:00.RTCADAY wouldbe setto5,RTCAHOUR wouldbe setto6 and RTCAMIN wouldbe setto30.By settingtheAE bitsof RTCADAY, RTCAHOUR, and RTCAMIN, thealarmisenabled.Once enabled,theRTCAIFG isset when thetimecounttransitionsfrom06:29:59to06:30:00and theRTCDAY equals5. NOTE: Settingthealarm Priortosettingan initialalarm,allalarmregistersincludingtheAE bitsshouldbe cleared. To preventpotentialerroneousalarmconditionsfromoccurring,thealarmsshouldbe disabledby clearingtheRTCAIE, RTCAIFG, and AE bitspriortowritinginitialornew time valuestotheRTC timeregisters. NOTE: Invalidalarm settings Invalidalarmsettingsarenotcheckedviahardware.Itistheuser'sresponsibilitythatvalid alarmsettingsareentered. NOTE: Invalidtimeand datevalues Writingofinvaliddateand/ortimeinformationordatavaluesoutsidethelegalranges specifiedintheRTCSEC, RTCMIN, RTCHOUR, RTCDAY, RTCDOW, RTCYEAR, RTCAMIN, RTCAHOUR, RTCADAY, and RTCADOW registerscan resultinunpredictable behavior. Alsoafterswitchingfromcountermode tocalendarmode theregistersmust be correctly initializedtoensurevaluesinsidetheirlegalranges. 16.2.2.3Reading or WritingReal-TimeClock RegistersinCalendarMode Because thesystemclockmay be asynchronoustotheRTC_D clocksource,specialcaremust be taken when accessingthereal-timeclockregisters. 451SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_D Operation www.ti.com The real-timeclockregistersareupdatedonce persecond.To preventreadingany real-timeclockregister atthetimeofan updatethatcouldresultinan invalidtimebeingread,a keep-outwindow isprovided.The keep-outwindow iscenteredapproximately128/32768secondsaroundtheupdatetransition.The read- onlyRTCRDY bitisresetduringthekeep-outwindow periodand setoutsidethekeep-outthewindow period.Any readoftheclockregisterswhileRTCRDY isresetisconsideredtobe potentiallyinvalid,and thetimereadshouldbe ignored. An easy way tosafelyreadthereal-timeclockregistersistoutilizetheRTCRDYIFG interruptflag.Setting RTCRDYIE enablestheRTCRDYIFG interrupt.Once enabled,an interruptisgeneratedbased on the risingedge oftheRTCRDY bit,causingtheRTCRDYIFG tobe set.Atthispoint,theapplicationhas nearlya completesecond tosafelyreadany orallofthereal-timeclockregisters.Thissynchronization processpreventsreadingthetimevalueduringtransition.The RTCRDYIFG flagisresetautomatically when theinterruptisserviced,oritcan be resetwithsoftware. Incountermode, theRTCRDY bitremainsreset.RTCRDYIE isa don'tcareand RTCRDYIFG remains reset. NOTE: Reading or writingreal-timeclockregisters When thecounterclockisasynchronoustotheCPU clock,any readfromany RTCSEC, RTCMIN, RTCHOUR, RTCDOW, RTCDAY, RTCMON, orRTCYEAR registerwhilethe RTCRDY isresetmay resultininvaliddatabeingread.To safelyreadthecountingregisters, eitherpollingoftheRTCRDY bitorthesynchronizationprocedurepreviouslydescribedcan be used.Alternatively,thecounterregistercan be readmultipletimeswhileoperating,and a majorityvotetakeninsoftwaretodeterminethecorrectreading.ReadingtheRT0PS and RT1PS can onlybe handledby readingtheregistersmultipletimesand a majorityvotetaken insoftwaretodeterminethecorrectreadingorby haltingthecounters. Any writetoany countingregistertakeseffectimmediately.However,theclockisstopped duringthewrite.Inaddition,RT0PS and RT1PS registersarereset.Thiscouldresultin losingup to1 second duringa write.Writingofdataoutsidethelegalrangesorinvalidtime stamp combinationsresultsinunpredictablebehavior.

452 Real-TimeClockD (RTC_D) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_D Operation

16.2.3 Real-TimeClock Interrupts

The RTC_D module has sixinterruptsourcesavailable,each withindependentenablesand flags. 16.2.3.1Real-TimeClock InterruptsinCalendarMode Sixsourcesforinterruptsareavailable,namely RT0PSIFG, RT1PSIFG, RTCRDYIFG, RTCTEVIFG, RTCAIFG, and RTCOFIFG. These flagsareprioritizedand combined tosourcea singleinterruptvector. The interruptvectorregister(RTCIV)isused todeterminewhichflagrequestedan interrupt. The highest-priorityenabledinterruptgeneratesa number intheRTCIV register(seeregisterdescription). Thisnumber can be evaluatedoradded totheprogramcounter(PC)toautomaticallyenterthe appropriatesoftwareroutine.DisabledRTC interruptsdo notaffecttheRTCIV value. Any access,readorwrite,oftheRTCIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. Inaddition,allflagscan be clearedviasoftware. The user-programmablealarmeventsourcesthereal-timeclockinterrupt,RTCAIFG. SettingRTCAIE enablestheinterrupt.Inadditiontotheuser-programmablealarm,theRTC_D module providesforan intervalalarmthatsourcesreal-timeclockinterrupt,RTCTEVIFG. The intervalalarmcan be selectedto cause an alarmeventwhen RTCMIN changed orRTCHOUR changed,everyday atmidnight(00:00:00) oreveryday atnoon (12:00:00).The eventisselectablewiththeRTCTEV bits.SettingtheRTCTEVIE bit enablestheinterrupt. The RTCRDY bitsourcesthereal-timeclockinterrupt,RTCRDYIFG, and isusefulinsynchronizingthe readoftimeregisterswiththesystemclock.SettingtheRTCRDYIE bitenablestheinterrupt. RT0PSIFG can be used togenerateinterruptintervalsselectableby theRT0IP bits.RT0PS issourced withlow-frequencyoscillatorclockat32768 Hz,so intervalsof16384 Hz,8192 Hz,4096 Hz,2048 Hz, 1024 Hz,512 Hz,256 Hz,or128 Hz arepossible.SettingtheRT0PSIE bitenablestheinterrupt. RT1PSIFG can be used togenerateinterruptintervalsselectableby theRT1IP bits.RT1PS issourced withtheoutputofRT0PS, whichis128 Hz (32768/256Hz).Therefore,intervalsof64 Hz,32 Hz,16 Hz, 8 Hz,4 Hz,2 Hz,1 Hz,or0.5Hz arepossible.SettingtheRT1PSIE bitenablestheinterrupt. The RTCOFIFG bitflagsa failureofthe32-kHzcrystaloscillator.It'smain purposeistowake-up theCPU fromLPM3.5 incase an oscillatorfailureoccurred.

16.2.3.2 Real-TimeClock InterruptsinCounter Mode

Incountermode, fourinterruptsourcesareavailable:RT0PSIFG, RT1PSIFG, RTCTEVIFG, and RTCOFIFG. RTCAIFG and RTCRDYIFG arecleared.RTCRDYIE and RTCAIE aredon'tcare. RT0PSIFG can be used togenerateinterruptintervalsselectableby theRT0IP bits.Incountermode, divideratiosof/2,/4,/8,/16,/32,/64,/128,and /256oftheclocksourcearepossible.Settingthe RT0PSIE bitenablestheinterrupt. RT1PSIFG can be used togenerateinterruptintervalsselectableby theRT1IP bits.Incountermode, RT1PS issourcedwithlow-frequencyoscillatorclock,ortheoutputofRT0PS, so divideratiosof/2,/4,/8, /16,/32,/64,/128,and /256oftherespectiveclocksourcearepossible.SettingtheRT1PSIE bitenables theinterrupt. InCounterMode, theRTC_D module providesforan intervaltimerthatsourcesreal-timeclockinterrupt, RTCTEVIFG. The intervaltimercan be selectedtocause an interrupteventwhen an 8-bit,16-bit,24-bit, or32-bitoverflowoccurswithinthe32-bitcounter.The eventisselectablewiththeRTCTEV bits.Setting theRTCTEVIE bitenablestheinterrupt. The RTCOFIFG bitflagsa failureofthe32-kHzcrystaloscillator.It'smain purposeistowake-up theCPU fromLPM3.5 incase an oscillatorfailureoccurred. 16.2.3.2.1RTCIV SoftwareExample The followingsoftwareexample shows therecommended use ofRTCIV and thehandlingoverhead.The RTCIV valueisadded tothePC toautomaticallyjump totheappropriateroutine. 453SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_D Operation www.ti.com The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself. ;InterrupthandlerforRTCinterruptflags. RTC_HND ;Interruptlatency 6 ADD&RTCIV,PC;AddoffsettoJumptable3 RETI ;Vector0:Nointerrupt5 JMPRTCRDYIFG_HND;Vector2:RTCRDYIFG2 JMPRTCTEVIFG_HND;Vector4:RTCTEVIFG2 JMPRTCAIFG_HND;Vector6:RTCAIFG 5 JMPRT0PSIFG_HND;Vector8:RT0PSIFG5 JMPRT1PSIFG_HND;VectorA:RT1PSIFG5 JMPRTCOFIFG_HND;VectorC:RTCOFIFG5 RETI ;VectorE:Reserved5 RTCRDYIFG_HND ;Vector2:RTCRDYIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5 RTCTEVIFG_HND ;Vector4:RTCTEVIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5 RTCAIFG_HND ;Vector6:RTCAIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5 RT0PSIFG_HND ;Vector8:RT0PSIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5 RT1PSIFG_HND ;VectorA:RT1PSIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5 RTCOFIFG_HND ;VectorC:RTCOFIFGFlag ... ;Taskstartshere RETI ;Backtomainprogram5

16.2.4 Real-TimeClock Calibration

The RTC_D module has calibrationlogicthatallowsforadjustingthecrystalfrequencyinapproximately +4-ppm or–2-ppm steps,allowingforhighertimekeepingaccuracyfromstandardcrystals.TheRTCCALx bitsareused toadjustthefrequency.When RTCCALS isset,each RTCCALx LSB causesa ≈ +4-ppm adjustment.When RTCCALS iscleared,each RTCCALx LSB causesa ≈ –2-ppm adjustment.Calibration isavailableincalendarmode only.Incountermode (RTCMODE=0), thecalibrationlogicisdisabled. Calibrationisaccomplishedby periodicallyadjustingtheRT1PS counterbased on theRTCCALS and RTCCALx settings.Incalendarmode, theRT0PS dividesthenominial37268-Hz low-frequency(LF) crystalclockinputby 256.A 60-minuteperiodhas 32768 cycles/sec× 60 sec/min× 60 min = 117964800 cycles.Therefore,a –2-ppm reductioninfrequency(down calibration)approximatelyequatestoaddingan additional256 cyclesevery117964800 cycles(256/117964800= 2.17ppm).Thisisaccomplishedby holdingtheRT1PS counterforone additionalclockoftheRT0PS outputwithina 60-minuteperiod. Similary,a +4-ppm increaseinfrequency(upcalibration)approximatelyequatestoremoving512 cycles every117964800 cycle(512/117964800= 4.34ppm).Thisisaccomplishedby incrementingtheRT1PS counterfortwo additionalclocksoftheRT0PS outputwithina 60-minuteperiod.Each RTCCALx calibrationbitcauseseither256 LF crystalclockcyclestobe added every60 minutesor512 LF crystal clockcyclestobe subtractedevery60 minutes,givinga frequencyadjustmentofapproximately-2ppm or +4 ppm, respectively.

454 Real-TimeClockD (RTC_D) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_D Operation To calibratethefrequency,theRTCCLK outputsignalisavailableata pin.RTCCALF bitscan be used to selectthefrequencyrateoftheoutputsignal,eitherno signal,512 Hz,256 Hz,or1 Hz. The basicflowtocalibratethefrequencyisas follows: 1. ConfiguretheRTCCLK pin. 2. Measure theRTCCLK outputsignalwithan appropriateresolutionfrequencycounter;thatis,within theresolutionrequired. 3. Compute theabsoluteerrorinppm: Absoluteerror(ppm)= |106 (fMEASURED -fRTCCLK )/fRTCCLK |,where fRTCCLK istheexpectedfrequencyof512 Hz,256 Hz,or1 Hz. 4. Adjustthefrequencyby performingthefollowing: (a)Ifthefrequencyistoolow,setRTCCALS = 1 and applytheappropriateRTCCALx bits,where RTCCALx = (AbsoluteError)/4.34roundedtothenearestinteger (b)Ifthefrequencyistoohigh,clearRTCCALS = 0 and applytheappropriateRTCCALx bits,where RTCCALx = (AbsoluteError)/2.17roundedtothenearestinteger Forexample,assume thatRTCCLK isconfiguredtooutputata frequencyof512 Hz.The measured RTCCLK is511.9658Hz.Thisfrequencyerrorisapproximately66.8ppm toolow.To increasethe frequencyby 66.8ppm, RTCCALS wouldbe set,and RTCCALx wouldbe setto15 (66.8/4.34).Similarly, assume thatthemeasured RTCCLK is512.0125Hz.The frequencyerrorisapproximately24.4ppm too high.To decreasethefrequencyby 24.4ppm, RTCCALS wouldbe cleared,and RTCCAL wouldbe setto 11 (24.4/2.17). The calibrationcorrectsonlyinitialoffsetsand does notadjustfortemperatureand agingeffects.These effectscan be handledby periodicallymeasuringtemperatureand usingthecrystal'scharateristiccurveto adjusttheppm based on temperature,as required.Incountermode (RTCMODE = 0),thecalibrationlogic isdisabled. NOTE: Calibrationoutputfrequency The 512-Hz and 256-Hz outputfrequenciesobservedattheRTCCLK pinarenotaffectedby changes inthecalibrationsettingssincetheseoutputfrequenciesaregeneratedpriortothe calibrationlogic.The 1-Hz outputfrequencyisaffectedby changes inthecalibrationsettings. Because thefrequencychange issmalland infrequentovera verylongtimeinterval,itcan be difficulttoobserve. 455SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_D Operation www.ti.com 16.2.5 Real-TimeClock OperationinLPMx.5 Low-Power Mode The regulatorofthePower Management Module (PMM) isdisabledupon enteringLPMx.5,whichcauses most oftheRTC_D configurationregisterstobe lost;onlythecountersareretained.Table16-1liststhe retainedregistersinLPMx.5.Alsotheconfigurationoftheinterruptsisstoredso thattheconfigured interruptscan cause a wakeup upon exitfromLPMx.5. The followinginterruptflagscan be used as RTC_D wake-up interruptsources:

RTCTEVIFG: Real-timeclocktimeeventinterruptflag
RTCAIFG: Real-timeclockalarminterruptflag
RT1PSIFG: Prescaletimer1 interruptflag
RTCOFIFG: 32-kHzcrystaloscillatorfaultinterruptflag Afterrestoringtheconfigurationregistersand clearingLOCKLPM5, theinterruptscan be servicedas usual.The detailedflowisas follows: 1. SetallI/OstogeneralpurposeI/Osand configureas needed.Optionallyconfigureinputinterruptpins forwake-up.ConfigureRTC_D interruptsforwake-up (setRTCTEVIE, RTCAIE, RT1PSIE, or RTCOFIE. Ifthealarminterruptisalsoused as wake-up event,thealarmregistersmust be configured as needed). 2. EnsureclocksystemsettingsallowLPMx.5 entryaccordingtoTable3-1inUCS chapter. 3. EnterLPMx.5 withLPMx.5 entrysequence. bis#PMMKEY + REGOFF, &PMMCTL0 bis#LPM4, SR 4. LOCKLPM5 isautomaticallysetby hardwareupon enteringLPMx.5,thecorevoltageregulatoris disabled,and allclocksaredisabledexceptforthe32-kHzcrystaloscillatorclockiftheRTC isenabled withRTCHOLD = 0. 5. An LPMx.5 wake-up event,such as an edge on a wake-up inputpin,arean RTC_D interruptevent and starttheBOR entrysequence togetherwiththecorevoltageregulator.Allperipheralregistersare settotheirdefaultconditions.The I/Opinstateremainslockedas wellas theinterruptconfigurationfor theRTC_D. 6. The devicecan be configured.The I/Oconfigurationand theRTC_D controland interruptconfiguration thatwas notretainedduringLPMx.5 shouldbe restoredtothevaluespriortoenteringLPMx.5.After restoringtheconfigurationregisterstheLOCKLPM5 bitcan be cleared,thisreleasestheI/Opin conditionsas wellas theRTC_D interruptconfiguration. 7. AfterenablingI/Oand RTC_D interrupts,theinterruptthatcaused thewake-up can be serviced. IftheRTC isenabled(RTCHOLD = 0),the32-kHzoscillatorremainsactiveduringLPMx.5.The fault detectionalsoremainsfunctional.Ifa faultoccursduringLPMx.5 and theRTCOFIE was setbefore enteringLPMx.5,a wake-up eventisissued.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_D Registers

16.3 RTC_D Registers

The RTC_D registersarelistedinTable16-1.ThistablealsoliststheretentionduringLPMx.5.Registers thatarenotretainedduringLPMx.5 must be restoredafterexitfromLPMx.5.The base addressforthe RTC_D module registerscan be foundinthedevice-specificdatasheet.The addressoffsetsaregivenin Table16-1. NOTE: Most registershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table16-1.RTC_D Registers Offset Acronym RegisterName Type Access Reset LPMx.5 or Backup 00h RTCCTL01 Real-TimeClockControl0,1 Read/write Word 4000h notretained 00h RTCCTL0 Real-TimeClockControl0 Read/write Byte 00h notretained orRTCCTL01_L 01h RTCCTL1 Real-TimeClockControl1 Read/write Byte 40h notretained orRTCCTL01_H 02h RTCCTL23 Real-TimeClockControl2,3 Read/write Word 0000h retained 02h RTCCTL2 Real-TimeClockControl2 Read/write Byte 00h retained orRTCCTL23_L 03h RTCCTL3 Real-TimeClockControl3 Read/write Byte 00h retained orRTCCTL23_H 08h RTCPS0CTL Real-TimePrescaleTimer0 Control Read/write Word 0000h notretained 08h RTCPS0CTLL Read/write Byte 00h notretained orRTCPS0CTL_L 09h RTCPS0CTLH Read/write Byte 00h notretained orRTCPS0CTL_H 0Ah RTCPS1CTL Real-TimePrescaleTimer1 Control Read/write Word 0000h notretained 0Ah RTCPS1CTLL Read/write Byte 00h notretained orRTCPS1CTL_L 0Bh RTCPS0CTLH Read/write Byte 00h notretained orRTCPS0CTL_H 0Ch RTCPS Real-TimePrescaleTimer0,1 Counter Read/write Word none retained 0Ch RT0PS Real-TimePrescaleTimer0 Counter Read/write Byte none retained orRTCPS_L 0Dh RT1PS Real-TimePrescaleTimer1 Counter Read/write Byte none retained orRTCPS_H 0Eh RTCIV RealTime ClockInterruptVector Read Word 0000h notretained 10h RTCTIM0 Real-TimeClockSeconds,Minutes Read/write Word undefined retained orRTCNT12 Real-TimeCounter1,2 10h RTCSEC Real-TimeClockSeconds Read/write Byte undefined retained RTCNT1 Real-TimeCounter1 orRTCTIM0_L 11h RTCMIN Real-TimeClockMinutes Read/write Byte undefined retained RTCNT2 Real-TimeCounter2 orRTCTIM0_H 457SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_D Registers www.ti.com Table16-1.RTC_D Registers(continued) Offset Acronym RegisterName Type Access Reset LPMx.5 or Backup 12h RTCTIM1 Real-TimeClockHour,Day ofWeek Read/write Word undefined retained orRTCNT34 Real-TimeCounter3,4 12h RTCHOUR Real-TimeClockHour Read/write Byte undefined retained RTCNT3 Real-TimeCounter3 orRTCTIM1_L 13h RTCDOW Real-TimeClockDay ofWeek Read/write Byte undefined retained RTCNT4 Real-TimeCounter4 orRTCTIM1_H 14h RTCDATE Real-TimeClockDate Read/write Word undefined retained 14h RTCDAY Real-TimeClockDay ofMonth Read/write Byte undefined retained orRTCDATE_L 15h RTCMON Real-TimeClockMonth Read/write Byte undefined retained orRTCDATE_H 16h RTCYEAR Real-TimeClockYear(1) Read/write Word undefined retained 18h RTCAMINHR Real-TimeClockMinutes,Hour Alarm Read/write Word undefined retained 18h RTCAMIN Real-TimeClockMinutesAlarm Read/write Byte undefined retained orRTCAMINHR_L 19h RTCAHOUR Real-TimeClockHours Alarm Read/write Byte undefined retained orRTCAMINHR_H 1Ah RTCADOWDAY Real-TimeClockDay ofWeek, Day of Read/write Word undefined retained Month Alarm 1Ah RTCADOW Real-TimeClockDay ofWeek Alarm Read/write Byte undefined retained or RTCADOWDAY_L 1Bh RTCADAY Real-TimeClockDay ofMonth Alarm Read/write Byte undefined retained or RTCADOWDAY_H 1Ch BIN2BCD Binary-to-BCDconversionregister Read/write Word 00h notretained 1Eh BCD2BIN BCD-to-binaryconversionregister Read/write Word 00h notretained (1) Do notaccesstheyearregisterRTCYEAR inbytemode.

458 Real-TimeClockD (RTC_D) SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com RTC_D Registers

16.3.1 RTCCTL0 Register

Real-TimeClockControl0 Register Figure16-2.RTCCTL0 Register 7 6 5 4 3 2 1 0 RTCOFIE (1) RTCTEVIE (1) RTCAIE (1) RTCRDYIE RTCOFIFG RTCTEVIFG RTCAIFG RTCRDYIFG rw-0 rw-0 rw-0 rw-0 rw-(0) rw-(0) rw-(0) rw-(0) (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. Table16-2.RTCCTL0 RegisterDescription Bit Field Type Reset Description 7 RTCOFIE RW 0h 32-kHzcrystaloscillatorfaultinterruptenable.Thisinterruptcan be used as LPMx.5 wake-up event. 0b = Interruptnotenabled 1b = Interruptenabled(LPMx.5wake-up enabled) 6 RTCTEVIE RW 0h Real-timeclocktimeeventinterruptenable.Inmodules supportingLPMx.5 this interruptcan be used as LPMx.5 wake-up event. 0b = Interruptnotenabled 1b = Interruptenabled(LPMx.5wake-up enabled) 5 RTCAIE RW 0h Real-timeclockalarminterruptenable.Inmodules supportingLPMx.5 this interruptcan be used as LPMx.5 wake-up event. 0b = Interruptnotenabled 1b = Interruptenabled(LPMx.5wake-up enabled) 4 RTCRDYIE RW 0h Real-timeclockreadyinterruptenable. 0b = Interruptnotenabled 1b = Interruptenabled 3 RTCOFIFG RW 0h 32-kHzcrystaloscillatorfaultinterruptflag.Thisinterruptcan be used as LPMx.5 wake-up event.Italsoindicatesa clockfailureduringbackup operation. 0b = No interruptpending 1b = Interruptpending.A 32-kHzcrystaloscillatorfaultoccurredafterlastreset. 2 RTCTEVIFG RW 0h Real-timeclocktimeeventinterruptflag.Inmodules supportingLPMx.5 this interruptcan be used as LPMx.5 wake-up event. 0b = No timeeventoccurred. 1b = Time eventoccurred. 1 RTCAIFG RW 0h Real-timeclockalarminterruptflag.Inmodules supportingLPMx.5 thisinterrupt can be used as LPMx.5 wake-up event. 0b = No timeeventoccurred. 1b = Time eventoccurred.

0 RTCRDYIFG RW 0h Real-timeclockreadyinterruptflag

0b = RTC cannotbe readsafely. 1b = RTC can be readsafely. 459SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.2 RTCCTL1 Register

Real-TimeClockControlRegister1 Figure16-3.RTCCTL1 Register 7 6 5 4 3 2 1 0 RTCBCD RTCHOLD (1) RTCMODE (1) RTCRDY RTCSSELx (1) RTCTEVx (1) rw-(0) rw-(1) rw-(1) r-(1) rw-(0) rw-(0) rw-(0) rw-(0) (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. Table16-3.RTCCTL1 RegisterDescription Bit Field Type Reset Description 7 RTCBCD RW 0h Real-timeclockBCD select.SelectsBCD countingforreal-timeclock.Appliesto calendarmode (RTCMODE = 1)only;settingisignoredincountermode. 0b = Binaryhexadecimalcode selected 1b = BCD Binarycoded decimal(BCD) code selected 0b = Real-timeclock(32-bitcounterorcalendarmode) isoperational. 1b = Incountermode (RTCMODE = 0),onlythe32-bitcounterisstopped.In calendarmode (RTCMODE = 1),thecalendarisstoppedas wellas theprescale counters,RT0PS and RT1PS. RT0PSHOLD and RT1PSHOLD aredon'tcare.

5 RTCMODE RW 1h Real-timeclockmode

0b = 32-bitcountermode 1b = Calendarmode. Switchingbetween counterand calendarmode does not resetthereal-timeclock/counterregisters.These registersmust be configuredby usersoftwarebeforeuse.

4 RTCRDY RW 1h Real-timeclockready

0b = RTC timevaluesintransition(calendarmode only). 1b = RTC timevaluessafeforreading(calendarmode only).Thisbitindicates when thereal-timeclocktimevaluesaresafeforreading(calendarmode only). Incountermode, RTCRDY remainscleared. 3-2 RTCSSELx RW 0h Real-timeclocksourceselect.Incountermode, selectsclockinputsourcetothe 32-bitcounter.Incalendarmode, thesebitsaredon'tcare.The clockinputis automaticallysettotheoutputofRT1PS. 00b = 32-kHzcrystaloscillatorclock 01b = 32-kHzcrystaloscillatorclock 10b = OutputfromRT1PS 11b = OutputfromRT1PS 1-0 RTCTEVx RW 0h Real-timeclocktimeevent.Specifiestheinterruptinterval. CalendarMode (RTCMODE = 1) 00b = Minutechanged 01b = Hour changed 10b = Everyday atmidnight(00:00) 11b = Everyday atnoon (12:00) CounterMode (RTCMODE = 0) 00b = 8-bitoverflow 01b = 16-bitoverflow 10b = 24-bitoverflow 11b = 32-bitoverflow

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16.3.3 RTCCTL2 Register

Real-TimeClockControl2 Register Figure16-4.RTCCTL2 Register 7 6 5 4 3 2 1 0 RTCCALS Reserved RTCCALx rw-(0) r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table16-4.RTCCTL2 RegisterDescription Bit Field Type Reset Description 0b = Frequencyadjusteddown 1b = Frequencyadjustedup 6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-0 RTCCALx RW 0h Real-timeclockcalibration.Each LSB representsapproximately+4-ppm (RTCCALS = 1)ora –2-ppm (RTCCALS = 0)adjustmentinfrequency.

16.3.4 RTCCTL3 Register

Real-TimeClockControl3 Register Figure16-5.RTCCTL3 Register 7 6 5 4 3 2 1 0 Reserved RTCCALFx r0 r0 r0 r0 r0 r0 rw-(0) rw-(0) Table16-5.RTCCTL3 RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1-0 RTCCALFx RW 0h Real-timeclockcalibrationfrequency.SelectsfrequencyoutputtoRTCCLK pin forcalibrationmeasurement.The correspondingportmust be configuredforthe peripheralmodule function.The RTCCLK isnotavailableincountermode and remainslow,and theRTCCALF bitsaredon'tcare. 00b = No frequencyoutputtoRTCCLK pin 01b = 512 Hz 10b = 256 Hz 11b = 1 Hz 461SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.5 RTCNT1 Register

Real-TimeClockCounter1 Register– CounterMode Figure16-6.RTCNT1 Register 7 6 5 4 3 2 1 0 RTCNT1 rw rw rw rw rw rw rw rw Table16-6.RTCNT1 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT1 RW undefined The RTCNT1 registeristhecountofRTCNT1

16.3.6 RTCNT2 Register

Real-TimeClockCounter2 Register– CounterMode Figure16-7.RTCNT2 Register 7 6 5 4 3 2 1 0 RTCNT2 rw rw rw rw rw rw rw rw Table16-7.RTCNT2 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT2 RW undefined The RTCNT2 registeristhecountofRTCNT2

16.3.7 RTCNT3 Register

Real-TimeClockCounter3 Register– CounterMode Figure16-8.RTCNT3 Register 7 6 5 4 3 2 1 0 RTCNT3 rw rw rw rw rw rw rw rw Table16-8.RTCNT3 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT3 RW undefined The RTCNT3 registeristhecountofRTCNT3

16.3.8 RTCNT4 Register

Real-TimeClockCounter4 Register– CounterMode Figure16-9.RTCNT4 Register 7 6 5 4 3 2 1 0 RTCNT4 rw rw rw rw rw rw rw rw Table16-9.RTCNT4 RegisterDescription Bit Field Type Reset Description 7-0 RTCNT4 RW undefined The RTCNT4 registeristhecountofRTCNT4.

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16.3.9 RTCSEC Register– Hexadecimal Format

Real-TimeClockSeconds Register– HexadecimalFormat Figure16-10.RTCSEC Register 7 6 5 4 3 2 1 0 Table16-10.RTCSEC RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Alwaysreadsas 0. 5-0 Seconds RW undefined Seconds (0to59)

16.3.10 RTCSEC Register– BCD Format

Real-TimeClockSeconds Register– BCD Format Figure16-11.RTCSEC Register 7 6 5 4 3 2 1 0 Table16-11.RTCSEC RegisterDescription Bit Field Type Reset Description 7 0 R 0h Alwaysreadsas 0. 6-4 Seconds – highdigit RW undefined Seconds – highdigit(0to5) 3-0 Seconds – lowdigit RW undefined Seconds – lowdigit(0to9) 463SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.11 RTCMIN Register– Hexadecimal Format

Real-TimeClockMinutesRegister– HexadecimalFormat Figure16-12.RTCMIN Register 7 6 5 4 3 2 1 0 Table16-12.RTCMIN RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Alwaysreadsas 0. 5-0 Minutes RW undefined Minutes(0to59)

16.3.12 RTCMIN Register– BCD Format

Real-TimeClockMinutesRegister– BCD Format Figure16-13.RTCMIN Register 7 6 5 4 3 2 1 0 Table16-13.RTCMIN RegisterDescription Bit Field Type Reset Description 7 0 R 0h Alwaysreadsas 0. 6-4 Minutes– highdigit RW undefined Minutes– highdigit(0to5) 3-0 Minutes– lowdigit RW undefined Minutes– lowdigit(0to9)

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16.3.13 RTCHOUR Register– Hexadecimal Format

Real-TimeClockHours Register– HexadecimalFormat Figure16-14.RTCHOUR Register 7 6 5 4 3 2 1 0 r-0 r-0 r-0 rw rw rw rw rw Table16-14.RTCHOUR RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Alwaysreadsas 0. 4-0 Hours RW undefined Hours (0to23)

16.3.14 RTCHOUR Register– BCD Format

Real-TimeClockHours Register– BCD Format Figure16-15.RTCHOUR Register 7 6 5 4 3 2 1 0 Table16-15.RTCHOUR RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h Alwaysreadsas 0. 5-4 Hours – highdigit RW undefined Hours – highdigit(0to2) 3-0 Hours – lowdigit RW undefined Hours – lowdigit(0to9) 465SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.15 RTCDOW Register– CalendarMode

Real-TimeClockDay ofWeek Register– CalendarMode Figure16-16.RTCDOW Register 7 6 5 4 3 2 1 0 r-0 r-0 r-0 r-0 r-0 rw rw rw Table16-16.RTCDOW RegisterDescription Bit Field Type Reset Description 7-3 0 R 0h Alwaysreadsas 0. 2-0 Day ofweek RW undefined Day ofweek (0to6)

16.3.16 RTCDAY Register– Hexadecimal Format

Real-TimeClockDay ofMonth Register– HexadecimalFormat Figure16-17.RTCDAY Register 7 6 5 4 3 2 1 0 r-0 r-0 r-0 rw rw rw rw rw Table16-17.RTCDAY RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Alwaysreadsas 0. 4-0 Day ofmonth RW undefined Day ofmonth (1to28,29,30,31)

16.3.17 RTCDAY Register– BCD Format

Real-TimeClockDay ofMonth Register– BCD Format Figure16-18.RTCDAY Register 7 6 5 4 3 2 1 0 Table16-18.RTCDAY RegisterDescription Bit Field Type Reset Description 7-6 0 R 0h 5-4 Day ofmonth – high RW undefined Day ofmonth – highdigit(0to3) digit 3-0 Day ofmonth – low RW undefined Day ofmonth – lowdigit(0to9) digit

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16.3.18 RTCMON Register– Hexadecimal Format

Real-TimeClockMonth Register– HexadecimalFormat Figure16-19.RTCMON Register 7 6 5 4 3 2 1 0 r-0 r-0 r-0 r-0 rw rw rw rw Table16-19.RTCMON RegisterDescription Bit Field Type Reset Description 7-4 0 R 0h Alwaysreadsas 0. 3-0 Month RW undefined Month (1to12)

16.3.19 RTCMON Register– BCD Format

Real-TimeClockMonth Register– BCD Format Figure16-20.RTCMON Register 7 6 5 4 3 2 1 0 r-0 r-0 r-0 rw rw rw rw rw Table16-20.RTCMON RegisterDescription Bit Field Type Reset Description 7-5 0 R 0h Alwaysreadsas 0. 3-0 Month – lowdigit RW undefined Month – lowdigit(0to9) 467SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.20 RTCYEAR Register– CalendarMode With Hexadecimal Format

Real-TimeClockYear Register– CalendarMode WithHexadecimalFormat Figure16-21.RTCYEAR Register 15 14 13 12 11 10 9 8 r-0 r-0 r-0 r-0 rw rw rw rw 7 6 5 4 3 2 1 0 Year – lowbyteof0 to4095 rw rw rw rw rw rw rw rw Table16-21.RTCYEAR RegisterDescription Bit Field Type Reset Description 15-12 0 R 0h Alwaysreadsas 0. 11-0 Year RW undefined Year (0to4095)

16.3.21 RTCYEAR Register– CalendarMode With BCD Format

Real-TimeClockYear Register– CalendarMode WithBCD Format Figure16-22.RTCYEAR Register 15 14 13 12 11 10 9 8 Decade Year – lowestdigit rw rw rw rw rw rw rw rw Table16-22.RTCYEAR RegisterDescription Bit Field Type Reset Description 15 0 R 0h Alwaysreadsas 0. 14-12 Century– lowdigit RW undefined Century– highdigit(0to4) 11-8 Century_Low RW undefined Century– lowdigit(0to9) 7-4 Decade RW undefined Decade (0to9) 3-0 Year – lowestdigit RW undefined Year – lowestdigit(0to9)

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16.3.22 RTCAMIN Register– Hexadecimal Format

Real-TimeClockMinutesAlarmRegister– HexadecimalFormat Figure16-23.RTCAMIN Register 7 6 5 4 3 2 1 0 AE 0 Minutes rw r-0 rw rw rw rw rw rw Table16-23.RTCAMIN RegisterDescription Bit Field Type Reset Description

7 AE RW undefined AE

6 0 R 0h Alwaysreadsas 0. 5-0 Minutes RW undefined Minutes(0to59)

16.3.23 RTCAMIN Register– BCD Format

Real-TimeClockMinutesAlarmRegister– BCD Format Figure16-24.RTCAMIN Register 7 6 5 4 3 2 1 0 AE Minutes– highdigit Minutes– lowdigit rw rw rw rw rw rw rw rw Table16-24.RTCAMIN RegisterDescription Bit Field Type Reset Description

7 AE RW 0h AE

6-4 Minutes– highdigit RW undefined Minutes– highdigit(0to5) 3-0 Minutes– lowdigit RW undefined Minutes– lowdigit(0to9) 469SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.24 RTCAHOUR Register– Hexadecimal Format

Real-TimeClockHours AlarmRegister– HexadecimalFormat Figure16-25.RTCAHOUR Register 7 6 5 4 3 2 1 0 AE 0 Hours rw r-0 r-0 rw rw rw rw rw Table16-25.RTCAHOUR RegisterDescription Bit Field Type Reset Description 6-5 0 R 0h Alwaysreadsas 0. 4-0 Hours RW undefined Hours (0to23)

16.3.25 RTCAHOUR Register– BCD Format

Real-TimeClockHours AlarmRegister– BCD Format Figure16-26.RTCAHOUR Register 7 6 5 4 3 2 1 0 AE 0 Hours – highdigit Hours – lowdigit rw r-0 rw rw rw rw rw rw Table16-26.RTCAHOUR RegisterDescription Bit Field Type Reset Description 6 0 R 0h Alwaysreadsas 0. 5-4 Hours – highdigit RW undefined Hours – highdigit(0to2) 3-0 Hours – lowdigit RW undefined Hours – lowdigit(0to9)

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16.3.26 RTCADOW Register

Real-TimeClockDay ofWeek AlarmRegister– CalendarMode Figure16-27.RTCADOW Register 7 6 5 4 3 2 1 0 AE 0 Day ofweek rw r-0 r-0 r-0 r-0 rw rw rw Table16-27.RTCADOW RegisterDescription Bit Field Type Reset Description 6-3 0 R 0h Alwaysreadsas 0. 2-0 Day ofweek RW undefined Day ofweek (0to6)

16.3.27 RTCADAY Register– Hexadecimal Format

Real-TimeClockDay ofMonth AlarmRegister– HexadecimalFormat Figure16-28.RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day ofmonth rw r-0 r-0 rw rw rw rw rw Table16-28.RTCADAY RegisterDescription Bit Field Type Reset Description 6-5 0 R 0h Alwaysreadsas 0. 4-0 Day ofmonth RW undefined Day ofmonth (1to28,29,30,31)

16.3.28 RTCADAY Register– BCD Format

Real-TimeClockDay ofMonth AlarmRegister– BCD Format Figure16-29.RTCADAY Register 7 6 5 4 3 2 1 0 AE 0 Day ofmonth – highdigit Day ofmonth – lowdigit rw r-0 rw rw rw rw rw rw Table16-29.RTCADAY RegisterDescription Bit Field Type Reset Description

7 AE RW undefined

5-4 Day ofmonth – high RW undefined Day ofmonth – highdigit(0to3) digit 3-0 Day ofmonth – low RW undefined Day ofmonth – lowdigit(0to9) digit 471SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.29 RTCPS0CTL Register

Real-TimeClockPrescaleTimer0 ControlRegister Figure16-30.RTCPS0CTL Register 15 14 13 12 11 10 9 8 Reserved RT0PSDIV (1) Reserved RT0PSHOLD (1) r0 r0 rw-(0) rw-(0) rw-(0) r0 r0 rw-(1) 7 6 5 4 3 2 1 0 Reserved RT0IP(1) RT0PSIE RT0PSIFG r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-0 rw-(0) (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. Table16-30.RTCPS0CTL RegisterDescription Bit Field Type Reset Description 15-14 Reserved R 0h Reserved.Alwaysreadsas 0. 13-11 RT0PSDIV RW 0h Prescaletimer0 clockdivide.These bitscontrolthedivideratiooftheRT0PS counter.Inreal-timeclockcalendarmode, thesebitsaredon'tcareforRT0PS and RT1PS. RT0PS clockoutputisautomaticallysetto/256.RT1PS clock outputisautomaticallysetto/128. 000b = Divideby 2 001b = Divideby 4 010b = Divideby 8 011b = Divideby 16 100b = Divideby 32 101b = Divideby 64 110b = Divideby 128 111b = Divideby 256 10-9 Reserved R 0h Reserved.Alwaysreadsas 0. 8 RT0PSHOLD RW 1h Prescaletimer0 hold.Inreal-timeclockcalendarmode, thisbitisdon'tcare. RT0PS isstoppedviatheRTCHOLD bit. 0b = RT0PS isoperational. 1b = RT0PS isheld. 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-2 RT0IP RW 0h Prescaletimer0 interruptinterval 000b = Divideby 2 001b = Divideby 4 010b = Divideby 8 011b = Divideby 16 100b = Divideby 32 101b = Divideby 64 110b = Divideby 128 111b = Divideby 256 0b = Interruptnotenabled 1b = Interruptenabled 0b = No timeeventoccurred. 1b = Time eventoccurred.

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16.3.30 RTCPS1CTL Register

Real-TimeClockPrescaleTimer1 ControlRegister Figure16-31.RTCPS1CTL Register 15 14 13 12 11 10 9 8 RT1SSELx (1) RT1PSDIVx (1) Reserved RT1PSHOLD (1) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r0 r0 rw-(1) 7 6 5 4 3 2 1 0 Reserved RT1IPx(1) RT1PSIE RT1PSIFG r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-0 rw-(0) (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. (1) The configurationofthesebitsisretainedduringLPMx.5 untilLOCKLPM5 iscleared,butnottheregisterbitsitself;therefore, reconfigurationafterwake-up fromLPMx.5 beforeclearingLOCKLPM5 isrequired. Table16-31.RTCPS1CTL RegisterDescription Bit Field Type Reset Description 15-14 RT1SSELx RW 0h Prescaletimer1 clocksourceselect.SelectsclockinputsourcetotheRT1PS counter.Inreal-timeclockcalendarmode, thesebitsaredo notcare.RT1PS clockinputisautomaticallysettotheoutputofRT0PS. 00b = 32-kHzcrystaloscillatorclock 01b = 32-kHzcrystaloscillatorclock 10b = OutputfromRT0PS 11b = OutputfromRT0PS 13-11 RT1PSDIVx RW 0h Prescaletimer1 clockdivide.These bitscontrolthedivideratiooftheRT0PS counter.Inreal-timeclockcalendarmode, thesebitsaredon'tcareforRT0PS and RT1PS. RT0PS clockoutputisautomaticallysetto/256.RT1PS clock outputisautomaticallysetto/128. 000b = Divideby 2 001b = Divideby 4 010b = Divideby 8 011b = Divideby 16 100b = Divideby 32 101b = Divideby 64 110b = Divideby 128 111b = Divideby 256 10-9 Reserved R 0h Reserved.Alwaysreadsas 0. 8 RT1PSHOLD RW 1h Prescaletimer1 hold.Inreal-timeclockcalendarmode, thisbitisdon'tcare. RT1PS isstoppedviatheRTCHOLD bit. 0b = RT1PS isoperational. 1b = RT1PS isheld. 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4-2 RT1IPx RW 0h Prescaletimer1 interruptinterval 000b = Divideby 2 001b = Divideby 4 010b = Divideby 8 011b = Divideby 16 100b = Divideby 32 101b = Divideby 64 110b = Divideby 128 111b = Divideby 256 0b = Interruptnotenabled 1b = Interruptenabled(LPMx.5wake-up enabled.) 473SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. RTC_D Registers www.ti.com Table16-31.RTCPS1CTL RegisterDescription(continued) Bit Field Type Reset Description 0 RT1PSIFG RW 0h Prescaletimer1 interruptflag.Thisinterruptcan be used as LPMx.5 wake-up event. 0b = No timeeventoccurred. 1b = Time eventoccurred.

16.3.31 RTCPS0 Register

Real-TimeClockPrescaleTimer0 CounterRegister Figure16-32.RTCPS0 Register 7 6 5 4 3 2 1 0 RT0PS rw rw rw rw rw rw rw rw Table16-32.RTCPS0 RegisterDescription Bit Field Type Reset Description 7-0 RT0PS RW undefined Prescaletimer0 countervalue

16.3.32 RTCPS1 Register

Real-TimeClockPrescaleTimer1 CounterRegister Figure16-33.RTCPS1 Register 7 6 5 4 3 2 1 0 RT1PS rw rw rw rw rw rw rw rw Table16-33.RTCPS1 RegisterDescription Bit Field Type Reset Description 7-0 RT1PS RW undefined Prescaletimer1 countervalue

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16.3.33 RTCIV Register

Real-TimeClockInterruptVectorRegister Figure16-34.RTCIV Register 15 14 13 12 11 10 9 8 RTCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 RTCIVx r0 r0 r0 r0 r-(0) r-(0) r-(0) r0 Table16-34.RTCIV RegisterDescription Bit Field Type Reset Description 15-0 RTCIVx R 0h Real-timeclockinterruptvectorvalue 00h = No interruptpending 02h = InterruptSource:RTC ready;InterruptFlag:RTCRDYIFG; Interrupt Priority:Highest 04h = InterruptSource:RTC intervaltimer;InterruptFlag:RTCTEVIFG 06h = InterruptSource:RTC useralarm;InterruptFlag:RTCAIFG 08h = InterruptSource:RTC prescaler0;InterruptFlag:RT0PSIFG 0Ah = InterruptSource:RTC prescaler1;InterruptFlag:RT1PSIFG 0Ch = InterruptSource:RTC oscillatorfailure;InterruptFlag:RTCOFIFG 0Eh = Reserved;InterruptPriority:Lowest 475SLAU259E –May 2009–RevisedJanuary2013 Real-TimeClockD (RTC_D) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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16.3.34 BIN2BCD Register

Binary-to-BCDConversionRegister Figure16-35.BIN2BCD Register 15 14 13 12 11 10 9 8 BIN2BCDx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 BIN2BCDx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table16-35.BIN2BCD RegisterDescription Bit Field Type Reset Description 15-0 BIN2BCDx RW 0h Read: 16-bitBCD conversionofpreviouslywritten12-bitbinarynumber Write:12-bitbinarynumber tobe converted

16.3.35 BCD2BIN Register

BCD-to-BinaryConversionRegister Figure16-36.BCD2BIN Register 15 14 13 12 11 10 9 8 BCD2BINx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 BCD2BINx rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table16-36.BCD2BIN RegisterDescription Bit Field Type Reset Description 15-0 BCD2BINx RW 0h Read: 12-bitbinaryconversionofpreviouslywritten16-bitBCD number Write:16-bitBCD number tobe converted

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter17 SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) Thischapterdescribesthe32-bithardwaremultiplier(MPY32).The MPY32 module isimplementedinall devices. 477SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. 32-BitHardware Multiplier(MPY32) Introduction www.ti.com 17.1 32-BitHardware Multiplier(MPY32) Introduction The MPY32 isa peripheraland isnotpartoftheCPU. Thismeans itsactivitiesdo notinterferewiththe CPU activities.The multiplierregistersareperipheralregistersthatareloadedand readwithCPU instructions. The MPY32 supports:

Unsignedmultiply
Signedmultiply
Unsignedmultiplyaccumulate
Signedmultiplyaccumulate
8-bit,16-bit,24-bit,and 32-bitoperands
Saturation
Fractionalnumbers
8-bitand 16-bitoperationcompatiblewith16-bithardwaremultiplier
8-bitand 24-bitmultiplicationswithoutrequiringa "signextend"instruction The MPY32 blockdiagramisshown inFigure17-1. 478 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

OP1 (high word) 16×16 Multiplier Accessible Register 32-bit Adder RES0/RESLO OP2 (high word) OP2 (low word) OP2 OP2LOP2HMACS32L MAC32L MPYS32L MPY32L MACS32H MAC32H MPYS32H MPY32H MACS MAC MPYS MPY RES1/RESHIRES2RES3SUMEXT 31 0151631 0 32-bit Demultiplexer 32-bit Multiplexer 16-bit Multiplexer 16-bit Multiplexer OP1_32 OP2_32 MPYMx MPYSAT MPYFRAC MPYC

2 Control

OP1 (low word) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com 32-BitHardware Multiplier(MPY32) Introduction Figure17-1.MPY32 Block Diagram 479SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com

17.2 MPY32 Operation

The MPY32 supports8-bit,16-bit,24-bit,and 32-bitoperandswithunsignedmultiply,signedmultiply, unsignedmultiply-accumulate,and signedmultiply-accumulateoperations.The sizeoftheoperandsare definedby theaddresstheoperandiswrittentoand ifitiswrittenas word orbyte.The typeofoperationis selectedby theaddressthefirstoperandiswrittento. The hardwaremultiplierhas two 32-bitoperandregisters– operandone (OP1) and operandtwo (OP2), and a 64-bitresultregisteraccessibleviaregistersRES0 toRES3. Forcompatibilitywiththe16×16 hardwaremultiplier,theresultofa 8-bitor16-bitoperationisaccessibleviaRESLO, RESHI, and SUMEXT, as well.RESLO storesthelowword ofthe16×16-bitresult,RESHI storesthehighword ofthe result,and SUMEXT storesinformationabouttheresult. The resultofa 8-bitor16-bitoperationisreadyinthreeMCLK cyclesand can be readwiththenext instructionafterwritingtoOP2, exceptwhen usingan indirectaddressingmode toaccesstheresult. When usingindirectaddressingfortheresult,a NOPisrequiredbeforetheresultisready. The resultofa 24-bitor32-bitoperationcan be readwithsuccessiveinstructionsafterwritingOP2 or OP2H startingwithRES0, exceptwhen usingan indirectaddressingmode toaccesstheresult.When usingindirectaddressingfortheresult,a NOPisrequiredbeforetheresultisready. Table17-1summarizeswhen each word ofthe64-bitresultisavailableforthevariouscombinationsof operandsizes.Witha 32-bit-widesecond operand,OP2L and OP2H must be written.Dependingon when thetwo 16-bitpartsarewritten,theresultavailabilitymay vary;thus,thetableshows two entries,one for OP2L writtenand one forOP2H written.The worstcase definestheactualresultavailability. Table17-1.ResultAvailability(MPYFRAC = 0,MPYSAT = 0) ResultReady inMCLK CyclesOperation After(OP1 × OP2) RES0 RES1 RES2 RES3 MPYC Bit 8/16× 8/16 3 3 4 4 3 OP2 written 24/32× 8/16 3 5 6 7 7 OP2 written 8/16× 24/32 3 5 6 7 7 OP2L written N/A 3 4 4 4 OP2H written 24/32× 24/32 3 8 10 11 11 OP2L written N/A 3 5 6 6 OP2H written 480 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation

17.2.1 Operand Registers

Operand one (OP1) has 12 registers(seeTable17-2)used toloaddataintothemultiplierand alsoselect themultiplymode. Writingthelowword ofthefirstoperandtoa givenaddressselectsthetypeofmultiply operationtobe performed,butdoes notstartany operation.When writinga second word toa high-word registerwithsuffix32H, themultiplierassumes a 32-bit-wideOP1, otherwise,16 bitsareassumed. The lastaddresswrittenpriortowritingOP2 definesthewidthofthefirstoperand.Forexample,ifMPY32L is writtenfirstfollowedby MPY32H, all32 bitsareused and thedatawidthofOP1 issetto32 bits.If MPY32H iswrittenfirstfollowedby MPY32L, themultiplicationignoresMPY32H and assumes a 16-bit- wideOP1 usingthedatawrittenintoMPY32L. Repeated multiplyoperationsmay be performedwithoutreloadingOP1 iftheOP1 valueisused for successiveoperations.ItisnotnecessarytorewritetheOP1 valuetoperformtheoperations. Table17-2.OP1 Registers OP1 Register Operation MPY Unsignedmultiply– operandbits0 up to15 MPYS Signedmultiply– operandbits0 up to15 MAC Unsignedmultiplyaccumulate–operandbits0 up to15 MACS Signedmultiplyaccumulate– operandbits0 up to15 MPY32L Unsignedmultiply– operandbits0 up to15 MPY32H Unsignedmultiply– operandbits16 up to31 MPYS32L Signedmultiply– operandbits0 up to15 MPYS32H Signedmultiply– operandbits16 up to31 MAC32L Unsignedmultiplyaccumulate– operandbits0 up to15 MAC32H Unsignedmultiplyaccumulate– operandbits16 up to31 MACS32L Signedmultiplyaccumulate– operandbits0 up to15 MACS32H Signedmultiplyaccumulate– operandbits16 up to31 Writingthesecond operandtotheOP2 initiatesthemultiplyoperation.WritingOP2 startstheselected operationwitha 16-bit-widesecond operandtogetherwiththevaluesstoredinOP1. WritingOP2L starts theselectedoperationwitha 32-bit-widesecond operandand themultiplierexpectsa thehighword tobe writtentoOP2H. WritingtoOP2H withouta precedingwritetoOP2L isignored. Table17-3.OP2 Registers OP2 Register Operation OP2 Startmultiplicationwith16-bit-wideOP2 – operandbits0 up to15 OP2L Startmultiplicationwith32-bit-wideOP2 – operandbits0 up to15 OP2H Continuemultiplicationwith32-bit-wideOP2 – operandbits16 up to31 For8-bitor24-bitoperands,theoperandregisterscan be accessedwithbyteinstructions.Accessingthe multiplierwitha byteinstructionduringa signedoperationautomaticallycausesa signextensionofthe bytewithinthemultipliermodule.For24-bitoperands,onlythehighword shouldbe writtenas byte.Ifthe 24-bitoperandsaresign-extendedas definedby theregister,thatisused towritethelowword to, because thisregisterdefinesiftheoperationisunsignedorsigned. The high-wordofa 32-bitoperandremainsunchanged when changingthesizeoftheoperandto16 bit, eitherby modifyingtheoperandsizebitsorby writingtotherespectiveoperandregister.Duringthe executionofthe16-bitoperation,thecontentofthehigh-wordisignored. 481SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com NOTE: Changing offirstor second operand duringmultiplication By default,changingOP1 orOP2 whiletheselectedmultiplyoperationisbeingcalculated rendersany resultsinvalidthatarenotreadyatthetimethenew operandsarechanged. WritingOP2 orOP2L abortsany ongoingcalculationand startsa new operation.Resultsthat arenotreadyatthattimearealsoinvalidforfollowingMAC orMACS operations. To avoidthisbehavior,theMPYDLYWRTEN bitcan be setto1.Then,allwritestoany MPY32 registersaredelayedwithMPYDLY32 = 0 untilthe64-bitresultisreadyorwith MPYDLY32 = 1 untilthe32-bitresultisready.ForMAC and MACS operations,thecomplete 64-bitresultshouldalwaysbe ready. See Table17-1forhow many CPU cyclesareneeded untila certainresultregisterisready and validforeach ofthedifferentmodes.

17.2.2 ResultRegisters

The multiplicationresultisalways64 bitswide.ItisaccessibleviaregistersRES0 toRES3. Used witha signedoperation,MPYS orMACS, theresultsareappropriatelysignextended.Iftheresultregistersare loadedwithinitialvaluesbeforea MACS operation,theusersoftwaremust takecarethatthewrittenvalue isproperlysignextendedto64 bits. NOTE: Changing ofresultregistersduringmultiplication The resultregistersmust notbe modifiedby theusersoftwareafterwritingthesecond operandintoOP2 orOP2L untiltheinitiatedoperationiscompleted. InadditiontoRES0 toRES3, forcompatibilitywiththe16×16 hardwaremultiplier,the32-bitresultofa 8- bitor16-bitoperationisaccessibleviaRESLO, RESHI, and SUMEXT. Inthiscase,theresultlowregister RESLO holdsthelower16 bitsofthecalculationresultand theresulthighregisterRESHI holdstheupper 16 bits.RES0 and RES1 areidenticaltoRESLO and RESHI, respectively,inusage and accessof calculatedresults. The sum extensionregisterSUMEXT contentsdepend on themultiplyoperationand arelistedin Table17-4.Ifalloperandsare16 bitswideorless,the32-bitresultisused todeterminesignand carry.If one oftheoperandsislargerthan16 bits,the64-bitresultisused. The MPYC bitreflectsthemultiplier'scarryas listedinTable17-4and,thus,can be used as 33rdor65th bitoftheresult,iffractionalorsaturationmode isnotselected.WithMAC orMACS operations,theMPYC bitreflectsthecarryofthe32-bitor64-bitaccumulationand isnottakenintoaccountforsuccessiveMAC and MACS operationsas the33rdor65thbit. Table17-4.SUMEXT and MPYC Contents Mode SUMEXT MPYC MPY SUMEXT isalways0000h. MPYC isalways0. MPYS SUMEXT containstheextendedsignoftheresult. MPYC containsthesignoftheresult. 00000h Resultwas positiveorzero 0 Resultwas positiveorzero 0FFFFh Resultwas negative 1 Resultwas negative MAC SUMEXT containsthecarryoftheresult. MPYC containsthecarryoftheresult. 0000h No carryforresult 0 No carryforresult 0001h Resulthas a carry 1 Resulthas a carry MACS SUMEXT containstheextendedsignoftheresult. MPYC containsthecarryoftheresult. 00000h Resultwas positiveorzero 0 No carryforresult 0FFFFh Resultwas negative 1 Resulthas a carry 482 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation 17.2.2.1MACS Underflow and Overflow The multiplierdoes notautomaticallydetectunderfloworoverflowinMACS mode. Forexample,working with16-bitinputdataand 32-bitresults(thatis,usingonlyRESLO and RESHI),theavailablerangefor positivenumbers is0 to07FFF FFFFh and fornegativenumbers is0FFFF FFFFh to08000 0000h.An underflowoccurswhen thesum oftwo negativenumbers yieldsa resultthatisintherangefora positive number.An overflowoccurswhen thesum oftwo positivenumbers yieldsa resultthatisintherangefora negativenumber. The SUMEXT registercontainsthesignoftheresultinbothcasesdescribedabove,0FFFFh fora 32-bit overflowand 0000h fora 32-bitunderflow.The MPYC bitinMPY32CTL0 can be used todetectthe overflowcondition.Ifthecarryisdifferentfromthesignreflectedby theSUMEXT register,an overflowor underflowoccurred.User softwaremust handletheseconditionsappropriately.

17.2.3 SoftwareExamples

Examples forallmultipliermodes follow.All8×8 modes use theabsoluteaddressfortheregisters, because theassemblerdoes notallow.Baccesstoword registerswhen usingthelabelsfromthe standarddefinitionsfile. Thereisno signextensionnecessaryinsoftware.Accessingthemultiplierwitha byteinstructionduringa signedoperationautomaticallycausesa signextensionofthebytewithinthemultipliermodule. ;32x32UnsignedMultiply MOV #01234h,&MPY32L;Loadlowwordof1stoperand MOV #01234h,&MPY32H;Loadhighwordof1stoperand MOV #05678h,&OP2L ;Loadlowwordof2ndoperand MOV #05678h,&OP2H ;Loadhighwordof2ndoperand ; ... ;Processresults ;16x16UnsignedMultiply MOV #01234h,&MPY ;Load1stoperand MOV #05678h,&OP2 ;Load2ndoperand ; ... ;Processresults ;8x8UnsignedMultiply.Absoluteaddressing. MOV.B#012h,&MPY_B ;Load1stoperand MOV.B#034h,&OP2_B ;Load2ndoperand ; ... ;Processresults ;32x32SignedMultiply MOV #01234h,&MPYS32L;Loadlowwordof1stoperand MOV #01234h,&MPYS32H;Loadhighwordof1stoperand MOV #05678h,&OP2L ;Loadlowwordof2ndoperand MOV #05678h,&OP2H ;Loadhighwordof2ndoperand ; ... ;Processresults ;16x16SignedMultiply MOV #01234h,&MPYS ;Load1stoperand MOV #05678h,&OP2 ;Load2ndoperand ; ... ;Processresults ;8x8SignedMultiply.Absoluteaddressing. MOV.B#012h,&MPYS_B;Load1stoperand MOV.B#034h,&OP2_B ;Load2ndoperand ; ... ;Processresults 483SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

16 ...1 14 bits S 1 16 ... Fractional part Radix point Sign bit 15 bits ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com

17.2.4 FractionalNumbers

The MPY32 providessupportforfixed-pointsignalprocessing.Infixed-pointsignalprocessing,fractional number arenumbers thathave a fixednumber ofdigitsafter(andsometimesalsobefore)theradixpoint. To classifydifferentrangesofbinaryfixed-pointnumbers,a Q-formatisused.DifferentQ-formats representdifferentlocationsoftheradixpoint.Figure17-2shows theformatofa signedQ15 number using16 bits.Everybitaftertheradixpointhas a resolutionof1/2,and themost significantbit(MSB) is used as thesignbit.The most negativenumber is08000h and themaximum positivenumber is07FFFh. Thisgivesa rangefrom–1.0to0.999969482≈ 1.0forthesignedQ15 formatwith16 bits. Figure17-2.Q15 Format Representation The rangecan be increasedby shiftingtheradixpointtotherightas shown inFigure17-3.The signed Q14 formatwith16 bitsgivesa rangefrom–2.0to1.999938965≈ 2.0. Figure17-3.Q14 Format Representation The benefitofusing16-bitsignedQ15 or32-bitsignedQ31 numbers withmultiplicationisthattheproduct oftwo number intherangefrom–1.0to1.0isalwaysinthatsame range. 17.2.4.1FractionalNumber Mode Multiplyingtwo fractionalnumbers usingthedefaultmultiplicationmode withMPYFRAC = 0 and MPYSAT = 0 givesa resultwithtwo signbits.Forexample,iftwo 16-bitQ15 numbers aremultiplied,a 32-bitresultinQ30 formatisobtained.To converttheresultintoQ15 formatmanually,thefirst15 trailing bitsand theextendedsignbitmust be removed.However,when thefractionalmode ofthemultiplieris used,theredundantsignbitisautomaticallyremoved,yieldinga resultinQ31 formatforthemultiplication oftwo 16-bitQ15 numbers.ReadingtheresultregisterRES1 givestheresultas 16-bitQ15 number.The 32-bitQ31 resultofa multiplicationoftwo 32-bitQ31 numbers isaccessedby readingregistersRES2 and RES3. The fractionalmode isenabledwithMPYFRAC = 1 inregisterMPY32CTL0. The actualcontentofthe resultregistersisnotmodifiedwhen MPYFRAC = 1.When theresultisaccessedusingsoftware,the valueisleftshiftedone bit,resultinginthefinalQ formattedresult.Thisallowsusersoftwaretoswitch between readingboththeshifted(fractional)and theunshiftedresult.The fractionalmode shouldonlybe enabledwhen requiredand disabledafteruse. Infractionalmode, theSUMEXT registercontainsthesignextendedbits32 and 33 oftheshiftedresultfor 16×16-bitoperationsand bits64 and 65 for32×32-bitoperations– notonlybits32 or64,respectively. 484 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation The MPYC bitisnotaffectedby thefractionalmode. Italwaysreadsthecarryofthenonfractionalresult. ;Exampleusing ;Fractional16x16multiplication BIS #MPYFRAC,&MPY32CTL0;Turnonfractionalmode MOV &FRACT1,&MPYS ;Load1stoperandasQ15 MOV &FRACT2,&OP2 ;Load2ndoperandasQ15 MOV &RES1,&PROD ;SaveresultasQ15 BIC #MPYFRAC,&MPY32CTL0;Backtonormalmode Table17-5.ResultAvailabilityinFractionalMode (MPYFRAC = 1,MPYSAT = 0) ResultReady inMCLK CyclesOperation After(OP1 × OP2) RES0 RES1 RES2 RES3 MPYC Bit 8/16× 8/16 3 3 4 4 3 OP2 written 24/32× 8/16 3 5 6 7 7 OP2 written 8/16× 24/32 3 5 6 7 7 OP2L written N/A 3 4 4 4 OP2H written 24/32× 24/32 3 8 10 11 11 OP2L written N/A 3 5 6 6 OP2H written 17.2.4.2SaturationMode The multiplierpreventsoverflowand underflowofsignedoperationsinsaturationmode. The saturation mode isenabledwithMPYSAT = 1 inregisterMPY32CTL0. Ifan overflowoccurs,theresultissettothe most-positivevalueavailable.Ifan underflowoccurs,theresultissettothemost-negativevalueavailable. Thisisusefultoreducemathematicalartifactsincontrolsystemson overflowand underflowconditions. The saturationmode shouldonlybe enabledwhen requiredand disabledafteruse. The actualcontentoftheresultregistersisnotmodifiedwhen MPYSAT = 1.When theresultisaccessed usingsoftware,thevalueisautomaticallyadjustedtoprovidethemost-positiveormost-negativeresult when an overfloworunderflowhas occurred.The adjustedresultisalsoused forsuccessivemultiply-and- accumulateoperations.Thisallowsusersoftwaretoswitchbetween readingthesaturatedand the nonsaturatedresult. With16×16 operations,thesaturationmode onlyappliestotheleastsignificant32 bits;thatis,theresult registersRES0 and RES1. Usingthesaturationmode inMAC orMACS operationsthatmix 16×16 operationswith32×32,16×32,or32×16 operationsleadstounpredictableresults. With32×32,16×32,and 32×16 operations,thesaturatedresultcan onlybe calculatedwhen RES3 is ready. Enablingthesaturationmode does notaffectthecontentoftheSUMEXT registernorthecontentofthe MPYC bit. ;Exampleusing ;Fractional16x16multiplyaccumulatewithSaturation ;Turnonfractionalandsaturationmode: BIS #MPYSAT+MPYFRAC,&MPY32CTL0 MOV &A1,&MPYS ;LoadA1for1stterm MOV &K1,&OP2 ;LoadK1togetA1*K1 MOV &A2,&MACS ;LoadA2for2ndterm MOV &K2,&OP2 ;LoadK2togetA2*K2 MOV &RES1,&PROD ;SaveA1*K1+A2*K2asresult BIC #MPYSAT+MPYFRAC,&MPY32CTL0;turnbacktonormal 485SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Overflow: RES3 unchanged RES2 unchanged RES1 = 07FFFh RES0 = 0FFFFh Yes No Underflow: RES3 unchanged RES2 unchanged RES1 = 08000h RES0 = 00000h Yes No No Yes Overflow: RES3 unchanged RES2 unchanged RES1 = 07FFFh RES0 = 0FFFFh Yes No Yes No 32-bit Saturation completed Yes No Yes No No Yes Yes No Yes No Underflow: RES3 unchanged RES2 unchanged RES1 = 08000h RES0 = 00000h Overflow: RES3 = 07FFFh RES2 = 0FFFFh RES1 = 0FFFFh RES0 = 0FFFFh Underflow: RES3 = 08000h RES2 = 00000h RES1 = 00000h RES0 = 00000h Overflow: RES3 = 07FFFh RES2 = 0FFFFh RES1 = 0FFFFh RES0 = 0FFFFh Underflow: RES3 = 08000h RES2 = 00000h RES1 = 00000h RES0 = 00000h 64-bit Saturation completed 32-bit Saturation MPYC=0 and unshifted RES3, bit15=1 MPYC=1 and unshifted RES3, bit15=0 MPYFRAC=1 Unshifted RES3, bit 15=0 and bit 14=1 Unshifted RES3, bit 15=1 and bit 14=0 MPYC=0 and unshifted RES1, bit15=1 MPYC=1 and unshifted RES1, bit15=0 MPYFRAC=1 Unshifted RES1, bit 15=0 and bit 14=1 Unshifted RES1, bit 15=1 and bit 14=0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com Table17-6.ResultAvailabilityinSaturationMode (MPYSAT = 1) ResultReady inMCLK CyclesOperation After(OP1 × OP2) RES0 RES1 RES2 RES3 MPYC Bit 8/16× 8/16 3 3 N/A N/A 3 OP2 written 24/32× 8/16 7 7 7 7 7 OP2 written 8/16× 24/32 7 7 7 7 7 OP2L written 4 4 4 4 4 OP2H written 24/32× 24/32 11 11 11 11 11 OP2L written 6 6 6 6 6 OP2H written Figure17-4shows theflowfor32-bitsaturationused for16×16 bitmultiplicationsand theflowfor64-bit saturationused inallothercases.Primarily,thesaturatedresultsdepends on thecarrybitMPYC and the MSB oftheresult.Secondly,ifthefractionalmode isenabled,itdepends alsoon thetwo MSBs ofthe unshiftresult,thatis,theresultthatisreadwithfractionalmode disabled. Figure17-4.SaturationFlow Chart 486 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation NOTE: Saturationinfractionalmode Incase ofmultiplying–1.0× –1.0infractionalmode, theresultof+1.0isoutofrange,thus, thesaturatedresultgivesthemost positiveresult. When usingmultiply-and-accumulateoperations,theaccumulatedvaluesaresaturatedas if MPYFRAC = 0;onlyduringreadaccessestotheresultregistersthevaluesaresaturated takingthefractionalmode intoaccount.Thisprovidesadditionaldynamicrangeduringthe calculationand onlytheend resultisthensaturatedifneeded. The followingexample illustratesa specialcase showingthesaturationfunctioninfractionalmode. Italso uses the8-bitfunctionalityoftheMPY32 module. ;Turnonfractionalandsaturationmode, ;clearallotherbitsinMPY32CTL0: MOV #MPYSAT+MPYFRAC,&MPY32CTL0 ;Pre-loadresultregisterstodemonstrateoverflow MOV #0,&RES3 ; MOV #0,&RES2 ; MOV #07FFFh,&RES1 ; MOV #0FA60h,&RES0 ; MOV.B#050h,&MACS_B;8-bitsignedMACoperation MOV.B#012h,&OP2_B ;Start16x16bitoperation MOV &RES0,R6 ;R6=0FFFFh MOV &RES1,R7 ;R7=07FFFh The resultissaturatedbecause alreadytheresultnotconvertedintoa fractionalnumber shows an overflow.The multiplicationofthetwo positivenumbers 00050h and 00012h gives005A0h.005A0h added to07FFF FA60h resultsin8000 059Fh,withoutMPYC beingset.Because theMSB oftheunmodified resultRES1 is1 and MPYC = 0,theresultissaturatedaccordingFigure17-4. NOTE: Validityofsaturatedresult The saturatedresultisvalidonlyiftheregistersRES0 toRES3, thesizeofOP1 and OP2, and MPYC arenotmodified. Ifthesaturationmode isused witha preloadedresult,usersoftwaremust ensurethatMPYC intheMPY32CTL0 registerisloadedwiththesignbitofthewrittenresult;otherwise,the saturationmode erroneouslysaturatestheresult.

17.2.5 PuttingItAllTogether

Figure17-5shows thecompletemultiplicationflow,dependingon thevariousselectablemodes forthe MPY32 module. 487SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

New□Multiplication Started 16×16 MAC□or□MACS MPYSAT=1 Clear□Result: RES1□=□00000h RES0□=□00000h Perform□16×16 MPY or□MPYS Operation Yes No YesNo Yes No MPYFRAC=1 non-fractional 32-bit□Saturation Shift 64bit□result . Calculate□SUMEXT based□on MPYC□and□bit15 of unshifted RES1. MPYSA T=1 Yes No Yes No Multiplication completed MPYSAT=1 ? Clear□Result : RES3 = 00000h RES2 = 00000h RES1 = 00000h RES0 = 00000h Yes No Yes No MPYFRAC=1 non-fractional 64-bit□Saturation MPYSA T=1 Yes No Yes No Shift 64bit□result . Calculate□SUMEXT based□on MPYC□and□bit15 of unshifted RES3. Perform□16×16 MAC□or□MACS Operation Perform MAC□or□MACS Operation Perform MPY or□MPYS Operation MAC□or□MACS 32-bit□Saturation 64-bit□Saturation ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com Figure17-5.MultiplicationFlow Chart 488 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation Giventheseparationinprocessingof16-bitoperations(32-bitresults)and 32-bitoperations(64-bit results)by themodule,itisimportanttounderstandtheimplicationswhen usingMAC/MACS operations and mixing16-bitoperandsorresultswith32-bitoperandsorresults.User softwaremust addressthese pointsduringuse when mixingtheseoperations.The followingcode illustratestheissue. ;Mixing32x24multiplicationwith16x16MACSoperation MOV #MPYSAT,&MPY32CTL0;Saturationmode MOV #052C5h,&MPY32L;Loadlowwordof1stoperand MOV #06153h,&MPY32H;Loadhighwordof1stoperand MOV #001ABh,&OP2L ;Loadlowwordof2ndoperand MOV.B#023h,&OP2H_B ;Loadhighwordof2ndoperand ;...5NOPsrequired MOV &RES0,R6 ;R6=00E97h MOV &RES1,R7 ;R7=0A6EAh MOV &RES2,R8 ;R8=04F06h MOV &RES3,R9 ;R9=0000Dh ;NotethatMPYC=0! MOV #0CCC3h,&MACS ;SignedMACoperation MOV #0FFB6h,&OP2 ;16x16bitoperation MOV &RESLO,R6 ;R6=0FFFFh MOV &RESHI,R7 ;R7=07FFFh The second operationgivesa saturatedresultbecause the32-bitvalueused forthe16×16-bitMACS operationwas alreadysaturatedwhen theoperationwas started;thecarrybitMPYC was 0 fromthe previousoperation,buttheMSB inresultregisterRES1 isset.As one can see intheflowchart,the contentoftheresultregistersaresaturatedformultiply-and-accumulateoperationsafterstartinga new operationbased on thepreviousresults,butdependingon thesizeoftheresult(32bitor64 bit)ofthe newlyinitiatedoperation. The saturationbeforethemultiplicationcan cause issuesiftheMPYC bitisnotproperlysetas the followingcode shows. ;Pre-loadresultregisterstodemonstrateoverflow MOV #0,&RES3 ; MOV #0,&RES2 ; MOV #0,&RES1 ; MOV #0,&RES0 ; ;SaturationmodeandsetMPYC: MOV #MPYSAT+MPYC,&MPY32CTL0 MOV.B#082h,&MACS_B;8-bitsignedMACoperation MOV.B#04Fh,&OP2_B ;Start16x16bitoperation MOV &RES0,R6 ;R6=00000h MOV &RES1,R7 ;R7=08000h Even thoughtheresultregisterswere loadedwithallzeros,thefinalresultissaturated.Thisisbecause theMPYC bitwas set,causingtheresultused forthemultiply-and-accumulatetobe saturatedto 08000 0000h.Addinga negativenumber toitwouldagaincause an underflow,thus,thefinalresultisalso saturatedto08000 0000h. 489SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. MPY32 Operation www.ti.com

17.2.6 IndirectAddressing ofResultRegisters

When usingindirectorindirectautoincrementaddressingmode toaccesstheresultregistersand the multiplierrequiresthreecyclesuntilresultavailabilityaccordingtoTable17-1,atleastone instructionis needed between loadingthesecond operandand accessingtheresultregisters: ;Accessmultiplier16x16resultswithindirectaddressing MOV #RES0,R5 ;RES0addressinR5forindirect MOV &OPER1,&MPY ;Load1stoperand MOV &OPER2,&OP2 ;Load2ndoperand NOP ;Needonecycle MOV @R5+,&xxx ;MoveRES0 MOV @R5,&xxx ;MoveRES1 Incase ofa 32×16 multiplication,thereisalsoone instructionrequiredbetween readingthefirstresult registerRES0 and thesecond resultregisterRES1: ;Accessmultiplier32x16resultswithindirectaddressing MOV#RES0,R5 ;RES0addressinR5forindirect MOV&OPER1L,&MPY32L;Loadlowwordof1stoperand MOV&OPER1H,&MPY32H;Loadhighwordof1stoperand MOV&OPER2,&OP2 ;Load2ndoperand(16bits) NOP ;Needonecycle MOV@R5+,&xxx ;MoveRES0 NOP ;Needoneadditionalcycle MOV@R5,&xxx ;MoveRES1 ;Noadditionalcyclesrequired! MOV@R5,&xxx ;MoveRES2

17.2.7 Using Interrupts

Ifan interruptoccursafterwritingOP, butbeforewritingOP2, and themultiplierisused inservicingthat interrupt,theoriginalmultipliermode selectionislostand theresultsareunpredictable.To avoidthis, disableinterruptsbeforeusingtheMPY32, do notuse theMPY32 ininterruptserviceroutines,oruse the save and restorefunctionalityoftheMPY32. ;Disableinterruptsbeforeusingthehardwaremultiplier DINT ;Disableinterrupts NOP ;RequiredforDINT MOV #xxh,&MPY ;Load1stoperand MOV #xxh,&OP2 ;Load2ndoperand EINT ;Interruptsmaybeenabledbefore ;processingresultsifresult ;registersarestoredandrestoredin ;interruptserviceroutines 490 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Operation 17.2.7.1Save and Restore Ifthemultiplierisused ininterruptserviceroutines,itsstatecan be saved and restoredusingthe MPY32CTL0 register.The followingcode example shows how thecompletemultiplierstatuscan be saved and restoredtoallowinterruptiblemultiplicationstogetherwiththeusage ofthemultiplierininterrupt serviceroutines.Because thestateoftheMPYSAT and MPYFRAC bitsareunknown,theyshouldbe clearedbeforetheregistersaresaved as shown inthecode example. ;Interruptserviceroutineusingmultiplier MPY_USING_ISR PUSH&MPY32CTL0;Savemultipliermode,etc. BIC #MPYSAT+MPYFRAC,&MPY32CTL0 ;ClearMPYSAT+MPYFRAC PUSH&RES3 ;Saveresult3 PUSH&RES2 ;Saveresult2 PUSH&RES1 ;Saveresult1 PUSH&RES0 ;Saveresult0 PUSH&MPY32H ;Saveoperand1,highword PUSH&MPY32L ;Saveoperand1,lowword PUSH&OP2H ;Saveoperand2,highword PUSH&OP2L ;Saveoperand2,lowword ... ;MainpartofISR ;UsingstandardMPYroutines POP &OP2L ;Restoreoperand2,lowword POP &OP2H ;Restoreoperand2,highword ;Startsdummymultiplicationbut ;resultisoverwrittenby ;followingrestoreoperations: POP &MPY32L ;Restoreoperand1,lowword POP &MPY32H ;Restoreoperand1,highword POP &RES0 ;Restoreresult0 POP &RES1 ;Restoreresult1 POP &RES2 ;Restoreresult2 POP &RES3 ;Restoreresult3 POP &MPY32CTL0;Restoremultipliermode,etc. reti ;Endofinterruptserviceroutine

17.2.8 Using DMA

Indeviceswitha DMA controller,themultipliercan triggera transferwhen thecompleteresultisavailable. The DMA controllerneeds tostartreadingtheresultwithMPY32RES0 successivelyup toMPY32RES3. Not allregistersneed tobe read.The triggertimingissuch thattheDMA controllerstartsreading MPY32RES0 when itsready,and thattheMPY32RES3 can be readexactlyintheclockcyclewhen itis availabletoallowfastestaccessviaDMA. The signalintotheDMA controlleris'Multiplierready'(seethe DMA Controllerchapterfordetails). 491SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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17.3 MPY32 Registers

MPY32 registersarelistedinTable17-7.The base addresscan be foundinthedevice-specificdata sheet.The addressoffsetsarelistedinTable17-7. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table17-7.MPY32 Registers Offset Acronym RegisterName Type Access Reset 00h MPY 16-bitoperandone – multiply Read/write Word Undefined 00h MPY_L Read/write Byte Undefined 01h MPY_H Read/write Byte Undefined 00h MPY_B 8-bitoperandone – multiply Read/write Byte Undefined 02h MPYS 16-bitoperandone – signedmultiply Read/write Word Undefined 02h MPYS_L Read/write Byte Undefined 03h MPYS_H Read/write Byte Undefined 02h MPYS_B 8-bitoperandone – signedmultiply Read/write Byte Undefined 04h MAC 16-bitoperandone – multiplyaccumulate Read/write Word Undefined 04h MAC_L Read/write Byte Undefined 05h MAC_H Read/write Byte Undefined 04h MAC_B 8-bitoperandone – multiplyaccumulate Read/write Byte Undefined 06h MACS 16-bitoperandone – signedmultiplyaccumulate Read/write Word Undefined 06h MACS_L Read/write Byte Undefined 07h MACS_H Read/write Byte Undefined 06h MACS_B 8-bitoperandone – signedmultiplyaccumulate Read/write Byte Undefined 08h OP2 16-bitoperandtwo Read/write Word Undefined 08h OP2_L Read/write Byte Undefined 09h OP2_H Read/write Byte Undefined 08h OP2_B 8-bitoperandtwo Read/write Byte Undefined 0Ah RESLO 16x16-bitresultlowword Read/write Word Undefined 0Ah RESLO_L Read/write Byte Undefined 0Ch RESHI 16x16-bitresulthighword Read/write Word Undefined 0Eh SUMEXT 16x16-bitsum extensionregister Read Word Undefined 10h MPY32L 32-bitoperand1 – multiply– lowword Read/write Word Undefined 10h MPY32L_L Read/write Byte Undefined 11h MPY32L_H Read/write Byte Undefined 12h MPY32H 32-bitoperand1 – multiply– highword Read/write Word Undefined 12h MPY32H_L Read/write Byte Undefined 13h MPY32H_H Read/write Byte Undefined 12h MPY32H_B 24-bitoperand1 – multiply– highbyte Read/write Byte Undefined 14h MPYS32L 32-bitoperand1 – signedmultiply– lowword Read/write Word Undefined 14h MPYS32L_L Read/write Byte Undefined 15h MPYS32L_H Read/write Byte Undefined 16h MPYS32H 32-bitoperand1 – signedmultiply– highword Read/write Word Undefined 16h MPYS32H_L Read/write Byte Undefined 17h MPYS32H_H Read/write Byte Undefined 16h MPYS32H_B 24-bitoperand1 – signedmultiply– highbyte Read/write Byte Undefined 18h MAC32L 32-bitoperand1 – multiplyaccumulate– lowword Read/write Word Undefined 492 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com MPY32 Registers Table17-7.MPY32 Registers(continued) Offset Acronym RegisterName Type Access Reset 18h MAC32L_L Read/write Byte Undefined 19h MAC32L_H Read/write Byte Undefined 1Ah MAC32H 32-bitoperand1 – multiplyaccumulate– highword Read/write Word Undefined 1Ah MAC32H_L Read/write Byte Undefined 1Bh MAC32H_H Read/write Byte Undefined 1Ah MAC32H_B 24-bitoperand1 – multiplyaccumulate– highbyte Read/write Byte Undefined 1Ch MACS32L 32-bitoperand1 – signedmultiplyaccumulate– lowword Read/write Word Undefined 1Ch MACS32L_L Read/write Byte Undefined 1Dh MACS32L_H Read/write Byte Undefined 1Eh MACS32H 32-bitoperand1 – signedmultiplyaccumulate– highword Read/write Word Undefined 1Eh MACS32H_L Read/write Byte Undefined 1Fh MACS32H_H Read/write Byte Undefined 1Eh MACS32H_B 24-bitoperand1 – signedmultiplyaccumulate– highbyte Read/write Byte Undefined 20h OP2L 32-bitoperand2 – lowword Read/write Word Undefined 20h OP2L_L Read/write Byte Undefined 21h OP2L_H Read/write Byte Undefined 22h OP2H 32-bitoperand2 – highword Read/write Word Undefined 22h OP2H_L Read/write Byte Undefined 23h OP2H_H Read/write Byte Undefined 22h OP2H_B 24-bitoperand2 – highbyte Read/write Byte Undefined 24h RES0 32x32-bitresult0 – leastsignificantword Read/write Word Undefined 24h RES0_L Read/write Byte Undefined 26h RES1 32x32-bitresult1 Read/write Word Undefined 28h RES2 32x32-bitresult2 Read/write Word Undefined 2Ah RES3 32x32-bitresult3 – most significantword Read/write Word Undefined 2Ch MPY32CTL0 MPY32 controlregister0 Read/write Word Undefined 2Ch MPY32CTL0_L Read/write Byte Undefined 2Dh MPY32CTL0_H Read/write Byte 00h The registerslistedinTable17-8aretreatedequally. Table17-8.AlternativeRegisters Register Alternative1 Alternative2 16-bitoperandone – multiply MPY MPY32L 8-bitoperandone – multiply MPY_B orMPY_L MPY32L_B orMPY32L_L 16-bitoperandone – signedmultiply MPYS MPYS32L 8-bitoperandone – signedmultiply MPYS_B orMPYS_L MPYS32L_B orMPYS32L_L 16-bitoperandone – multiplyaccumulate MAC MAC32L 8-bitoperandone – multiplyaccumulate MAC_B orMAC_L MAC32L_B orMAC32L_L 16-bitoperandone – signedmultiplyaccumulate MACS MACS32L 8-bitoperandone – signedmultiplyaccumulate MACS_B orMACS_L MACS32L_B orMACS32L_L 16x16-bitresultlowword RESLO RES0 16x16-bitresulthighword RESHI RES1 493SLAU259E –May 2009–RevisedJanuary2013 32-BitHardware Multiplier(MPY32) SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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17.3.1 MPY32CTL0 Register

32-BitHardware MultiplierControl0 Register Figure17-6.MPY32CTL0 Register 15 14 13 12 11 10 9 8 Reserved MPYDLY32 MPYDLYWRTE N r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 7 6 5 4 3 2 1 0 MPYOP2_32 MPYOP1_32 MPYMx MPYSAT MPYFRAC Reserved MPYC rw rw rw rw rw-0 rw-0 rw-0 rw Table17-9.MPY32CTL0 RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0.

9 MPYDLY32 RW 0h Delayedwritemode

0b = Writesaredelayeduntil64-bitresult(RES0 toRES3) isavailable. 1b = Writesaredelayeduntil32-bitresult(RES0 toRES1) isavailable.

8 MPYDLYWRTEN RW 0h Delayedwriteenable

Allwritestoany MPY32 registeraredelayeduntilthe64-bit(MPYDLY32 = 0)or 32-bit(MPYDLY32 = 1)resultisready. 0b = Writesarenotdelayed. 1b = Writesaredelayed.

7 MPYOP2_32 RW 0h Multiplierbitwidthofoperand2

0b = 16 bits 1b = 32 bits

6 MPYOP1_32 RW 0h Multiplierbitwidthofoperand1

0b = 16 bits 1b = 32 bits 5-4 MPYMx RW 0h Multipliermode 00b = MPY – Multiply 01b = MPYS – Signedmultiply 10b = MAC – Multiplyaccumulate 11b = MACS – Signedmultiplyaccumulate

3 MPYSAT RW 0h Saturationmode

0b = Saturationmode disabled 1b = Saturationmode enabled

2 MPYFRAC RW 0h Fractionalmode

0b = Fractionalmode disabled 1b = Fractionalmode enabled 1 Reserved RW 0h Reserved.Alwaysreadsas 0. 0 MPYC RW 0h Carryofthemultiplier.Itcan be consideredas 33rdor65thbitoftheresultif fractionalorsaturationmode isnotselected,because theMPYC bitdoes not change when switchingtosaturationorfractionalmode. Itisused torestoretheSUMEXT contentinMAC mode. 0b = No carryforresult 1b = Resulthas a carry 494 32-BitHardware Multiplier(MPY32) SLAU259E –May 2009–RevisedJanuary2013 SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter18 SLAU259E –May 2009–RevisedJanuary2013 REF The REF module isa generalpurpose referencesystem thatisused to generatevoltagereferences requiredforothersubsystemsavailableon a givendevicesuch as digital-to-analogconverters,analog-to- digitalconverters,comparators,etc.ThischapterdescribestheREF module. 495SLAU259E –May 2009–RevisedJanuary2013 REF SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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18.1 REF Introduction

The referencemodule (REF) isresponsibleforgenerationofallcriticalreferencevoltagesthatcan be used by variousanalogperipheralsina givendevice.These include,butarenotnecessarilylimitedto,the ADC10_A, ADC12_A, DAC12_A, LCD_B, and COMP_B modules dependentupon theparticulardevice. The heartofthereferencesystemisthebandgap fromwhichallotherreferencesarederivedby unityor non-invertinggainstages.The REFGEN subsystemconsistsofthebandgap,thebandgap bias,and the non-invertingbufferstagewhichgeneratesthethreeprimaryvoltagereferenceavailableinthesystem, FeaturesoftheREF include:

Centralized,factorytrimmedbandgap withexcellentPSRR, temperaturecoefficient,and accuracy
1.5-V,2.0-V,or2.5-Vuserselectableinternalreferences
Bufferedbandgap voltageavailabletorestofsystem
Power savingfeatures
Backward compatibilitytoexistingreferencesystem The blockdiagramoftheREF module (exampleofa devicewithADC12_A) isshown inFigure18-1. DeviceswithADC10_A mightnotincludethereferencevoltageoutputtotheexternalpad.Pleasereferto thedevice-specificdatasheet.

496 REF SLAU259E –May 2009–RevisedJanuary2013

1.5/2.0/2.5V To external pad To ADC12_A capacitor array COMP_B0 REFGEN Variable Reference ADC12_A DAC12OG DAC12_A Channel 0 DAC12OG DAC12_A Channel 1 To DAC12 To DAC12 From REFGEN From REFGEN Switch Mux Bandgap Reference Local Buffer COMP_B1 Local Buffer Vref/2 Vref/3 Vref REFMODEREQ BIAS REFBGREQ REFGENREQ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com REF Introduction Figure18-1.REF Block Diagram 497SLAU259E –May 2009–RevisedJanuary2013 REF SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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18.2 PrincipleofOperation

The REF module providesallthenecessaryvoltagereferencestobe used by variousperipheralmodules throughoutthesystem.These may include,butarenotlimitedto,devicesthatcontainan ADC10_A, ADC12_A, DAC12_A, LCD_B, orCOMP_B. The REFGEN subsystemcontainsa high-performancebandgap.Thisbandgap has verygood accuracy (factorytrimmed),lowtemperaturecoefficient,and highPSRR whileoperatingatlowpower.The bandgap voltageisused togeneratethreevoltagesviaa non-invertingamplifierstage,namely 1.5V,2.0V,and 2.5V.One voltagecan be selectedata time.One outputoftheREFGEN subsystemisthevariable A second outputoftheREFGEN subsystemprovidesa bufferedbandgap referencelinethatcan alsobe used by modules throughoutthesystem.Additionally,theREFGEN supportsvoltagereferencesrequired fortheDAC12_A module,when available.Lastly,theREFGEN subsystemalsoincludesthetemperature sensorcircuitry,because itisderivedfromthebandgap.The temperaturesensorisused by an ADC to measure a voltageproportionaltotemperature.

18.2.1 Low-Power Operation

The REF module iscapableofsupportinglow-powerapplicationssuch as LCD generation.Many ofthese applicationsdo notrequirea veryaccuratereference,compared todataconversion,yetpower isofprime concern.To supportthesekindsofapplications,thebandgap iscapableofbeingused ina sampled mode. Insampled mode, thebandgap circuitryisclockedviatheVLO atan appropriatedutycycle.This reducestheaveragepower ofthebandgap circuitrysignificantly,atthecostofaccuracy.When notin sampled mode, thebandgap isinstaticmode. Itspower isatitshighest,butso isitsaccuracy. Modules automaticallycan requeststaticmode orsampled mode viatheirown individualrequestlines.In thisway,theparticularmodule determineswhat mode isappropriateforitsproperoperationand performance.Any one activemodule thatrequestsstaticmode causesallothermodules touse static mode, even ifanothermodule isrequestingsampled mode. Inotherwords,staticmode alwayshas higher prioritythansampled mode.

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18.2.2 REFCTL

The REFCTL registersprovidea way tocontrolthereferencesystemfromone centralizedsetofregisters. By default,REFCTL isused as theprimarycontrolofthereferencesystem. 18.2.2.1REFMSTR = 1 Thismode isimplementedinalldeviceswithADC10_A. AlsoallADC12_A devicesexceptfor MSP430F5438 and MSP430F5438A supportthismode. Settingthereferencemasterbit(REFMSTR = 1),allowsthereferencesystemtobe controlledviathe REFCTL register.Thisisthedefaultsetting. DeviceswithADC12_A: Inthismode (REFMSTR = 1),thelegacycontrolbitsinsidetheADC registerset (ADC12REFON, ADC12REF2_5, ADC12TCOFF, and ADC12REFOUT) aredo notcare.The ADC12SR and ADC12REFBURST arestillcontrolledviatheADC12_A, because theseareveryspecifictothe ADC12_A module.IfREFMSTR iscleared,allsettingsintheREFCTL aredo notcareand thereference systemiscontrolledcompletelyby thelegacycontrolbitsinsidetheADC12_A module. DeviceswithADC10_A: Thisistheonlymode supported.REFMSTR must be setatalltimes.ADC10SR iscontrolledviatheADC10_A, because theseareveryspecifictotheADC10_A module. Table18-1summarizestheREFCTL bitsand theireffecton theREF module. Table18-1.REF ControlofReferenceSystem (REFMSTR = 1)(Default) REF RegisterSetting Function SettingthisbitenablestheREFGEN subsystemwhichincludesthebandgap,the bandgap biascircuitry,and the1.5-V,2.0-V,2.5-Vbuffer.Settingthisbitcausesthe REFGEN subsystemtoremainenabledregardlessofwhetherornotany module hasREFON requestedit.ClearingthisbitdisablestheREFGEN subsystemonlywhen thereareno pendingrequestsforREFGEN fromany module.REFON must alsobe settoenable thetemperaturesensorwhen required. Selects1.5V,2.0V,or2.5V tobe presenton thevariablereferencelinewhenREFVSEL REFON = 1 orREFGEN isrequestedby any module. Settingthisbitsenablesthevariablereferencelinevoltagetobe presentexternaltotheREFOUT deviceviaa buffer(externalreferencebuffer). REFTCOFF Settingthisbitdisablesthetemperaturesensor(when available)toconservepower. 18.2.2.2REFMSTR = 0 ThissettingisapplicabletodeviceswithADC12_A. On legacydevices,theADC12_A providedthecontrolbitsnecessarytoconfigurethereferencesystem, namely ADC12REFON, ADC12REF2_5, ADC12TCOFF, ADC12REFOUT, ADC12SR, and ADC12REFBURST. The ADC12SR and ADC12REFBURST bitsareveryspecifictotheADC12 operation and thereforearenotincludedinREFCTL. Alllegacycontrolbitscan stillbe used toconfigurethe referencesystemallowingforbackwardcompatibilityby clearingREFMSTR. Inthiscase,theREFCTL registerbitsarea 'donotcare'. DeviceswithADC10_A do notsupportthismode. REFMSTR bitmust notbe cleared. Table18-2summarizestheADC12_A controlbitsand theireffecton theREF module.Pleasesee the ADC12_A module descriptionforfurtherdetails. NOTE: AlthoughtheREF module supportsusingtheADC12_A bitsas controlforthereference system,itisrecommended thattheuse ofthenew REFCTL registerbe used and oldercode migratedtothismethodology.Thisallowsthelogicalpartitioningofthereferencesystemto be separatefromtheADC12_A systemand formsa more naturalpartitioningforfuture products. 499SLAU259E –May 2009–RevisedJanuary2013 REF SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. PrincipleofOperation www.ti.com Table18-2.ControlofReferenceSystem (REFMSTR = 0,ADC12_A only) ADC12_A RegisterSetting Function SettingthisbitenablestheREFGEN subsystemwhichincludesthebandgap,the bandgap biascircuitry,and the1.5-V,2.0-V,2.5-Vbuffer.Settingthisbitcausesthe ADC12REFON REFGEN subsystemtoremainenabledregardlessifany module has requestedit. ClearingthisbitdisablestheREFGEN subsystemonlywhen thereareno pending requestsforREFGEN fromallmodules. Settingthisbitscauses2.5V tobe presenton thevariablereferencelinewhen ADC12REF2_5 ADC12REFON = 1.Clearingthisbitcauses1.5V tobe presenton thevariable referencelinewhen ADC12REFON = 1. Settingthisbitsenablesthevariablereferencelinevoltagetobe presentexternaltotheADC12REFOUT deviceviaa buffer(externalreferencebuffer). ADC12TCOFF Settingthisbitdisablesthetemperaturesensortoconservepower. As statedpreviously,theADC12REFBURST does have an effecton thereferencesystemand can be controlledviatheADC12_A. ThisbitisineffectregardlessifREFCTL ortheADC12_A iscontrollingthe referencesystem.SettingADC12REFBURST = 1 enablesburstmode when REFON = 1 and REFMSTR = 1 orwhen ADC12REFON = 1 and REFMSTR = 0.Inburstmode, theinternalbuffer(ADC12REFOUT = 0) ortheexternalbuffer(ADC12REFOUT = 1)isenabledonlyduringa conversionand disabled automaticallytoconservepower. NOTE: The legacyADC12_A bitADC12REF2_5 onlyallowsforselectingeither1.5V or2.5V.To select2.0V,theREFVSEL controlbitsmust be used (REFMSTR = 1).

18.2.3 ReferenceSystem Requests

Therearethreebasicreferencesystemrequeststhatareused by thereferencesystem.Each module can utilizetheserequeststoobtaintheproperresponsefromthereferencesystem.The threebasicrequests areREFGENREQ, REFBGREQ, and REFMODEREQ. No interactionisrequiredby theusercode.The modules selecttheproperrequestsautomatically. A referencerequestsignal,REFGENREQ, isavailableas an inputintotheREFGEN subsystem.This signalrepresentsa logicalOR ofindividualrequestscoming fromthevariousmodules inthesystemthat requirea voltagereferencetobe availableon thevariablereferenceline.When a module requiresa voltagereference,itassertsitscorrespondingREFGENREQ signal.When theREFGENREQ isasserted, theREFGEN subsystemisenabled.Afterthespecifiedsettlingtime,thevariablereferencelinevoltageis stableand readyforuse.The REFVSEL settingsdeterminewhichvoltageisgeneratedon thevariable referenceline. InadditiontotheREFGENREQ, a second referencerequestsignal,REFBGREQ isavailable.The REFBGREQ signalrepresentsa logicalOR ofrequestscoming fromthevariousmodules thatrequirethe bandgap referenceline.When theREFBGREQ isasserted,thebandgap,alongwithitsbiascircuitryand localbuffer,isenabledifitisnotalreadyenabledby a priorrequest. The REFMODEREQ requestsignalisavailablethatconfiguresthebandgap and itsbiascircuitryto operateina sampled orstaticmode ofoperation.The REFMODEREQ signalbasicallyrepresentsa logicalAND ofindividualrequestscoming fromthevariousanalogmodules.Inreality,a REFMODEREQ occursonlyifa module'sREFGENREQ orREFBGQ isalsoasserted,otherwiseitisa do notcare.When REFMODEREQ = 1,thebandgap operatesinsampled mode. When a module assertsitscorresponding REFMODEREQ signal,itisrequestingthatthebandgap operateinsampled mode. Because REMODEREQ isa logicalAND ofallindividualrequests,any modules requestingstaticmode cause the bandgap tooperateinstaticmode. The BGMODE bitcan be used as an indicatorofstaticorsampled mode ofoperation. 18.2.3.1REFBGACT, REFGENACT, REFGENBUSY Any module thatisusingthevariablereferencelinecausesREFGENACT tobe setinsidetheREFCTL register.Thisbitisreadonlyand indicatestotheuserthattheREFGEN isactiveoroff.Similarly,the REFBGACT isactiveany timeone ormore modules isactivelyutilizingthebandgap referencelineand indicatestotheuserthattheREFBG isactiveoroff.

500 REF SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com PrincipleofOperation The REFGENBUSY signal,when asserted,indicatesthata module isusingthereferenceand cannot have any ofitsettingschanged.Forexample,duringan activeADC12_A conversion,thereference voltagelevelshouldnotbe changed.REFGENBUSY isassertedwhen thereisan activeADC12_A conversion(ENC = 1)orwhen theDAC12_A isactivelyconverting(DAC12AMPx > 1 and DAC12SREFx = 0).REFGENBUSY when asserted,writeprotectstheREFCTL register.Thispreventsthereferencefrom beingdisabledoritslevelchanged duringany activeconversion.Pleasenotethatthereisno such protectionfortheDAC12_A iftheADC12_A legacycontrolbitsareused forthereferencecontrol.Ifthe userchanges theADC12_A settingsand theDAC12_A isusingthereference,theDAC12_A conversion isaffected. 18.2.3.2ADC10_A Fordevicesthatcontainan ADC10_A module,theADC10_A module containsonlyone localbuffer.This bufferisrequiredwhen usingtheinternalreferencevoltageand must be enabledand stablepriortoa conversion. Indeviceswithouta referenceoutputbufferREFOUT must be written0.Pleaserefertothedevice-specific datasheet. IndeviceswithADC10_A theREFMSTR bitmust be setatalltimes. IndeviceswithADC10_A theREFON bitmust be setiftheinternalreferencevoltageisused. 18.2.3.3ADC12_A Fordevicesthatcontainan ADC12_A module,theADC12_A module containstwo localbuffers.The largerbuffercan be used todrivethereferencevoltage,presenton thevariablereferenceline,externalto thedevice.Thisbufferhas largerpower consumptiondue toa selectableburstmode, as wellas,itsneed todrivelargerDC loadsthatmay be presentoutsidethedevice.The largebufferisenabledcontinuously when REFON = 1,REFOUT =1,and ADC12REFBURST = 0.When ADC12REFBURST = 1,thebufferis enabledonlyduringan ADC conversion,shuttingdown automaticallyupon completionofa conversionto save power.Inaddition,when REFON = 1 and REFOUT = 1,thesecond smallerbufferisautomatically disabled.Inthiscase,theoutputofthelargebufferisconnectedtothecapacitorarrayviaan internal analogswitch.Thisensuresthesame referenceisused throughoutthesystem.IfREFON = 1 and REFOUT = 0,theinternalbufferisused forADC conversionand thelargebufferremainsdisabled.The smallinternalbuffercan operateinburstmode as wellby settingADC12REFBURST = 1 18.2.3.4DAC12_A Some devicesmay containa DAC12_A module.The DAC12_A can use the1.5V,2.0V,or2.5V from thevariablereferencelineforitsreference.The DAC12_A can requestitsreferencedirectlyby the settingswithintheDAC12_A module itself.Therefore,iftheDAC isenabledand theinternalreferenceis selected,theDAC requeststhereferencevoltagefromtheREF module.Inaddition,as before,setting REFON = 1 (REFMSTR = 1)orADC12REFON = 1 (REFMSTR = 0)can enablethevariablereferenceline independentoftheDAC12_A controlbits. The REGEN subsystemprovidesdividedversionsofthevariablereferencelineforuse intheDAC12_A module.The DAC12_A module requireseither/2or/3ofthevariablereference.The selectionofthese depends on thecontrolbitsinsidetheDAC12_A module (DAC12IR,DAC12OG) and ishandled automaticallyby theREF module. When theDAC12_A selectsAVcc orVeREF+ as itsreference,theDAC12_A has itsown /2and /3 resistorstringavailablethatscalestheinputreferenceappropriatelybased on theDAC12IR and DAC12OG settings. 18.2.3.5LCD_B Devicesthatcontainan LCD use theLCD_B module.The LCD_B module requiresa referenceto generatetheproperLCD voltages.The bandgap referencelinefromtheREFGEN subsystemisused for thispurpose.The LCD isenabledwhen LCDON = 1 oftheLCD_B module.Thiscausesa REFBGREQ fromtheLCD module tobe asserted.The bufferedbandgap ismade availableon thebandgap reference lineforuse insidetheLCD_B module. 501SLAU259E –May 2009–RevisedJanuary2013 REF SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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18.3 REF Registers

The REF registersarelistedinTable18-3.The base addresscan be foundinthedevicespecific datasheet.The addressoffsetislistedinTable18-3. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table18-3.REF Registers Offset Acronym RegisterName Type Access Reset Section 00h REFCTL0 REFCTL0 Read/write Word 0080h Section18.3.1 00h REFCTL0_L Read/write Byte 80h 01h REFCTL0_H Read/write Byte 00h

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com REF Registers

18.3.1 REFCTL0 Register(offset= 00h)[reset= 0080h]

Figure18-2.REFCTL0 Register 15 14 13 12 11 10 9 8 Reserved BGMODE REFGENBUSY REFBGACT REFGENACT 7 6 5 4 3 2 1 0 REFMSTR Reserved REFVSEL REFTCOFF Reserved REFOUT REFON rw-(1) r0 rw-(0) rw-(0) rw-(0) r0 rw-(0) rw-(0) Can be modifiedonlywhen REFGENBUSY = 0. Table18-4.REFCTL0 RegisterDescription Bit Field Type Reset Description 15-12 Reserved R 0h Reserved.Alwaysreadsas 0. 11 BGMODE R 0h Bandgap mode. Read only. 0b = Staticmode 1b = Sampled mode 10 REFGENBUSY R 0h Referencegeneratorbusy.Read only. 0b = Referencegeneratornotbusy 1b = Referencegeneratorbusy 9 REFBGACT R 0h Referencebandgap active.Read only. 0b = Referencebandgap buffernotactive 1b = Referencebandgap bufferactive 8 REFGENACT R 0h Referencegeneratoractive.Read only. 0b = Referencegeneratornotactive 1b = Referencegeneratoractive 7 REFMSTR RW 0h REF mastercontrol.ADC10_A devices:Must be written1. 0b = Referencesystemcontrolledby legacycontrolbitsinsidetheADC12_A module when available. 1b = Referencesystemcontrolledby REFCTL register.Common settingsinside theADC12_A module (ifexists)aredo notcare. 6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-4 REFVSEL RW 0h Referencevoltagelevelselect 00b = 1.5V availablewhen referencerequestedorREFON = 1 01b = 2.0V availablewhen referencerequestedorREFON = 1 10b = 2.5V availablewhen referencerequestedorREFON = 1 11b = 2.5V availablewhen referencerequestedorREFON = 1

3 REFTCOFF RW 0h Temperaturesensordisabled

0b = Temperaturesensorenabled 1b = Temperaturesensordisabledtosave power 2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 REFOUT RW 0h Referenceoutputbuffer.ADC10_A deviceswithoutreferenceoutputbuffer:Must be written0. 0b = Referenceoutputnotavailableexternally. 1b = Referenceoutputavailableexternally.IfADC12REFBURST = 0,or DAC12_A isenabled,outputisavailablecontinuously.IfADC12REFBURST = 1, outputisavailableonlyduringan ADC12_A conversion. 503SLAU259E –May 2009–RevisedJanuary2013 REF SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. REF Registers www.ti.com Table18-4.REFCTL0 RegisterDescription(continued) Bit Field Type Reset Description 0 REFON RW 0h Referenceenable. ADC10_A: The ADC10_A does notsupportthereferencerequest.REFON must be setiftheinternalreferencevoltageisused. 0b = Disablesreferenceifno otherreferencerequestsarepending. 1b = Enablesreference.

504 REF SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter19 SLAU259E –May 2009–RevisedJanuary2013 ADC10_A The ADC10_A module is a high-performance10-bitanalog-to-digitalconverter(ADC). This chapter describestheoperationoftheADC10_A module. 505SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Introduction www.ti.com

19.1 ADC10_A Introduction

The ADC10_A module supportsfast10-bitanalog-to-digitalconversions.The module implementsa 10-bit SAR corewithsample selectcontroland a window comparator. ADC10_A featuresinclude:

Greaterthan200-kspsmaximum conversionrate
Monotonic10-bitconverterwithno missingcodes
Sample-and-holdwithprogrammablesamplingperiodscontrolledby softwareortimers.
Conversioninitiationby softwareordifferentTimers
Software-selectableon-chipreferenceusingtheREF module orexternalreference
12 individuallyconfigurableexternalinputchannels
ConversionchannelfortemperaturesensoroftheREF module
Selectableconversionclocksource
Single-channel,repeat-single-channel,sequence (autoscan),and repeat-sequence(repeated autoscan)conversionmodes
Window comparatorforlowpower monitoringofinputsignals
InterruptvectorregisterforfastdecodingofsixADC Interrupts(ADC10IFG0, ADC10TOVIFG, ADC10OVIFG, ADC10LOIFG, ADC10INIFG, ADC10HIIFG) The blockdiagramofADC10_A isshown inFigure19-1.The on-chipreferencevoltagegenerationis locatedinthereferencemodule (seethedevice-specificdatasheet).

506 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

/1 .. /8 :64 10-bit ADC Core VR- VR+ Convert Sample and Hold S/H 0011 0110 1 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Sample Timer /4 .. /10241 Sync MODOSC from UCS ACLK MCLK SMCLK ADC10SC 3 inputs from Timers Data Format ADC10MEM 10-bit Window Comparator VSS Vcc VREF 1.5 / 2.0 / 2.5 V from shared reference ADC10SR ADC10ON ADC10SREFx ADC10SREF2 Auto ADC10CONSEQx ADC10INCHx A15 A14 A13 A12 TempSense Batt.Monitor VEREF+ VEREF- ADC10DIVx ADC10 PDIVx ADC10 SSELx ADC10BUSYADC10SHP ADC10 MSC ADC10 SHTx SHI ADC10ISSH SAMPCON ADC10 MSC ADC10HIx ADC10LOx ADC10DF To Interrupt Logic ADC10CLK Reference Buffer ADC10 SHSx ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Introduction A The MODOSC ispartoftheUCS. See theUCS chapterformore information. B When usingADC10SHP = 0 no synchronisationofthetriggerinputisdone. Figure19-1.ADC10_A Block Diagram 507SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

R~ 50 kOhm ADC10MCTL0.0–3 InputAx N =□1023□×ADC Vin – V R– V – VR+ R– ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com

19.2 ADC10_A Operation

The ADC10_A module isconfiguredwithusersoftware.The setupand operationoftheADC10_A is discussedinthefollowingsections. 19.2.1 10-BitADC Core The ADC coreconvertsan analoginputtoits10-bitdigitalrepresentationand storestheresultinthe conversionregisterADC10MEM0. The coreuses two programmable/selectablevoltagelevels(VR+ and VR- )todefinetheupperand lowerlimitsoftheconversion.The digitaloutput(NADC )isfullscale(03FFh)when theinputsignalisequaltoorhigherthanVR+ ,and zerowhen theinputsignalisequaltoorlowerthanVR-. The inputchanneland thereferencevoltagelevels(VR+ and VR-)aredefinedintheconversion-control memory. The conversionformulafortheADC resultN ADC isshown inEquation11: (11) The ADC10_A coreisconfiguredby thecontrolregistersADC10CTL0, ADC10CTL1 and ADC10CTL2. The coreisenabledwiththeADC10ON bit.The ADC10_A can be turnedoffwhen notinuse tosave power.Withfew exceptions,theADC10_A controlbitscan onlybe modifiedwhen ADC10ENC = 0. ADC10ENC must be setto1 beforeany conversioncan takeplace. 19.2.1.1Conversion Clock Selection The ADC10CLK isused bothas theconversionclockand togeneratethesamplingperiodwhen thepulse samplingmode isselected.The ADC10_A sourceclockisselectedusingtheADC10SSELx bits.Possible ADC10CLK sourcesareSMCLK, MCLK, ACLK, and theMODOSC. The inputclockcan be dividedfrom 1–512 usingboththeADC10DIVx bitsand theADC10PDIVx bits. MODOSC, generatedinternallyintheUCS, isinthe5-MHz range,butvarieswithindividualdevices, supplyvoltage,and temperature.See thedevice-specificdatasheetfortheMODOSC specification. The usermust ensurethattheclockchosen forADC10CLK remainsactiveuntiltheend ofa conversion.If theclockisremoved duringa conversion,theoperationdoes notcompleteand any resultisinvalid.

19.2.2 ADC10_A Inputsand Multiplexer

The 14 externaland 2 internalanalogsignalsareselectedas thechannelforconversionby theanalog inputmultiplexer.The inputmultiplexerisa break-before-maketypetoreduceinput-to-inputnoiseinjection resultingfromchannelswitching(seeFigure19-2).The inputmultiplexerisalsoa T-switchtominimizethe couplingbetween channels.ChannelsthatarenotselectedareisolatedfromtheA/D and theintermediate node isconnectedtoanalogground(AVSS ),so thatthestraycapacitanceisgroundedtoeliminate crosstalk. The ADC10_A uses thechargeredistributionmethod.When theinputsareinternallyswitched,the switchingactionmay cause transientson theinputsignal.These transientsdecay and settlebefore causingerrantconversion. Figure19-2.Analog Multiplexer

508 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation 19.2.2.1Analog PortSelection The ADC10_A inputsaremultiplexedwithdigitalportpins.When analogsignalsareappliedtodigital gates,parasiticcurrentcan flowfromVCC toGND. Thisparasiticcurrentoccursiftheinputvoltageisnear thetransitionlevelofthegate.Disablingthedigitalpartoftheportpineliminatestheparasiticcurrentflow and,therefore,reducesoverallcurrentconsumption.The PySELx bitsprovidetheabilitytodisablethe portpininputand outputbuffers. ;Py.0andPy.1configuredforanaloginput BIS.B#3h,&PySEL;Py.1andPy.0ADC10_Afunction

19.2.3 VoltageReferenceGenerator

The ADC10_A module isdesignedtobe used eitherwiththeon-chipreferencesuppliedby theREF module oran externallyreferencevoltagesuppliedon externalpins. The on-chipreferenceiscapableofsupplying1.5V,2.0V,and 2.5V.The referencevoltagesare controlledby thecontrolregistersoftheREF module (seetheREF chapterfordetails).The internalVCC can alsobe used as thevoltagereference. Externalreferencevoltagesmay be suppliedforVR+ and VR- throughpinsVEREF+ and VEREF-, respectively. 19.2.3.1InternalReferenceLow-Power Features The on-chipreferenceisdesignedforlow-powerapplications.Thisreferenceincludesa band-gapvoltage sourceand a separatereferencebufferbothlocatedintheREF module.The currentconsumptionofeach isspecifiedseparatelyinthedevice-specificdatasheet.The ADC10_A alsocontainsan internalbufferfor referencevoltages.Thisbufferisautomaticallyenabledwhen theinternalreferenceisselectedfor VREF+, butitisalsooptionallyavailableforVEREF+. The on-chipreferencefromtheREF module must be enabledby software.Itssettlingtimeistypical25 µs.See thedevice-specificdatasheetand theREF chapterforfurtherinformationon theon-chipreference. The referencebufferoftheADC10_A alsohas selectablespeed versuspower settings.When the maximum conversionrateisbelow50 ksps,settingADC10SR = 1 reducesthecurrentconsumptionofthe bufferapproximately50%.

19.2.4 Auto Power Down

The ADC10_A isdesignedforlow-powerapplications.When theADC10_A isnotactivelyconverting,the coreisautomaticallydisabledand automaticallyreenabledwhen needed.The MODOSC isalso automaticallyenabledwhen needed and disabledwhen notneeded.

19.2.5 Sample and Conversion Timing

An analog-to-digitalconversionisinitiatedwitha risingedge ofthesample inputsignalSHI.The source forSHI isselectedwiththeADC10SHSx bitsand includesthefollowing:

ADC10SC bitand
Threetimeroutputs The polarityoftheSHI signalsourcecan be invertedwiththeADC10ISSH bit.The SAMPCON signal controlsthesample periodand startofconversion.When SAMPCON ishigh,samplingisactive.The high- to-lowSAMPCON transitionstartstheanalog-to-digitalconversion,whichrequires12 ADC10CLK cycles in10-bitresolutionmode. One additionalADC10CLK isused forthewindow comparator.Two different sample-timingmethods aredefinedby controlbitADC10SHP, extendedsample mode, and pulsemode. 509SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

12 × ADC10CLK Start Conversion ADC10CLK Start Sampling Stop Sampling Conversion Complete SAMPCON SHI tsample tconvert tsync 12□× ADC10CLK Start Conversion ADC10CLK ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com 19.2.5.1Extended Sample Mode The extendedsample mode isselectedwhen ADC10SHP = 0.The SHI signaldirectlycontrolsSAMPCON and definesthelengthofthesample periodtsample.When SAMPCON ishigh,samplingisactive.The high- to-lowSAMPCON transitionstartstheconversionaftersynchronizationwithADC10CLK (seeFigure19-3). Figure19-3.Extended Sample Mode 19.2.5.2Pulse Sample Mode The pulsesample mode isselectedwhen ADC10SHP = 1.The SHI signalisused totriggerthesampling timer.The ADC10SHTx bitsinADC10CTL0 controltheintervalofthesamplingtimerthatdefinesthe SAMPCON sample periodtsample.The samplingtimerkeeps SAMPCON highaftersynchronizationwith AD10CLK fora programmed intervaltsample.The totalsamplingtimeistsample plustsync (seeFigure19-4). The ADC10SHTx bitsselectthesamplingtimein4× multiplesofADC10CLK. Figure19-4.Pulse Sample Mode

510 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

V = Input voltage at pin Ax V = External source voltage R = External source resistance R = Internal MUX-on input resistance C = Input capacitance V = Capacitance-charging voltage I S S I I C C = Parasitic capacitance, internal C = Parasitic capacitance, external pint Pext ~1pF MSP430 CpintCpext ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation 19.2.5.3Sample Timing Considerations When SAMPCON = 0,allAx inputsarehighimpedance.When SAMPCON = 1,theselectedAx inputcan be modeled as an RC low-passfilterduringthesamplingtimetsample (seeFigure19-5).An internalMUX-on inputresistanceR I (seedevicespecificdatasheet)inserieswithcapacitorC I (seedevicespecific datasheet)isseen by thesource.The capacitorC I voltageVC must be chargedtowithinone-halfLSB of thesourcevoltageVS foran accurate10-bitconversion. Figure19-5.Analog InputEquivalentCircuit The resistanceofthesourceR S and R I affecttsample.The minimum sample timemust notbe violated. Violationoftheminimum sample timemay cause a conversionnottotakeplace.See thedevicespecific datasheetforthetsample limits.

19.2.6 Conversion Result

The conversionresultisaccessibleusingtheADC10MEM0 registerindependentlyoftheconversionmode selectedby theuser.When a conversionresultiswrittentoADC10MEM0, theADC10IFG0 isset.

19.2.7 ADC10_A Conversion Modes

The ADC10_A has fouroperatingmodes selectedby theCONSEQx bitsas listedinTable19-1. Table19-1.Conversion Mode Summary ADC10CONSEQx Mode Operation 00 Single-channelsingle-conversion A singlechannelisconvertedonce. 01 Sequence-of-channels(autoscan) A sequence ofchannelsisconvertedonce. 10 Repeat-single-channel A singlechannelisconvertedrepeatedly. 11 Repeat-sequence-of-channels A sequence ofchannelsisconvertedrepeatedly. (repeatedautoscan) 511SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

x = ADC10INCHx Wait for Enable Wait for Trigger SAMPCON□= SAMPCON□=□1 Convert SAMPCON□= ADC10ENC =□0 ADC10ENC =□0□* 10 × ADC10CLK Conversion Completed, Result Stored Into ADC10MEM0, ADC10IFG0 is Set 1 × ADC10CLK ADC10ON = 1 ADC10CONSEQx = 00 ADC10ENC ADC10ENC = ADC10ENC = ADC10ENC =□0□* ADC10SHSx ADC10ENC ADC10SC = = 0 and = 1 or and *□□□Conversion□result□is□unpredictable ** Two ADC10CLK□cycles□needed x□-□pointer□to□the□selected ADC10_A channel□defined□by All□bit-□or□registernames□are□marked□with□bold□font,□signals□are□noted□in□normal□font ADC10INCHx Sample□Input Channel□x ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com 19.2.7.1Single-ChannelSingle-ConversionMode A singlechannelselectedby ADC10INCHx issampled and convertedonce.The ADC resultiswrittento ADC10MEM0. Figure19-6shows theflowofthesingle-channelsingle-conversionmode. When ADC10SC triggersa conversion,successiveconversionscan be triggeredby theADC10SC bit.When any other triggersourceisused,ADC10ENC must be toggledbetween each conversion. ResettingADC10ON bitwithina conversioncausestheADC10_A togo back into"ADC10 off"state.In thiscase,thevalueoftheconversionregisterand thevalueoftheinterruptflagsareunpredictable. Figure19-6.Single-ChannelSingle-ConversionMode

512 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

x = ADC10INCH x Wait for Enable ADC10ENC Wait for Trigger ADC10ENC =ADC10SHSx ADC10ENC ADC10SC = 0 and = 1 or and SAMPCON□= SAMPCON□=□1 Convert SAMPCON□= 10 × ADC10CLK Conversion Completed, Result Stored Into ADC10MEM0, ADC10IFG0 is set 1 × ADC10CLK ADC10ON = 1 ADC10CONSEQx = 01 ( =□0 or =□0) and x□□□□0 ADC10MSC ADC10SHP ADC10ENC = ADC10MSC ADC10SHP =□1 and =□1 and x□□□□0 x□-□input□channel Ax All□bit-□or□registernames□are□marked□with□bold□font,□signals□are□noted□in□normal□font ** Two ADC10CLK□cycles□needed Sample□Input Channel□x x□=□0 x□=□x□-□1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation 19.2.7.2Sequence-of-ChannelsMode (Autoscan Mode) Insequence-of-channelsmode, alsoreferredtoas autoscanmode, a sequence ofchannelsissampled and convertedonce.The sequence beginswiththechannelselectedby theADC10INCHx bitsand decrementstochannelA0.Each ADC resultiswrittentoADC10MEM0. The sequence stopsafter conversionofchannelA0.Figure19-7shows thesequence-of-channelsmode. When ADC10SC triggersa sequence,successivesequencescan be triggeredby theADC10SC bit.When any othertriggersourceis used,ADC10ENC must be toggledbetween each sequence.As inallconversionmodes resetting ADC10ON bitwithina conversioncausestheADC10_A togo back into"ADC10 off"state. Figure19-7.Sequence-of-ChannelsMode 513SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

x = ADC10INCHx Wait for Enable ADC10ENC Wait for Trigger ADC10SHSx ADC10ENC ADC10SC = 0 and = 1 or and SAMPCON□= SAMPCON□=□1 Convert SAMPCON = 10 × ADC10CLK Conversion Completed, Result Stored Into ADC10MEM0, ADC10IFG0 is Set 1 × ADC10CLK ADC10ON = 1 ADC10CONSEQx = 10 ADC10MSC ADC10SHP ADC10ENC =□1 and =□1 and =□1 ADC10ENC =□0 ( =□0 or =□0) and =□1 ADC10MSC ADC10SHP ADC10ENC ADC10ENC ADC10ENC x□-□pointer□to□the□selected ADC10_A channel□defined□by All□bit-□or□registernames□are□marked□with□bold□font,□signals□are□noted□in□normal□font ADC10INCHx ** Two ADC10CLK□cycles□needed Sample□Input Channel□x ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com 19.2.7.3Repeat-Single-ChannelMode A singlechannelselectedby ADC10INCHx issampled and convertedcontinuously.Each ADC resultis writtentoADC10MEM0. Figure19-8shows therepeat-single-channelmode. Figure19-8.Repeat-Single-ChannelMode

514 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

= 0 and = 1 or and SAMPCON□= SAMPCON□=□1 10 × ADC10CLK Conversion□Completed, Result□Stored□Into is□Set ADC10MEM0, ADC10IFG0 1 × ADC10CLK ADC10ON = 1 ADC10CONSEQx = 1 1 ADC10MSC ADC10SHP ADC10ENC =□1 and =□1 and ( =□1 or x□□□□0) ADC10ENC =□0 and x□=□0 ( =□0 or =□0) and ( =□1 or x□□□□0 ADC10MSC ADC10SHP ADC10ENC Convert ADC10ENC = ADC10ENC = Sample□Input Channel□x else x□= ADC10INCHx SAMPCON else x□= ADC10INCHx ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation 19.2.7.4Repeat-Sequence-of-ChannelsMode (RepeatedAutoscan Mode) Inthismode, a sequence ofchannelsissampled and convertedrepeatedly.Thismode isalsoreferredto as repeatedautoscanmode. The sequence beginswiththechannelselectedby ADC10INCHx and decrementstochannelA0.Each ADC resultiswrittentoADC10MEM0. The sequence ends after conversionofchannelA0,and thenexttriggersignalre-startsthesequence.Figure19-9shows the repeat-sequence-of-channelsmode. Figure19-9.Repeat-Sequence-of-ChannelsMode 515SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com 19.2.7.5Using theMultipleSample and Convert (ADC10MSC) Bit To configuretheconvertertoperformsuccessiveconversionsautomaticallyand as quicklyas possible,a multiplesample and convertfunctionisavailable.When ADC10MSC = 1,CONSEQx > 0,and thesample timerisused,thefirstrisingedge oftheSHI signaltriggersthefirstconversion.Successiveconversions aretriggeredautomaticallyas soon as thepriorconversioniscompleted.Additionalrisingedges on SHI areignoreduntilthesequence iscompletedinthesingle-sequencemode, oruntiltheADC10ENC bitis toggledinrepeat-single-channelorrepeated-sequencemodes. The functionoftheADC10ENC bitis unchanged when usingtheADC10MSC bit. 19.2.7.6Stopping Conversions StoppingADC10_A activitydepends on themode ofoperation.The recommended ways tostopan active conversionorconversionsequence are:

ResettingADC10ENC insingle-channelsingle-conversionmode stopsa conversionimmediatelyand theresultsareunpredictable.Forcorrectresults,pollthebusy bituntilresetbeforeclearing ADC10ENC.
ResettingADC10ENC duringrepeat-single-channeloperationstopstheconverterattheend ofthe currentconversion.
ResettingADC10ENC duringa sequence orrepeat-sequencemode stopstheconverterattheend of thesequence.
Any conversionmode may be stoppedimmediatelyby settingtheCONSEQx = 0 and resettingthe ADC10ENC bit.Conversiondataareunreliable.

19.2.8 Window Comparator

The window comparatorallowstomonitoranalogsignalswithoutany CPU interaction.Inthefollowinglist one can findtheavailableInterruptflagsand theconditions,when theyareasserted:

The ADC10LO-Interruptflag(ADC10LOIFG) getssetifthecurrentresultoftheADC10_A conversion isbelowthelowthresholddefinedinregisterADC10LO
The ADC10HI-Interruptflag(ADC10HIIFG) getssetifthecurrentresultoftheADC10_A conversionis greaterthanthehighthresholddefinedinregisterADC10HI
The ADC10IN-Interruptflag(ADC10INIFG) getssetifthecurrentresultoftheADC10_A conversionis greaterthanthelowthresholddefinedinregisterADC10LO and lessthanthehighthresholddefinedin ADC10HI These Interruptsaregeneratedindependentlyoftheconversionmode selectedby theuser.The updateof thewindow comparatorinterrupt-flagshappens inparalleltotheADC10IFG0. The useralwaysneeds toensure,thatthevaluesintheADC10HI and ADC10LO registersareinthe correctdataformat.Ifforexample thebinarydataformatisselected(ADC10DF = 0),thenthethresholds inthethresholdregistersADC10HI and ADC10LO alsoneed tobe enteredbinarycoded.Changingthe ADC10DF ortheADC10RES resetsthethresholdregisters. The interruptflagsneed tobe resetby theusersoftware.The ADC10_A onlyupdatestheflagseach time a new valueisavailableintheADC10MEM0. Thisupdateisonlya setofthecorrespondinginterruptflag. When theuseruses thewindow comparatorflags,itmust be ensuredthattheyareresetby software accordingtotheapplicationneeds.

516 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

–50 0 50 100 0.500 0.600 0.700 0.800 0.900 1.000 V = 0.00252 x (TEMP ) + 0.688TEMP C T emperature – °C Voltage ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation

19.2.9 Using theIntegratedTemperature Sensor

To use theon-chiptemperaturesensor,theuserselectstheanaloginputchannelADC10INCHx = 1010. Any otherconfigurationisdone as ifan externalchannelwas selected,includingreferenceselection, conversion-modeselection,etc.The temperaturesensorislocatedintheREF module ofthedeviceis configuredby usingtheREF module'scontrolregisters. The typicaltemperaturesensortransferfunctionisshown inFigure19-10.When usingthetemperature sensor,thesample periodmust be greaterthan30 µs.The temperaturesensoroffseterrorcan be large and may need tobe calibratedformost applications(seethedevice-specificdatasheetforparameters). Figure19-10.TypicalTemperature Sensor TransferFunction 517SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

100 nF10 F µ Analog Power Supply Decoupling DVCC DVSS A VCC A VSS 100 nF10 F µ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC10_A Operation www.ti.com

19.2.10 ADC10_A Grounding and Noise Considerations

As withany high-resolutionADC, appropriateprinted-circuit-boardlayoutand groundingtechniquesshould be followedtoeliminategroundloops,unwanted parasiticeffects,and noise. Ground loopsareformedwhen returncurrentfromtheA/D flowsthroughpathsthatarecommon with otheranalogordigitalcircuitry.Ifcareisnottaken,thiscurrentcan generatesmall,unwanted offset voltagesthatcan add toorsubtractfromthereferenceorinputvoltagesoftheADC. The connections shown inFigure19-11preventthis. Inadditiontogrounding,rippleand noisespikeson thepower-supplylinesdue todigitalswitchingor switchingpower suppliescan corrupttheconversionresult.A noise-freedesignusingseparateanalogand digitalgroundplaneswitha single-pointconnectionisrecommended toachievehighaccuracy. Figure19-11.ADC10_A Grounding and Noise Considerations

19.2.11 ADC10_A Interrupts

The ADC10_A has 6 Interruptsources:

ADC10IFG0 :conversionreadyInterrupt
ADC10OVIFG :ADC10MEM0 overflow
ADC10TOVIFG :ADC10_A conversiontimeoverflow
ADC10LOIFG, ADC10INIFG, ADC10HIIFG :window comparatorInterruptflags The ADC10IFG0 bitissetwhen theADC10MEM0 memory registerisloadedwiththeconversionresult. An InterruptrequestisgeneratedifADC10IE0 bitand theGIE bitareset.The ADC10OV conditionoccurs when a conversionresultiswrittentotheADC10MEM0 beforeitspreviousconversionresultwas read. The ADC10TOV conditionisgeneratedwhen anothersample-and-conversionisrequestedbeforethe currentconversioniscompleted.The DMA istriggeredaftereach conversion. The window comparatorInterruptflagsaresetcorrespondingtothedescriptionintheWindow Comparator section(seeSection19.2.8). 19.2.11.1ADC10IV, InterruptVectorGenerator AllADC10_A Interruptsourcesareprioritizedand combined tosourcea singleInterruptvector.The InterruptvectorregisterADC10IV isused todeterminewhichenabledADC10_A Interruptsource requestedan Interrupt. The highest-priorityenabledADC10_A Interruptgeneratesa number intheADC10IV register(seeregister description).Thisnumber can be evaluatedoradded totheprogramcounter(PC)toautomaticallyenter theappropriatesoftwareroutine.DisabledADC10_A Interruptsdo notaffecttheADC10IV value. Read accessoftheADC10IV registerautomaticallyresetsthehighest-pendingInterruptconditionand flag.OnlytheADC10IFG0 isnotresetby thisADC10IV readaccess.ADC10IFG0 isautomaticallyresetby readingtheADC10MEM0 registerormay be resetwithsoftware. WriteaccessoftheADC10IV registerclearsallpendingInterruptconditionsand flags.

518 ADC10_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Operation IfanotherInterruptispendingafterservicingofan Interrupt,anotherInterruptisgenerated.Forexample,if theADC10OV, ADC10HIIFG and ADC10IFG0 Interruptsarependingwhen theInterruptserviceroutine accessestheADC10IV register,thehighestpriorityinterrupt(ADC10OV Interruptcondition)isreset automatically.AftertheRETI instructionoftheInterruptserviceroutineisexecuted,theADC10HIIFG generatesanotherInterrupt. 19.2.11.2ADC10_A InterruptHandlingSoftwareExample The followingsoftwareexample shows therecommended use oftheADC10IV. The ADC10IV valueis added tothePC toautomaticallyjump totheappropriateroutine.

ADC10IFG0, ADC10TOV, and ADC10OV: 16 cycles ;InterrupthandlerforADC10_A. INT_ADC10_A ;EnterInterruptServiceRoutine ADD&ADC10IV,PC ;AddoffsettoPC RETI ;Vector0:NoInterrupt JMPADOV ;Vector2:ADC10_Aoverflow JMPADTOV ;Vector4:ADC10_Atimingoverflow JMPADHI ;Vector6:ADC10_Awindowcomparatorhigh Interrupt JMPADLO ;Vector8:ADC10_Awindowcomparatorlow Interrupt JMPADIN ;Vector10:ADC10_Awindowcomparatorin Interrupt ;HandlerforADC10IFG0startshere.NoJMPrequired. ADMEMMOV&ADC10MEM0,xxx ;Moveresult,flagisreset ... ;Otherinstructionneeded? RETI ;Return; ADOV... ;HandleADCMEM0overflow RETI ;Return; ADTOV... ;HandleConv.timeoverflow RETI ;Return; ADHI... ;HandlewindowcomparatorhighInterrupt RETI ;Return; ADLO... ;HandlewindowcomparatorlowInterrupt RETI ;Return; ADIN... ;HandlewindowcomparatorinwindowInterrupt RETI ;Return 519SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3 ADC10_A Registers

The ADC10_A registersarelistedinTable19-2.The base addressoftheADC10_A can be foundinthe device-specificdatasheet.The addressoffsetofeach ADC10_A registerisgiveninTable19-2. Table19-2.ADC10_A Registers Offset Acronym RegisterName Type Reset Section 00h ADC10CTL0 ADC10_A Control0 register Read/write 0000h Section19.3.1 02h ADC10CTL1 ADC10_A Control1 register Read/write 0000h Section19.3.2 04h ADC10CTL2 ADC10_A Control2 register Read/write 1000h Section19.3.3 06h ADC10LO ADC10_A Window ComparatorLow Read/write 0000h Section19.3.9 Thresholdregister 08h ADC10HI ADC10_A Window ComparatorHigh Read/write FF03h Section19.3.7 Thresholdregister 0Ah ADC10MCTL0 ADC10_A Memory Controlregister Read/write 00h Section19.3.6 12h ADC10MEM0 ADC10_A ConversionMemory register Read/write undefined Section19.3.4 1Ah ADC10IE ADC10_A InterruptEnableregister Read/write 0000h Section19.3.11 1Ch ADC10IFG ADC10_A InterruptFlagregister Read/write 0000h Section19.3.12 1Eh ADC10IV ADC10_A InterruptVectorregister Read/write 0000h Section19.3.13

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19.3.1 ADC10CTL0 Register

ADC10_A ControlRegister0 Figure19-12.ADC10CTL0 Register 15 14 13 12 11 10 9 8 Reserved ADC10SHTx r0 r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC10MSC Reserved ADC10ON Reserved ADC10ENC ADC10SC rw-(0) r0 r0 rw-(0) r0 r0 rw-(0) rw-(0) Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefields immediatelyshows effectalsowhen a conversionisactive. Table19-3.ADC10CTL0 RegisterDescription Bit Field Type Reset Description 15-12 Reserved R 0h Reserved.Alwaysreadsas 0. 11-8 ADC10SHTx RW 0h ADC10_A sample-and-holdtime.These bitsdefinethenumber ofADC10CLK cyclesinthesamplingperiodfortheADC10. 0000b = 4 ADC10CLK cycles 0001b = 8 ADC10CLK cycles 0010b = 16 ADC10CLK cycles 0011b = 32 ADC10CLK cycles 0100b = 64 ADC10CLK cycles 0101b = 96 ADC10CLK cycles 0110b = 128 ADC10CLK cycles 0111b = 192 ADC10CLK cycles 1000b = 256 ADC10CLK cycles 1001b = 384 ADC10CLK cycles 1010b = 512 ADC10CLK cycles 1011b = 768 ADC10CLK cycles 1100b = 1024 ADC10CLK cycles 1101b = 1024 ADC10CLK cycles 1110b = 1024 ADC10CLK cycles 1111b = 1024 ADC10CLK cycles 7 ADC10MSC RW 0h ADC10_A multiplesample and conversion.Validonlyforsequence orrepeated modes. 0b = The samplingtimerrequiresa risingedge oftheSHI signaltotriggereach sample-and-convert. 1b = The firstrisingedge oftheSHI signaltriggersthesamplingtimer,butfurther sample-and-conversionsareperformedautomaticallyas soon as theprior conversioniscompleted. 6-5 Reserved R 0h Reserved.Alwaysreadsas 0.

4 ADC10ON RW 0h ADC10_A on

0b = ADC10_A off 1b = ADC10_A on 3-2 Reserved R 0h Reserved.Alwaysreadsas 0.

1 ADC10ENC RW 0h ADC10_A enableconversion

0b = ADC10_A disabled 1b = ADC10_A enabled 0 ADC10SC RW 0h ADC10_A startconversion.Software-controlledsample-and-conversionstart. ADC10SC and ADC10ENC may be settogetherwithone instruction.ADC10SC isresetautomatically. 0b = No sample-and-conversion-start 1b = Startsample-and-conversion 521SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3.2 ADC10CTL1 Register

ADC10_A ControlRegister1 Figure19-13.ADC10CTL1 Register 15 14 13 12 11 10 9 8 Reserved ADC10SHSx ADC10SHP ADC10ISSH r0 r0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC10DIVx ADC10SSELx ADC10CONSEQx ADC10BUSY rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-(0) Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefields immediatelyshows effectalsowhen a conversionisactive. Table19-4.ADC10CTL1 RegisterDescription Bit Field Type Reset Description 15-12 Reserved R 0h Reserved.Alwaysreadsas 0. 11-10 ADC10SHSx RW 0h ADC10_A sample-and-holdsourceselect Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 00b = ADC10SC bit 01b = Timertrigger0 -see devicespecificdatasheet 10b = Timertrigger1 -see devicespecificdatasheet 11b = Timertrigger2 -see devicespecificdatasheet 9 ADC10SHP RW 0h ADC10_A sample-and-holdpulse-modeselect.Thisbitselectsthesourceofthe samplingsignal(SAMPCON) tobe eithertheoutputofthesamplingtimerorthe sample-inputsignaldirectly. Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 0b = SAMPCON signalissourcedfromthesample-inputsignal. 1b = SAMPCON signalissourcedfromthesamplingtimer.

8 ADC10ISSH RW 0h ADC10_A invertsignalsample-and-hold

Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 0b = The sample-inputsignalisnotinverted. 1b = The sample-inputsignalisinverted. 7-5 ADC10DIVx RW 0h ADC10_A clockdivider Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 000b = Divideby 1 001b = Divideby 2 010b = Divideby 3 011b = Divideby 4 100b = Divideby 5 101b = Divideby 6 110b = Divideby 7 111b = Divideby 8

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC10_A Registers Table19-4.ADC10CTL1 RegisterDescription(continued) Bit Field Type Reset Description 4-3 ADC10SSELx RW 0h ADC10_A clocksourceselect Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 00b = MODCLK 01b = ACLK 10b = MCLK 11b = SMCLK 2-1 ADC10CONSEQx RW 0h ADC10_A conversionsequence mode select Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 00b = Single-channel,single-conversion 01b = Sequence-of-channels 10b = Repeat-single-channel 11b = Repeat-sequence-of-channels 0 ADC10BUSY R 0h ADC10_A busy.Thisbitindicatesan activesample orconversionoperation. 0b = No operationisactive. 1b = A sequence,sample,orconversionisactive. 523SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3.3 ADC10CTL2 Register

ADC10_A ControlRegister2 Figure19-14.ADC10CTL2 Register 15 14 13 12 11 10 9 8 Reserved ADC10PDIVx r0 r0 r0 r0 r0 r0 rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Reserved ADC10RES ADC10DF ADC10SR Reserved r0 r0 r0 rw-(1) rw-(0) rw-(0) r0 r0 Can be modifieedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefields immediatelyshows effectalsowhen a conversionisactive. Table19-5.ADC10CTL2 RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9-8 ADC10PDIVx RW 0h ADC10_A predivider.ThisbitpredividestheselectedADC10_A clocksource beforeitgetsdividedagainusingADC10DIVx. 00b = Predivideby 1 01b = Predivideby 4 10b = Predivideby 64 11b = Reserved 7-5 Reserved R 0h Reserved.Alwaysreadsas 0. 4 ADC10RES RW 1h ADC10_A resolution.Thisbitdefinestheconversionresultresolution. 0b = 8 bit(10clockcycleconversiontime) 1b = 10 bit(12clockcycleconversiontime) 3 ADC10DF RW 0h ADC10_A dataread-backformat.Data isalwaysstoredinthebinaryunsigned format. 0b = Binaryunsigned.Theoreticallytheanaloginputvoltage–V(REF) resultsin 0000h,theanaloginputvoltage+V(REF) resultsin03FFh. 1b = Signedbinary(2scomplement),leftaligned.Theoreticallytheanaloginput voltage–V(REF) resultsin8000h,theanaloginputvoltage+V(REF) resultsin 7FC0h. 2 ADC10SR RW 0h ADC10_A samplingrate.ThisbitselectsdrivecapabilityoftheADC10_A referencebufferforthemaximum samplingrate.SettingADC10SR reducesthe currentconsumptionofthisbuffer. 0b = ADC10_A buffersupportsup toapproximately200 ksps. 1b = ADC10_A buffersupportsup toapproximately50 ksps. 1-0 Reserved R 0h Reserved.Alwaysreadsas 0.

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19.3.4 ADC10MEM0 Register

ADC10_A ConversionMemory Register Figure19-15.ADC10MEM0 Register 15 14 13 12 11 10 9 8 Reserved Conversion_Results r0 r0 r0 r0 r0 r0 rw rw 7 6 5 4 3 2 1 0 Conversion_Results rw rw rw rw rw rw rw rw Table19-6.ADC10MEM0 RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9-0 Conversion_Results RW undefined The 10-bitconversionresultsarerightjustified.Bit9 istheMSB. Bits15–10 are 0 in10-bitmode, and bits15–8 are0 in8-bitmode. Writingtotheconversion memory registercorruptstheresults.Thisdataformatisused ifADC10DF = 0.

19.3.5 ADC10MEM0 Register,2s-Complement Format

ADC10_A ConversionMemory Register,2s-ComplementFormat Figure19-16.ADC10MEM0 Register 15 14 13 12 11 10 9 8 Conversion_Results rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Conversion_Results Reserved rw rw r0 r0 r0 r0 r0 r0 Table19-7.ADC10MEM0 RegisterDescription Bit Field Type Reset Description 15-6 Conversion_Results RW undefined The 10-bitconversionresultsareleftjustified,2s-complementformat.Bit15 is theMSB. Bits5–0 are0 in10-bitmode, and bits7–0 are0 in8-bitmode. This dataformatisused ifADC10DF = 1.The dataisstoredintheright-justified formatand isconvertedtotheleft-justified2s-complementformatduringread back.Writingtotheconversionmemory registercorruptstheresults. 5-0 Reserved R 0h Reserved.Alwaysreadsas 0. 525SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3.6 ADC10MCTL0 Register

ADC10_A ConversionMemory ControlRegister Figure19-17.ADC10MCTL0 Register 7 6 5 4 3 2 1 0 Reserved ADC10SREFx ADC10INCHx r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefields immediatelyshows effectalsowhen a conversionisactive. Table19-8.ADC10MCTL0 RegisterDescription Bit Field Type Reset Description 7 Reserved R 0h Reserved.Alwaysreadsas 0. 6-4 ADC10SREFx RW 0h Selectreference.Itisnotrecommended tochange thissettingwhilea conversionisongoing. Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 000b = V(R+) = AVCC and V(R-)= AVSS 001b = V(R+) = VREF and V(R-)= AVSS 010b = V(R+) = VEREF+ bufferedand V(R-)= AVSS 011b =V(R+) = VEREF+ and V(R-)= AVSS 100b = V(R+) = AVCC and V(R-)= VEREF- 101b = V(R+) = VREF and V(R-)= VEREF- 110b = V(R+) = VEREF+ bufferedand V(R-)= VEREF- 111b = V(R+) = VEREF+ and V(R-)= VEREF- 3-0 ADC10INCHx RW 0h Inputchannelselect.Writingthesebitsselectthechannelfora single-conversion orthehighestchannelfora sequence ofconversions.Readingthesebitsin ADC10CONSEQ = 01,11returnsthechannelcurrentlyconverted.ADC10INCHx isnotsynchronized,so a readwhilethestatemachine isnotin"waitforenable" or"waitfortrigger"couldleadtoa wrong result. Can be modifiedonlywhen ADC10ENC = 0.ResettingADC10ENC = 0 by softwareand changingthesefieldsimmediatelyshows effectalsowhen a conversionisactive. 0000b = A0 0001b = A1 0010b = A2 0011b = A3 0100b = A4 0101b = A5 0110b = A6 0111b = A7 1000b = A8 1001b = A9 1010b = A10 1011b = A11 1100b = A12 1101b = A13 1110b = A14 1111b = A15

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19.3.7 ADC10HI Register

ADC10_A Window ComparatorHighThresholdRegister Figure19-18.ADC10HI Register 15 14 13 12 11 10 9 8 Reserved High_Threshold r0 r0 r0 r0 r0 r0 rw-(1) rw-(1) 7 6 5 4 3 2 1 0 High_Threshold rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) Table19-9.ADC10HI RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9-0 High_Threshold RW 3FFh The 10-bitthresholdvalueneeds tobe rightjustified.Bit9 istheMSB. Bits 15–10 are0 in10-bitmode, and bits15–8 are0 in8-bitmode. Thisdataformat isused ifADC10DF = 0.

19.3.8 ADC10HI Register,2s-Complement Format

ADC10_A Window ComparatorHighThresholdRegister,2s-ComplementFormat Figure19-19.ADC10HI Register 15 14 13 12 11 10 9 8 High_Threshold rw-(0) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) rw-(1) 7 6 5 4 3 2 1 0 High_Threshold Reserved rw-(1) rw-(1) r0 r0 r0 r0 r0 r0 Table19-10.ADC10HI RegisterDescription Bit Field Type Reset Description 15-6 High_Threshold RW 1FFh The 10-bitthresholdvalueneeds tobe leftjustifiedif2s-complementformatis chosen.Bit15 istheMSB. Bits5–0 are0 in10-bitmode, and bits7–0 are0 in8- bitmode. Thisdataformatisused ifADC10DF = 1. 5-0 Reserved R 0h Reserved.Alwaysreadsas 0. 527SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3.9 ADC10LO Register

ADC10_A Window ComparatorLow ThresholdRegister Figure19-20.ADC10LO Register 15 14 13 12 11 10 9 8 Reserved Low_Threshold r0 r0 r0 r0 r0 r0 rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Low_Threshold rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table19-11.ADC10LO RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0. 9-0 Low_Threshold RW 0h The 10-bitthresholdvalueneeds tobe rightjustified.Bit9 istheMSB. Bits 15–10 are0 in10-bitmode, and bits15–8 are0 in8-bitmode. Thisdataformat isused ifADC10DF = 0.

19.3.10 ADC10LO Register,2s-Complement Format

ADC10_A Window ComparatorLow ThresholdRegister,2s-ComplementFormat Figure19-21.ADC10LO Register 15 14 13 12 11 10 9 8 Low_Threshold rw-(1) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 Low_Threshold Reserved rw-(0) rw-(0) r0 r0 r0 r0 r0 r0 Table19-12.ADC10LO RegisterDescription Bit Field Type Reset Description 15-6 Low_Threshold RW 200h The 10-bitthresholdvalueneeds tobe leftjustifiedif2s-complementformatis chosen.Bit15 istheMSB. Bits5–0 are0 in10-bitmode, and bits7–0 are0 in8- bitmode. Thisdataformatisused ifADC10DF = 1. 5-0 Reserved R 0h Reserved.Alwaysreadsas 0.

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19.3.11 ADC10IE Register

ADC10_A InterruptEnableRegister Figure19-22.ADC10IE Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved ADC10TOVIE ADC10OVIE ADC10HIIE ADC10LOIE ADC10INIE ADC10IE0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table19-13.ADC10IE RegisterDescription Bit Field Type Reset Description 15-6 Reserved R 0h Reserved.Alwaysreadsas 0. 5 ADC10TOVIE RW 0h ADC10_A conversion-time-overflowInterruptenable. 0b = ConversiontimeoverflowInterruptdisabled 1b = ConversiontimeoverflowInterruptenabled 4 ADC10OVIE RW 0h ADC10MEM0 overflowInterruptenable. 0b = OverflowInterruptdisabled 1b = OverflowInterruptenabled

3 ADC10HIIE RW 0h Interruptenablefortheabove upperthresholdInterruptoftheWindow

comparator. 0b = Above upperthresholdInterruptdisabled 1b = Above upperthresholdInterruptenabled

2 ADC10LOIE RW 0h InterruptenableforthebelowlowerthresholdInterruptoftheWindow

comparator. 0b = Below lowerthresholdInterruptdisabled 1b = Below lowerthresholdInterruptenabled 1 ADC10INIE RW 0h Interruptenablefortheinsideofwindow InterruptoftheWindow comparator. 0b = Insideofwindow Interruptdisabled 1b = Insideofwindow Interruptenabled 0 ADC10IE0 RW 0h Interruptenable.ThisbitsenableordisabletheInterruptrequestfora completed ADC10_A conversion. 0b = Interruptdisabled 1b = Interruptenabled 529SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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19.3.12 ADC10IFG Register

ADC10_A InterruptFlagRegister Figure19-23.ADC10IFG Register 15 14 13 12 11 10 9 8 Reserved r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 Reserved ADC10TOVIFG ADC10OVIFG ADC10HIIFG ADC10LOIFG ADC10INIFG ADC10IFG0 r0 r0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table19-14.ADC10IFG RegisterDescription Bit Field Type Reset Description 15-6 Reserved R 0h Reserved.Alwaysreadsas 0.

5 ADC10TOVIFG RW 0h The ADC10TOVIFG issetwhen an ADC10_A conversionistriggeredbeforethe

actualconversionhas completed. 0b = No Interruptpending 1b = Interruptpending

4 ADC10OVIFG RW 0h The ADC10OVIFG issetwhen theADC10MEM0 registeriswrittenbeforethe

lastconversionresulthas been read. 0b = No Interruptpending 1b = Interruptpending

3 ADC10HIIFG RW 0h The ADC10HIIFG issetwhen theresultofthecurrentADC10_A conversionis

greaterthantheupperthresholddefinedby theWindow Comparatorsupper thresholdregister. 0b = No Interruptpending 1b = Interruptpending

2 ADC10LOIFG RW 0h The ADC10LOIFG issetwhen theresultofthecurrentADC10_A conversionis

belowthelowerthresholddefinedby theWindow Comparatorslowerthreshold register. 0b = No Interruptpending 1b = Interruptpending

1 ADC10INIFG RW 0h The ADC10INIFG issetwhen theresultofthecurrentADC10_A conversionis

withinthethresholdsdefinedby theWindow Comparatorsthresholdregisters. 0b = No Interruptpending 1b = Interruptpending 0 ADC10IFG0 RW 0h The ADC10IFG0 issetwhen an ADC10_A conversioniscompleted.Thisbitgets reset,when theADC10MEM0 getread,ormay be resetby software. 0b = No Interruptpending 1b = Interruptpending

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19.3.13 ADC10IV Register

ADC10_A InterruptVectorRegister Figure19-24.ADC10IV Register 15 14 13 12 11 10 9 8 ADC10IVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 ADC10IVx r0 r0 r0 r0 r-(0) r-(0) r-(0) r0 Table19-15.ADC10IV RegisterDescription Bit Field Type Reset Description 15-0 ADC10IVx R 0h ADC10_A Interruptvectorvalue.Itgeneratesan valuethatcan be used as addressoffsetforfastinterruptserviceroutinehandling.Writingtothisregister clearsallpendinginterruptflags. 00h = No interruptpending 02h = InterruptSource:ADC10MEM0 overflow;InterruptFlag:ADC10OVIFG; InterruptPriority:Highest 04h = InterruptSource:Conversiontimeoverflow;InterruptFlag:ADC10TOVIFG 06h = InterruptSource:ADC10HI Interruptflag;InterruptFlag:ADC10HIIFG 08h = InterruptSource:ADC10LO Interruptflag;InterruptFlag:ADC10LOIFG 0Ah = InterruptSource:ADC10IN Interruptflag;InterruptFlag:ADC10INIFG 0Ch = InterruptSource:ADC10_A memory Interruptflag;InterruptFlag: ADC10IFG0; InterruptPriority:Lowest 531SLAU259E –May 2009–RevisedJanuary2013 ADC10_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter20 SLAU259E –May 2009–RevisedJanuary2013 ADC12_A The ADC12_A module is a high-performance12-bitanalog-to-digitalconverter(ADC). This chapter describestheoperationoftheADC12_A module.

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20.1 ADC12_A Introduction

The ADC12_A module supportsfast12-bitanalog-to-digitalconversions.The module implementsa 12-bit SAR core,sample selectcontrol,referencegenerator(MSP430F54xx (non-Aonly)– inotherdevices, separateREF module),and a 16-wordconversion-and-controlbuffer.The conversion-and-controlbuffer allowsup to16 independentanalog-to-digitalconverter(ADC) samplestobe convertedand storedwithout any CPU intervention. ADC12_A featuresinclude:

Greaterthan200-kspsmaximum conversionrate
Monotonic12-bitconverterwithno missingcodes
Sample-and-holdwithprogrammablesamplingperiodscontrolledby softwareortimers
Conversioninitiationby softwareortimers
Software-selectableon-chipreferencevoltagegeneration(MSP430F54xx (non-Aonly):1.5V or2.5V, allotherdevices:1.5V,2.0V,or2.5V)
Software-selectableinternalorexternalreference
Up to12 individuallyconfigurableexternalinputchannels
Conversionchannelsforinternaltemperaturesensor,AV CC ,and externalreferences
Independentchannel-selectablereferencesourcesforbothpositiveand negativereferences
Selectableconversionclocksource
Single-channel,repeat-single-channel,sequence (autoscan),and repeat-sequence(repeated autoscan)conversionmodes
ADC coreand referencevoltagecan be powered down separately
Interruptvectorregisterforfastdecodingof18 ADC interrupts
16 conversion-resultstorageregisters The blockdiagramofADC12_A isshown inFigure20-1.InMSP430F54xx (non-Aonly),thereference generatorislocatedintheADC12_A module itself.Inotherdevices,thereferencegeneratorislocatedin thereferencemodule,REF. See theREF module chapterand thedevice-specificdatasheetforfurther details.Figure20-1shows theblockdiagramfordevicesthathave theREF module available.Figure20-2 shows theblockdiagramfortheMSP430F54xx (non-Aonly)whichdoes notincorporatetheREF module. 533SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

/4 ../1024 ADC12BUSY ADC12ISSH SHI ADC12SHTx ADC12MSC Divider /1 .. /8 ADC12CLK ADC12DIVx Ref_x on Reference* AVCC1 ACLK MCLK SMCLK ADC12OSC (see Note A) ADC12SSELx Sync R R AVCC AVSS Ref_x INCHx = 0Bh 16 x 8 Memory Control Timer sources (see Note B) ADC12SHSx ADC12SC ADC12MCTL0 ADC12MCTL15 16 x 12 Memory Buffer ADC12MEM0 ADC12MEM15 CSTARTADDx CONSEQx ADC12SHP ADC12SHT0x 4A12 A13 A14 A15 ADC12PDIV REFOUT* ADC12ENC 1.5/2.0/2.5 V REFMSTR* ADC12REFOUT 1 0 REFVSELx* REFMSTR* ADC12REF2_5V 1 0 REFON* REFMSTR* ADC12REFON 1 0 AVSS Temp. Sensor* 1 0 REFTCOFF* REFMSTR* ADC12TCOFF EN * Resides in REF module. ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Introduction www.ti.com A The MODOSC ispartoftheUCS. See theUCS chapterformore information. B See thedevice-specificdatasheetfortimersourcesavailable. Figure20-1.ADC12_A Block Diagram (DevicesWith REF Module)

534 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

/4 ../1024 ADC12BUSY ADC12ISSH SHI ADC12SHTx ADC12MSC Divider /1 .. /8 ADC12CLK ADC12DIVx Ref_x on 1.5V or2.5 V Reference AVCC ADC12REF2_5V ACLK MCLK SMCLK ADC12OSC (see Note A) ADC12SSELx Sync ADC12REFON R R AVCC AVSS Ref_x INCHx = 0Bh 16 x 8 Memory Control Timer sources (see Note B) ADC12SHSx ADC12SC ADC12MCTL0 ADC12MCTL15 16 x 12 Memory Buffer ADC12MEM0 ADC12MEM15 CSTARTADDx CONSEQx ADC12SHP ADC12SHT0x 4A12 A13 A14 A15 ADC12PDIV AVSS ADC12ENC Temp. Sensor EN ADC12TCOFF INCHx = 0Ah ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Introduction A The MODOSC ispartoftheUCS. See theUCS chapterformore information. B See thedevice-specificdatasheetfortimersourcesavailable. Figure20-2.ADC12_A MSP430F54xx (non-A)Block Diagram 535SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

R ~ 100 /c87 ADC12MCTLx.0–3 InputAx N = 4095 ×ADC Vin – V R– V – VR+ R– ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com

20.2 ADC12_A Operation

The ADC12_A module isconfiguredwithusersoftware.The setupand operationoftheADC12_A is discussedinthefollowingsections. 20.2.1 12-BitADC Core The ADC coreconvertsan analoginputtoits12-bitdigitalrepresentationand storestheresultin conversionmemory. The coreuses two programmableand selectablevoltagelevels(VR+ and VR-)to definetheupperand lowerlimitsoftheconversion.The digitaloutput(NADC )isfullscale(0FFFh)when the inputsignalisequaltoorhigherthanVR+ .The digitaloutput(NADC )iszerowhen theinputsignalisequal toorlowerthanVR-.The inputchanneland thereferencevoltagelevels(VR+ and VR-)aredefinedinthe conversion-controlmemory. The conversionformulafortheADC resultN ADC is: The ADC12_A coreisconfiguredby two controlregisters,ADC12CTL0 and ADC12CTL1. The coreis enabledwiththeADC12ON bit.The ADC12_A can be turnedoffwhen itisnotinuse tosave power.With few exceptions,theADC12_A controlbitscan be modifiedonlywhen ADC12ENC = 0.ADC12ENC must be setto1 beforeany conversioncan takeplace. 20.2.1.1Conversion Clock Selection The ADC12CLK isused bothas theconversionclockand togeneratethesamplingperiodwhen thepulse samplingmode isselected.The ADC12_A sourceclockisselectedusingthepredividercontrolledby the ADC12PDIV bitand thedividerusingtheADC12SSELx bits.The inputclockcan be dividedfrom1 to32 usingboththeADC12DIVx bitsand theADC12PDIV bit.PossibleADC12CLK sourcesareSMCLK, MCLK, ACLK, and theADC12OSC. The ADC12OSC intheblockdiagram(seeFigure20-1)referstotheMODOSC 5-MHz oscillatorfromthe UCS (seetheUCS module formore information)whichcan varywithindividualdevices,supplyvoltage, and temperature.See thedevice-specificdatasheetfortheADC12OSC specification. The usermust ensurethattheclockchosen forADC12CLK remainsactiveuntiltheend ofa conversion.If theclockisremoved duringa conversion,theoperationdoes notcompleteand theresultsareinvalid.

20.2.2 ADC12_A Inputsand Multiplexer

The 12 externaland 4 internalanalogsignalsareselectedas thechannelforconversionby theanalog inputmultiplexer.The inputmultiplexerisa break-before-maketypetoreduceinput-to-inputnoiseinjection resultingfromchannelswitching(seeFigure20-3).The inputmultiplexerisalsoa T-switchtominimizethe couplingbetween channels.ChannelsthatarenotselectedareisolatedfromtheA/D and theintermediate node isconnectedtoanalogground(AVSS ),so thatthestraycapacitanceisgroundedtoeliminate crosstalk. The ADC12_A uses thechargeredistributionmethod.When theinputsareinternallyswitched,the switchingactionmay cause transientson theinputsignal.These transientsdecay and settlebefore causingerrantconversion. Figure20-3.Analog Multiplexer

536 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation 20.2.2.1Analog PortSelection The ADC12_A inputsaremultiplexedwithdigitalportpins.When analogsignalsareappliedtodigital gates,parasiticcurrentcan flowfromVCC toGND. Thisparasiticcurrentoccursiftheinputvoltageisnear thetransitionlevelofthegate.Disablingthedigitalpartoftheportpineliminatestheparasiticcurrentflow and,therefore,reducesoverallcurrentconsumption.The PySELx bitsprovidetheabilitytodisablethe portpininputand outputbuffers. ;Py.0andPy.1configuredforanaloginput BIS.B#3h,&PySEL;Py.1andPy.0ADC12_Afunction

20.2.3 VoltageReferenceGenerator

The ADC12_A modules have a separatereferencemodule (REF) thatsuppliesthreeselectablevoltage levels,1.5V,2.0V,and 2.5V totheADC12_A. Any ofthesevoltagesmay be used internallyand externallyon pinVREF+. The internalAV CC can alsobe used as thereference. The ADC12_A module oftheMSP430F54xx devices(non-Aonly)does notuse theREF module and only has two selectablevoltagelevels,1.5V and 2.5V.The internalAV CC can alsobe used as thereference. On deviceswiththeREF module,thevoltagereferencesettingscan be controlledeitherby theREF module orby theADC12_A module.Thisistoallowforbackwardcompatabilitywitholderfamilies.Thisis handledby theREFMSTR bitintheREF module.IfREFMSTR = 1 (default),theREF module registers controlthereferencesettings.IfREFMSTR = 0,theADC12_A referencesettingdefinethereference voltageoftheADC12_A module.FourcontrolsettingsthatresideintheADC12_A can be controlledalso by fourcorrespondingsettingsintheREF module:ADC12REF2_5V (REFVSEL), ADC12REFON (REFON), ADC12REFOUT (REFOUT), and ADC12TCOFF (REFTCOFF), respectively.When REFMSTR = 1,ADC12REF2_5V, ADC12REFON, ADC12REFOUT, and ADC12TCOFF aredo notcare.Similarly, when REFMSTR = 0,REFVSEL, REFON, REFOUT, and REFTCOFF aredo notcare.See theREF module chapterforfurtherdetails. On deviceswiththeREF module,touse theADC12_A referencecontrolbits,setREFMSTR = 0.Inthis case,settingADC12REFON = 1 enablesthereferencevoltageoftheADC12_A module.When ADC12REF2_5V = 1,theinternalreferenceis2.5V;when ADC12REF2_5V = 0,thereferenceis1.5V. Similarly,on deviceswiththeREF module,touse theREF module referencecontrolbits,setREFMSTR = 1.Inthiscase,settingREFON = 1 oftheREF module enablesthereferencevoltage.The REFVSEL bits oftheREF module can be used toselecteither1.5V,2.0V,or2.5V.The referencecan be turnedoffto save power when notinuse.On theMSP430F54xx devices(non-Aonly),as statedpreviously,theREF module isnotpresentand behaves thesame as devicestheREF module withREFMSTR = 0. Externalreferencesmay be suppliedforVR+ and VR- throughpinsVREF+/VeREF+ and VREF-/VeREF-, respectively. ExternalstoragecapacitorsarerequiredonlyifADC12REFOUT = 1 (REFOUT = 1 when usingREF module)and thereferencevoltageismade availableatthepins. 20.2.3.1InternalReferenceLow-Power Features The ADC12_A internalreferencegeneratorisdesignedforlow-powerapplications.The reference generatorincludesa bandgap voltagesourceand a separatebuffer.The currentconsumptionand settling timeofeach isspecifiedseparatelyinthedevice-specificdatasheet.When ADC12REFON = 1 (REFON = 1 when usingREF module),bothareenabled;when ADC12REFON = 0 (REFON = 0 when usingREF module),botharedisabled. When ADC12REFON = 1 (REFON = 1 when usingREF module)and ADC12REFBURST = 1 butno conversionisactive,thebufferisautomaticallydisabledand automaticallyreenabledwhen needed.When thebufferisdisabled,itconsumes no current.Inthiscase,thebandgap voltagesourceremainsenabled. The ADC12REFBURST bitcontrolstheoperationofthereferencebuffer.When ADC12REFBURST = 1, thebufferisautomaticallydisabledwhen theADC12_A isnotactivelyconverting,and isautomatically reenabledwhen needed.When ADC12REFBURST = 0,thebufferison continuously.Thisallowsthe referencevoltagetobe presentoutsidethedevicecontinuouslyifADC12REFOUT = 1 (REFOUT = 1 when usingREF module). 537SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

13 × ADC12CLK Start Conversion ADC12CLK ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com The internalreferencebufferalsohas selectablespeed versuspower settings.When themaximum conversionrateisbelow50 ksps,settingADC12SR = 1 reducesthecurrentconsumptionofthebufferby approximately50%.

20.2.4 Auto Power Down

The ADC12_A isdesignedforlow-powerapplications.When theADC12_A isnotactivelyconverting,the coreisautomaticallydisabled,and itisautomaticallyreenabledwhen needed.The MODOSC isalso automaticallyenabledwhen needed and disabledwhen notneeded.

20.2.5 Sample and Conversion Timing

An analog-to-digitalconversionisinitiatedwitha risingedge ofthesample inputsignalSHI.The source forSHI isselectedwiththeSHSx bitsand includesthefollowing:

ADC12SC bit
Up tothreetimeroutputs(seethedevice-specificdatasheetforavailabletimersources) The ADC12_A supports8-bit,10-bit,and 12-bitresolutionmodes selectableby theADC12RES bits.The analog-to-digitalconversionrequires9,11,and 13 ADC12CLK cycles,respectively.The polarityoftheSHI signalsourcecan be invertedwiththeADC12ISSH bit.The SAMPCON signalcontrolsthesample period and startofconversion.When SAMPCON ishigh,samplingisactive.The high-to-lowSAMPCON transitionstartstheanalog-to-digitalconversion.Two differentsample-timingmethods aredefinedby controlbitADC12SHP, extendedsample mode, and pulsemode. See thedevice-specificdatasheetfor availabletimersforSHI sources. 20.2.5.1Extended Sample Mode The extendedsample mode isselectedwhen ADC12SHP = 0.The SHI signaldirectlycontrolsSAMPCON and definesthelengthofthesample periodtsample.When SAMPCON ishigh,samplingisactive.The high- to-lowSAMPCON transitionstartstheconversionaftersynchronizationwithADC12CLK (seeFigure20-4). Figure20-4.Extended Sample Mode 20.2.5.2Pulse Sample Mode SetADC12SHP = 1 toselectthepulsesample mode. The SHI signalisused totriggerthesamplingtimer. The ADC12SHT0x and ADC12SHT1x bitsinADC12CTL0 controltheintervalofthesamplingtimerthat definestheSAMPCON sample periodtsample.The samplingtimerkeeps SAMPCON highafter synchronizationwithAD12CLK fora programmed intervaltsample.The totalsamplingtimeistsample plustsync (seeFigure20-5). The ADC12SHTx bitsselectthesamplingtimein4× multiplesofADC12CLK. ADC12SHT0x selectsthe samplingtimeforADC12MCTL0 toADC12MCTL7. ADC12SHT1x selectsthesamplingtimefor ADC12MCTL8 toADC12MCTL15.

538 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

V = Input voltage at pin Ax V = External source voltage R = External source resistance R = Internal MUX-on input resistance C = Input capacitance V = Capacitance-charging voltage I S S I I C MSP430 Start Sampling Stop Sampling Conversion Complete SAMPCON SHI tsample tconvert tsync 13 × ADC12CLK Start Conversion ADC12CLK ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation Figure20-5.Pulse Sample Mode 20.2.5.3Sample Timing Considerations When SAMPCON = 0,allAx inputsarehighimpedance.When SAMPCON = 1,theselectedAx inputcan be modeled as an RC low-passfilterduringthesamplingtimetsample (seeFigure20-6).An internalMUX-on inputresistanceR I (maximum 1.8kΩ)inserieswithcapacitorC I (25pF maximum) isseen by thesource. The capacitorC I voltageVC must be chargedtowithinone-halfLSB ofthesourcevoltageVS foran accuraten-bitconversion,where n isthebitsofresolutionrequired. Figure20-6.Analog InputEquivalentCircuit The resistanceofthesourceR S and R I affecttsample.The followingequationcan be used tocalculatethe minimum samplingtimetsample fora n-bitconversion,where n equalsthebitsofresolution: tsample > (RS + R I)× ln(2n+1)× C I + 800 ns SubstitutingthevaluesforR I and C I givenabove,theequationbecomes: tsample > (RS + 1.8kΩ)× ln(2n+1)× 25 pF + 800 ns Forexample,for12-bitresolution,ifR S is10 kΩ,tsample must be greaterthan3.46μs. 539SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com

20.2.6 Conversion Memory

Thereare16 ADC12MEMx conversionmemory registerstostoreconversionresults.Each ADC12MEMx isconfiguredwithan associatedADC12MCTLx controlregister.The SREFx bitsdefinethevoltage referenceand theINCHx bitsselecttheinputchannel.The ADC12EOS bitdefinestheend ofsequence when a sequentialconversionmode isused.A sequence rollsoverfromADC12MEM15 toADC12MEM0 when theADC12EOS bitinADC12MCTL15 isnotset. The CSTARTADDx bitsdefinethefirstADC12MCTLx used forany conversion.Iftheconversionmode is single-channelorrepeat-single-channel,theCSTARTADDx pointstothesingleADC12MCTLx tobe used. Iftheconversionmode selectediseithersequence-of-channelsorrepeat-sequence-of-channels, CSTARTADDx pointstothefirstADC12MCTLx locationtobe used ina sequence.A pointer,notvisibleto software,isincrementedautomaticallytothenextADC12MCTLx ina sequence when each conversion completes.The sequence continuesuntilan ADC12EOS bitinADC12MCTLx isprocessed;thisisthelast controlbyteprocessed. When conversionresultsarewrittentoa selectedADC12MEMx, thecorrespondingflagintheADC12IFGx registerisset. Therearetwo formatsavailabletostoretheconversionresult,ADC12MEMx. When ADC12DF = 0,the conversionisrightjustified,unsigned.For8-bit,10-bit,and 12-bitresolutions,theupper8,6,and 4 bitsof ADC12MEMx arealwayszeros,respectively.When ADC12DF = 1,theconversionresultisleftjustified, two'scomplement.For8-bit,10-bit,and 12-bitresolutions,thelower8,6,and 4 bitsofADC12MEMx are alwayszeros,respectively.Thisissummarized inTable20-1. Table20-1.ADC12_A Conversion ResultFormats Analog Input ADC12DF ADC12RES IdealConversion Results ADC12MEMxVoltage 0 00 0 to255 0000h -00FFh 0 01 0 to1023 0000h -03FFh 0 10 0 to4095 0000h -0FFFh –VREF to+VREF 1 00 -128to127 8000h -7F00h 1 01 -512to511 8000h -7FC0h 1 10 -2048to2047 8000h -7FF0h

20.2.7 ADC12_A Conversion Modes

The ADC12_A has fouroperatingmodes selectedby theCONSEQx bitsas listedinTable20-2.Allstate diagramsassume a 12-bitresolutionsetting. Table20-2.Conversion Mode Summary ADC12CONSEQx Mode Operation 00 Single-channelsingle-conversion A singlechannelisconvertedonce. 01 Sequence-of-channels(autoscan) A sequence ofchannelsisconvertedonce. 10 Repeat-single-channel A singlechannelisconvertedrepeatedly. 11 Repeat-sequence-of-channels A sequence ofchannelsisconvertedrepeatedly. (repeatedautoscan)

540 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

x = CST ART ADDx Wait for Enable Wait for Trigger Sample, Input Channel Defined in ADC12MCTLx SAMPCON = SAMPCON = 1 Convert SAMPCON = ADC12ENC = 0 ADC12ENC = 0 (see Note A) 12 × ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set 1 × ADC12CLK ADC12ON = 1 CONSEQx = 00 x = pointer to ADC12MCTLx ADC12ENC /c185 ADC12ENC = ADC12ENC = ADC12ENC = 0 (see Note A) SHSx = 0 and ADC12ENC = 1 or and ADC12SC = ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation 20.2.7.1Single-ChannelSingle-ConversionMode A singlechannelissampled and convertedonce.The ADC resultiswrittentotheADC12MEMx defined by theCSTARTADDx bits.Figure20-7shows theflowofthesingle-channelsingle-conversionmode. When ADC12SC triggersa conversion,successiveconversionscan be triggeredby theADC12SC bit. When any othertriggersourceisused,ADC12ENC must be toggledbetween each conversion. A Conversionresultisunpredictable. Figure20-7.Single-ChannelSingle-ConversionMode 541SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

x = CST ART ADDx Wait for Enable ADC12ENC /c185 Wait for Trigger Sample, Input Channel Defined in ADC12MCTLx ADC12ENC =SHSx = 0 and ADC12ENC = 1 or and ADC12SC = SAMPCON = SAMPCON = 1 Convert SAMPCON = 12 × ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set 1 × ADC12CLK ADC12ON = 1 CONSEQx = 01 ADC12MSC = 1 and ADC12SHP = 1 and ADC12EOS.x = 0 ADC12EOS.x = 1 If x < 15 then x = x + 1 else x = 0 If x < 15 then x = x + 1 else x = 0 (ADC12MSC = 0 or ADC12SHP = 0) and ADC12EOS.x = 0 x = pointer to ADC12MCTLx ADC12ENC = ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com 20.2.7.2Sequence-of-ChannelsMode (Autoscan Mode) Insequence-of-channelsmode, alsoreferredtoas autoscanmode, a sequence ofchannelsissampled and convertedonce.The ADC resultsarewrittentotheconversionmemories startingwiththeADCMEMx definedby theCSTARTADDx bits.The sequence stopsafterthemeasurement ofthechannelwitha set ADC12EOS bit.Figure20-8shows thesequence-of-channelsmode. When ADC12SC triggersa sequence,successivesequencescan be triggeredby theADC12SC bit.The ADC12SC must be cleared by softwareaftereach sequence totriggeranothersequence.When any othertriggersourceisused, ADC12ENC must be toggledbetween each sequence. Figure20-8.Sequence-of-ChannelsMode

542 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

x = CST ART ADDx Wait for Enable ADC12ENC /c185 Wait for Trigger Sample, Input Channel Defined in ADC12MCTLx ADC12 ENC = ADC12 ENC =SHSx = 0 and ADC12ENC = 1 or and ADC12SC = SAMPCON = SAMPCON = 1 Convert SAMPCON = 12 × ADC12CLK Conversion Completed, Result Stored Into ADC12MEMx, ADC12IFG.x is Set 1 × ADC12CLK ADC12ON = 1 CONSEQx = 10 ADC12MSC = 1 and ADC12SHP = 1 and ADC12ENC = 1 ADC12ENC = 0 (ADC12MSC = 0 or ADC12SHP = 0) and ADC12ENC = 1 x = pointer to ADC12MCTLx ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation 20.2.7.3Repeat-Single-ChannelMode A singlechannelissampled and convertedcontinuously.The ADC resultsarewrittentotheADC12MEMx definedby theCSTARTADDx bits.Itisnecessarytoreadtheresultafterthecompletedconversion because onlyone ADC12MEMx memory isused and isoverwrittenby thenextconversion.Figure20-9 shows therepeat-single-channelmode. Figure20-9.Repeat-Single-ChannelMode 543SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

x = CST ART ADDx Wait for Enable ADC12ENC /c185 Wait for Trigger Sample, Input Channel Defined in ADC12MCTLx SHSx = 0 and ADC12ENC = 1 or and ADC12SC = SAMPCON□= SAMPCON□=□1 SAMPCON□= 12 × ADC12CLK Conversion□Completed, Result□Stored□Into ADC12MEMx, ADC12IFG.x□is□Set 1 × ADC12CLK ADC12ON = 1 CONSEQx = 1 1 ADC12MSC□=□1□and ADC12SHP =□1 and□(ADC12ENC□=□1□or ADC12EOS.x□=□0) ADC12ENC□=□0 and ADC12EOS.x□=□1 (ADC12MSC□=□0 or ADC12SHP =□0) and (ADC12ENC□=□1 or ADC12EOS.x□=□0) If ADC12EOS.x = 1 then x =CST ART ADDx else {if x < 15 then x = x + 1 else x = 0} If ADC12EOS.x = 1 then x =CST ART ADDx else {if x < 15 then x = x + 1 else x = 0} Convert ADC12ENC□□= ADC12ENC□□= x□=□pointer□to ADC12MCTLx ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com 20.2.7.4Repeat-Sequence-of-ChannelsMode (RepeatedAutoscan Mode) Inthismode, a sequence ofchannelsissampled and convertedrepeatedly.Thismode isalsoreferredto as repeatedautoscanmode. The ADC resultsarewrittentotheconversionmemories startingwiththe ADC12MEMx definedby theCSTARTADDx bits.The sequence ends afterthemeasurement ofthe channelwitha setADC12EOS bitand thenexttriggersignalrestartsthesequence.Figure20-10shows therepeat-sequence-of-channelsmode. Figure20-10.Repeat-Sequence-of-ChannelsMode

544 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation 20.2.7.5Using theMultipleSample and Convert (ADC12MSC) Bit To configuretheconvertertoperformsuccessiveconversionsautomaticallyand as quicklyas possible,a multiplesample and convertfunctionisavailable.When ADC12MSC = 1,CONSEQx > 0,and thesample timerisused,thefirstrisingedge oftheSHI signaltriggersthefirstconversion.Successiveconversions aretriggeredautomaticallyas soon as thepriorconversioniscompleted.Additionalrisingedges on SHI areignoreduntilthesequence iscompletedinthesingle-sequencemode, oruntiltheADC12ENC bitis toggledinrepeat-single-channelorrepeated-sequencemodes. The functionoftheADC12ENC bitis unchanged when usingtheADC12MSC bit. 20.2.7.6Stopping Conversions StoppingADC12_A activitydepends on themode ofoperation.The recommended ways tostopan active conversionorconversionsequence are:

ResettingADC12ENC insingle-channelsingle-conversionmode stopsa conversionimmediatelyand theresultsareunpredictable.Forcorrectresults,pollthebusy bituntilresetbeforeclearing ADC12ENC.
ResettingADC12ENC duringrepeat-single-channeloperationstopstheconverterattheend ofthe currentconversion.
ResettingADC12ENC duringa sequence orrepeat-sequencemode stopstheconverterattheend of thesequence.
Any conversionmode may be stoppedimmediatelyby settingtheCONSEQx = 0 and resettingthe ADC12ENC bit.Conversiondataareunreliable. NOTE: No ADC12EOS bitsetforsequence Ifno ADC12EOS bitissetand a sequence mode isselected,resettingtheADC12ENC bit does notstopthesequence.To stopthesequence,firstselecta single-channelmode and thenresetADC12ENC. 545SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0.550 0.600 0.650 0.700 0.750 0.800 0.850 0.900 −40 −20 0 20 40 60 80 100 Ambient□Temperature – °C Typical□Temperature□Sensor□Voltage – V 0.950 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com

20.2.8 Using theIntegratedTemperature Sensor

To use theon-chiptemperaturesensor,theuserselectstheanaloginputchannelINCHx = 1010.Any otherconfigurationisdone as ifan externalchannelwere selected,includingreferenceselection, conversion-memoryselection,etc.The temperaturesensorispartofthereference.Therefore,fordevices withtheREF module,inadditiontotheinputchannelsselectionINCHx = 1010,configuring ADC12REFON = 1 (forREFMSTR = 0)orREFON = 1 (forREFMSTR = 1)isrequiredtoenablethe temperaturesensor. FortheMSP430F54xx (non-A)devices,whichdo notincludetheREF module,selectingthetemperature sensorby configuringINCHx = 1010 automaticallyenablesthereferencegeneratorrequiredforthe temperaturesensor.Any otherconfigurationisdone as ifan externalchannelwere selected,included referenceselection,conversion-memoryselection,etc. A typicaltemperaturesensortransferfunctionisshown inFigure20-11.The transferfunctionshown in Figure20-11isonlyan example— thedevice-specificdatasheetcontainstheactualparametersfora givendevice.When usingthetemperaturesensor,thesample periodmust be greaterthan30 μs.The temperaturesensoroffseterrorcan be largeand may need tobe calibratedformost applications. Temperaturecalibrationvaluesareavailableforuse intheTLV descriptors(seethedevice-specificdata sheetforlocations). Figure20-11.TypicalTemperature Sensor TransferFunction

546 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

100 nF10 F µ Analog Power Supply Decoupling Using an External Positive Reference Using an External Negative Reference DVCC DVSS A VCC A VSS V /VREF– eREF– V /VREF+ eREF + 100 nF10 F µ 100 nF10 F µ 100 nF10 F µ ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation

20.2.9 ADC12_A Grounding and Noise Considerations

As withany high-resolutionADC, appropriateprintedcircuitboardlayoutand groundingtechniquesshould be followedtoeliminategroundloops,unwanted parasiticeffects,and noise. Ground loopsareformedwhen returncurrentfromtheADC flowsthroughpathsthatarecommon with otheranalogordigitalcircuitry.Ifcareisnottaken,thiscurrentcan generatesmallunwanted offset voltagesthatcan add toorsubtractfromthereferenceorinputvoltagesoftheADC. The connections shown inFigure20-12preventthis. Inadditiontogrounding,rippleand noisespikeson thepower-supplylinesdue todigitalswitchingor switchingpower suppliescan corrupttheconversionresult.A noise-freedesignusingseparateanalogand digitalgroundplaneswitha single-pointconnectionisrecommend toachievehighaccuracy. Figure20-12.ADC12_A Grounding and Noise Considerations 547SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Operation www.ti.com

20.2.10 ADC12_A Interrupts

The ADC12_A has 18 interruptsources:

ADC12IFG0 toADC12IFG15
ADC12OV, ADC12MEMx overflow
ADC12TOV, ADC12_A conversiontimeoverflow The ADC12IFGx bitsaresetwhen theircorrespondingADC12MEMx memory registerisloadedwitha conversionresult.An interruptrequestisgeneratedifthecorrespondingADC12IEx bitand theGIE bitare set.The ADC12OV conditionoccurswhen a conversionresultiswrittentoany ADC12MEMx beforeits previousconversionresultwas read.The ADC12TOV conditionisgeneratedwhen anothersample-and- conversionisrequestedbeforethecurrentconversioniscompleted.The DMA istriggeredafterthe conversioninsingle-channelconversionmode orafterthecompletionofa sequence ofchannel conversionsinsequence-of-channelsconversionmode. 20.2.10.1ADC12IV, InterruptVectorGenerator AllADC12_A interruptsourcesareprioritizedand combined tosourcea singleinterruptvector.The interruptvectorregisterADC12IV isused todeterminewhichenabledADC12_A interruptsource requestedan interrupt. The highest-priorityenabledADC12_A interruptgeneratesa number intheADC12IV register(seeregister description).Thisnumber can be evaluatedoradded totheprogramcounter(PC)toautomaticallyenter theappropriatesoftwareroutine.DisabledADC12_A interruptsdo notaffecttheADC12IV value. Any access,readorwrite,oftheADC12IV registerautomaticallyresetstheADC12OV conditionorthe ADC12TOV condition,ifeitherwas thehighest-pendinginterrupt.Neitherinterruptconditionhas an accessibleinterruptflag.The ADC12IFGx flagsarenotresetby an ADC12IV access.ADC12IFGx bitsare resetautomaticallyby accessingtheirassociatedADC12MEMx registerormay be resetwithsoftware. Ifanotherinterruptispendingafterservicingofan interrupt,anotherinterruptisgenerated.Forexample,if theADC12OV and ADC12IFG3 interruptsarependingwhen theinterruptserviceroutineaccessesthe ADC12IV register,theADC12OV interruptconditionisresetautomatically.AftertheRETI instructionofthe interruptserviceroutineisexecuted,theADC12IFG3 generatesanotherinterrupt.

548 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Operation 20.2.10.2ADC12_A InterruptHandlingSoftwareExample The followingsoftwareexample shows therecommended use oftheADC12IV and handlingoverhead. The ADC12IV valueisadded tothePC toautomaticallyjump totheappropriateroutine. The numbers attherightmarginshow thenecessaryCPU cyclesforeach instruction.The software overheadfordifferentinterruptsourcesincludesinterruptlatencyand return-from-interruptcycles,butnot thetaskhandlingitself.The latenciesare:

ADC12IFG0 toADC12IFG14, ADC12TOV, and ADC12OV: 16 cycles
ADC12IFG15: 14 cycles The interrupthandlerforADC12IFG15 shows a way tocheckimmediatelyifa higher-prioritizedinterrupt occurredduringtheprocessingofADC12IFG15. ThissavesninecyclesifanotherADC12_A interruptis pending. ;InterrupthandlerforADC12. INT_ADC12 ;EnterInterruptServiceRoutine ADD &ADC12IV,PC;AddoffsettoPC RETI ;Vector0:Nointerrupt JMP ADOV ;Vector2:ADCoverflow JMP ADTOV ;Vector4:ADCtimingoverflow JMP ADM0 ;Vector6:ADC12IFG0 ... ;Vectors8-32 JMP ADM14 ;Vector34:ADC12IFG14 ;HandlerforADC12IFG15startshere.NoJMPrequired. ADM15MOV&ADC12MEM15,xxx;Moveresult,flagisreset ... ;Otherinstructionneeded? JMPINT_ADC12 ;Checkotherintpending ;ADC12IFG14-ADC12IFG1handlersgohere ADM0 MOV&ADC12MEM0,xxx;Moveresult,flagisreset ... ;Otherinstructionneeded? RETI ;Return ADTOV... ;HandleConv.timeoverflow RETI ;Return ADOV ... ;HandleADCMEMxoverflow RETI ;Return 549SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3 ADC12_A Registers

The ADC12_A registersarelistedinTable20-3.The base addressoftheADC12_A can be foundinthe device-specificdatasheet.The addressoffsetofeach ADC12_A registerisgiveninTable20-3. NOTE: Allregistershave word orbyteregisteraccess.Fora genericregisterANYREG ,thesuffix "_L"(ANYREG_L )referstothelowerbyteoftheregister(bits0 through7).The suffix"_H" (ANYREG_H )referstotheupperbyteoftheregister(bits8 through15). Table20-3.ADC12_A Registers Offset Acronym RegisterName Type Access Reset Section 00h ADC12CTL0 ADC12_A Control0 Read/write Word 0000h Section20.3.1 00h ADC12CTL0_L Read/write Byte 00h 01h ADC12CTL0_H Read/write Byte 00h 02h ADC12CTL1 ADC12_A Control1 Read/write Word 0000h Section20.3.2 02h ADC12CTL1_L Read/write Byte 00h 03h ADC12CTL1_H Read/write Byte 00h 04h ADC12CTL2 ADC12_A Control2 Read/write Word 0020h Section20.3.3 04h ADC12CTL2_L Read/write Byte 20h 05h ADC12CTL2_H Read/write Byte 00h 0Ah ADC12IFG ADC12_A InterruptFlag Read/write Word 0000h Section20.3.7 0Ah ADC12IFG_L Read/write Byte 00h 0Bh ADC12IFG_H Read/write Byte 00h 0Ch ADC12IE ADC12_A InterruptEnable Read/write Word 0000h Section20.3.6 0Ch ADC12IE_L Read/write Byte 00h 0Dh ADC12IE_H Read/write Byte 00h 0Eh ADC12IV ADC12_A InterruptVector Read Word 0000h Section20.3.8 0Eh ADC12IV_L Read Byte 00h 0Fh ADC12IV_H Read Byte 00h 20h ADC12MEM0 ADC12_A Memory 0 Read/write Word undefined Section20.3.4 20h ADC12MEM0_L Read/write Byte undefined 21h ADC12MEM0_H Read/write Byte undefined 22h ADC12MEM1 ADC12_A Memory 1 Read/write Word undefined Section20.3.4 22h ADC12MEM1_L Read/write Byte undefined 23h ADC12MEM1_H Read/write Byte undefined 24h ADC12MEM2 ADC12_A Memory 2 Read/write Word undefined Section20.3.4 24h ADC12MEM2_L Read/write Byte undefined 25h ADC12MEM2_H Read/write Byte undefined 26h ADC12MEM3 ADC12_A Memory 3 Read/write Word undefined Section20.3.4 26h ADC12MEM3_L Read/write Byte undefined 27h ADC12MEM3_H Read/write Byte undefined 28h ADC12MEM4 ADC12_A Memory 4 Read/write Word undefined Section20.3.4 28h ADC12MEM4_L Read/write Byte undefined 29h ADC12MEM4_H Read/write Byte undefined 2Ah ADC12MEM5 ADC12_A Memory 5 Read/write Word undefined Section20.3.4 2Ah ADC12MEM5_L Read/write Byte undefined 2Bh ADC12MEM5_H Read/write Byte undefined 2Ch ADC12MEM6 ADC12_A Memory 6 Read/write Word undefined Section20.3.4 2Ch ADC12MEM6_L Read/write Byte undefined 2Dh ADC12MEM6_H Read/write Byte undefined

550 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Registers Table20-3.ADC12_A Registers(continued) Offset Acronym RegisterName Type Access Reset Section 2Eh ADC12MEM7 ADC12_A Memory 7 Read/write Word undefined Section20.3.4 2Eh ADC12MEM7_L Read/write Byte undefined 2Fh ADC12MEM7_H Read/write Byte undefined 30h ADC12MEM8 ADC12_A Memory 8 Read/write Word undefined Section20.3.4 30h ADC12MEM8_L Read/write Byte undefined 31h ADC12MEM8_H Read/write Byte undefined 32h ADC12MEM9 ADC12_A Memory 9 Read/write Word undefined Section20.3.4 32h ADC12MEM9_L Read/write Byte undefined 33h ADC12MEM9_H Read/write Byte undefined 34h ADC12MEM10 ADC12_A Memory 10 Read/write Word undefined Section20.3.4 34h ADC12MEM10_L Read/write Byte undefined 35h ADC12MEM10_H Read/write Byte undefined 36h ADC12MEM11 ADC12_A Memory 11 Read/write Word undefined Section20.3.4 36h ADC12MEM11_L Read/write Byte undefined 37h ADC12MEM11_H Read/write Byte undefined 38h ADC12MEM12 ADC12_A Memory 12 Read/write Word undefined Section20.3.4 38h ADC12MEM12_L Read/write Byte undefined 39h ADC12MEM12_H Read/write Byte undefined 3Ah ADC12MEM13 ADC12_A Memory 13 Read/write Word undefined Section20.3.4 3Ah ADC12MEM13_L Read/write Byte undefined 3Bh ADC12MEM13_H Read/write Byte undefined 3Ch ADC12MEM14 ADC12_A Memory 14 Read/write Word undefined Section20.3.4 3Ch ADC12MEM14_L Read/write Byte undefined 3Dh ADC12MEM14_H Read/write Byte undefined 3Dh ADC12MEM15 ADC12_A Memory 15 Read/write Word undefined Section20.3.4 3Dh ADC12MEM15_L Read/write Byte undefined 3Eh ADC12MEM15_H Read/write Byte undefined 10h ADC12MCTL0 ADC12_A Memory Control0 Read/write Byte undefined Section20.3.5 11h ADC12MCTL1 ADC12_A Memory Control1 Read/write Byte undefined Section20.3.5 12h ADC12MCTL2 ADC12_A Memory Control2 Read/write Byte undefined Section20.3.5 13h ADC12MCTL3 ADC12_A Memory Control3 Read/write Byte undefined Section20.3.5 14h ADC12MCTL4 ADC12_A Memory Control4 Read/write Byte undefined Section20.3.5 15h ADC12MCTL5 ADC12_A Memory Control5 Read/write Byte undefined Section20.3.5 16h ADC12MCTL6 ADC12_A Memory Control6 Read/write Byte undefined Section20.3.5 17h ADC12MCTL7 ADC12_A Memory Control7 Read/write Byte undefined Section20.3.5 18h ADC12MCTL8 ADC12_A Memory Control8 Read/write Byte undefined Section20.3.5 19h ADC12MCTL9 ADC12_A Memory Control9 Read/write Byte undefined Section20.3.5 1Ah ADC12MCTL10 ADC12_A Memory Control10 Read/write Byte undefined Section20.3.5 1Bh ADC12MCTL11 ADC12_A Memory Control11 Read/write Byte undefined Section20.3.5 1Ch ADC12MCTL12 ADC12_A Memory Control12 Read/write Byte undefined Section20.3.5 1Dh ADC12MCTL13 ADC12_A Memory Control13 Read/write Byte undefined Section20.3.5 1Eh ADC12MCTL14 ADC12_A Memory Control14 Read/write Byte undefined Section20.3.5 1Fh ADC12MCTL15 ADC12_A Memory Control15 Read/write Byte undefined Section20.3.5 551SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3.1 ADC12CTL0 Register

ADC12_A ControlRegister0 Figure20-13.ADC12CTL0 Register 15 14 13 12 11 10 9 8 ADC12SHT1x ADC12SHT0x rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC12MSC ADC12REF2_5 ADC12REFON ADC12ON ADC12OVIE ADC12TOVIE ADC12ENC ADC12SC V rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Can be modifiedonlywhen ADC12ENC = 0 Table20-4.ADC12CTL0 RegisterDescription Bit Field Type Reset Description 15-12 ADC12SHT1x RW 0h ADC12_A sample-and-holdtime.These bitsdefinethenumber ofADC12CLK cyclesinthesamplingperiodforregistersADC12MEM8 toADC12MEM15. 11-8 ADC12SHT0x RW 0h ADC12_A sample-and-holdtime.These bitsdefinethenumber ofADC12CLK cyclesinthesamplingperiodforregistersADC12MEM0 toADC12MEM7. 0000b = 4 ADC12CLK cycles 0001b = 8 ADC12CLK cycles 0010b = 16 ADC12CLK cycles 0011b = 32 ADC12CLK cycles 0100b = 64 ADC12CLK cycles 0101b = 96 ADC12CLK cycles 0110b = 128 ADC12CLK cycles 0111b = 192 ADC12CLK cycles 1000b = 256 ADC12CLK cycles 1001b = 384 ADC12CLK cycles 1010b = 512 ADC12CLK cycles 1011b = 768 ADC12CLK cycles 1100b = 1024 ADC12CLK cycles 1101b = 1024 ADC12CLK cycles 1110b = 1024 ADC12CLK cycles 1111b = 1024 ADC12CLK cycles 7 ADC12MSC RW 0h ADC12_A multiplesample and conversion.Validonlyforsequence orrepeated modes. 0b = The samplingtimerrequiresa risingedge oftheSHI signaltotriggereach sample-and-convert. 1b = The firstrisingedge oftheSHI signaltriggersthesamplingtimer,butfurther sample-and-conversionsareperformedautomaticallyas soon as theprior conversioniscompleted. 6 ADC12REF2_5V RW 0h ADC12_A referencegeneratorvoltage.ADC12REFON must alsobe set.In deviceswiththeREF module,thisbitisonlyvalidiftheREFMSTR bitoftheREF module issetto0.IntheF54xx devices(non-A),theREF module isnot available. 0b = 1.5V 1b = 2.5V 5 ADC12REFON RW 0h ADC12_A referencegeneratoron.IndeviceswiththeREF module,thisbitis onlyvalidiftheREFMSTR bitoftheREF module issetto0.IntheF54xx devices(non-A),theREF module isnotavailable. 0b = Referenceoff 1b = Referenceon

552 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Registers Table20-4.ADC12CTL0 RegisterDescription(continued) Bit Field Type Reset Description

4 ADC12ON RW 0h ADC12_A on

0b = ADC12_A off 1b = ADC12_A on 3 ADC12OVIE RW 0h ADC12MEMx overflow-interruptenable.The GIE bitmust alsobe settoenable theinterrupt. 0b = Overflowinterruptdisabled 1b = Overflowinterruptenabled 2 ADC12TOVIE RW 0h ADC12_A conversion-time-overflowinterruptenable.The GIE bitmust alsobe settoenabletheinterrupt. 0b = Conversiontimeoverflowinterruptdisabled 1b = Conversiontimeoverflowinterruptenabled

1 ADC12ENC RW 0h ADC12_A enableconversion

0b = ADC12_A disabled 1b = ADC12_A enabled 0 ADC12SC RW 0h ADC12_A startconversion.Software-controlledsample-and-conversionstart. ADC12SC and ADC12ENC may be settogetherwithone instruction.ADC12SC isresetautomatically. 0b = No sample-and-conversion-start 1b = Startsample-and-conversion 553SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3.2 ADC12CTL1 Register

ADC12_A ControlRegister1 Figure20-14.ADC12CTL1 Register 15 14 13 12 11 10 9 8 ADC12CSTARTADDx ADC12SHSx ADC12SHP ADC12ISSH rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC12DIVx ADC12SSELx ADC12CONSEQx ADC12BUSY rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) r-(0) Can be modifiedonlywhen ADC12ENC = 0 Table20-5.ADC12CTL1 RegisterDescription Bit Field Type Reset Description 15-12 ADC12CSTARTADDx RW 0h ADC12_A conversionstartaddress.These bitsselectwhichADC12_A conversion-memoryregisterisused fora singleconversionorforthefirst conversionina sequence.The valueofCSTARTADDx is0 to0Fh, correspondingtoADC12MEM0 toADC12MEM15. 11-10 ADC12SHSx RW 0h ADC12_A sample-and-holdsourceselect 00b = ADC12SC bit 01b = Timersource(seedevice-specificdatasheetforexacttimerand locations) 10b = Timersource(seedevice-specificdatasheetforexacttimerand locations) 11b = Timersource(seedevice-specificdatasheetforexacttimerand locations) 9 ADC12SHP RW 0h ADC12_A sample-and-holdpulse-modeselect.Thisbitselectsthesourceofthe samplingsignal(SAMPCON) tobe eithertheoutputofthesamplingtimerorthe sample-inputsignaldirectly. 0b = SAMPCON signalissourcedfromthesample-inputsignal. 1b = SAMPCON signalissourcedfromthesamplingtimer.

8 ADC12ISSH RW 0h ADC12_A invertsignalsample-and-hold

0b = The sample-inputsignalisnotinverted. 1b = The sample-inputsignalisinverted. 7-5 ADC12DIVx RW 0h ADC12_A clockdivider 000b = Divideby 1 001b = Divideby 2 010b = Divideby 3 011b = Divideby 4 100b = Divideby 5 101b = Divideby 6 110b = Divideby 7 111b = Divideby 8 4-3 ADC12SSELx RW 0h ADC12_A clocksourceselect 00b = ADC12OSC (MODOSC) 01b = ACLK 10b = MCLK 11b = SMCLK 2-1 ADC12CONSEQx RW 0h ADC12_A conversionsequence mode select 00b = Single-channel,single-conversion 01b = Sequence-of-channels 10b = Repeat-single-channel 11b = Repeat-sequence-of-channels 0 ADC12BUSY R 0h ADC12_A busy.Thisbitindicatesan activesample orconversionoperation. 0b = No operationisactive. 1b = A sequence,sample,orconversionisactive.

554 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

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20.3.3 ADC12CTL2 Register

ADC12_A ControlRegister2 Figure20-15.ADC12CTL2 Register 15 14 13 12 11 10 9 8 Reserved ADC12PDIV r-0 r-0 r-0 r-0 r-0 r-0 r-0 rw-0 7 6 5 4 3 2 1 0 ADC12TCOFF Reserved ADC12RES ADC12DF ADC12SR ADC12REFOU ADC12REFBU T RST rw-(0) r-0 rw-(1) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Can be modifiedonlywhen ADC12ENC = 0 Table20-6.ADC12CTL2 RegisterDescription Bit Field Type Reset Description 15-9 Reserved R 0h Reserved.Alwaysreadsas 0. 8 ADC12PDIV RW 0h ADC12_A predivider.ThisbitpredividestheselectedADC12_A clocksource. 0b = Predivideby 1 1b = Predivideby 4 7 ADC12TCOFF RW 0h ADC12_A temperaturesensoroff.Ifthebitisset,thetemperaturesensorturned off.Thisisused tosave power. IndeviceswiththeREF module,thisbitisonlyvalidiftheREFMSTR bitofthe REF module issetto0.IntheF54xx devices(non-A),theREF module isnot available. 0b = Temperaturesensoron 1b = Temperaturesensoroff 6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-4 ADC12RES RW 2h ADC12_A resolution.Thisbitdefinestheconversionresultresolution. 00b = 8 bit(9clockcycleconversiontime) 01b = 10 bit(11clockcycleconversiontime) 10b = 12 bit(13clockcycleconversiontime) 11b = Reserved 3 ADC12DF RW 0h ADC12_A dataread-backformat.Data isalwaysstoredinthebinaryunsigned format. 0b = Binaryunsigned.Theoretically,theanaloginputvoltage-VREF resultsin 0000h,theanaloginputvoltage+VREF resultsin0FFFh. 1b = Signedbinary(2scomplement),leftaligned.Theoretically,theanaloginput voltage-VREF resultsin8000h,theanaloginputvoltage+VREF resultsin 7FF0h. 2 ADC12SR RW 0h ADC12_A samplingrate.Thisbitselectsthereferencebufferdrivecapabilityfor themaximum samplingrate.SettingADC12SR reducesthecurrentconsumption ofthereferencebuffer. 0b = Referencebuffersupportsup toapproximately200 ksps. 1b = Referencebuffersupportsup toapproximately50 ksps. 1 ADC12REFOUT RW 0h Referenceoutput.IndeviceswiththeREF module,thisbitisonlyvalidifthe REFMSTR bitoftheREF module issetto0.IntheF54xx devices(non-A),the REF module isnotavailable. 0b = Referenceoutputoff 1b = Referenceoutputon

0 ADC12REFBURST RW 0h Referenceburst

0b = Referencebufferon continuously 1b = Referencebufferon onlyduringsample-and-conversion 555SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3.4 ADC12MEMx Register

ADC12_A ConversionMemory Register Figure20-16.ADC12MEMx Register 15 14 13 12 11 10 9 8 ConversionResults rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 ConversionResults rw rw rw rw rw rw rw rw Table20-7.ADC12MEMx RegisterDescription Bit Field Type Reset Description 15-0 ConversionResults RW undefined Binaryunsignedformat:Thisdataformatisused ifADC12DF = 0.The 12-bit conversionresultsarerightjustified.Bit11 istheMSB. Bits15–12 are0 in12- bitmode, bits15–10 are0 in10-bitmode, and bits15–8 are0 in8-bitmode. Writingtotheconversionmemory registerscorruptstheresults. 2s-complementformat:Thisdataformatisused ifADC12DF = 1.The 12-bit conversionresultsareleftjustified,2s-complementformat.Bit15 istheMSB. Bits3–0 are0 in12-bitmode, bits5–0 are0 in10-bitmode, and bits7–0 are0 in8-bitmode. The dataisstoredintheright-justifiedformatand isconvertedto theleft-justified2s-complementformatduringreadback.

556 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

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20.3.5 ADC12MCTLx Register

ADC12_A ConversionMemory ControlRegister Figure20-17.ADC12MCTLx Register 7 6 5 4 3 2 1 0 ADC12EOS ADC12SREFx ADC12INCHx rw rw rw rw rw rw rw rw Can be modifiedonlywhen ADC12ENC = 0 Table20-8.ADC12MCTLx RegisterDescription Bit Field Type Reset Description 7 ADC12EOS RW 0h End ofsequence.Indicatesthelastconversionina sequence. 0b = Not end ofsequence 1b = End ofsequence 6-4 ADC12SREFx RW 0h Selectreference 000b = V(R+) = AVCC and V(R-)= AVSS 001b = V(R+) = VREF+ and V(R-)= AVSS 010b = V(R+) = VeREF+ and V(R-)= AVSS 011b = V(R+) = VeREF+ and V(R-)= AVSS 100b = V(R+) = AVCC and V(R-)= VREF-/VeREF- 101b = V(R+) = VREF+ and V(R-)= VREF-/VeREF- 110b = V(R+) = VeREF+ and V(R-)= VREF-/VeREF- 111b = V(R+) = VeREF+ and V(R-)= VREF-/VeREF- 3-0 ADC12INCHx RW 0h Inputchannelselect 0000b = A0 0001b = A1 0010b = A2 0011b = A3 0100b = A4 0101b = A5 0110b = A6 0111b = A7 1000b = VeREF+ 1001b = VREF-/VeREF- 1010b = Temperaturediode 1011b = (AVCC – AVSS) /2 1100b = A12.On deviceswiththeBatteryBackup System,VBAT can be measured internallyby theADC. 1101b = A13 1110b = A14 1111b = A15 557SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3.6 ADC12IE Register

ADC12_A InterruptEnableRegister Figure20-18.ADC12IE Register 15 14 13 12 11 10 9 8 ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IE9 ADC12IE8 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC12IE7 ADC12IE6 ADC12IE5 ADC12IE4 ADC12IE3 ADC12IE2 ADC12IE1 ADC12IE0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table20-9.ADC12IE RegisterDescription Bit Field Type Reset Description 15 ADC12IE15 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG15 bit. 0b = Interruptdisabled 1b = Interruptenabled 14 ADC12IE14 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG14 bit. 0b = Interruptdisabled 1b = Interruptenabled 13 ADC12IE13 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG13 bit. 0b = Interruptdisabled 1b = Interruptenabled 12 ADC12IE12 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG12 bit. 0b = Interruptdisabled 1b = Interruptenabled 11 ADC12IE11 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG11 bit. 0b = Interruptdisabled 1b = Interruptenabled 10 ADC12IE10 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG10 bit. 0b = Interruptdisabled 1b = Interruptenabled 9 ADC12IE9 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG9 bit. 0b = Interruptdisabled 1b = Interruptenabled 8 ADC12IE8 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG8 bit. 0b = Interruptdisabled 1b = Interruptenabled 7 ADC12IE7 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG7 bit. 0b = Interruptdisabled 1b = Interruptenabled 6 ADC12IE6 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG6 bit. 0b = Interruptdisabled 1b = Interruptenabled

558 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Registers Table20-9.ADC12IE RegisterDescription(continued) Bit Field Type Reset Description 5 ADC12IE5 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG5 bit. 0b = Interruptdisabled 1b = Interruptenabled 4 ADC12IE4 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG4 bit. 0b = Interruptdisabled 1b = Interruptenabled 3 ADC12IE3 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG3 bit. 0b = Interruptdisabled 1b = Interruptenabled 2 ADC12IE2 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG2 bit. 0b = Interruptdisabled 1b = Interruptenabled 1 ADC12IE1 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG1 bit. 0b = Interruptdisabled 1b = Interruptenabled 0 ADC12IE0 RW 0h Interruptenable.Thisbitenablesordisablestheinterruptrequestforthe ADC12IFG0 bit. 0b = Interruptdisabled 1b = Interruptenabled 559SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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20.3.7 ADC12IFG Register

ADC12_A InterruptFlagRegister Figure20-19.ADC12IFG Register 15 14 13 12 11 10 9 8 ADC12IFG15 ADC12IFG14 ADC12IFG13 ADC12IFG12 ADC12IFG11 ADC12IFG10 ADC12IFG9 ADC12IFG8 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 ADC12IFG7 ADC12IFG6 ADC12IFG5 ADC12IFG4 ADC12IFG3 ADC12IFG2 ADC12IFG1 ADC12IFG0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table20-10.ADC12IFG RegisterDescription Bit Field Type Reset Description 15 ADC12IFG15 RW 0h ADC12MEM15 interruptflag.Thisbitissetwhen ADC12MEM15 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM15 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 14 ADC12IFG14 RW 0h ADC12MEM14 interruptflag.Thisbitissetwhen ADC12MEM14 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM14 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 13 ADC12IFG13 RW 0h ADC12MEM13 interruptflag.Thisbitissetwhen ADC12MEM13 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM13 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 12 ADC12IFG12 RW 0h ADC12MEM12 interruptflag.Thisbitissetwhen ADC12MEM12 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM12 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 11 ADC12IFG11 RW 0h ADC12MEM11 interruptflag.Thisbitissetwhen ADC12MEM11 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM11 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 10 ADC12IFG10 RW 0h ADC12MEM10 interruptflag.Thisbitissetwhen ADC12MEM10 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM10 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 9 ADC12IFG9 RW 0h ADC12MEM9 interruptflag.Thisbitissetwhen ADC12MEM9 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM9 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 8 ADC12IFG8 RW 0h ADC12MEM8 interruptflag.Thisbitissetwhen ADC12MEM8 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM8 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending

560 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com ADC12_A Registers Table20-10.ADC12IFG RegisterDescription(continued) Bit Field Type Reset Description 7 ADC12IFG7 RW 0h ADC12MEM7 interruptflag.Thisbitissetwhen ADC12MEM7 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM7 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 6 ADC12IFG6 RW 0h ADC12MEM6 interruptflag.Thisbitissetwhen ADC12MEM6 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM6 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 5 ADC12IFG5 RW 0h ADC12MEM5 interruptflag.Thisbitissetwhen ADC12MEM5 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM5 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 4 ADC12IFG4 RW 0h ADC12MEM4 interruptflag.Thisbitissetwhen ADC12MEM4 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM4 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 3 ADC12IFG3 RW 0h ADC12MEM3 interruptflag.Thisbitissetwhen ADC12MEM3 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM3 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 2 ADC12IFG2 RW 0h ADC12MEM2 interruptflag.Thisbitissetwhen ADC12MEM2 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM2 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 1 ADC12IFG1 RW 0h ADC12MEM1 interruptflag.Thisbitissetwhen ADC12MEM1 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM1 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 0 ADC12IFG0 RW 0h ADC12MEM0 interruptflag.Thisbitissetwhen ADC12MEM0 isloadedwitha conversionresult.ThisbitisresetiftheADC12MEM0 isaccessed,oritmay be resetwithsoftware. 0b = No interruptpending 1b = Interruptpending 561SLAU259E –May 2009–RevisedJanuary2013 ADC12_A SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. ADC12_A Registers www.ti.com

20.3.8 ADC12IV Register

ADC12_A InterruptVectorRegister Figure20-20.ADC12IV Register 15 14 13 12 11 10 9 8 ADC12IVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 ADC12IVx Table20-11.ADC12IV RegisterDescription Bit Field Type Reset Description 15-0 ADC12IVx R 0h ADC12_A interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:ADC12MEMx overflow;InterruptFlag:–;Interrupt Priority:Highest 04h = InterruptSource:Conversiontimeoverflow;InterruptFlag:– 06h = InterruptSource:ADC12MEM0 interruptflag;InterruptFlag:ADC12IFG0 08h = InterruptSource:ADC12MEM1 interruptflag;InterruptFlag:ADC12IFG1 0Ah = InterruptSource:ADC12MEM2 interruptflag;InterruptFlag:ADC12IFG2 0Ch = InterruptSource:ADC12MEM3 interruptflag;InterruptFlag:ADC12IFG3 0Eh = InterruptSource:ADC12MEM4 interruptflag;InterruptFlag:ADC12IFG4 10h = InterruptSource:ADC12MEM5 interruptflag;InterruptFlag:ADC12IFG5 12h = InterruptSource:ADC12MEM6 interruptflag;InterruptFlag:ADC12IFG6 14h = InterruptSource:ADC12MEM7 interruptflag;InterruptFlag:ADC12IFG7 16h = InterruptSource:ADC12MEM8 interruptflag;InterruptFlag:ADC12IFG8 18h = InterruptSource:ADC12MEM9 interruptflag;InterruptFlag:ADC12IFG9 1Ah = InterruptSource:ADC12MEM10 interruptflag;InterruptFlag: ADC12IFG10 1Ch = InterruptSource:ADC12MEM11 interruptflag;InterruptFlag: ADC12IFG11 1Eh = InterruptSource:ADC12MEM12 interruptflag;InterruptFlag: ADC12IFG12 20h = InterruptSource:ADC12MEM13 interruptflag;InterruptFlag: ADC12IFG13 22h = InterruptSource:ADC12MEM14 interruptflag;InterruptFlag: ADC12IFG14 24h = InterruptSource:ADC12MEM15 interruptflag;InterruptFlag: ADC12IFG15; InterruptPriority:Lowest

562 ADC12_A SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter21 SLAU259E –May 2009–RevisedJanuary2013 Comp_B Comp_B isan analogvoltagecomparator.ThischapterdescribestheComp_B. Comp_B coversgeneral comparatorfunctionalityforup to16 channels. 563SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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21.1 Comp_B Introduction

The Comp_B module supportsprecisionslopeanalog-to-digitalconversions,supplyvoltagesupervision, and monitoringofexternalanalogsignals. FeaturesofComp_B include:

Invertingand noninvertingterminalinputmultiplexer
Software-selectableRC filterforthecomparatoroutput
OutputprovidedtoTimer_A captureinput
Softwarecontroloftheportinputbuffer
Interruptcapability
Selectablereferencevoltagegenerator,voltagehysteresisgenerator
Referencevoltageinputfromsharedreference
Ultra-low-powercomparatormode
Interruptdrivenmeasurement system– low-poweroperationsupport The Comp_B blockdiagramisshown inFigure21-1. Figure21-1.Comp_B Block Diagram

564 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Operation

21.2 Comp_B Operation

The Comp_B module isconfiguredby usersoftware.The setupand operationofComp_B isdiscussedin thefollowingsections.

21.2.1 Comparator

The comparatorcompares theanalogvoltagesatthe+ and – inputterminals.Ifthe+ terminalismore positivethanthe– terminal,thecomparatoroutputCBOUT ishigh.The comparatorcan be switchedon or offusingcontrolbitCBON. The comparatorshouldbe switchedoffwhen notinuse toreducecurrent consumption.When thecomparatorisswitchedoff,CBOUT isalwayslow.The biascurrentofthe comparatorisprogrammable.

21.2.2 Analog InputSwitches

The analoginputswitchesconnectordisconnectthetwo comparatorinputterminalstoassociatedport pinsusingtheCBIPSELx and CBIMSELx bits.The comparatorterminalinputscan be controlled individually.The CBIPSELx/CBIMSELx bitsallow:

Applicationofan externalsignaltothe+ and – terminalsofthecomparator
Routingofan internalreferencevoltagetoan associatedoutputportpin
Applicationofan externalcurrentsource(forexample,a resistor)tothe+ or– terminalofthe comparator
The mapping ofbothterminalsoftheinternalmultiplexertotheoutside Internally,theinputswitchisconstructedas a T-switchtosuppressdistortioninthesignalpath. NOTE: Comparator InputConnection When thecomparatorison,theinputterminalsshouldbe connectedtoa signal,power,or ground.Otherwise,floatinglevelsmay cause unexpectedinterruptsand increasedcurrent consumption. The CBEX bitcontrolstheinputmultiplexer,permutingtheinputsignalsofthecomparator's+ and – terminals.Additionally,when thecomparatorterminalsarepermuted,theoutputsignalfromthe comparatorisinvertedtoo.Thisallowstheusertodetermineorcompensate forthecomparatorinput offsetvoltage.

21.2.3 PortLogic

The Px.ypinsassociatedwitha comparatorchannelareenabledby theCBIPSELx orCBIMSELx bitsto disableitsdigitalcomponents whileused as comparatorinput.Onlyone ofthecomparatorinputpinsis selectedas inputtothecomparatorby theinputmultiplexerata time.

21.2.4 InputShortSwitch

The CBSHORT bitshortstheComp_B inputs.Thiscan be used tobuilda simplesample-and-holdforthe comparatoras shown inFigure21-2. 565SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Sampling capacitor, CS Analog Inputs ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Comp_B Operation www.ti.com Figure21-2.Comp_B Sample-And-Hold The requiredsamplingtimeisproportionaltothesizeofthesamplingcapacitor(CS),theresistanceofthe inputswitchesinserieswiththeshortswitch(Ri),and theresistanceoftheexternalsource(RS).The total internalresistance(RI)istypicallyintherangeof1 kΩ.The samplingcapacitorC S shouldbe greaterthan 100 pF.The timeconstant,Tau,tochargethesamplingcapacitorC S can be calculatedwiththefollowing equation: Tau = (RI + R S)× C S Dependingon therequiredaccuracy,3 to10 Tau shouldbe used as a samplingtime.With3 Tau the samplingcapacitorischargedtoapproximately95% oftheinputsignalsvoltagelevel,with5 Tau itis chargedtomore than99%, and with10 Tau thesampled voltageissufficientfor12-bitaccuracy.

21.2.5 Output Filter

The outputofthecomparatorcan be used withorwithoutinternalfiltering.When controlbitCBF isset,the outputisfilteredwithan on-chipRC filter.The delayofthefiltercan be adjustedinfourdifferentsteps. Allcomparatoroutputsareoscillatingifthevoltagedifferenceacrosstheinputterminalsissmall.Internal and externalparasiticeffectsand crosscouplingon and between signallines,power supplylines,and otherpartsofthesystemareresponsibleforthisbehavioras shown inFigure21-3.The comparator outputoscillationreducestheaccuracyand resolutionofthecomparisonresult.Selectingtheoutputfilter can reduceerrorsassociatedwithcomparatoroscillation.

566 Comp_B SLAU259E –May 2009–RevisedJanuary2013

CBRS = 11 0110 00, 11 CBRSx 2 VREF VREF1 VREF0

1.2 V from the

+ Terminal - Terminal Comparator Inputs Comparator Output Unfiltered at CBOUT Comparator Output Filtered at CBOUT ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Operation Figure21-3.RC-FilterResponse attheOutput oftheComparator

21.2.6 ReferenceVoltageGenerator

The Comp_B referenceblockdiagramisshown inFigure21-4. Figure21-4.ReferenceGeneratorBlock Diagram The voltagereferencegeneratorisused togenerateVREF, whichcan be appliedtoeithercomparator inputterminal.The CBREF1x (VREF1) and CBREF0x (VREF0) bitscontroltheoutputofthevoltage generator.The CBRSEL bitselectsthecomparatorterminaltowhichVREF isapplied.Ifexternalsignals areappliedtobothcomparatorinputterminals,theinternalreferencegeneratorshouldbe turnedoffto reducecurrentconsumption.The voltagereferencegeneratorcan generatea fractionofthedevice'sVCC orofthevoltagereferenceoftheintegratedprecisionvoltagereferencesource.Vref1isused while CBOUT is1 and Vref0isused whileCBOUT is0.Thisallowsthegenerationofa hysteresiswithoutusing externalcomponents. 567SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0.25 × VCC CCI1B Capture Input Of Timer_A CB0 Px.x Px.y V C C V S S ICCVOVI

0 V CC

CBPD.x = 1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Comp_B Operation www.ti.com

21.2.7 Comp_B, PortDisableRegisterCBPD

The comparatorinputand outputfunctionsaremultiplexedwiththeassociatedI/Oportpins,whichare digitalCMOS gates.When analogsignalsareappliedtodigitalCMOS gates,parasiticcurrentcan flow fromVCC toGND. Thisparasiticcurrentoccursiftheinputvoltageisnearthetransitionlevelofthegate. Disablingtheportpinbuffereliminatestheparasiticcurrentflowand thereforereducesoverallcurrent consumption. The CBPDx bits,when set,disablethecorrespondingPx.yinputbufferas shown inFigure21-5.When currentconsumptioniscritical,any Px.ypinconnectedtoanalogsignalsshouldbe disabledwiththeir associatedCBPDx bits. Selectingan inputpintothecomparatormultiplexerwiththeCBIPSEL orCBIMSEL bitsautomatically disablestheinputbufferforthatpin,regardlessofthestateoftheassociatedCBPDx bit. Figure21-5.TransferCharacteristicand Power Dissipationina CMOS Inverter/Buffer

21.2.8 Comp_B Interrupts

One interruptflagand one interruptvectorisassociatedwiththeComp_B. The interruptflagCBIFG isseton eithertherisingorfallingedge ofthecomparatoroutput,selectedby theCBIES bit.IfboththeCBIE and theGIE bitsareset,thentheCBIFG interruptflaggeneratesan interruptrequest.

21.2.9 Comp_B Used toMeasure ResistiveElements

The Comp_B can be optimizedtopreciselymeasure resistiveelementsusingsingleslopeanalog-to- digitalconversion.Forexample,temperaturecan be convertedintodigitaldatausinga thermistor,by comparingthethermistor'scapacitordischargetimetothatofa referenceresistoras shown inFigure21- 6.A referenceresisterRrefiscompared toRmeas. Figure21-6.Temperature Measurement System

568 Comp_B SLAU259E –May 2009–RevisedJanuary2013

–R × C × lnmeas Vref1 VCC –R × C × lnref Vref1 VCC Nmeas Nref Rmeas Rref R = R ×meas ref Nmeas Nref VC V or VCC REF0 VREF1 Phase I: Charge Phase II: Discharge Phase III: Charge tref Phase IV Discharge tmeas t Rmeas Rref ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Operation The resourcesused tocalculatethetemperaturesensed by Rmeas are:

Two digitalI/Opinschargeand dischargethecapacitor.
I/Oissettooutputhigh(VCC )tochargecapacitor,resettodischarge.
I/Oisswitchedtohigh-impedanceinputwithCBPDx setwhen notinuse.
One outputchargesand dischargesthecapacitorviaRref.
One outputdischargescapacitorviaRmeas.
The + terminalisconnectedtothepositiveterminalofthecapacitor.
The – terminalisconnectedtoa referencelevel,forexample 0.25× VCC .
The outputfiltershouldbe used tominimizeswitchingnoise.
CBOUT isused togateTimer_A CCI1B, capturingcapacitordischargetime. More thanone resistiveelementcan be measured.AdditionalelementsareconnectedtoCB0 with availableI/Opinsand switchedtohighimpedance when notbeingmeasured. The thermistormeasurement isbased on a ratiometricconversionprinciple.The ratiooftwo capacitor dischargetimesiscalculatedas shown inFigure21-7. Figure21-7.Timing forTemperature Measurement Systems The VCC voltageand thecapacitorvalueshouldremainconstantduringtheconversion,butarenotcritical sincetheycancelintheratio: 569SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Comp_B Registers www.ti.com

21.3 Comp_B Registers

The Comp_B registersarelistedinTable21-1.The base addressoftheComp_B module can be foundin thedevice-specificdatasheet. Table21-1.Comp_B Registers Offset Acronym RegisterName Type Access Reset Section 00h CBCTL0 Comp_B controlregister0 Read/write Word 0000h Section21.3.1 02h CBCTL1 Comp_B controlregister1 Read/write Word 0000h Section21.3.2 04h CBCTL2 Comp_B controlregister2 Read/write Word 0000h Section21.3.3 06h CBCTL3 Comp_B controlregister3 Read/write Word 0000h Section21.3.4 0Ch CBINT Comp_B interruptregister Read/write Word 0000h Section21.3.5 0Eh CBIV Comp_B interruptvectorword Read Word 0000h Section21.3.6

570 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Registers

21.3.1 CBCTL0 Register

Comp_B ControlRegister0 Figure21-8.CBCTL0 Register 15 14 13 12 11 10 9 8 CBIMEN Reserved CBIMSEL rw-0 r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CBIPEN Reserved CBIPSEL rw-0 r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 Table21-2.CBCTL0 RegisterDescription Bit Field Type Reset Description 15 CBIMEN RW 0h ChannelinputenablefortheV– terminalofthecomparator. 0b = SelectedanaloginputchannelforV– terminalisdisabled. 1b = SelectedanaloginputchannelforV– terminalisenabled. 14-12 Reserved R 0h Reserved.Alwaysreadsas 0. 11-8 CBIMSEL RW 0h ChannelinputselectedfortheV– terminalofthecomparatorifCBIMEN issetto 7 CBIPEN RW 0h ChannelinputenablefortheV+ terminalofthecomparator. 0b = SelectedanaloginputchannelforV+ terminalisdisabled. 1b = SelectedanaloginputchannelforV+ terminalisenabled. 6-4 Reserved R 0h Reserved.Alwaysreadsas 0. 3-0 CBIPSEL RW 0h ChannelinputselectedfortheV+ terminalofthecomparatorifCBIPEN issetto 571SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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21.3.2 CBCTL1 Register

Comp_B ControlRegister1 Figure21-9.CBCTL1 Register 15 14 13 12 11 10 9 8 Reserved CBMRVS CBMRVL CBON CBPWRMD r-0 r-0 r-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CBFDLY CBEX CBSHORT CBIES CBF CBOUTPOL CBOUT rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0 Table21-3.CBCTL1 RegisterDescription Bit Field Type Reset Description 15-13 Reserved R 0h Reserved.Alwaysreadsas 0.

12 CBMRVS RW 0h Thisbitdefinesifthecomparatoroutputselectsbetween VREF0 orVREF1 if

CBRS = 00,01,or10. 0b = Comparatoroutputstateselectsbetween VREF0 orVREF1. 1b = CBMRVL selectsbetween VREF0 orVREF1. 11 CBMRVL RW 0h ThisbitisvalidofCBMRVS issetto1. 0b = VREF0 isselectedifCBRS = 00,01,or10. 1b = VREF1 isselectedifCBRS = 00,01,or10. 10 CBON RW 0h On. Thisbitturnsthecomparatoron.When thecomparatoristurnedoffthe Comp_B consumes no power. 0b = Off 1b = On 9-8 CBPWRMD RW 0h Power mode. Not allmodes aresupportedinallproducts.See devicesspecific datasheetfordetails. 00b = High-speedmode (optional) 01b = Normal mode (optional) 10b = Ultra-low-powermode (optional) 11b = Reserved 7-6 CBFDLY RW 0h Filterdelay.The filterdelaycan be selectedin4 steps.See thedevice-specific datasheetfordetails. 00b = Typicalfilterdelayof450 ns 01b = Typicalfilterdelayof900 ns 10b = Typicalfilterdelayof1800 ns 11b = Typicalfilterdelayof3600 ns 5 CBEX RW 0h Exchange.Thisbitpermutesthecomparator0 inputsand invertsthecomparator 0 output. 4 CBSHORT RW 0h Inputshort.Thisbitshortsthe+ and – inputterminals. 0b = Inputsnotshorted 1b = Inputsshorted

3 CBIES RW 0h Interruptedge selectforCBIIFG and CBIFG

0b = Risingedge forCBIFG, fallingedge forCBIIFG 1b = Fallingedge forCBIFG, risingedge forCBIIFG

2 CBF RW 0h Outputfilter

0b = Comp_B outputisnotfiltered 1b = Comp_B outputisfiltered 1 CBOUTPOL RW 0h Outputpolarity.ThisbitdefinestheCBOUT polarity. 0b = Noninverted 1b = Inverted

572 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Registers Table21-3.CBCTL1 RegisterDescription(continued) Bit Field Type Reset Description 0 CBOUT R 0h Outputvalue.ThisbitreflectsthevalueoftheComp_B output.Writingthisbit has no effecton thecomparatoroutput. 573SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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21.3.3 CBCTL2 Register

Comp_B ControlRegister2 Figure21-10.CBCTL2 Register 15 14 13 12 11 10 9 8 CBREFACC CBREFL CBREF1 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 7 6 5 4 3 2 1 0 CBRS CBRSEL CBREF0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table21-4.CBCTL2 RegisterDescription Bit Field Type Reset Description 15 CBREFACC RW 0h Referenceaccuracy.A referencevoltageisrequestedonlyifCBREFL > 0. 0b = Staticmode 1b = Clocked(low-power,low-accuracy)mode 14-13 CBREFL RW 0h Referencevoltagelevel 00b = Referencevoltageisdisabled.No referencevoltageisrequested. 01b = 1.5V 10b = 2.0V 11b = 2.5V 12-8 CBREF1 RW 0h Referenceresistortap1.Thisregisterdefinesthetapoftheresistorstringwhile CBOUT = 1. 7-6 CBRS RW 0h Referencesource.ThisbitdefineifthereferencevoltageisderivedfromVCC or fromtheprecisesharedreference. 00b = No currentisdrawn by thereferencecurcuitry. 01b = VCC appliedtotheresistorladder 10b = Shared referencevoltageappliedtotheresistorladder. 11b = Shared referencevoltagesuppliedtoV(CREF). Resistorladderisoff. 5 CBRSEL RW 0h Referenceselect.ThisbitselectswhichterminaltheV(CCREF) isappliedto. 0b = When CBEX = 0:V(REF) isappliedtothe+ terminal;When CBEX = 1: V(REF) isappliedtothe– terminal 1b = When CBEX = 0:V(REF) isappliedtothe– terminal;When CBEX = 1: V(REF) isappliedtothe+ terminal 4-0 CBREF0 RW 0h Referenceresistortap0.Thisregisterdefinesthetapoftheresistorstringwhile CBOUT = 0.

574 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Registers

21.3.4 CBCTL3 Register

Comp_B ControlRegister3 Figure21-11.CBCTL3 Register 15 14 13 12 11 10 9 8 CBPD15 CBPD14 CBPD13 CBPD14 CBPD11 CBPD10 CBPD9 CBPD8 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) 7 6 5 4 3 2 1 0 CBPD7 CBPD6 CBPD5 CBPD4 CBPD3 CBPD2 CBPD1 CBPD0 rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) rw-(0) Table21-5.CBCTL3 RegisterDescription Bit Field Type Reset Description 15 CBPD15 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD15 disablestheportofthecomparator channel15. 0b = Inputbufferenabled 1b = Inputbufferdisabled 14 CBPD14 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD14 disablestheportofthecomparator channel14. 0b = Inputbufferenabled 1b = Inputbufferdisabled 13 CBPD13 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD13 disablestheportofthecomparator channel13. 0b = Inputbufferenabled 1b = Inputbufferdisabled 12 CBPD12 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD12 disablestheportofthecomparator channel12. 0b = Inputbufferenabled 1b = Inputbufferdisabled 11 CBPD11 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD11 disablestheportofthecomparator channel11. 0b = Inputbufferenabled 1b = Inputbufferdisabled 10 CBPD10 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD10 disablestheportofthecomparator channel10. 0b = Inputbufferenabled 1b = Inputbufferdisabled 9 CBPD9 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD9 disablestheportofthecomparator channel9. 0b = Inputbufferenabled 1b = Inputbufferdisabled 8 CBPD8 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD8 disablestheportofthecomparator channel8. 0b = Inputbufferenabled 1b = Inputbufferdisabled 575SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Comp_B Registers www.ti.com Table21-5.CBCTL3 RegisterDescription(continued) Bit Field Type Reset Description 7 CBPD7 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD7 disablestheportofthecomparator channel7. 0b = Inputbufferenabled 1b = Inputbufferdisabled 6 CBPD6 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD6 disablestheportofthecomparator channel6. 0b = Inputbufferenabled 1b = Inputbufferdisabled 5 CBPD5 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD5 disablestheportofthecomparator channel5. 0b = Inputbufferenabled 1b = Inputbufferdisabled 4 CBPD4 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD4 disablestheportofthecomparator channel4. 0b = Inputbufferenabled 1b = Inputbufferdisabled 3 CBPD3 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD3 disablestheportofthecomparator channel3. 0b = Inputbufferenabled 1b = Inputbufferdisabled 2 CBPD2 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD2 disablestheportofthecomparator channel2. 0b = Inputbufferenabled 1b = Inputbufferdisabled 1 CBPD1 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD1 disablestheportofthecomparator channel1. 0b = Inputbufferenabled 1b = Inputbufferdisabled 0 CBPD0 RW 0h Portdisable.Thisbitindividuallydisablestheinputbufferforthepinsoftheport associatedwithComp_B. The bitCBPD0 disablestheportofthecomparator channel0. 0b = Inputbufferenabled 1b = Inputbufferdisabled

576 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com Comp_B Registers

21.3.5 CBINT Register

Comp_B InterruptControlRegister Figure21-12.CBINT Register 15 14 13 12 11 10 9 8 Reserved CBIIE CBIE r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 7 6 5 4 3 2 1 0 Reserved CBIIFG CBIFG r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 Table21-6.CBINT RegisterDescription Bit Field Type Reset Description 15-10 Reserved R 0h Reserved.Alwaysreadsas 0.

9 CBIIE RW 0h Comp_B outputinterruptenableinvertedpolarity

0b = Interruptisdisabled 1b = Interruptisenabled

8 CBIE RW 0h Comp_B outputinterruptenable

0b = Interruptisdisabled 1b = Interruptisenabled 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 CBIIFG RW 0h Comp_B outputinvertedinterruptflag.The bitCBIES definesthetransitionofthe outputsettingthisbit. 0b = No interruptpending 1b = Outputinterruptpending 0 CBIFG RW 0h Comp_B outputinterruptflag.The bitCBIES definesthetransitionoftheoutput settingthisbit. 0b = No interruptpending 1b = Outputinterruptpending 577SLAU259E –May 2009–RevisedJanuary2013 Comp_B SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Comp_B Registers www.ti.com

21.3.6 CBIV Register

Comp_B InterruptVectorWord Register Figure21-13.CBIV Register 15 14 13 12 11 10 9 8 CBIV r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 CBIV r0 r0 r0 r0 r0 r-0 r-0 r0 Table21-7.CBIV RegisterDescription Bit Field Type Reset Description 15-0 CBIV R 0h Comp_B interruptvectorword register.The interruptvectorregisterreflectsonly interruptflagswhose interruptenablebitareset.ReadingtheCBIV register clearsthependinginterruptflagwiththehighestpriority. 00h = No interruptpending 02h = InterruptSource:CBOUT interrupt;InterruptFlag:CBIFG; Interrupt Priority:Highest 04h = InterruptSource:CBOUT interruptinvertedpolarity;InterruptFlag: CBIIFG;InterruptPriority:Lowest

578 Comp_B SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter22 SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunication Interface– UART Mode The universalserialcommunicationinterface(USCI)supportsmultipleserialcommunicationmodes with one hardwaremodule.ThischapterdiscussestheoperationoftheasynchronousUART mode. 579SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UniversalSerialCommunicationInterface(USCI)Overview www.ti.com

22.1 UniversalSerialCommunication Interface(USCI)Overview

The USCI modules supportmultipleserialcommunicationmodes. DifferentUSCI modules support differentmodes. Each differentUSCI module isnamed witha differentletter.Forexample,USCI_A is differentfromUSCI_B, etc.Ifmore thanone identicalUSCI module isimplementedon one device,those modules arenamed withincrementingnumbers.Forexample,ifone devicehas two USCI_A modules, theyarenamed USCI_A0 and USCI_A1. See thedevice-specificdatasheettodeterminewhichUSCI modules,ifany,areimplementedon whichdevices. USCI_Ax modules support:

UART mode
PulseshapingforIrDAcommunications
Automaticbaud-ratedetectionforLIN communications
SPI mode USCI_Bx modules support:
I2C mode
SPI mode

580 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Introduction– UART Mode

22.2 USCI Introduction– UART Mode

Inasynchronousmode, theUSCI_Ax modules connectthedevicetoan externalsystemviatwo external pins,UCAxRXD and UCAxTXD. UART mode isselectedwhen theUCSYNC bitiscleared. UART mode featuresinclude:

7-or8-bitdatawithodd,even,ornon-parity
Independenttransmitand receiveshiftregisters
Separatetransmitand receivebufferregisters
LSB-firstorMSB-firstdatatransmitand receive
Built-inidle-lineand address-bitcommunicationprotocolsformultiprocessorsystems
Receiverstart-edgedetectionforautowake up fromLPMx modes
Programmable baud ratewithmodulationforfractionalbaud-ratesupport
Statusflagsforerrordetectionand suppression
Statusflagsforaddressdetection
Independentinterruptcapabilityforreceiveand transmit 581SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Receive□Baudrate□Generator UC0BRx UCBRFx UCBRSx UCOS16 UCRXERRError□Flags Set□Flags UCPE UCFE UCOE UCABEN Receive□Shift□Register Receive□Buffer□UCAxRXBUF Receive□State□Machine UCIREN UCPEN UCPAR UCMSB UC7BIT UCDORMUCMODEx UCSPB Set□UCBRK Set□UCADDR /UCIDLE UCLISTEN UCAxRXD UCIRRXPL IrDA Decoder UCIRRXFE UCIRRXFLx Transmit□Buffer□UCAxTXBUF Transmit□State□Machine UCTXADDR UCTXBRK Transmit□Shift□Register UCPEN UCPAR UCMSB UC7BIT UCIREN UCIRTXPLx IrDA Encoder UCAxTXD Transmit□Clock Receive□Clock BRCLK UCMODEx UCSPB UCRXEIE UCRXBRKIE Set□UCRXIFG Set□UCTXIFG Set□RXIFG ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Introduction– UART Mode www.ti.com Figure22-1shows theUSCI_Ax when configuredforUART mode. Figure22-1.USCI_Ax Block Diagram – UART Mode (UCSYNC = 0)

582 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

[Parity Bit, UCPEN = 1] [Address Bit, UCMODEx = 10] Mark Space D0 D6 D7 AD PA SP SP [Optional Bit, Condition] [2nd Stop Bit, UCSPB = 1] [8th Data Bit, UC7BIT = 0] ST ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode

22.3 USCI Operation– UART Mode

InUART mode, theUSCI transmitsand receivescharactersata bitrateasynchronoustoanotherdevice. Timingforeach characterisbased on theselectedbaud rateoftheUSCI. The transmitand receive functionsuse thesame baud-ratefrequency.

22.3.1 USCI Initializationand Reset

The USCI isresetby a PUC orby settingtheUCSWRST bit.Aftera PUC, theUCSWRST bitis automaticallyset,keepingtheUSCI ina resetcondition.When set,theUCSWRST bitresetstheUCRXIE, UCTXIE, UCRXIFG, UCRXERR, UCBRK, UCPE, UCOE, UCFE, UCSTOE, and UCBTOE bits,and sets theUCTXIFG bit.ClearingUCSWRST releasestheUSCI foroperation. To avoidunpredictablebehavior,configureorreconfiguretheUSCI_A module onlywhen UCSWRST is set. NOTE: Initializingor reconfiguringtheUSCI module The recommended USCI initialization/reconfigurationprocessis: 1. SetUCSWRST (BIS.B #UCSWRST,&UCAxCTL1). 2. InitializeallUSCI registerswithUCSWRST = 1 (includingUCAxCTL1). 3. Configureports. 4. ClearUCSWRST viasoftware(BIC.B #UCSWRST,&UCAxCTL1). 5. Enableinterrupts(optional)viaUCRXIE and/orUCTXIE.

22.3.2 CharacterFormat

The UART characterformat(seeFigure22-2)consistsofa startbit,seven oreightdatabits,an even/odd/noparitybit,an addressbit(address-bitmode),and one ortwo stopbits.The UCMSB bit controlsthedirectionofthetransferand selectsLSB orMSB first.LSB firstistypicallyrequiredforUART communication. Figure22-2.CharacterFormat

22.3.3 Asynchronous Communication Format

When two devicescommunicateasynchronously,no multiprocessorformatisrequiredfortheprotocol. When threeormore devicescommunicate,theUSCI supportstheidle-lineand address-bitmultiprocessor communicationformats. 22.3.3.1Idle-LineMultiprocessorFormat When UCMODEx = 01,theidle-linemultiprocessorformatisselected.Blocksofdataareseparatedby an idletimeon thetransmitorreceivelines(seeFigure22-3).An idlereceivelineisdetectedwhen tenor more continuousones (marks)arereceivedaftertheone ortwo stopbitsofa character.The baud-rate generatorisswitchedoffafterreceptionofan idlelineuntilthenextstartedge isdetected.When an idle lineisdetected,theUCIDLE bitisset. 583SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com The firstcharacterreceivedafteran idleperiodisan addresscharacter.The UCIDLE bitisused as an addresstagforeach blockofcharacters.Inidle-linemultiprocessorformat,thisbitissetwhen a received characterisan address. Figure22-3.Idle-LineFormat The UCDORM bitisused tocontroldatareceptionintheidle-linemultiprocessorformat.When UCDORM = 1,allnon-addresscharactersareassembledbutnottransferredintotheUCAxRXBUF, and interruptsarenotgenerated.When an addresscharacterisreceived,thecharacteristransferredinto UCAxRXBUF, UCRXIFG isset,and any applicableerrorflagissetwhen UCRXEIE = 1.When UCRXEIE = 0 and an addresscharacterisreceivedbuthas a framingerrororparityerror,thecharacterisnot transferredintoUCAxRXBUF and UCRXIFG isnotset. Ifan addressisreceived,usersoftwarecan validatetheaddressand must resetUCDORM tocontinue receivingdata.IfUCDORM remainsset,onlyaddresscharactersarereceived.When UCDORM iscleared duringthereceptionofa character,thereceiveinterruptflagissetafterthereceptioncompleted.The UCDORM bitisnotmodifiedby theUSCI hardwareautomatically. Foraddresstransmissioninidle-linemultiprocessorformat,a preciseidleperiodcan be generatedby the USCI togenerateaddresscharacteridentifierson UCAxTXD. The double-bufferedUCTXADDR flag indicatesifthenextcharacterloadedintoUCAxTXBUF isprecededby an idlelineof11 bits.UCTXADDR isautomaticallyclearedwhen thestartbitisgenerated. 22.3.3.1.1Transmittingan IdleFrame The followingproceduresends outan idleframetoindicatean addresscharacterfollowedby associated data: 1. SetUCTXADDR, thenwritetheaddresscharactertoUCAxTXBUF. UCAxTXBUF must be readyfor new data(UCTXIFG = 1). Thisgeneratesan idleperiodofexactly11 bitsfollowedby theaddresscharacter.UCTXADDR isreset automaticallywhen theaddresscharacteristransferredfromUCAxTXBUF intotheshiftregister. 2. WritedesireddatacharacterstoUCAxTXBUF. UCAxTXBUF must be readyfornew data(UCTXIFG = 1). The datawrittentoUCAxTXBUF istransferredtotheshiftregisterand transmittedas soon as theshift registerisreadyfornew data. The idle-linetimemust notbe exceeded between addressand datatransmissionorbetween data transmissions.Otherwise,thetransmitteddataismisinterpretedas an address.

584 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ST Address SP ST Data SP ST Data SP Blocks of Characters Idle Periods of No Significance UCAxTXD/UCAxRXD Expanded UCAxTXD/UCAxRXD First Character Within Block Is an Address. AD Bit Is 1 AD Bit Is 0 for Data Within Block. Idle Time Is of No Significance UCAxTXD/UCAxRXD 1 0 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode 22.3.3.2Address-BitMultiprocessorFormat When UCMODEx = 10,theaddress-bitmultiprocessorformatisselected.Each processedcharacter containsan extrabitused as an addressindicator(seeFigure22-4).The firstcharacterina blockof characterscarriesa setaddressbitthatindicatesthatthecharacterisan address.The USCI UCADDR bit issetwhen a receivedcharacterhas itsaddressbitsetand istransferredtoUCAxRXBUF. The UCDORM bitisused tocontroldatareceptionintheaddress-bitmultiprocessorformat.When UCDORM isset,datacharacterswithaddressbit= 0 areassembledby thereceiverbutarenot transferredtoUCAxRXBUF and no interruptsaregenerated.When a charactercontaininga setaddress bitisreceived,thecharacteristransferredintoUCAxRXBUF, UCRXIFG isset,and any applicableerror flagissetwhen UCRXEIE = 1.When UCRXEIE = 0 and a charactercontaininga setaddressbitis receivedbuthas a framingerrororparityerror,thecharacterisnottransferredintoUCAxRXBUF and UCRXIFG isnotset. Ifan addressisreceived,usersoftwarecan validatetheaddressand must resetUCDORM tocontinue receivingdata.IfUCDORM remainsset,onlyaddresscharacterswithaddressbit= 1 arereceived.The UCDORM bitisnotmodifiedby theUSCI hardwareautomatically. When UCDORM = 0,allreceivedcharacterssetthereceiveinterruptflagUCRXIFG. IfUCDORM is clearedduringthereceptionofa character,thereceiveinterruptflagissetafterthereceptionis completed. Foraddresstransmissioninaddress-bitmultiprocessormode, theaddressbitofa characteriscontrolled by theUCTXADDR bit.The valueoftheUCTXADDR bitisloadedintotheaddressbitofthecharacter transferredfromUCAxTXBUF tothetransmitshiftregister.UCTXADDR isautomaticallyclearedwhen the startbitisgenerated. Figure22-4.Address-BitMultiprocessorFormat 22.3.3.2.1Break Receptionand Generation When UCMODEx = 00,01,or10,thereceiverdetectsa breakwhen alldata,parity,and stopbitsarelow, regardlessoftheparity,addressmode, orothercharactersettings.When a breakisdetected,theUCBRK bitisset.Ifthebreakinterruptenablebit(UCBRKIE) isset,thereceiveinterruptflagUCRXIFG isalsoset. Inthiscase,thevalueinUCAxRXBUF is0h,because alldatabitswere zero. To transmita break,settheUCTXBRK bit,thenwrite0h toUCAxTXBUF. UCAxTXBUF must be readyfor new data(UCTXIFG = 1).Thisgeneratesa breakwithallbitslow.UCTXBRK isautomaticallycleared when thestartbitisgenerated. 585SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

8 Bit Times

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com

22.3.4 Automatic Baud-Rate Detection

When UCMODEx = 11,UART mode withautomaticbaud-ratedetectionisselected.Forautomaticbaud- ratedetection,a dataframeisprecededby a synchronizationsequence thatconsistsofa breakand a synchfield.A breakisdetectedwhen 11 ormore continuouszeros(spaces)arereceived.Ifthelengthof thebreakexceeds21 bittimesthebreaktimeouterrorflagUCBTOE isset.The USCI can nottransmit datawhilereceivingthebreak/syncfield.The synchfieldfollowsthebreakas shown inFigure22-5. Figure22-5.Auto Baud-Rate Detection– Break/Synch Sequence ForLIN conformance,thecharacterformatshouldbe settoeightdatabits,LSB first,no parity,and one stopbit.No addressbitisavailable. The synchfieldconsistsofthedata055h insidea bytefield(seeFigure22-6).The synchronizationis based on thetimemeasurement between thefirstfallingedge and thelastfallingedge ofthepattern.The transmitbaud-rategeneratorisused forthemeasurement ifautomaticbaud-ratedetectionisenabledby settingUCABDEN. Otherwise,thepatternisreceivedbutnotmeasured.The resultofthemeasurement is transferredintothebaud-ratecontrolregisters(UCAxBR0, UCAxBR1, and UCAxMCTL). Ifthelengthof thesynchfieldexceedsthemeasurabletime,thesynchtimeouterrorflagUCSTOE isset. Figure22-6.Auto Baud-Rate Detection– Synch Field The UCDORM bitisused tocontroldatareceptioninthismode. When UCDORM isset,allcharactersare receivedbutnottransferredintotheUCAxRXBUF, and interruptsarenotgenerated.When a break/synch fieldisdetected,theUCBRK flagisset.The characterfollowingthebreak/synchfieldistransferredinto UCAxRXBUF and theUCRXIFG interruptflagisset.Any applicableerrorflagisalsoset.IftheUCBRKIE bitisset,receptionofthebreak/synchsetstheUCRXIFG. The UCBRK bitisresetby usersoftwareorby readingthereceivebufferUCAxRXBUF. When a break/synchfieldisreceived,usersoftwaremust resetUCDORM tocontinuereceivingdata.If UCDORM remainsset,onlythecharacterafterthenextreceptionofa break/synchfieldisreceived.The UCDORM bitisnotmodifiedby theUSCI hardwareautomatically. When UCDORM = 0,allreceivedcharacterssetthereceiveinterruptflagUCRXIFG. IfUCDORM is clearedduringthereceptionofa character,thereceiveinterruptflagissetafterthereceptioniscomplete. The counterused todetectthebaud rateislimitedto07FFFh (32767)counts.Thismeans theminimum baud ratedetectableis488 baud inoversamplingmode and 30 baud inlow-frequencymode. The automaticbaud-ratedetectionmode can be used ina full-duplexcommunicationsystemwithsome restrictions.The USCI can nottransmitdatawhilereceivingthebreak/syncfieldand,ifa 0h bytewith framingerrorisreceived,any datatransmittedduringthistimegetscorrupted.The lattercase can be discoveredby checkingthereceiveddataand theUCFE bit.

586 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode 22.3.4.1Transmittinga Break/Synch Field The followingproceduretransmitsa break/synchfield: 1. SetUCTXBRK withUMODEx = 11. 2. Write055h toUCAxTXBUF. UCAxTXBUF must be readyfornew data(UCTXIFG = 1). Thisgeneratesa breakfieldof13 bitsfollowedby a breakdelimiterand thesynchcharacter.The lengthofthebreakdelimiteriscontrolledwiththeUCDELIMx bits.UCTXBRK isresetautomatically when thesynchcharacteristransferredfromUCAxTXBUF intotheshiftregister. 3. WritedesireddatacharacterstoUCAxTXBUF. UCAxTXBUF must be readyfornew data (UCTXIFG = 1). The datawrittentoUCAxTXBUF istransferredtotheshiftregisterand transmittedas soon as theshift registerisreadyfornew data.

22.3.5 IrDA Encoding and Decoding

When UCIREN isset,theIrDAencoderand decoderareenabledand providehardwarebitshapingfor IrDAcommunication. 22.3.5.1IrDA Encoding The encodersends a pulseforeveryzerobitinthetransmitbitstreamcoming fromtheUART (see Figure22-7).The pulsedurationisdefinedby UCIRTXPLx bitsspecifyingthenumber ofone-halfclock periodsoftheclockselectedby UCIRTXCLK. Figure22-7.UART vs IrDA Data Format To setthepulsetimeof3/16bitperiodrequiredby theIrDAstandard,theBITCLK16 clockisselectedwith UCIRTXCLK = 1 ,andthepulselengthissettosixone-halfclockcycleswithUCIRTXPLx = 6 – 1 = 5. When UCIRTXCLK = 0,thepulselengthtPULSE isbased on BRCLK and iscalculatedas: UCIRTXPLx = tPULSE × 2 × fBRCLK – 1 When UCIRTXCLK = 0 ,theprescalerUCBRx must tobe settoa valuegreaterorequalto5. 22.3.5.2IrDA Decoding The decoderdetectshighpulseswhen UCIRRXPL = 0.Otherwise,itdetectslowpulses.Inadditiontothe analogdeglitchfilter,an additionalprogrammabledigitalfilterstagecan be enabledby settingUCIRRXFE. When UCIRRXFE isset,onlypulseslongerthantheprogrammed filterlengtharepassed.Shorterpulses arediscarded.The equationtoprogramthefilterlengthUCIRRXFLx is: UCIRRXFLx = (tPULSE − tWAKE )× 2 × fBRCLK – 4 Where: tPULSE = Minimum receivepulsewidth tWAKE = Wake timefromany low-powermode. Zerowhen thedeviceisinactivemode. 587SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com

22.3.6 Automatic ErrorDetection

GlitchsuppressionpreventstheUSCI frombeingaccidentallystarted.Any pulseon UCAxRXD shorter thanthedeglitchtimett (approximately150 ns)isignored(seethedevice-specificdatasheetfor parameters). When a lowperiodon UCAxRXD exceedstt,a majorityvoteistakenforthestartbit.Ifthemajorityvote failstodetecta validstartbit,theUSCI haltscharacterreceptionand waitsforthenextlowperiodon UCAxRXD. The majorityvoteisalsoused foreach bitina charactertopreventbiterrors. The USCI module automaticallydetectsframingerrors,parityerrors,overrunerrors,and breakconditions when receivingcharacters.The bitsUCFE, UCPE, UCOE, and UCBRK aresetwhen theirrespective conditionisdetected.When theerrorflagsUCFE, UCPE, orUCOE areset,UCRXERR isalsoset.The errorconditionsaredescribedinTable22-1. Table22-1.Receive ErrorConditions ErrorCondition ErrorFlag Description Framingerror UCFE A framingerroroccurswhen a lowstopbitisdetected.When two stopbitsareused,both stopbitsarecheckedforframingerror.When a framingerrorisdetected,theUCFE bitisset. Parityerror UCPE A parityerrorisa mismatchbetween thenumber of1s ina characterand thevalueofthe paritybit.When an addressbitisincludedinthecharacter,itisincludedintheparity calculation.When a parityerrorisdetected,theUCPE bitisset. Receiveoverrun UCOE An overrunerroroccurswhen a characterisloadedintoUCAxRXBUF beforetheprior characterhas been read.When an overrunoccurs,theUCOE bitisset. Breakcondition UCBRK When notusingautomaticbaud-ratedetection,a breakisdetectedwhen alldata,parity,and stopbitsarelow.When a breakconditionisdetected,theUCBRK bitisset.A breakcondition can alsosettheinterruptflagUCRXIFG ifthebreakinterruptenableUCBRKIE bitisset. When UCRXEIE = 0 and a framingerrororparityerrorisdetected,no characterisreceivedinto UCAxRXBUF. When UCRXEIE = 1,charactersarereceivedintoUCAxRXBUF and any applicableerror bitisset. When any oftheUCFE, UCPE, UCOE, UCBRK, orUCRXERR bitisset,thebitremainssetuntiluser softwareresetsitorUCAxRXBUF isread.UCOE must be resetby readingUCAxRXBUF. Otherwise,it does notfunctionproperly.To detectoverflowsreliablythefollowingflowisrecommended. Aftera characterwas receivedand UCAxRXIFG isset,firstreadUCAxSTAT tochecktheerrorflagsincludingthe overflowflagUCOE. Read UCAxRXBUF next.ThisclearsallerrorflagsexceptUCOE, ifUCAxRXBUF was overwrittenbetween thereadaccesstoUCAxSTAT and toUCAxRXBUF. Therefore,theUCOE flag shouldbe checkedafterreadingUCAxRXBUF todetectthiscondition.Note that,inthiscase,the UCRXERR flagisnotset.

588 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

Majority□Vote Taken t/c116 t/c116 UCAxRXD URXS ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode

22.3.7 USCI Receive Enable

The USCI module isenabledby clearingtheUCSWRST bitand thereceiverisreadyand inan idlestate. The receivebaud rategeneratorisina readystatebutisnotclockednorproducingany clocks. The fallingedge ofthestartbitenablesthebaud rategeneratorand theUART statemachine checksfora validstartbit.Ifno validstartbitisdetectedtheUART statemachine returnstoitsidlestateand thebaud rategeneratoristurnedoffagain.Ifa validstartbitisdetected,a characterisreceived. When theidle-linemultiprocessormode isselectedwithUCMODEx = 01 theUART statemachine checks foran idlelineafterreceivinga character.Ifa startbitisdetectedanothercharacterisreceived.Otherwise theUCIDLE flagissetafter10 ones arereceivedand theUART statemachine returnstoitsidlestateand thebaud rategeneratoristurnedoff. 22.3.7.1Receive Data GlitchSuppression GlitchsuppressionpreventstheUSCI frombeingaccidentallystarted.Any glitchon UCAxRXD shorter thanthedeglitchtimett (approximately150 ns)isignoredby theUSCI, and furtheractionisinitiatedas shown inFigure22-8(seethedevice-specificdatasheetforparameters). Figure22-8.GlitchSuppression,USCI Receive Not Started When a glitchislongerthantt,ora validstartbitoccurson UCAxRXD, theUSCI receiveoperationis startedand a majorityvoteistaken(seeFigure22-9).Ifthemajorityvotefailstodetecta startbit,the USCI haltscharacterreception. Figure22-9.GlitchSuppression,USCI Activated

22.3.8 USCI TransmitEnable

The USCI module isenabledby clearingtheUCSWRST bitand thetransmitterisreadyand inan idle state.The transmitbaud-rategeneratorisreadybutisnotclockednorproducingany clocks. A transmissionisinitiatedby writingdatatoUCAxTXBUF. When thisoccurs,thebaud-rategeneratoris enabled,and thedatainUCAxTXBUF ismoved tothetransmitshiftregisteron thenextBITCLK afterthe transmitshiftregisterisempty.UCTXIFG issetwhen new datacan be writtenintoUCAxTXBUF. Transmissioncontinuesas longas new dataisavailableinUCAxTXBUF attheend ofthepreviousbyte transmission.Ifnew dataisnotinUCAxTXBUF when thepreviousbytehas transmitted,thetransmitter returnstoitsidlestateand thebaud-rategeneratoristurnedoff. 589SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

0 N/2 N/2-11

INT(N/2) + m(= 0) INT(N/2) + m(= 1) 1 0 N/2 Bit Period NEVEN: INT(N/2) NODD: INT(N/2) + R(= 1) m: corresponding modulation bit R: Remainder from N/2 division Majority Vote: (m= 0) (m= 1) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com

22.3.9 UART Baud-Rate Generation

The USCI baud-rategeneratoriscapableofproducingstandardbaud ratesfromnonstandardsource frequencies.Itprovidestwo modes ofoperationselectedby theUCOS16 bit.The baud-rateisgenerate usingtheBRCLK thatcan be sourcedby theexternalclockUCAxCLK, ortheinternalclocksACLK or SMCLK dependingon theUCSSELx settings. 22.3.9.1Low-Frequency Baud-Rate Generation The low-frequencymode isselectedwhen UCOS16 = 0.Thismode allowsgenerationofbaud ratesfrom lowfrequencyclocksources(forexample,9600 baud froma 32768-Hz crystal).By usinga lowerinput frequency,thepower consumptionofthemodule isreduced.Usingthismode withhigherfrequenciesand higherprescalersettingscausesthemajorityvotestobe takeninan increasinglysmallerwindow and, thus,decreasethebenefitofthemajorityvote. Inlow-frequencymode, thebaud-rategeneratoruses one prescalerand one modulatortogeneratebit clocktiming.Thiscombinationsupportsfractionaldivisorsforbaud-rategeneration.Inthismode, the maximum USCI baud rateisone-thirdtheUART sourceclockfrequencyBRCLK. Timingforeach bitisshown inFigure22-10.Foreach bitreceived,a majorityvoteistakentodetermine thebitvalue.These samplesoccurattheN/2 – 1/2,N/2,and N/2 + 1/2BRCLK periods,where N isthe number ofBRCLKs perBITCLK. Figure22-10.BITCLK Baud-Rate Timing With UCOS16 = 0 Modulationisbased on theUCBRSx setting(seeTable22-2).A 1 inthetableindicatesthatm = 1 and the correspondingBITCLK periodisone BRCLK periodlongerthana BITCLK periodwithm = 0.The modulationwraps aroundaftereightbitsbutrestartswitheach new startbit. Table22-2.BITCLK ModulationPattern Bit0UCBRSx Bit1 Bit2 Bit3 Bit4 Bit5 Bit6 Bit7(StartBit) 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 2 0 1 0 0 0 1 0 0 3 0 1 0 1 0 1 0 0 4 0 1 0 1 0 1 0 1 5 0 1 1 1 0 1 0 1 6 0 1 1 1 0 1 1 1 7 0 1 1 1 1 1 1 1

590 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode 22.3.9.2Oversampling Baud-Rate Generation The oversamplingmode isselectedwhen UCOS16 = 1.Thismode supportssamplinga UART bitstream withhigherinputclockfrequencies.Thisresultsinmajorityvotesthatarealways1/16ofa bitclockperiod apart.Thismode alsoeasilysupportsIrDApulseswitha 3/16bittimewhen theIrDAencoderand decoder areenabled. Thismode uses one prescalerand one modulatortogeneratetheBITCLK16 clockthatis16 timesfaster thantheBITCLK. An additionaldividerand modulatorstagegeneratesBITCLK fromBITCLK16. This combinationsupportsfractionaldivisionsofbothBITCLK16 and BITCLK forbaud-rategeneration.Inthis mode, themaximum USCI baud rateis1/16theUART sourceclockfrequencyBRCLK. When UCBRx is setto0 or1,thefirstprescalerand modulatorstageisbypassedand BRCLK isequaltoBITCLK16 – in thiscase,no modulationfortheBITCLK16 ispossibleand,thus,theUCBRFx bitsareignored. ModulationforBITCLK16 isbased on theUCBRFx setting(seeTable22-3).A 1 inthetableindicatesthat thecorrespondingBITCLK16 periodisone BRCLK periodlongerthantheperiodsm = 0.The modulation restartswitheach new bittiming. ModulationforBITCLK isbased on theUCBRSx setting(seeTable22-2)as previouslydescribed. Table22-3.BITCLK16 ModulationPattern No. ofBITCLK16 Clocks AfterLastFallingBITCLK Edge UCBRFx 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 00h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 01h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 02h 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 03h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 04h 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 05h 0 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 06h 0 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 07h 0 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 08h 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 09h 0 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 0Ah 0 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 0Bh 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 0Ch 0 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0Dh 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 0Eh 0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 0Fh 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 591SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

mUCBR x F[j] j = 0 /c83 T [i] =bit,TX fBRCLK (((16 + m [i]) × UCBRx + [j]UCBRSx UCBR xm F/c83 j = 0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com

22.3.10 Settinga Baud Rate

Fora givenBRCLK clocksource,thebaud rateused determinestherequireddivisionfactorN: N = fBRCLK /Baudrate The divisionfactorN isoftena nonintegervalue,thus,atleastone dividerand one modulatorstageis used tomeet thefactoras closelyas possible. IfN isequalorgreaterthan16,theoversamplingbaud-rategenerationmode can be chosen by setting UCOS16. 22.3.10.1Low-Frequency Baud-Rate Mode Setting Inlow-frequencymode, theintegerportionofthedivisorisrealizedby theprescaler: UCBRx = INT(N) and thefractionalportionisrealizedby themodulatorwiththefollowingnominalformula: UCBRSx = round[(N – INT(N))× 8] IncrementingordecrementingtheUCBRSx settingby one countmay givea lowermaximum biterrorfor any givenbit.To determineifthisisthecase,a detailederrorcalculationmust be performedforeach bit foreach UCBRSx setting. 22.3.10.2Oversampling Baud-Rate Mode Setting Intheoversamplingmode, theprescalerissetto: UCBRx = INT(N/16) and thefirststagemodulatorissetto: UCBRFx = round([(N/16)– INT(N/16)]× 16) When greateraccuracyisrequired,theUCBRSx modulatorcan alsobe implementedwithvaluesfrom0 to7.To findthesettingthatgivesthelowestmaximum biterrorrateforany givenbit,a detailederror calculationmust be performedforallsettingsofUCBRSx from0 to7 withtheinitialUCBRFx setting,and withtheUCBRFx settingincrementedand decrementedby one.

22.3.11 TransmitBitTiming

The timingforeach characteristhesum oftheindividualbittimings.Usingthemodulationfeaturesofthe baud-rategeneratorreducesthecumulativebiterror.The individualbiterrorcan be calculatedusingthe followingsteps. 22.3.11.1Low-Frequency Baud-Rate Mode BitTiming Inlow-frequencymode, calculatethelengthofbitiTbit,TX[i]based on theUCBRx and UCBRSx settings: Tbit,TX[i]= (1/fBRCLK )(UCBRx + m UCBRSx [i]) Where: m UCBRSx [i]= ModulationofbitifromTable22-2 22.3.11.2Oversampling Baud-Rate Mode BitTiming Inoversamplingbaud-ratemode, calculatethelengthofbitiTbit,TX[i]based on thebaud-rategenerator UCBRx, UCBRFx and UCBRSx settings: Where: = Sum ofones fromthecorrespondingrow inTable22-3 m UCBRSx [i]= ModulationofbitifromTable22-2

592 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

T [j] +bit,RX i – 1 j = 0 /c83 1 fBRCLK t [i] = t +bit,RX SYNC INT(½UCBRx) + m [i]UCBRSx( ( 1 2 3 4 5 6 t0tideal 7 8 1 2 9 10 11 12 13 14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 2 3 4 5 6 7 ST D0 D1 D0 D1ST Synchronization Error ± 0.5x BRCLK Majority Vote Taken Majority Vote Taken Majority Vote Taken BRCLK UCAxRXD RXD synch. tactual Sample RXD synch. t1 t2 Tbit,TX[j] i j = 0 /c83Tbit,TX[i] = ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode Thisresultsinan end-of-bittimetbit,TX[i]equaltothesum ofallpreviousand thecurrentbittimes: To calculatebiterror,thistimeiscompared totheidealbittimetbit,ideal,TX[i]: tbit,ideal,TX[i]= (1/Baudrate)(i+ 1) Thisresultsinan errornormalizedtoone idealbittime(1/baudrate): ErrorTX [i]= (tbit,TX[i]– tbit,ideal,TX[i])× Baudrate× 100%

22.3.12 Receive BitTiming

Receivetimingerrorconsistsoftwo errorsources.The firstisthebit-to-bittimingerrorsimilartothe transmitbittimingerror.The second istheerrorbetween a startedge occurringand thestartedge being acceptedby theUSCI module.Figure22-11shows theasynchronoustimingerrorsbetween dataon the UCAxRXD pinand theinternalbaud-rateclock.Thisresultsinan additionalsynchronizationerror.The synchronizationerrortSYNC isbetween –0.5BRCLKs and +0.5 RCLKs, independentoftheselectedbaud- rategenerationmode. Figure22-11.Receive Error The idealsamplingtimetbit,ideal,RX[i]isinthemiddleofa bitperiod: tbit,ideal,RX[i]= (1/Baudrate)(i+ 0.5) The realsamplingtime,tbit,RX[i],isequaltothesum ofallpreviousbitsaccordingtotheformulasshown in thetransmittimingsection,plusone-halfBITCLK forthecurrentbiti,plusthesynchronizationerrortSYNC . Thisresultsinthefollowingtbit,RX[i]forthelow-frequencybaud-ratemode: Where: Tbit,RX[i]= (1/fBRCLK )(UCBRx + m UCBRSx [i]) m UCBRSx [i]= ModulationofbitifromTable22-2 593SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

m [j]UCBRFx 7 + m [i]UCBRSx j = 0 /c83 (16 + m [i]) × UCBRx +UCBRSxT [i] =bit,RX fBRCLK ( (m [j]UCBRFx j = 0 /c83 t [i] = t +bit,RX SYNC (8 + m [i]) × UCBRx +UCBRSxT [j] +bit,RX i – 1 j = 0 /c83 fBRCLK ( (m [j]UCBRFx 7 + m [i]UCBRSx j = 0 /c83 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com Fortheoversamplingbaud-ratemode, thesamplingtimetbit,RX[i]ofbitiiscalculatedby: Where: = Sum ofones fromcolumns0 to(7+ m UCBRSx [i])fromthecorrespondingrow in Table22-3. m UCBRSx [i]= ModulationofbitifromTable22-2 Thisresultsinan errornormalizedtoone idealbittime(1/baudrate)accordingtothefollowingformula: ErrorRX [i]= (tbit,RX[i]– tbit,ideal,RX[i])× Baudrate× 100%

22.3.13 TypicalBaud Rates and Errors

Standardbaud-ratedataforUCBRx, UCBRSx, and UCBRFx arelistedinTable22-4and Table22-5fora 32,768-HzcrystalsourcingACLK and typicalSMCLK frequencies.Pleaseensurethattheselected BRCLK frequencydoes notexceed thedevicespecificmaximum USCI inputfrequency(seethedevice- specificdatasheet). The receiveerroristheaccumulatedtimeversustheidealscanningtimeinthemiddleofeach bit.The worst-caseerrorisgivenforthereceptionofan 8-bitcharacterwithparityand one stopbitincluding synchronizationerror. The transmiterroristheaccumulatedtimingerrorversustheidealtimeofthebitperiod.The worst-case errorisgivenforthetransmissionofan 8-bitcharacterwithparityand stopbit. Table22-4.Commonly Used Baud Rates,Settings,and Errors,UCOS16 = 0 BRCLK Baud Rate Maximum TX Error Maximum RX ErrorFrequency UCBRx UCBRSx UCBRFx(baud) (%) (%)(Hz) 32,768 1200 27 2 0 -2.8 1.4 -5.9 2.0 32,768 2400 13 6 0 -4.8 6.0 -9.7 8.3 32,768 4800 6 7 0 -12.1 5.7 -13.4 19.0 32,768 9600 3 3 0 -21.1 15.2 -44.3 21.3 1,000,000 9600 104 1 0 -0.5 0.6 -0.9 1.2 1,000,000 19200 52 0 0 -1.8 0 -2.6 0.9 1,000,000 38400 26 0 0 -1.8 0 -3.6 1.8 1,000,000 57600 17 3 0 -2.1 4.8 -6.8 5.8 1,000,000 115200 8 6 0 -7.8 6.4 -9.7 16.1 1,048,576 9600 109 2 0 -0.2 0.7 -1.0 0.8 1,048,576 19200 54 5 0 -1.1 1.0 -1.5 2.5 1,048,576 38400 27 2 0 -2.8 1.4 -5.9 2.0 1,048,576 57600 18 1 0 -4.6 3.3 -6.8 6.6 1,048,576 115200 9 1 0 -1.1 10.7 -11.5 11.3 4,000,000 9600 416 6 0 -0.2 0.2 -0.2 0.4 4,000,000 19200 208 3 0 -0.2 0.5 -0.3 0.8 4,000,000 38400 104 1 0 -0.5 0.6 -0.9 1.2 4,000,000 57600 69 4 0 -0.6 0.8 -1.8 1.1 4,000,000 115200 34 6 0 -2.1 0.6 -2.5 3.1 4,000,000 230400 17 3 0 -2.1 4.8 -6.8 5.8 4,194,304 9600 436 7 0 -0.3 0 -0.3 0.2

594 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode Table22-4.Commonly Used Baud Rates,Settings,and Errors,UCOS16 = 0 (continued) BRCLK Baud Rate Maximum TX Error Maximum RX ErrorFrequency UCBRx UCBRSx UCBRFx(baud) (%) (%)(Hz) 4,194,304 19200 218 4 0 -0.2 0.2 -0.3 0.6 4,194,304 57600 72 7 0 -1.1 0.6 -1.3 1.9 4,194,304 115200 36 3 0 -1.9 1.5 -2.7 3.4 8,000,000 9600 833 2 0 -0.1 0 -0.2 0.1 8,000,000 19200 416 6 0 -0.2 0.2 -0.2 0.4 8,000,000 38400 208 3 0 -0.2 0.5 -0.3 0.8 8,000,000 57600 138 7 0 -0.7 0 -0.8 0.6 8,000,000 115200 69 4 0 -0.6 0.8 -1.8 1.1 8,000,000 230400 34 6 0 -2.1 0.6 -2.5 3.1 8,000,000 460800 17 3 0 -2.1 4.8 -6.8 5.8 8,388,608 9600 873 7 0 -0.1 0.06 -0.2 0,1 8,388,608 19200 436 7 0 -0.3 0 -0.3 0.2 8,388,608 57600 145 5 0 -0.5 0.3 -1.0 0.5 8,388,608 115200 72 7 0 -1.1 0.6 -1.3 1.9 12,000,000 9600 1250 0 0 0 0 -0.05 0.05 12,000,000 19200 625 0 0 0 0 -0.2 0 12,000,000 38400 312 4 0 -0.2 0 -0.2 0.2 12,000,000 57600 208 2 0 -0.5 0.2 -0.6 0.5 12,000,000 115200 104 1 0 -0.5 0.6 -0.9 1.2 12,000,000 230400 52 0 0 -1.8 0 -2.6 0.9 12,000,000 460800 26 0 0 -1.8 0 -3.6 1.8 16,000,000 9600 1666 6 0 -0.05 0.05 -0.05 0.1 16,000,000 19200 833 2 0 -0.1 0.05 -0.2 0.1 16,000,000 38400 416 6 0 -0.2 0.2 -0.2 0.4 16,000,000 57600 277 7 0 -0.3 0.3 -0.5 0.4 16,000,000 115200 138 7 0 -0.7 0 -0.8 0.6 16,000,000 230400 69 4 0 -0.6 0.8 -1.8 1.1 16,000,000 460800 34 6 0 -2.1 0.6 -2.5 3.1 16,777,216 9600 1747 5 0 -0.04 0.03 -0.08 0.05 16,777,216 19200 873 7 0 -0.09 0.06 -0.2 0.1 16,777,216 57600 291 2 0 -0.2 0.2 -0.5 0.2 16,777,216 115200 145 5 0 -0.5 0.3 -1.0 0.5 20,000,000 9600 2083 2 0 -0.05 0.02 -0.09 0.02 20,000,000 19200 1041 6 0 -0.06 0.06 -0.1 0.1 20,000,000 38400 520 7 0 -0.2 0.06 -0.2 0.2 20,000,000 57600 347 2 0 -0.06 0.2 -0.3 0.3 20,000,000 115200 173 5 0 -0.4 0.3 -0.8 0.5 20,000,000 230400 86 7 0 -1.0 0.6 -1.0 1.7 20,000,000 460800 43 3 0 -1.4 1.3 -3.3 1.8 595SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com Table22-5.Commonly Used Baud Rates,Settings,and Errors,UCOS16 = 1 BRCLK Baud Rate Maximum TX Error Maximum RX ErrorFrequency UCBRx UCBRSx UCBRFx(baud) (%) (%)(Hz) 1,000,000 9600 6 0 8 -1.8 0 -2.2 0.4 1,000,000 19200 3 0 4 -1.8 0 -2.6 0.9 1,048,576 9600 6 0 13 -2.3 0 -2.2 0.8 1,048,576 19200 3 1 6 -4.6 3.2 -5.0 4.7 4,000,000 9600 26 0 1 0 0.9 0 1.1 4,000,000 19200 13 0 0 -1.8 0 -1.9 0.2 4,000,000 38400 6 0 8 -1.8 0 -2.2 0.4 4,000,000 57600 4 5 3 -3.5 3.2 -1.8 6.4 4,000,000 115200 2 3 2 -2.1 4.8 -2.5 7.3 4,194,304 9600 27 0 5 0 0.2 0 0.5 4,194,304 19200 13 0 10 -2.3 0 -2.4 0.1 4,194,304 57600 4 4 7 -2.5 2.5 -1.3 5.1 4,194,304 115200 2 6 3 -3.9 2.0 -1.9 6.7 8,000,000 9600 52 0 1 -0.4 0 -0.4 0.1 8,000,000 19200 26 0 1 0 0.9 0 1.1 8,000,000 38400 13 0 0 -1.8 0 -1.9 0.2 8,000,000 57600 8 0 11 0 0.88 0 1.6 8,000,000 115200 4 5 3 -3.5 3.2 -1.8 6.4 8,000,000 230400 2 3 2 -2.1 4.8 -2.5 7.3 8,388,608 9600 54 0 10 0 0.2 -0.05 0.3 8,388,608 19200 27 0 5 0 0.2 0 0.5 8,388,608 57600 9 0 2 0 2.8 -0.2 3.0 8,388,608 115200 4 4 7 -2.5 2.5 -1.3 5.1 12,000,000 9600 78 0 2 0 0 -0.05 0.05 12,000,000 19200 39 0 1 0 0 0 0.2 12,000,000 38400 19 0 8 -1.8 0 -1.8 0.1 12,000,000 57600 13 0 0 -1.8 0 -1.9 0.2 12,000,000 115200 6 0 8 -1.8 0 -2.2 0.4 12,000,000 230400 3 0 4 -1.8 0 -2.6 0.9 16,000,000 9600 104 0 3 0 0.2 0 0.3 16,000,000 19200 52 0 1 -0.4 0 -0.4 0.1 16,000,000 38400 26 0 1 0 0.9 0 1.1 16,000,000 57600 17 0 6 0 0.9 -0.1 1.0 16,000,000 115200 8 0 11 0 0.9 0 1.6 16,000,000 230400 4 5 3 -3.5 3.2 -1.8 6.4 16,000,000 460800 2 3 2 -2.1 4.8 -2.5 7.3 16,777,216 9600 109 0 4 0 0.2 -0.02 0.3 16,777,216 19200 54 0 10 0 0.2 -0.05 0.3 16,777,216 57600 18 0 3 -1.0 0 -1.0 0.3 16,777,216 115200 9 0 2 0 2.8 -0.2 3.0 20,000,000 9600 130 0 3 -0.2 0 -0.2 0.04 20,000,000 19200 65 0 2 0 0.4 -0.03 0.4 20,000,000 38400 32 0 9 0 0.4 0 0.5 20,000,000 57600 21 0 11 -0.7 0 -0.7 0.3 20,000,000 115200 10 0 14 0 2.5 -0.2 2.6 20,000,000 230400 5 0 7 0 2.5 0 3.5

596 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– UART Mode Table22-5.Commonly Used Baud Rates,Settings,and Errors,UCOS16 = 1 (continued) BRCLK Baud Rate Maximum TX Error Maximum RX ErrorFrequency UCBRx UCBRSx UCBRFx(baud) (%) (%)(Hz) 20,000,000 460800 2 6 10 -3.2 1.8 -2.8 4.6

22.3.14 Using theUSCI Module inUART Mode With Low-Power Modes

22.3.15 USCI Interrupts

The USCI has onlyone interruptvectorthatissharedfortransmissionand forreception.USCI_Ax and USC_Bx do notsharethesame interruptvector. 22.3.15.1USCI TransmitInterruptOperation The UCTXIFG interruptflagissetby thetransmittertoindicatethatUCAxTXBUF isreadytoaccept anothercharacter.An interruptrequestisgeneratedifUCTXIE and GIE arealsoset.UCTXIFG is automaticallyresetifa characteriswrittentoUCAxTXBUF. UCTXIFG issetaftera PUC orwhen UCSWRST = 1.UCTXIE isresetaftera PUC orwhen UCSWRST = 1. 22.3.15.2USCI Receive InterruptOperation The UCRXIFG interruptflagisseteach timea characterisreceivedand loadedintoUCAxRXBUF. An interruptrequestisgeneratedifUCRXIE and GIE arealsoset.UCRXIFG and UCRXIE areresetby a systemresetPUC signalorwhen UCSWRST = 1.UCRXIFG isautomaticallyresetwhen UCAxRXBUF is read. Additionalinterruptcontrolfeaturesinclude:

When UCAxRXEIE = 0,erroneouscharactersdo notsetUCRXIFG.
When UCDORM = 1,nonaddresscharactersdo notsetUCRXIFG inmultiprocessormodes. Inplain UART mode, no charactersaresetUCRXIFG.
When UCBRKIE = 1,a breakconditionsetstheUCBRK bitand theUCRXIFG flag. 22.3.15.3UCAxIV, InterruptVectorGenerator The USCI interruptflagsareprioritizedand combined tosourcea singleinterruptvector.The interrupt vectorregisterUCAxIV isused todeterminewhichflagrequestedan interrupt.The highest-priority enabledinterruptgeneratesa number intheUCAxIV registerthatcan be evaluatedoradded tothe programcountertoautomaticallyentertheappropriatesoftwareroutine.Disabledinterruptsdo notaffect theUCAxIV value. Any access,readorwrite,oftheUCAxIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. 597SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– UART Mode www.ti.com 22.3.15.3.1UCAxIV SoftwareExample The followingsoftwareexample shows therecommended use ofUCAxIV. The UCAxIV valueisadded to thePC toautomaticallyjump totheappropriateroutine.The followingexample isgivenforUSCI_A0. USCI_UART_ISR ADD &UCA0IV,PC ;Addoffsettojumptable RETI ;Vector0:Nointerrupt JMP RXIFG_ISR;Vector2:RXIFG TXIFG_ISR ;Vector4:TXIFG ... ;Taskstartshere RETI ;Return RXIFG_ISR ;Vector2 ... ;Taskstartshere RETI ;Return

598 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI_A UART Mode Registers

22.4 USCI_A UART Mode Registers

The USCI registersapplicableinUART mode listedinTable22-6.The base addresscan be foundinthe device-specificdatasheet.The addressoffsetsarelistedinTable22-6. Table22-6.USCI_A UART Mode Registers Offset Acronym RegisterName Type Access Reset Section 00h UCAxCTLW0 USCI_Ax ControlWord 0 Read/write Word 0001h 00h UCAxCTL1 USCI_Ax Control1 Read/write Byte 01h Section22.4.2 01h UCAxCTL0 USCI_Ax Control0 Read/write Byte 00h Section22.4.1 06h UCAxBRW USCI_Ax Baud Rate ControlWord Read/write Word 0000h 06h UCAxBR0 USCI_Ax Baud Rate Control0 Read/write Byte 00h Section22.4.3 07h UCAxBR1 USCI_Ax Baud Rate Control1 Read/write Byte 00h Section22.4.4 08h UCAxMCTL USCI_Ax ModulationControl Read/write Byte 00h Section22.4.5 09h Reserved-readszero Read Byte 00h 0Ah UCAxSTAT USCI_Ax Status Read/write Byte 00h Section22.4.6 0Bh Reserved-readszero Read Byte 00h 0Ch UCAxRXBUF USCI_Ax ReceiveBuffer Read/write Byte 00h Section22.4.7 0Dh Reserved-readszero Read Byte 00h 0Eh UCAxTXBUF USCI_Ax TransmitBuffer Read/write Byte 00h Section22.4.8 0Fh Reserved-readszero Read Byte 00h 10h UCAxABCTL USCI_Ax AutoBaud Rate Control Read/write Byte 00h Section22.4.11 11h Reserved-readszero Read Byte 00h 12h UCAxIRCTL USCI_Ax IrDAControl Read/write Word 0000h 12h UCAxIRTCTL USCI_Ax IrDATransmitControl Read/write Byte 00h Section22.4.9 13h UCAxIRRCTL USCI_Ax IrDAReceiveControl Read/write Byte 00h Section22.4.10 1Ch UCAxICTL USCI_Ax InterruptControl Read/write Word 0000h 1Ch UCAxIE USCI_Ax InterruptEnable Read/write Byte 00h Section22.4.12 1Dh UCAxIFG USCI_Ax InterruptFlag Read/write Byte 00h Section22.4.13 1Eh UCAxIV USCI_Ax InterruptVector Read Word 0000h Section22.4.14 599SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI_A UART Mode Registers www.ti.com

22.4.1 UCAxCTL0 Register

USCI_Ax ControlRegister0 Figure22-12.UCAxCTL0 Register 7 6 5 4 3 2 1 0 UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Modifyonlywhen UCSWRST = 1. Table22-7.UCAxCTL0 RegisterDescription Bit Field Type Reset Description

7 UCPEN RW 0h Parityenable

0b = Paritydisabled 1b = Parityenabled.Paritybitisgenerated(UCAxTXD) and expected (UCAxRXD). Inaddress-bitmultiprocessormode, theaddressbitisincludedin theparitycalculation. 6 UCPAR RW 0h Parityselect.UCPAR isnotused when parityisdisabled. 0b = Odd parity 1b = Even parity 5 UCMSB RW 0h MSB firstselect.Controlsthedirectionofthereceiveand transmitshiftregister. 0b = LSB first 1b = MSB first 4 UC7BIT RW 0h Characterlength.Selects7-bitor8-bitcharacterlength. 0b = 8-bitdata 1b = 7-bitdata 3 UCSPB RW 0h Stopbitselect.Number ofstopbits. 0b = One stopbit 1b = Two stopbits 2-1 UCMODEx RW 0h USCI mode. The UCMODEx bitsselecttheasynchronousmode when UCSYNC = 0. 00b = UART mode 01b = Idle-linemultiprocessormode 10b = Address-bitmultiprocessormode 11b = UART mode withautomaticbaud-ratedetection

0 UCSYNC RW 0h Synchronousmode enable

0b = Asynchronousmode 1b = Synchronousmode

600 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI_A UART Mode Registers

22.4.2 UCAxCTL1 Register

USCI_Ax ControlRegister1 Figure22-13.UCAxCTL1 Register 7 6 5 4 3 2 1 0 UCSSELx UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 Modifyonlywhen UCSWRST = 1. Table22-8.UCAxCTL1 RegisterDescription Bit Field Type Reset Description 7-6 UCSSELx RW 0h USCI clocksourceselect.These bitsselecttheBRCLK sourceclock. 00b = UCAxCLK (externalUSCI clock) 01b = ACLK 10b = SMCLK 11b = SMCLK

5 UCRXEIE RW 0h Receiveerroneous-characterinterruptenable

0b = Erroneouscharactersrejectedand UCRXIFG isnotset. 1b = ErroneouscharactersreceivedsetUCRXIFG.

4 UCBRKIE RW 0h Receivebreakcharacterinterruptenable

0b = Receivedbreakcharactersdo notsetUCRXIFG. 1b = ReceivedbreakcharacterssetUCRXIFG. 3 UCDORM RW 0h Dormant.PutsUSCI intosleepmode. 0b = Not dormant.AllreceivedcharacterssetUCRXIFG. 1b = Dormant.Onlycharactersthatareprecededby an idle-lineorwithaddress bitsetUCRXIFG. InUART mode withautomaticbaud-ratedetection,onlythe combinationofa breakand synchfieldsetsUCRXIFG. 2 UCTXADDR RW 0h Transmitaddress.Nextframetobe transmittedismarked as address,depending on theselectedmultiprocessormode. 0b = Nextframetransmittedisdata. 1b = Nextframetransmittedisan address. 1 UCTXBRK RW 0h Transmitbreak.Transmitsa breakwiththenextwritetothetransmitbuffer.In UART mode withautomaticbaud-ratedetection,055h must be writteninto UCAxTXBUF togeneratetherequiredbreak/synchfields.Otherwise,0h must be writtenintothetransmitbuffer. 0b = Nextframetransmittedisnota break. 1b = Nextframetransmittedisa breakora break/synch.

0 UCSWRST RW 1h Softwareresetenable

0b = Disabled.USCI resetreleasedforoperation. 1b = Enabled.USCI logicheldinresetstate. 601SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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22.4.3 UCAxBR0 Register

USCI_Ax Baud Rate ControlRegister0 Figure22-14.UCAxBR0 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table22-9.UCAxBR0 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefine Low byteofclockprescalersettingofthebaud-rategenerator.The 16-bitvalue d of(UCAxBR0 + UCAxBR1 × 256)formstheprescalervalueUCBRx.

22.4.4 UCAxBR1 Register

USCI_Ax Baud Rate ControlRegister1 Figure22-15.UCAxBR1 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table22-10.UCAxBR1 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefined Highbyteofclockprescalersettingofthebaud-rategenerator.The 16-bitvalue of(UCAxBR0 + UCAxBR1 × 256)formstheprescalervalueUCBRx.

22.4.5 UCAxMCTL Register

USCI_Ax ModulationControlRegister Figure22-16.UCAxMCTL Register 7 6 5 4 3 2 1 0 UCBRFx UCBRSx UCOS16 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Modifyonlywhen UCSWRST = 1. Table22-11.UCAxMCTL RegisterDescription Bit Field Type Reset Description 7-4 UCBRFx RW 0h Firstmodulationstageselect.These bitsdeterminethemodulationpatternfor BITCLK16 when UCOS16 = 1.IgnoredwithUCOS16 = 0.Table22-2shows the modulationpattern. 3-1 UCBRSx RW 0h Second modulationstageselect.These bitsdeterminethemodulationpatternfor BITCLK. Table22-2shows themodulationpattern.

0 UCOS16 RW 0h Oversamplingmode enabled

0b = Disabled 1b = Enabled

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22.4.6 UCAxSTAT Register

USCI_Ax StatusRegister Figure22-17.UCAxSTAT Register 7 6 5 4 3 2 1 0 UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR/ UCBUSY UCIDLE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0 Modifyonlywhen UCSWRST = 1. Table22-12.UCAxSTAT RegisterDescription Bit Field Type Reset Description 7 UCLISTEN RW 0h Listenenable.The UCLISTEN bitselectsloopbackmode. 0b = Disabled 1b = Enabled.UCAxTXD isinternallyfedback tothereceiver. 6 UCFE RW 0h Framingerrorflag.UCFE isclearedwhen UCAxRXBUF isread. 0b = No error 1b = Characterreceivedwithlowstopbit 5 UCOE RW 0h Overrunerrorflag.Thisbitissetwhen a characteristransferredinto UCAxRXBUF beforethepreviouscharacterwas read.UCOE iscleared automaticallywhen UCxRXBUF isread,and must notbe clearedby software. Otherwise,itdoes notfunctioncorrectly. 0b = No error 1b = Overrunerroroccurred 4 UCPE RW 0h Parityerrorflag.When UCPEN = 0,UCPE isreadas 0.UCPE isclearedwhen UCAxRXBUF isread. 0b = No error 1b = Characterreceivedwithparityerror 3 UCBRK RW 0h Breakdetectflag.UCBRK isclearedwhen UCAxRXBUF isread. 0b = No breakcondition 1b = Breakconditionoccurred 2 UCRXERR RW 0h Receiveerrorflag.Thisbitindicatesa characterwas receivedwitherror(s). When UCRXERR = 1,on ormore errorflags,UCFE, UCPE, orUCOE isalso set.UCRXERR isclearedwhen UCAxRXBUF isread. 0b = No receiveerrorsdetected 1b = Receiveerrordetected 1 UCADDR/UCIDLE RW 0h UCADDR: Addressreceivedinaddress-bitmultiprocessormode. UCADDR is clearedwhen UCAxRXBUF isread. 0b = Receivedcharacterisdata. 1b = Receivedcharacterisan address. UCIDLE: Idlelinedetectedinidle-linemultiprocessormode. UCIDLE iscleared when UCAxRXBUF isread. 0b = No idlelinedetected 1b = Idlelinedetected 0 UCBUSY R 0h USCI busy.Thisbitindicatesifa transmitorreceiveoperationisinprogress. 0b = USCI inactive 1b = USCI transmittingorreceiving 603SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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22.4.7 UCAxRXBUF Register

USCI_Ax ReceiveBufferRegister Figure22-18.UCAxRXBUF Register 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r Table22-13.UCAxRXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCRXBUFx R undefined The receive-databufferisuseraccessibleand containsthelastreceived characterfromthereceiveshiftregister.ReadingUCAxRXBUF resetsthe receive-errorbits,theUCADDR orUCIDLE bit,and UCRXIFG. In7-bitdata mode, UCAxRXBUF isLSB justifiedand theMSB isalwaysreset.

22.4.8 UCAxTXBUF Register

USCI_Ax TransmitBufferRegister Figure22-19.UCAxTXBUF Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table22-14.UCAxTXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCTXBUFx RW undefined The transmitdatabufferisuseraccessibleand holdsthedatawaitingtobe moved intothetransmitshiftregisterand transmittedon UCAxTXD. Writingto thetransmitdatabufferclearsUCTXIFG. The MSB ofUCAxTXBUF isnotused for7-bitdataand isreset.

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22.4.9 UCAxIRTCTL Register

USCI_Ax IrDATransmitControlRegister Figure22-20.UCAxIRTCTL Register 7 6 5 4 3 2 1 0 UCIRTXPLx UCIRTXCLK UCIREN rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Modifyonlywhen UCSWRST = 1. Table22-15.UCAxIRTCTL RegisterDescription Bit Field Type Reset Description 7-2 UCIRTXPLx RW 0h Transmitpulselength.Pulselengtht(PULSE)= (UCIRTXPLx + 1)/[2× f(IRTXCLK)]

1 UCIRTXCLK RW 0h IrDAtransmitpulseclockselect

0b = BRCLK 1b = BITCLK16 when UCOS16 = 1.Otherwise,BRCLK.

0 UCIREN RW 0h IrDAencoderand decoderenable

0b = IrDAencoderand decoderdisabled 1b = IrDAencoderand decoderenabled

22.4.10 UCAxIRRCTL Register

USCI_Ax IrDAReceiveControlRegister Figure22-21.UCAxIRRCTL Register 7 6 5 4 3 2 1 0 UCIRRXFLx UCIRRXPL UCIRRXFE rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Modifyonlywhen UCSWRST = 1. Table22-16.UCAxIRRCTL RegisterDescription Bit Field Type Reset Description 7-2 UCIRRXFLx RW 0h Receivefilterlength.The minimum pulselengthforreceiveisgivenby:t(MIN)= (UCIRRXFLx + 4)/(2× f(BRCLK))

1 UCIRRXPL RW 0h IrDAreceiveinputUCAxRXD polarity

0b = IrDAtransceiverdeliversa highpulsewhen a lightpulseisseen. 1b = IrDAtransceiverdeliversa lowpulsewhen a lightpulseisseen.

0 UCIRRXFE RW 0h IrDAreceivefilterenabled

0b = Receivefilterdisabled 1b = Receivefilterenabled 605SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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22.4.11 UCAxABCTL Register

USCI_Ax AutoBaud Rate ControlRegister Figure22-22.UCAxABCTL Register 7 6 5 4 3 2 1 0 Reserved UCDELIMx UCSTOE UCBTOE Reserved UCABDEN r-0 r-0 rw-0 rw-0 rw-0 rw-0 r-0 rw-0 Modifyonlywhen UCSWRST = 1. Table22-17.UCAxABCTL RegisterDescription Bit Field Type Reset Description 7-6 Reserved R 0h Reserved.Alwaysreadsas 0. 5-4 UCDELIMx RW 0h Breakand synchdelimiterlength 00b = 1 bittime 01b = 2 bittimes 10b = 3 bittimes 11b = 4 bittimes

3 UCSTOE RW 0h Synch fieldtimeouterror

0b = No error 1b = Lengthofsynchfieldexceeded measurabletime.

2 UCBTOE RW 0h Breaktimeouterror

0b = No error 1b = Lengthofbreakfieldexceeded 22 bittimes. 1 Reserved R 0h Reserved.Alwaysreadsas 0.

0 UCABDEN RW 0h Automaticbaud-ratedetectenable

0b = Baud-ratedetectiondisabled.Lengthofbreakand synchfieldisnot measured. 1b = Baud-ratedetectionenabled.Lengthofbreakand synchfieldismeasured and baud-ratesettingsarechanged accordingly.

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22.4.12 UCAxIE Register

USCI_Ax InterruptEnableRegister Figure22-23.UCAxIE Register 7 6 5 4 3 2 1 0 Reserved UCTXIE UCRXIE r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 Table22-18.UCAxIE RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0.

1 UCTXIE RW 0h Transmitinterruptenable

0b = Interruptdisabled 1b = Interruptenabled

0 UCRXIE RW 0h Receiveinterruptenable

0b = Interruptdisabled 1b = Interruptenabled

22.4.13 UCAxIFG Register

USCI_Ax InterruptFlagRegister Figure22-24.UCAxIFG Register 7 6 5 4 3 2 1 0 Reserved UCTXIFG UCRXIFG r-0 r-0 r-0 r-0 r-0 r-0 rw-1 rw-0 Table22-19.UCAxIFG RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 UCTXIFG RW 1h Transmitinterruptflag.UCTXIFG issetwhen UCAxTXBUF empty. 0b = No interruptpending 1b = Interruptpending 0 UCRXIFG RW 0h Receiveinterruptflag.UCRXIFG issetwhen UCAxRXBUF has receiveda completecharacter. 0b = No interruptpending 1b = Interruptpending 607SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– UART Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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22.4.14 UCAxIV Register

USCI_Ax InterruptVectorRegister Figure22-25.UCAxIV Register 15 14 13 12 11 10 9 8 UCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table22-20.UCAxIV RegisterDescription Bit Field Type Reset Description 15-0 UCIVx R 0h USCI interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Data received;InterruptFlag:UCRXIFG; Interrupt Priority:Highest 04h = InterruptSource:Transmitbufferempty;InterruptFlag:UCTXIFG; InterruptPriority:Lowest

608 UniversalSerialCommunicationInterface– UART Mode SLAU259E –May 2009–RevisedJanuary2013

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter23 SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunication Interface– SPI Mode The universalserialcommunicationinterface(USCI)supportsmultipleserialcommunicationmodes with one hardwaremodule.Thischapterdiscussestheoperationofthesynchronousperipheralinterface(SPI) mode. 609SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. UniversalSerialCommunicationInterface(USCI)Overview www.ti.com

23.1 UniversalSerialCommunication Interface(USCI)Overview

The universalserialcommunicationinterface(USCI)modules supportmultipleserialcommunication modes. DifferentUSCI modules supportdifferentmodes. Each differentUSCI module isnamed witha differentletter.Forexample,USCI_A isdifferentfromUSCI_B, etc.Ifmore thanone identicalUSCI module isimplementedon one device,thosemodules arenamed withincrementingnumbers.For example,ifone devicehas two USCI_A modules,theyarenamed USCI_A0 and USCI_A1. See the device-specificdatasheettodeterminewhichUSCI modules,ifany,areimplementedon whichdevices. USCI_Ax modules support:

UART mode
PulseshapingforIrDAcommunications
Automaticbaud-ratedetectionforLIN communications
SPI mode USCI_Bx modules support:
I2C mode
SPI mode

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Introduction– SPI Mode

23.2 USCI Introduction– SPI Mode

Insynchronousmode, theUSCI connectsthedevicetoan externalsystemviathreeorfourpins: UCxSIMO, UCxSOMI, UCxCLK, and UCxSTE. SPI mode isselectedwhen theUCSYNC bitisset,and SPI mode (3-pinor4-pin)isselectedwiththeUCMODEx bits. SPI mode featuresinclude:

7-bitor8-bitdatalength
LSB-firstorMSB-firstdatatransmitand receive
3-pinand 4-pinSPI operation
Masterorslavemodes
Independenttransmitand receiveshiftregisters
Separatetransmitand receivebufferregisters
Continuoustransmitand receiveoperation
Selectableclockpolarityand phase control
Programmable clockfrequencyinmastermode
Independentinterruptcapabilityforreceiveand transmit
SlaveoperationinLPM4 Figure23-1shows theUSCI when configuredforSPI mode. 611SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Clock Direction, Phase and Polarity UCCKPH UCCKPL UCxSIMO UCxCLK Set UCOE Transmit Enable Control UCMODEx UCxSTE Set UCFE ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Introduction– SPI Mode www.ti.com Figure23-1.USCI Block Diagram – SPI Mode

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23.3 USCI Operation– SPI Mode

InSPI mode, serialdataistransmittedand receivedby multipledevicesusinga sharedclockprovidedby themaster.An additionalpin,UCxSTE, isprovidedtoenablea devicetoreceiveand transmitdataand is controlledby themaster. Threeorfoursignalsareused forSPI dataexchange:

UCxSIMO – slavein,masterout Mastermode: UCxSIMO isthedataoutputline. Slavemode: UCxSIMO isthedatainputline.
UCxSOMI – slaveout,masterin Mastermode: UCxSOMI isthedatainputline. Slavemode: UCxSOMI isthedataoutputline.
UCxCLK – USCI SPI clock Mastermode: UCxCLK isan output. Slavemode: UCxCLK isan input.
UCxSTE – slavetransmitenable Used in4-pinmode toallowmultiplemasterson a singlebus.Not used in3-pinmode. Table23-1describestheUCxSTE operation. Table23-1.UCxSTE Operation UCMODEx UCxSTE ActiveState UCxSTE Slave Master

0 Inactive Active

01 High

1 Active Inactive

0 Active Inactive

10 Low

1 Inactive Active

23.3.1 USCI Initializationand Reset

The USCI isresetby a PUC orby theUCSWRST bit.Aftera PUC, theUCSWRST bitisautomaticallyset, keepingtheUSCI ina resetcondition.When set,theUCSWRST bitresetstheUCRXIE, UCTXIE, UCRXIFG, UCOE, and UCFE bits,and setstheUCTXIFG flag.ClearingUCSWRST releasestheUSCI for operation. To avoidunpredictablebehavior,configureorreconfiguretheUSCI module onlywhen UCSWRST isset. NOTE: Initializingor reconfiguringtheUSCI module The recommended USCI initialization/reconfigurationprocessis: 1. SetUCSWRST (BIS.B #UCSWRST,&UCxCTL1). 2. InitializeallUSCI registerswithUCSWRST = 1 (includingUCxCTL1). 3. Configureports. 4. ClearUCSWRST viasoftware(BIC.B #UCSWRST,&UCxCTL1). 5. Enableinterrupts(optional)viaUCRXIE and/orUCTXIE.

23.3.2 CharacterFormat

The USCI module inSPI mode supports7-bitand 8-bitcharacterlengthsselectedby theUC7BIT bit.In7- bitdatamode, UCxRXBUF isLSB justifiedand theMSB isalwaysreset.The UCMSB bitcontrolsthe directionofthetransferand selectsLSB orMSB first. 613SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Data Shift Register (DSR) UCx SOMI SOMI UCxSIMO SIMOMASTER SLAVE Px.x STE UCxSTE SS Port.x UCxCLK SCLK MSP430 USCI COMMON SPI ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– SPI Mode www.ti.com NOTE: Defaultcharacterformat The defaultSPI charactertransmissionisLSB first.ForcommunicationwithotherSPI interfaces,MSB-firstmode may be required. NOTE: CharacterformatforFigures Figuresthroughoutthischapteruse MSB-firstformat.

23.3.3 Master Mode

Figure23-2.USCI Master and ExternalSlave Figure23-2shows theUSCI as a masterinboth3-pinand 4-pinconfigurations.The USCI initiatesdata transferwhen dataismoved tothetransmitdatabufferUCxTXBUF. The UCxTXBUF dataismoved tothe transmit(TX)shiftregisterwhen theTX shiftregisterisempty,initiatingdatatransferon UCxSIMO starting witheithertheMSB orLSB, dependingon theUCMSB setting.Data on UCxSOMI isshiftedintothe receiveshiftregisteron theoppositeclockedge.When thecharacterisreceived,thereceivedatais moved fromthereceive(RX)shiftregistertothereceiveddatabufferUCxRXBUF and thereceive interruptflagUCRXIFG isset,indicatingtheRX/TX operationiscomplete. A settransmitinterruptflag,UCTXIFG, indicatesthatdatahas moved fromUCxTXBUF totheTX shift registerand UCxTXBUF isreadyfornew data.Itdoes notindicateRX/TX completion. To receivedataintotheUSCI inmastermode, datamust be writtentoUCxTXBUF, because receiveand transmitoperationsoperateconcurrently. 23.3.3.14-PinSPI Master Mode In4-pinmastermode, UCxSTE isused topreventconflictswithanothermasterand controlsthemaster as describedinTable23-1.When UCxSTE isinthemaster-inactivestate:

UCxSIMO and UCxCLK aresettoinputsand no longerdrivethebus.
The errorbitUCFE isset,indicatinga communicationintegrityviolationtobe handledby theuser.
The internalstatemachinesareresetand theshiftoperationisaborted. IfdataiswrittenintoUCxTXBUF whilethemasterisheldinactiveby UCxSTE, itistransmitas soon as UCxSTE transitionstothemaster-activestate.Ifan activetransferisabortedby UCxSTE transitioningto themaster-inactivestate,thedatamust be rewrittenintoUCxTXBUF tobe transferredwhen UCxSTE transitionsback tothemaster-activestate.The UCxSTE inputsignalisnotused in3-pinmastermode.

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Px.x UCxSTE STE SS Port.x UCxCLKSCLK MSP430 USCICOMMON SPI ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– SPI Mode

23.3.4 SlaveMode

Figure23-3.USCI Slaveand ExternalMaster Figure23-3shows theUSCI as a slaveinboth3-pinand 4-pinconfigurations.UCxCLK isused as the inputfortheSPI clockand must be suppliedby theexternalmaster.The data-transferrateisdetermined by thisclockand notby theinternalbitclockgenerator.Data writtentoUCxTXBUF and moved totheTX shiftregisterbeforethestartofUCxCLK istransmittedon UCxSOMI. Data on UCxSIMO isshiftedintothe receiveshiftregisteron theoppositeedge ofUCxCLK and moved toUCxRXBUF when thesetnumber of bitsarereceived.When dataismoved fromtheRX shiftregistertoUCxRXBUF, theUCRXIFG interrupt flagisset,indicatingthatdatahas been received.The overrunerrorbitUCOE issetwhen thepreviously receiveddataisnotreadfromUCxRXBUF beforenew dataismoved toUCxRXBUF. 23.3.4.14-PinSPI SlaveMode In4-pinslavemode, UCxSTE isused by theslavetoenablethetransmitand receiveoperationsand is providedby theSPI master.When UCxSTE isintheslave-activestate,theslaveoperatesnormally. When UCxSTE isintheslave-inactivestate:

Any receiveoperationinprogresson UCxSIMO ishalted.
UCxSOMI issettotheinputdirection.
The shiftoperationishalteduntiltheUCxSTE linetransitionsintotheslavetransmitactivestate. The UCxSTE inputsignalisnotused in3-pinslavemode.

23.3.5 SPI Enable

When theUSCI module isenabledby clearingtheUCSWRST bit,itisreadytoreceiveand transmit.In mastermode, thebitclockgeneratorisready,butisnotclockednorproducingany clocks.Inslavemode, thebitclockgeneratorisdisabledand theclockisprovidedby themaster. A transmitorreceiveoperationisindicatedby UCBUSY = 1. A PUC orsetUCSWRST bitdisablestheUSCI immediatelyand any activetransferisterminated. 23.3.5.1TransmitEnable Inmastermode, writingtoUCxTXBUF activatesthebitclockgenerator,and thedatabeginstotransmit. Inslavemode, transmissionbeginswhen a masterprovidesa clockand,in4-pinmode, when the UCxSTE isintheslave-activestate. 615SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

CKPH CKPL Cycle# UCxCLK UCxCLK UCxCLK UCxCLK UCxSIMO/ UCxSOMI UCxSIMO UCxSOMI Move to UCxTXBUF RX Sample Points 1 1 0 X 1 X MSB MSB 1 2 3 4 5 6 7 8 LSB LSB TX Data Shifted Out UCxSTE UC UC ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– SPI Mode www.ti.com 23.3.5.2Receive Enable The SPI receivesdatawhen a transmissionisactive.Receiveand transmitoperationsoperate concurrently.

23.3.6 SerialClock Control

UCxCLK isprovidedby themasteron theSPI bus.When UCMST = 1,thebitclockisprovidedby the USCI bitclockgeneratoron theUCxCLK pin.The clockused togeneratethebitclockisselectedwiththe UCSSELx bits.When UCMST = 0,theUSCI clockisprovidedon theUCxCLK pinby themaster,thebit clockgeneratorisnotused,and theUCSSELx bitsaredon'tcare.The SPI receiverand transmitter operateinparalleland use thesame clocksourcefordatatransfer. The 16-bitvalueofUCBRx inthebitratecontrolregisters(UCxxBR1 and UCxxBR0) isthedivisionfactor oftheUSCI clocksource,BRCLK. The maximum bitclockthatcan be generatedinmastermode is BRCLK. Modulationisnotused inSPI mode, and UCAxMCTL shouldbe clearedwhen usingSPI mode forUSCI_A. The UCAxCLK/UCBxCLK frequencyisgivenby: fBitClock= fBRCLK /UCBRx 23.3.6.1SerialClock Polarityand Phase The polarityand phase ofUCxCLK areindependentlyconfiguredviatheUCCKPL and UCCKPH control bitsoftheUSCI. Timingforeach case isshown inFigure23-4. Figure23-4.USCI SPI Timing With UCMSB = 1

23.3.7 Using theSPI Mode With Low-Power Modes

The USCI module providesautomaticclockactivationforuse withlow-powermodes. When theUSCI clocksourceisinactivebecause thedeviceisina low-powermode, theUSCI module automatically activatesitwhen needed,regardlessofthecontrol-bitsettingsfortheclocksource.The clockremains activeuntiltheUSCI module returnstoitsidlecondition.AftertheUSCI module returnstotheidle condition,controloftheclocksourcerevertstothesettingsofitscontrolbits. InSPI slavemode, no internalclocksourceisrequiredbecause theclockisprovidedby theexternal master.ItispossibletooperatetheUSCI inSPI slavemode whilethedeviceisinLPM4 and allclock sourcesaredisabled.The receiveortransmitinterruptcan wake up theCPU fromany low-powermode.

616 UniversalSerialCommunicationInterface– SPI Mode SLAU259E –May 2009–RevisedJanuary2013

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23.3.8 SPI Interrupts

The USCI has onlyone interruptvectorthatissharedfortransmissionand forreception.USCI_Ax and USC_Bx do notsharethesame interruptvector. 23.3.8.1SPI TransmitInterruptOperation The UCTXIFG interruptflagissetby thetransmittertoindicatethatUCxTXBUF isreadytoacceptanother character.An interruptrequestisgeneratedifUCTXIE and GIE arealsoset.UCTXIFG isautomatically resetifa characteriswrittentoUCxTXBUF. UCTXIFG issetaftera PUC orwhen UCSWRST = 1. UCTXIE isresetaftera PUC orwhen UCSWRST = 1. NOTE: WritingtoUCxTXBUF inSPI mode Data writtentoUCxTXBUF when UCTXIFG = 0 may resultinerroneousdatatransmission. 23.3.8.2SPI Receive InterruptOperation The UCRXIFG interruptflagisseteach timea characterisreceivedand loadedintoUCxRXBUF. An interruptrequestisgeneratedifUCRXIE and GIE arealsoset.UCRXIFG and UCRXIE areresetby a systemresetPUC signalorwhen UCSWRST = 1.UCRXIFG isautomaticallyresetwhen UCxRXBUF is read. 23.3.8.3UCxIV, InterruptVectorGenerator The USCI interruptflagsareprioritizedand combined tosourcea singleinterruptvector.The interrupt vectorregisterUCxIV isused todeterminewhichflagrequestedan interrupt.The highest-priorityenabled interruptgeneratesa number intheUCxIV registerthatcan be evaluatedoradded totheprogramcounter (PC)toautomaticallyentertheappropriatesoftwareroutine.Disabledinterruptsdo notaffecttheUCxIV value. Any access,readorwrite,oftheUCxIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. 23.3.8.3.1UCxIV SoftwareExample The followingsoftwareexample shows therecommended use ofUCxIV.The UCxIV valueisadded tothe PC toautomaticallyjump totheappropriateroutine.The followingexample isgivenforUSCI_B0. USCI_SPI_ISR ADD &UCB0IV,PC;Addoffsettojumptable RETI ;Vector0:Nointerrupt JMP RXIFG_ISR;Vector2:RXIFG TXIFG_ISR ;Vector4:TXIFG ... ;Taskstartshere RETI ;Return RXIFG_ISR ;Vector2 ... ;Taskstartshere RETI ;Return 617SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.4 USCI_A SPI Mode Registers

The USCI_A registersthatareapplicableinSPI mode arelistedinTable23-2.The base addressescan be foundinthedevice-specificdatasheet.The addressoffsetsarelistedinTable23-2. Table23-2.USCI_A SPI Mode Registers Offset Acronym RegisterName Type Access Reset Section 00h UCAxCTLW0 USCI_Ax ControlWord 0 Read/write Word 0001h 00h UCAxCTL1 USCI_Ax Control1 Read/write Byte 01h Section23.4.2 01h UCAxCTL0 USCI_Ax Control0 Read/write Byte 00h Section23.4.1 06h UCAxBRW USCI_Ax BitRate ControlWord Read/write Word 0000h 06h UCAxBR0 USCI_Ax BitRate Control0 Read/write Byte 00h Section23.4.3 07h UCAxBR1 USCI_Ax BitRate Control1 Read/write Byte 00h Section23.4.4 08h UCAxMCTL USCI_Ax ModulationControl Read/write Byte 00h Section23.4.5 0Ah UCAxSTAT USCI_Ax Status Read/write Byte 00h Section23.4.6 0Bh Reserved-readszero Read Byte 00h 0Ch UCAxRXBUF USCI_Ax ReceiveBuffer Read/write Byte 00h Section23.4.7 0Dh Reserved-readszero Read Byte 00h 0Eh UCAxTXBUF USCI_Ax TransmitBuffer Read/write Byte 00h Section23.4.8 0Fh Reserved-readszero Read Byte 00h 1Ch UCAxICTL USCI_Ax InterruptControl Read/write Word 0200h 1Ch UCAxIE USCI_Ax InterruptEnable Read/write Byte 00h Section23.4.9 1Dh UCAxIFG USCI_Ax InterruptFlag Read/write Byte 02h Section23.4.10 1Eh UCAxIV USCI_Ax InterruptVector Read Word 0000h Section23.4.11

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23.4.1 UCAxCTL0 Register

USCI_Ax ControlRegister0 Figure23-5.UCAxCTL0 Register 7 6 5 4 3 2 1 0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Modifyonlywhen UCSWRST = 1. Table23-3.UCAxCTL0 RegisterDescription Bit Field Type Reset Description

7 UCCKPH RW 0h Clockphase select

0b = Data ischanged on thefirstUCLK edge and capturedon thefollowing edge. 1b = Data iscapturedon thefirstUCLK edge and changed on thefollowing edge.

6 UCCKPL RW 0h Clockpolarityselect

0b = The inactivestateislow. 1b = The inactivestateishigh. 5 UCMSB RW 0h MSB firstselect.Controlsthedirectionofthereceiveand transmitshiftregister. 0b = LSB first 1b = MSB first 4 UC7BIT RW 0h Characterlength.Selects7-bitor8-bitcharacterlength. 0b = 8-bitdata 1b = 7-bitdata

3 UCMST RW 0h Mastermode select

0b = Slavemode 1b = Mastermode 2-1 UCMODEx RW 0h USCI mode. The UCMODEx bitsselectthesynchronousmode when UCSYNC = 00b = 3-pinSPI 01b = 4-pinSPI withUCxSTE activehigh:Slaveenabledwhen UCxSTE = 1 10b = 4-pinSPI withUCxSTE activelow:Slaveenabledwhen UCxSTE = 0 11b = I2C mode 0b = Asynchronousmode 1b = Synchronousmode 619SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.4.2 UCAxCTL1 Register

USCI_Ax ControlRegister1 Figure23-6.UCAxCTL1 Register 7 6 5 4 3 2 1 0 UCSSELx Reserved UCSWRST rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 Modifyonlywhen UCSWRST = 1. Table23-4.UCAxCTL1 RegisterDescription Bit Field Type Reset Description 7-6 UCSSELx RW 0h USCI clocksourceselect.These bitsselecttheBRCLK sourceclockinmaster mode. UCxCLK isalwaysused inslavemode. 00b = Reserved 01b = ACLK 10b = SMCLK 11b = SMCLK 5-1 Reserved RW 0h Reserved.Alwayswriteas 0. 0b = Disabled.USCI resetreleasedforoperation. 1b = Enabled.USCI logicheldinresetstate.

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23.4.3 UCAxBR0 Register

USCI_Ax BitRate ControlRegister0 Figure23-7.UCAxBR0 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table23-5.UCAxBR0 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefine Bitclockprescalerlowbyte.The 16-bitvalueof(UCAxBR0 + UCAxBR1 × 256) d formstheprescalervalueUCBRx.

23.4.4 UCAxBR1 Register

USCI_Ax BitRate ControlRegister1 Figure23-8.UCAxBR1 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table23-6.UCAxBR1 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefined Bitclockprescalerhighbyte.The 16-bitvalueof(UCAxBR0 + UCAxBR1 × 256) formstheprescalervalueUCBRx.

23.4.5 UCAxMCTL Register

USCI_Ax ModulationControlRegister Figure23-9.UCAxMCTL Register 7 6 5 4 3 2 1 0 Reserved rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table23-7.UCAxMCTL RegisterDescription Bit Field Type Reset Description 7-0 Reserved R 0h Reserved.Alwayswriteas 0. 621SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.4.6 UCAxSTAT Register

USCI_Ax StatusRegister Figure23-10.UCAxSTAT Register 7 6 5 4 3 2 1 0 UCLISTEN UCFE UCOE Reserved UCBUSY rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-0 Modifyonlywhen UCSWRST = 1. Table23-8.UCAxSTAT RegisterDescription Bit Field Type Reset Description 7 UCLISTEN RW 0h Listenenable.The UCLISTEN bitselectsloopbackmode. 0b = Disabled 1b = Enabled.The transmitteroutputisinternallyfedback tothereceiver. 6 UCFE RW 0h Framingerrorflag.Thisbitindicatesa bus conflictin4-wiremastermode. UCFE isnotused in3-wiremasterorany slavemode. 0b = No error 1b = Bus conflictoccurred. 5 UCOE RW 0h Overrunerrorflag.Thisbitissetwhen a characteristransferredintoUCxRXBUF beforethepreviouscharacterwas read.UCOE isclearedautomaticallywhen UCxRXBUF isread,and must notbe clearedby software.Otherwise,itdoes not functioncorrectly. 0b = No error 1b = Overrunerroroccurred 4-1 Reserved R 0h Reserved.Alwaysreadsas 0. 0 UCBUSY R 0h USCI busy.Thisbitindicatesifa transmitorreceiveoperationisinprogress. 0b = USCI inactive 1b = USCI transmittingorreceiving

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23.4.7 UCAxRXBUF Register

USCI_Ax ReceiveBufferRegister Figure23-11.UCAxRXBUF Register 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r Table23-9.UCAxRXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCRXBUFx R undefined The receive-databufferisuseraccessibleand containsthelastreceived characterfromthereceiveshiftregister.ReadingUCRXBUF resetsthereceive- errorbitsand UCRXIFG. In7-bitdatamode, UCRXBUF isLSB justifiedand the MSB isalwaysreset.

23.4.8 UCAxTXBUF Register

USCI_Ax TransmitBufferRegister Figure23-12.UCAxTXBUF Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table23-10.UCAxTXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCTXBUFx RW undefined The transmitdatabufferisuseraccessibleand holdsthedatawaitingtobe moved intothetransmitshiftregisterand transmitted.Writingtothetransmit databufferclearsUCTXIFG. The MSB ofUCAxTXBUF isnotused for7-bitdata and isreset. 623SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.4.9 UCAxIE Register

USCI_Ax InterruptEnableRegister Figure23-13.UCAxIE Register 7 6 5 4 3 2 1 0 Reserved UCTXIE UCRXIE r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 Table23-11.UCAxIE RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 0b = Interruptdisabled 1b = Interruptenabled 0b = Interruptdisabled 1b = Interruptenabled

23.4.10 UCAxIFG Register

USCI_Ax InterruptFlagRegister Figure23-14.UCAxIFG Register 7 6 5 4 3 2 1 0 Reserved UCTXIFG UCRXIFG r-0 r-0 r-0 r-0 r-0 r-0 rw-1 rw-0 Table23-12.UCAxIFG RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 UCTXIFG RW 1h Transmitinterruptflag.UCTXIFG issetwhen UCAxTXBUF empty. 0b = No interruptpending 1b = Interruptpending 0 UCRXIFG RW 0h Receiveinterruptflag.UCRXIFG issetwhen UCAxRXBUF has receiveda completecharacter. 0b = No interruptpending 1b = Interruptpending

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23.4.11 UCAxIV Register

USCI_Ax InterruptVectorRegister Figure23-15.UCAxIV Register 15 14 13 12 11 10 9 8 UCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table23-13.UCAxIV RegisterDescription Bit Field Type Reset Description 15-0 UCIVx R 0h USCI interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Data received;InterruptFlag:UCRXIFG; Interrupt Priority:Highest 04h = InterruptSource:Transmitbufferempty;InterruptFlag:UCTXIFG; InterruptPriority:Lowest 625SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.5 USCI_B SPI Mode Registers

The USCI_B registersapplicableinSPI mode arelistedinTable23-14.The base addressescan be found inthedevice-specificdatasheet.The addressoffsetsarelistedinTable23-14. Table23-14.USCI_B SPI Mode Registers Offset Acronym RegisterName Type Access Reset Section 00h UCBxCTLW0 USCI_Bx ControlWord 0 Read/write Word 0101h 00h UCBxCTL1 USCI_Bx Control1 Read/write Byte 01h Section23.5.2 01h UCBxCTL0 USCI_Bx Control0 Read/write Byte 01h Section23.5.1 06h UCBxBRW USCI_Bx BitRate ControlWord Read/write Word 0000h 06h UCBxBR0 USCI_Bx BitRate Control0 Read/write Byte 00h Section23.5.3 07h UCBxBR1 USCI_Bx BitRate Control1 Read/write Byte 00h Section23.5.4 08h UCBxMCTL USCI_Bx ModulationControl Read/write Byte 00h Section23.5.5 0Ah UCBxSTAT USCI_Bx Status Read/write Byte 00h Section23.5.6 0Bh Reserved-readszero Read Byte 00h 0Ch UCBxRXBUF USCI_Bx ReceiveBuffer Read/write Byte 00h Section23.5.7 0Dh Reserved-readszero Read Byte 00h 0Eh UCBxTXBUF USCI_Bx TransmitBuffer Read/write Byte 00h Section23.5.8 0Fh Reserved-readszero Read Byte 00h 1Ch UCBxICTL USCI_Bx InterruptControl Read/write Word 0200h 1Ch UCBxIE USCI_Bx InterruptEnable Read/write Byte 00h Section23.5.9 1Dh UCBxIFG USCI_Bx InterruptFlag Read/write Byte 02h Section23.5.10 1Eh UCBxIV USCI_Bx InterruptVector Read Word 0000h Section23.5.11

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23.5.1 UCBxCTL0 Register

USCI_Bx ControlRegister0 Figure23-16.UCBxCTL0 Register 7 6 5 4 3 2 1 0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-1 Modifyonlywhen UCSWRST = 1. Table23-15.UCBxCTL0 RegisterDescription Bit Field Type Reset Description 0b = Data ischanged on thefirstUCLK edge and capturedon thefollowing edge. 1b = Data iscapturedon thefirstUCLK edge and changed on thefollowing edge. 0b = The inactivestateislow. 1b = The inactivestateishigh. 5 UCMSB RW 0h MSB firstselect.Controlsthedirectionofthereceiveand transmitshiftregister. 0b = LSB first 1b = MSB first 4 UC7BIT RW 0h Characterlength.Selects7-bitor8-bitcharacterlength. 0b = 8-bitdata 1b = 7-bitdata 0b = Slavemode 1b = Mastermode 2-1 UCMODEx RW 0h USCI mode. The UCMODEx bitsselectthesynchronousmode when UCSYNC = 00b = 3-pinSPI 01b = 4-pinSPI withUCxSTE activehigh:Slaveenabledwhen UCxSTE = 1 10b = 4-pinSPI withUCxSTE activelow:Slaveenabledwhen UCxSTE = 0 11b = I2C mode

0 UCSYNC RW 1h Synchronousmode enable

0b = Asynchronousmode 1b = Synchronousmode 627SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.5.2 UCBxCTL1 Register

USCI_Bx ControlRegister1 Figure23-17.UCBxCTL1 Register 7 6 5 4 3 2 1 0 UCSSELx Reserved UCSWRST rw-0 rw-0 r0 rw-0 rw-0 rw-0 rw-0 rw-1 Modifyonlywhen UCSWRST = 1. Table23-16.UCBxCTL1 RegisterDescription Bit Field Type Reset Description 7-6 UCSSELx RW 0h USCI clocksourceselect.These bitsselecttheBRCLK sourceclockinmaster mode. UCxCLK isalwaysused inslavemode. 00b = Reserved 01b = ACLK 10b = SMCLK 11b = SMCLK 5-1 Reserved RW 0h Reserved.Alwayswriteas 0. 0b = Disabled.USCI resetreleasedforoperation. 1b = Enabled.USCI logicheldinresetstate.

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23.5.3 UCBxBR0 Register

USCI_Bx BitRate ControlRegister0 Figure23-18.UCBxBR0 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table23-17.UCBxBR0 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefine Bitclockprescalerlowbyte.The 16-bitvalueof(UCBxBR0 + UCBxBR1 × 256) d formstheprescalervalueUCBRx.

23.5.4 UCBxBR1 Register

USCI_Bx BitRate ControlRegister1 Figure23-19.UCBxBR1 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table23-18.UCBxBR1 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefined Bitclockprescalerhighbyte.The 16-bitvalueof(UCBxBR0 + UCBxBR1 × 256) formstheprescalervalueUCBRx.

23.5.5 UCBxMCTL Register

USCI_Bx ModulationControlRegister Figure23-20.UCBxMCTL Register 7 6 5 4 3 2 1 0 Reserved rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 Table23-19.UCBxMCTL RegisterDescription Bit Field Type Reset Description 7-0 Reserved R 0h Reserved.Alwayswriteas 0. 629SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.5.6 UCBxSTAT Register

USCI_Bx StatusRegister Figure23-21.UCBxSTAT Register 7 6 5 4 3 2 1 0 UCLISTEN UCFE UCOE Reserved UCBUSY rw-0 rw-0 rw-0 r0 r0 r0 r0 r-0 Modifyonlywhen UCSWRST = 1. Table23-20.UCBxSTAT RegisterDescription Bit Field Type Reset Description 7 UCLISTEN RW 0h Listenenable.The UCLISTEN bitselectsloopbackmode. 0b = Disabled 1b = Enabled.The transmitteroutputisinternallyfedback tothereceiver. 6 UCFE RW 0h Framingerrorflag.Thisbitindicatesa bus conflictin4-wiremastermode. UCFE isnotused in3-wiremasterorany slavemode. 0b = No error 1b = Bus conflictoccurred. 5 UCOE RW 0h Overrunerrorflag.Thisbitissetwhen a characteristransferredintoUCxRXBUF beforethepreviouscharacterwas read.UCOE isclearedautomaticallywhen UCxRXBUF isread,and must notbe clearedby software.Otherwise,itdoes not functioncorrectly. 0b = No error 1b = Overrunerroroccurred 4-1 Reserved R 0h Reserved.Alwaysreadsas 0. 0 UCBUSY R 0h USCI busy.Thisbitindicatesifa transmitorreceiveoperationisinprogress. 0b = USCI inactive 1b = USCI transmittingorreceiving

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23.5.7 UCBxRXBUF Register

USCI_Bx ReceiveBufferRegister Figure23-22.UCBxRXBUF Register 7 6 5 4 3 2 1 0 UCRXBUFx r r r r r r r r Table23-21.UCBxRXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCRXBUFx R undefined The receive-databufferisuseraccessibleand containsthelastreceived characterfromthereceiveshiftregister.ReadingUCRXBUF resetsthereceive- errorbitsand UCRXIFG. In7-bitdatamode, UCRXBUF isLSB justifiedand the MSB isalwaysreset.

23.5.8 UCBxTXBUF Register

USCI_Bx TransmitBufferRegister Figure23-23.UCBxTXBUF Register 7 6 5 4 3 2 1 0 UCTXBUFx rw rw rw rw rw rw rw rw Table23-22.UCBxTXBUF RegisterDescription Bit Field Type Reset Description 7-0 UCTXBUFx RW undefined The transmitdatabufferisuseraccessibleand holdsthedatawaitingtobe moved intothetransmitshiftregisterand transmitted.Writingtothetransmit databufferclearsUCTXIFG. The MSB ofUCBxTXBUF isnotused for7-bitdata and isreset. 631SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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23.5.9 UCBxIE Register

USCI_Bx InterruptEnableRegister Figure23-24.UCBxIE Register 7 6 5 4 3 2 1 0 Reserved UCTXIE UCRXIE r-0 r-0 r-0 r-0 r-0 r-0 rw-0 rw-0 Table23-23.UCBxIE RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 0b = Interruptdisabled 1b = Interruptenabled 0b = Interruptdisabled 1b = Interruptenabled

23.5.10 UCBxIFG Register

USCI_Bx InterruptFlagRegister Figure23-25.UCBxIFG Register 7 6 5 4 3 2 1 0 Reserved UCTXIFG UCRXIFG r-0 r-0 r-0 r-0 r-0 r-0 rw-1 rw-0 Table23-24.UCBxIFG RegisterDescription Bit Field Type Reset Description 7-2 Reserved R 0h Reserved.Alwaysreadsas 0. 1 UCTXIFG RW 1h Transmitinterruptflag.UCTXIFG issetwhen UCBxTXBUF empty. 0b = No interruptpending 1b = Interruptpending 0 UCRXIFG RW 0h Receiveinterruptflag.UCRXIFG issetwhen UCBxRXBUF has receiveda completecharacter. 0b = No interruptpending 1b = Interruptpending

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23.5.11 UCBxIV Register

USCI_Bx InterruptVectorRegister Figure23-26.UCBxIV Register 15 14 13 12 11 10 9 8 UCIVx r0 r0 r0 r0 r0 r0 r0 r0 7 6 5 4 3 2 1 0 UCIVx r0 r0 r0 r-0 r-0 r-0 r-0 r0 Table23-25.UCBxIV RegisterDescription Bit Field Type Reset Description 15-0 UCIVx R 0h USCI interruptvectorvalue 00h = No interruptpending 02h = InterruptSource:Data received;InterruptFlag:UCRXIFG; Interrupt Priority:Highest 04h = InterruptSource:Transmitbufferempty;InterruptFlag:UCTXIFG; InterruptPriority:Lowest 633SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– SPI Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. Chapter24 SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunication Interface– I2C Mode The universalserialcommunicationinterface(USCI)supportsmultipleserialcommunicationmodes with one hardwaremodule.ThischapterdiscussestheoperationoftheI2C mode.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com UniversalSerialCommunicationInterface(USCI)Overview

24.1 UniversalSerialCommunication Interface(USCI)Overview

UART mode
PulseshapingforIrDAcommunications
Automaticbaud-ratedetectionforLIN communications
SPI mode USCI_Bx modules support:
I2C mode

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24.2 USCI Introduction– I2C Mode

InI2C mode, theUSCI module providesan interfacebetween thedeviceand I2C-compatibledevices connectedby thetwo-wireI2C serialbus.Externalcomponents attachedtotheI2C bus seriallytransmit and/orreceiveserialdatato/fromtheUSCI module throughthe2-wireI2C interface. The I2C mode featuresinclude:

CompliancetothePhilipsSemiconductorI2C specificationv2.1
7-bitand 10-bitdeviceaddressingmodes
Generalcall
START/RESTART/STOP
Multi-mastertransmitter/receivermode
Slavereceiver/transmittermode
Standardmode up to100 kbps and fastmode up to400 kbps support
Programmable UCxCLK frequencyinmastermode
Designedforlowpower
SlavereceiverSTART detectionforautowake up fromLPMx modes (wake up fromLPMx.5 isnot supported)
SlaveoperationinLPM4 Figure24-1shows theUSCI when configuredinI2C mode.

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ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode Figure24-1.USCI Block Diagram – I2C Mode

24.3 USCI Operation– I2C Mode

The I2C mode supportsany slaveormasterI2C-compatibledevice.Figure24-2shows an example ofan I2C bus.Each I2C deviceisrecognizedby a uniqueaddressand can operateas eithera transmitterora receiver.A deviceconnectedtotheI2C bus can be consideredas themasterortheslavewhen performingdatatransfers.A masterinitiatesa datatransferand generatestheclocksignalSCL. Any deviceaddressedby a masterisconsidereda slave. I2C dataiscommunicatedusingtheserialdata(SDA) pinand theserialclock(SCL)pin.BothSDA and SCL arebidirectionaland must be connectedtoa positivesupplyvoltageusinga pullupresistor. 637SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Serial Data (SDA) Serial Clock (SCL) Device A Device B Device C ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com Figure24-2.I2C Bus Connection Diagram NOTE: SDA and SCL levels The SDA and SCL pinsmust notbe pulledup above thedeviceVCC level.

24.3.1 USCI Initializationand Reset

The USCI isresetby a PUC orby settingtheUCSWRST bit.Aftera PUC, theUCSWRST bitis automaticallyset,keepingtheUSCI ina resetcondition.To selectI2C operation,theUCMODEx bitsmust be setto11.Aftermodule initialization,itisreadyfortransmitorreceiveoperation.ClearingUCSWRST releasestheUSCI foroperation. To avoidunpredictablebehavior,configureorreconfiguretheUSCI module onlywhen UCSWRST isset. SettingUCSWRST inI2C mode has thefollowingeffects:

I2C communicationstops.
SDA and SCL arehighimpedance.
UCBxI2CSTAT, bits6–0 arecleared.
RegistersUCBxIE and UCBxIFG arecleared.
Allotherbitsand registerremainunchanged. NOTE: Initializingor re-configuringtheUSCI module The recommended USCI initialization/reconfigurationprocessis: 1. SetUCSWRST (BIS.B #UCSWRST,&UCxCTL1). 2. InitializeallUSCI registerswithUCSWRST = 1. 3. Configureports. 4. ClearUCSWRST viasoftware(BIC.B #UCSWRST,&UCxCTL1). 5. Enableinterrupts(optional).

24.3.2 I2C SerialData

One clockpulseisgeneratedby themasterdeviceforeach databittransferred.The I2C mode operates withbytedata.Data istransferredMSB firstas shown inFigure24-3. The firstbyteaftera START conditionconsistsofa 7-bitslaveaddressand theR/W bit.When R/W = 0, themastertransmitsdatatoa slave.When R/W = 1,themasterreceivesdatafroma slave.The ACK bit issentfromthereceiveraftereach byteon theninthSCL clock.

638 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

Condition (S) STOP Condition (P)R/W ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode Figure24-3.I2C Module Data Transfer START and STOP conditionsaregeneratedby themasterand areshown inFigure24-3.A START conditionisa high-to-lowtransitionon theSDA linewhileSCL ishigh.A STOP conditionisa low-to-high transitionon theSDA linewhileSCL ishigh.The bus busy bit,UCBBUSY, issetaftera START and clearedaftera STOP. Data on SDA must be stableduringthehighperiodofSCL (seeFigure24-4).The highand lowstateof SDA can onlychange when SCL islow,otherwiseSTART orSTOP conditionsaregenerated. Figure24-4.BitTransferon I2C Bus 639SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

S Slave Address R/W ACK Data ACK S Slave Address ACK Data ACK P

1 Any

1 Any Number

S Slave Address 1st byte Slave Address 2nd byteACKR/W 11 8 ACK Data ACK P 1 1 1 1 0 X X S Slave Address R/W ACK Data ACK Data ACK P 7 8 81 1 1 1 1 1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com

24.3.3 I2C Addressing Modes

The I2C mode supports7-bitand 10-bitaddressingmodes. 24.3.3.17-BitAddressing Inthe7-bitaddressingformat(seeFigure24-5),thefirstbyteisthe7-bitslaveaddressand theR/W bit. The ACK bitissentfromthereceiveraftereach byte. Figure24-5.I2C Module 7-BitAddressing Format 24.3.3.210-BitAddressing Inthe10-bitaddressingformat(seeFigure24-6),thefirstbyteismade up of11110b plusthetwo MSBs ofthe10-bitslaveaddressand theR/W bit.The ACK bitissentfromthereceiveraftereach byte.The nextbyteistheremainingeightbitsofthe10-bitslaveaddress,followedby theACK bitand the8-bitdata. See I2C Slave10-bitAddressingMode and I2C Master10-bitAddressingMode fordetailshow touse the 10-bitaddressingmode withtheUSCI module. Figure24-6.I2C Module 10-BitAddressing Format 24.3.3.3Repeated StartConditions The directionofdataflowon SDA can be changed by themaster,withoutfirststoppinga transfer,by issuinga repeatedSTART condition.Thisiscalleda RESTART. Aftera RESTART isissued,theslave addressisagainsentoutwiththenew datadirectionspecifiedby theR/W bit.The RESTART conditionis shown inFigure24-7. Figure24-7.I2C Module Addressing Format With Repeated START Condition

640 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

... USCI Master USCI Slave Other Master Other Slave ... Bits set or reset by software Bits set or reset by hardware ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode

24.3.4 I2C Module OperatingModes

InI2C mode, theUSCI module can operateinmastertransmitter,masterreceiver,slavetransmitter,or slavereceivermode. The modes arediscussedinthefollowingsections.Time linesareused toillustrate themodes. Figure24-8shows how tointerpretthetime-linefigures.Data transmittedby themasterisrepresentedby greyrectangles;datatransmittedby theslaveisrepresentedby whiterectangles.Data transmittedby the USCI module,eitheras masterorslave,isshown by rectanglesthataretallerthantheothers. Actionstakenby theUSCI module areshown ingreyrectangleswithan arrowindicatingwhere inthedata streamtheactionoccurs.Actionsthatmust be handledwithsoftwareareindicatedwithwhiterectangles withan arrowpointingtowhere inthedatastreamtheactionmust takeplace. Figure24-8.I2C Time-LineLegend 24.3.4.1SlaveMode The USCI module isconfiguredas an I2C slaveby selectingtheI2C mode withUCMODEx = 11 and UCSYNC = 1 and clearingtheUCMST bit. Initially,theUSCI module must tobe configuredinreceivermode by clearingtheUCTR bittoreceivethe I2C address.Afterwards,transmitand receiveoperationsarecontrolledautomatically,dependingon the R/W bitreceivedtogetherwiththeslaveaddress. The USCI slaveaddressisprogrammed withtheUCBxI2COA register.When UCA10 = 0,7-bitaddressing isselected.When UCA10 = 1,10-bitaddressingisselected.The UCGCEN bitselectsiftheslave respondstoa generalcall. When a START conditionisdetectedon thebus,theUSCI module receivesthetransmittedaddressand compare itagainstitsown addressstoredinUCBxI2COA. The UCSTTIFG flagissetwhen address receivedmatches theUSCI slaveaddress. 641SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

UCTR=1□(Transmitter) UCSTTIFG=1 UCTXIFG=1 UCSTPIFG=0 UCBxTXBUF□discarded Reception□of□own address□and transmission□of□data bytes Bus□stalled (SCL held□low) until□data□available DATADATA A UCSTPIFG=1 UCSTTIFG=0 A A DATA A S SLA/R UCTR=1□(Transmitter) UCSTTIFG=1 UCTXIFG=1 UCBxTXBUF□discarded DATA A S SLA/W UCTR=0□(Receiver) UCSTTIFG=1 Arbitration□lost□as master□and addressed□as□slave UCALIFG=1 UCMST=0 UCTR=1□(Transmitter) UCSTTIFG=1 UCTXIFG=1 UCSTPIFG=0 UCTXIFG=0 Repeated□start - continue□as slave□transmitter Repeated□start - continue□as slave□receiver Write□data□to□UCBxTXBUF UCTXIFG=1 UCTXIFG=0 UCTXIFG=0 Write□data□to□UCBxTXBUF ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com 24.3.4.1.1I2C SlaveTransmitterMode Slavetransmittermode isenteredwhen theslaveaddresstransmittedby themasterisidenticaltoitsown addresswitha setR/W bit.The slavetransmittershiftstheserialdataouton SDA withtheclockpulses thataregeneratedby themasterdevice.The slavedevicedoes notgeneratetheclock,butitdoes hold SCL lowwhileinterventionoftheCPU isrequiredaftera bytehas been transmitted. Ifthemasterrequestsdatafromtheslave,theUSCI module isautomaticallyconfiguredas a transmitter and UCTR and UCTXIFG become set.The SCL lineisheldlowuntilthefirstdatatobe sentiswritteninto thetransmitbufferUCBxTXBUF. Then theaddressisacknowledged,theUCSTTIFG flagiscleared,and thedataistransmitted.As soon as thedataistransferredintotheshiftregister,theUCTXIFG issetagain. Afterthedataisacknowledgedby themaster,thenextdatabytewrittenintoUCBxTXBUF istransmitted or,ifthebufferisempty,thebus isstalledduringtheacknowledgecycleby holdingSCL lowuntilnew dataiswrittenintoUCBxTXBUF. Ifthemastersends a NACK succeededby a STOP condition,the UCSTPIFG flagisset.IftheNACK issucceededby a repeatedSTART condition,theUSCI I2C state machine returnstoitsaddress-receptionstate. Figure24-9shows theslavetransmitteroperation. Figure24-9.I2C SlaveTransmitterMode

642 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode 24.3.4.1.2I2C SlaveReceiverMode Slavereceivermode isenteredwhen theslaveaddresstransmittedby themasterisidenticaltoitsown addressand a clearedR/W bitisreceived.Inslavereceivermode, serialdatabitsreceivedon SDA are shiftedinwiththeclockpulsesthataregeneratedby themasterdevice.The slavedevicedoes not generatetheclock,butitcan holdSCL lowifinterventionoftheCPU isrequiredaftera bytehas been received. Iftheslaveshouldreceivedatafromthemaster,theUSCI module isautomaticallyconfiguredas a receiverand UCTR iscleared.Afterthefirstdatabyteisreceived,thereceiveinterruptflagUCRXIFG is set.The USCI module automaticallyacknowledgesthereceiveddataand can receivethenextdatabyte. Ifthepreviousdatawas notreadfromthereceivebufferUCBxRXBUF attheend ofa reception,thebus isstalledby holdingSCL low.As soon as UCBxRXBUF isread,thenew dataistransferredinto UCBxRXBUF, an acknowledgeissenttothemaster,and thenextdatacan be received. SettingtheUCTXNACK bitcausesa NACK tobe transmittedtothemasterduringthenext acknowledgmentcycle.A NACK issenteven ifUCBxRXBUF isnotreadytoreceivethelatestdata.Ifthe UCTXNACK bitissetwhileSCL isheldlow,thebus isreleased,a NACK istransmittedimmediately,and UCBxRXBUF isloadedwiththelastreceiveddata.Because thepreviousdatawas notread,thatdatais lost.To avoidlossofdata,theUCBxRXBUF must be readbeforeUCTXNACK isset. When themastergeneratesa STOP condition,theUCSTPIFG flagisset. Ifthemastergeneratesa repeatedSTART condition,theUSCI I2C statemachine returnstoitsaddress receptionstate. Figure24-10shows theI2C slavereceiveroperation. 643SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

S SLA/W A DATA A P or□SReception□of□own address□and□data bytes. All□are acknowledged . UCRXIFG=1 DATADATA A A UCTXNACK=1 Refer□to: ”Slave Transmitter” Timing□Diagram Bus not stalled□even□if UCBxRXBUF□not□read P or□SDATA A AArbitration□lost□as master□and addressed□as□slave UCALIFG=1 UCMST=0 UCTR=0□(Receiver) UCSTTIFG=1 (UCGC=1□if□general□call) UCTXIFG=0 UCSTPIFG=0 Last□byte□is□not acknowledged . UCTR=0□(Receiver) UCSTTIFG=1 UCSTPIFG=0 Gen□Call A UCTR=0□(Receiver) UCSTTIFG=1 UCGC=1 Reception□of□the general□call address . UCTXNACK=0 Bus□stalled (SCL held□low ) if□UCBxRXBUF□not□read Read□data□from□UCBxRXBUF UCSTPIFG=0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com Figure24-10.I2C SlaveReceiverMode

644 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

S S 11110 xx/W A SLA (2.) A P or□SReception□of□own address□and□data bytes. All□are acknowledged . UCRXIFG=1 DATA DATAA A UCTR=0□(Receiver) UCSTTIFG=1 UCSTPIFG=0 Gen□Call A UCTR=0□(Receiver) UCSTTIFG=1 UCGC=1 Reception□of□the general□call address. P or□S UCRXIFG=1 DATA DATAA A S 11110 xx/W A SLA (2.) A UCTR=0□(Receiver) UCSTTIFG=1 UCSTPIFG=0 11110 xx/R A UCTR=1□(Transmitter) UCSTTIFG=1 UCTXIFG=1 UCSTPIFG=0 UCSTTIFG=0 DATA A P or□SReception□of□own address□and transmission□of□data bytes Slave□Transmitter Slave□Receiver UCSTPIFG=0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode 24.3.4.1.3I2C Slave10-BitAddressing Mode The 10-bitaddressingmode isselectedwhen UCA10 = 1 and isas shown inFigure24-11.In10-bit addressingmode, theslaveisinreceivemode afterthefulladdressisreceived.The USCI module indicatesthisby settingtheUCSTTIFG flagwhiletheUCTR bitiscleared.To switchtheslaveinto transmittermode, themastersends a repeatedSTART conditiontogetherwiththefirstbyteoftheaddress butwiththeR/W bitset.ThissetstheUCSTTIFG flagifitwas previouslyclearedby software,and the USCI modules switchestotransmittermode withUCTR = 1. Figure24-11.I2C Slave10-BitAddressing Mode 24.3.4.2Master Mode The USCI module isconfiguredas an I2C masterby selectingtheI2C mode withUCMODEx = 11 and UCSYNC = 1 and settingtheUCMST bit.When themasterispartofa multi-mastersystem,UCMM must be setand itsown addressmust be programmed intotheUCBxI2COA register.When UCA10 = 0,7-bit addressingisselected.When UCA10 = 1,10-bitaddressingisselected.The UCGCEN bitselectsifthe USCI module respondstoa generalcall. 645SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com 24.3.4.2.1I2C Master TransmitterMode Afterinitialization,mastertransmittermode isinitiatedby writingthedesiredslaveaddresstothe UCBxI2CSA register,selectingthesizeoftheslaveaddresswiththeUCSLA10 bit,settingUCTR for transmittermode, and settingUCTXSTT togeneratea START condition. The USCI module checksifthebus isavailable,generatestheSTART condition,and transmitstheslave address.The UCTXIFG bitissetwhen theSTART conditionisgeneratedand thefirstdatatobe transmittedcan be writtenintoUCBxTXBUF. As soon as theslaveacknowledgestheaddress,the UCTXSTT bitiscleared. NOTE: HandlingofTXIFG ina multi-mastersystem Ina multi-mastersystem(UCMM =1),ifthebus isunavailable,theUSCI module waitsand checksforbus release.Bus unavailabilitycan occureven aftertheUCTXSTT bithas been set.Whilewaitingforthebus tobecome available,theUSCI may updatetheTXIFG based on SCL clocklineactivity.CheckingtheUCTXSTT bittoverifyiftheSTART conditionhas been sentensuresthattheTXIFG isbeingservicedcorrectly. The datawrittenintoUCBxTXBUF istransmittedifarbitrationisnotlostduringtransmissionoftheslave address.UCTXIFG issetagainas soon as thedataistransferredfromthebufferintotheshiftregister.If thereisno dataloadedtoUCBxTXBUF beforetheacknowledgecycle,thebus isheldduringthe acknowledgecyclewithSCL lowuntildataiswrittenintoUCBxTXBUF. Data istransmittedorthebus is held,as longas theUCTXSTP bitorUCTXSTT bitisnotset. SettingUCTXSTP generatesa STOP conditionafterthenextacknowledgefromtheslave.IfUCTXSTP is setduringthetransmissionoftheslave'saddressorwhiletheUSCI module waitsfordatatobe written intoUCBxTXBUF, a STOP conditionisgenerated,even ifno datawas transmittedtotheslave.When transmittinga singlebyteofdata,theUCTXSTP bitmust be setwhilethebyteisbeingtransmittedor anytimeaftertransmissionbegins,withoutwritingnew dataintoUCBxTXBUF. Otherwise,onlythe addressistransmitted.When thedataistransferredfromthebuffertotheshiftregister,UCTXIFG isset, indicatingdatatransmissionhas begun,and theUCTXSTP bitmay be set. SettingUCTXSTT generatesa repeatedSTART condition.Inthiscase,UCTR may be setorclearedto configuretransmitterorreceiver,and a differentslaveaddressmay be writtenintoUCBxI2CSA ifdesired. Iftheslavedoes notacknowledgethetransmitteddata,thenot-acknowledgeinterruptflagUCNACKIFG is set.The mastermust reactwitheithera STOP conditionora repeatedSTART condition.Ifdatawas alreadywrittenintoUCBxTXBUF, itisdiscarded.Ifthisdatashouldbe transmittedaftera repeated START, itmust be writtenintoUCBxTXBUF again.Any setUCTXSTT isalsodiscarded.To triggera repeatedSTART, UCTXSTT must be setagain. Figure24-12shows theI2C mastertransmitteroperation.

646 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

Other□master□continues S SLA/W A DATA A PSuccessful transmission□to□a slave□receiver UCTXIFG=1 DATADATA A A UCTXSTP=1 UCTXIFG=0 Next□transfer□started with□a□repeated□start condition DATA A S SLA/W 1) UCTR=1□(Transmitter) 2) UCTXSTT=1DATA A S SLA/R 1) UCTR=0□(Receiver) 2) UCTXSTT=1 3) UCTXIFG=0 Not□acknowledge received□after□slave address P S SLA/W S SLA/R UCTXSTP=1 1) UCTR=1□(Transmitter) 2) UCTXSTT=1 1) UCTR=0□(Receiver) 2) UCTXSTT=1 Arbitration□lost□in slave□address□or data□byte A A Other□master□continues Arbitration□lost□and addressed□as□slave Other□master□continuesA UCALIFG=1 UCMST=0 UCTR=0□(Receiver) UCSTTIFG=1 (UCGC=1□if□general□call) UCTXIFG=0 UCSTPIFG=0 USCI□continues□as□Slave□Receiver Not□acknowledge received□after□a□data byte UCTXSTT=0 UCTXSTP=0 UCTXSTP=0 UCALIFG=1 UCMST=0 (UCSTTIFG=0) Bus□stalled (SCL held□low ) until□data□available Write□data□to□UCBxTXBUF 1) UCTR=1□(Transmitter) 2) UCTXSTT=1 UCTXIFG=1 UCBxTXBUF□discarded UCTXSTT=0 UCNACKIFG=1 UCTXIFG=0 UCBxTXBUF□discarded UCTXIFG=1 UCBxTXBUF□discarded UCNACKIFG=1 UCTXIFG=0 UCBxTXBUF□discarded UCALIFG=1 UCMST=0 (UCSTTIFG=0) ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode Figure24-12.I2C Master TransmitterMode 647SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com 24.3.4.2.2I2C Master ReceiverMode Afterinitialization,masterreceivermode isinitiatedby writingthedesiredslaveaddresstothe UCBxI2CSA register,selectingthesizeoftheslaveaddresswiththeUCSLA10 bit,clearingUCTR for receivermode, and settingUCTXSTT togeneratea START condition. The USCI module checksifthebus isavailable,generatestheSTART condition,and transmitstheslave address.As soon as theslaveacknowledgestheaddress,theUCTXSTT bitiscleared. Aftertheacknowledgeoftheaddressfromtheslave,thefirstdatabytefromtheslaveisreceivedand acknowledgedand theUCRXIFG flagisset.Data isreceivedfromtheslave,as longas UCTXSTP or UCTXSTT isnotset.IfUCBxRXBUF isnotread,themasterholdsthebus duringreceptionofthelast databitand untiltheUCBxRXBUF isread. Iftheslavedoes notacknowledgethetransmittedaddress,thenot-acknowledgeinterruptflag UCNACKIFG isset.The mastermust reactwitheithera STOP conditionora repeatedSTART condition. SettingtheUCTXSTP bitgeneratesa STOP condition.AftersettingUCTXSTP, a NACK followedby a STOP conditionisgeneratedafterreceptionofthedatafromtheslave,orimmediatelyiftheUSCI module iscurrentlywaitingforUCBxRXBUF tobe read. Ifa masterwantstoreceivea singlebyteonly,theUCTXSTP bitmust be setwhilethebyteisbeing received.Forthiscase,theUCTXSTT may be polledtodeterminewhen itiscleared: BIS.B#UCTXSTT,&UCB0CTL1;TransmitSTARTcond. POLL_STTBIT.B#UCTXSTT,&UCB0CTL1;PollUCTXSTTbit JC POLL_STT ;Whencleared, BIS.B#UCTXSTP,&UCB0CTL1;transmitSTOPcond. SettingUCTXSTT generatesa repeatedSTART condition.Inthiscase,UCTR may be setorclearedto configuretransmitterorreceiver,and a differentslaveaddressmay be writtenintoUCBxI2CSA ifdesired. NOTE: Repeated START The UCTXSTT bitmust be setbeforethelastdatabyteisreceived;thatis,immediatelyafter theUCRXIFG issetand theUCRXBUF withthesecond tolastbyteisread,theUCTXSTT bitshouldbe set. NOTE: Consecutivemaster transactionswithoutrepeatedSTART When performingmultipleconsecutiveI2C mastertransactionswithouttherepeatedSTART feature,thecurrenttransactionmust be completedbeforethenextone isinitiated.Thiscan be done by ensuringthatthetransmitSTOP conditionflagUCTXSTP isclearedbeforethe nextI2C transactionisinitiatedwithsettingUCTXSTT = 1.Otherwise,thecurrenttransaction mightbe affected. Figure24-13shows theI2C masterreceiveroperation.

648 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

Other□master□continues S SLA/R A DATA A P 1)□UCTR=0□(Receiver) 2)□UCTXSTT=1 Successful reception□from□a slave□transmitter UCRXIFG=1 DATADATA A UCTXSTP=1 Next□transfer□started with□a□repeated□start condition DATA S SLA/W 1) UCTR=1□(Transmitter) 2) UCTXSTT=1DATA S SLA/R 1) UCTR=0□(Receiver) 2) UCTXSTT=1 Not□acknowledge received□after□slave address UCTXSTT=0 UCNACKIFG=1 P S SLA/W S SLA/R 1) UCTR=1□(Transmitter) 2) UCTXSTT=11) UCTR=0□(Receiver) 2) UCTXSTT=1Arbitration□lost□in slave□address□or data□byte A Other□master□continues UCALIFG=1 UCMST=0 (UCSTTIFG=0) Arbitration□lost□and addressed□as□slave Other□master□continuesA UCALIFG=1 UCMST=0 UCTR=1□(Transmitter) UCSTTIFG=1 UCTXIFG=1 UCSTPIFG=0 USCI□continues□as□Slave Transmitter A A A UCTXSTT=0 UCTXSTP=0 UCTXIFG=1 UCALIFG=1 UCMST=0 (UCSTTIFG=0) UCTXSTP=1 UCTXSTP=0 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode Figure24-13.I2C Master ReceiverMode 24.3.4.2.3I2C Master 10-BitAddressing Mode The 10-bitaddressingmode isselectedwhen UCSLA10 = 1 and isshown inFigure24-14. 649SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Master□Transmitter S A A P 1)□UCTR=1(Transmitter) 2)□UCTXSTT=1 Successful transmission□to□a slave□receiver UCTXIFG=1 UCTXIFG=1 DATADATA A A UCTXSTP=1 UCTXSTT=0 UCTXSTP=0 11110xx/W SLA(2.) S A P 1)□UCTR=0(Receiver) 2)□UCTXSTT=1 Successful reception□from□a slave□transmitter DA A TDATA A UCTXSTP=1 A UCTXSTT=0 UCTXSTP=0 A A11110xx□W / SLA(2.) 11110xx/R Master□Receiver S UCRXIFG=1 ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com Figure24-14.I2C Master 10-BitAddressing Mode

650 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

n Device #1 Lost Arbitration and Switches Off Bus Line SCL Data From Device #1 Data From Device #2 Bus Line SDA ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode 24.3.4.3Arbitration Iftwo ormore mastertransmitterssimultaneouslystarta transmissionon thebus,an arbitrationprocedure isinvoked.Figure24-15shows thearbitrationprocedurebetween two devices.The arbitrationprocedure uses thedatapresentedon SDA by thecompetingtransmitters.The firstmastertransmitterthatgenerates a logichighisoverruledby theopposingmastergeneratinga logiclow.The arbitrationproceduregives prioritytothedevicethattransmitstheserialdatastreamwiththelowestbinaryvalue.The master transmitterthatlostarbitrationswitchestotheslavereceivermode and setsthearbitrationlostflag UCALIFG. Iftwo ormore devicessend identicalfirstbytes,arbitrationcontinueson thesubsequentbytes. Figure24-15.ArbitrationProcedure Between Two Master Transmitters 651SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

Device #1 SCL From Device #2 Bus Line SCL ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com Ifthearbitrationprocedureisinprogresswhen a repeatedSTART conditionorSTOP conditionis transmittedon SDA, themastertransmittersinvolvedinarbitrationmust send therepeatedSTART conditionorSTOP conditionatthesame positionintheformatframe.Arbitrationisnotallowedbetween:

A repeatedSTART conditionand a databit
A STOP conditionand a databit
A repeatedSTART conditionand a STOP condition

24.3.5 I2C Clock Generationand Synchronization

The I2C clockSCL isprovidedby themasteron theI2C bus.When theUSCI isinmastermode, BITCLK is providedby theUSCI bitclockgeneratorand theclocksourceisselectedwiththeUCSSELx bits.Inslave mode, thebitclockgeneratorisnotused and theUCSSELx bitsaredon'tcare. The 16-bitvalueofUCBRx inregistersUCBxBR1 and UCBxBR0 isthedivisionfactoroftheUSCI clock source,BRCLK. The maximum bitclockthatcan be used insinglemastermode isfBRCLK /4.Inmulti-master mode, themaximum bitclockisfBRCLK /8.The BITCLK frequencyisgivenby: fBitClock= fBRCLK /UCBRx The minimum highand lowperiodsofthegeneratedSCL are: tLOW,MIN = tHIGH,MIN = (UCBRx/2)/fBRCLK when UCBRx iseven tLOW,MIN = tHIGH,MIN = (UCBRx – 1/2)/fBRCLK when UCBRx isodd The USCI clocksourcefrequencyand theprescalersettingUCBRx must tobe chosen such thatthe minimum lowand highperiodtimesoftheI2C specificationaremet. Duringthearbitrationproceduretheclocksfromthedifferentmastersmust be synchronized.A devicethat firstgeneratesa lowperiodon SCL overrulestheotherdevices,forcingthem tostarttheirown low periods.SCL isthenheldlowby thedevicewiththelongestlowperiod.The otherdevicesmust waitfor SCL tobe releasedbeforestartingtheirhighperiods.Figure24-16shows theclocksynchronization.This allowsa slowslavetoslowdown a fastmaster. Figure24-16.SynchronizationofTwo I2C Clock GeneratorsDuring Arbitration

652 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode 24.3.5.1Clock Stretching The USCI module supportsclockstretchingand alsomakes use ofthisfeatureas describedinthe OperationMode sections. The UCSCLLOW bitcan be used toobserveifanotherdevicepullsSCL lowwhiletheUSCI module alreadyreleasedSCL due tothefollowingconditions:

USCI isactingas masterand a connectedslavedrivesSCL low.
USCI isactingas masterand anothermasterdrivesSCL lowduringarbitration. The UCSCLLOW bitisalsoactiveiftheUSCI holdsSCL lowbecause itiswaitingas transmitterfordata beingwrittenintoUCBxTXBUF oras receiverforthedatabeingreadfromUCBxRXBUF. The UCSCLLOW bitmightgetsetfora shorttimewitheach risingSCL edge because thelogicobserves theexternalSCL and compares ittotheinternallygeneratedSCL.

24.3.6 Using theUSCI Module inI2C Mode With Low-Power Modes

The USCI module providesautomaticclockactivationforuse withlow-powermodes. When theUSCI clocksourceisinactivebecause thedeviceisina low-powermode, theUSCI module automatically activatesitwhen needed,regardlessofthecontrol-bitsettingsfortheclocksource.The clockremains activeuntiltheUSCI module returnstoitsidlecondition.AftertheUSCI module returnstotheidle condition,controloftheclocksourcerevertstothesettingsofitscontrolbits. InI2C slavemode, no internalclocksourceisrequiredbecause theclockisprovidedby theexternal master.ItispossibletooperatetheUSCI inI2C slavemode whilethedeviceisinLPM4 and allinternal clocksourcesaredisabled.The receiveortransmitinterruptscan wake up theCPU fromany low-power mode.

24.3.7 USCI InterruptsinI2C Mode

The USCI has onlyone interruptvectorthatissharedfortransmission,reception,and thestatechange. USCI_Ax and USC_Bx do notsharethesame interruptvector. Each interruptflaghas itsown interruptenablebit.When an interruptisenabledand theGIE bitisset,the interruptflaggeneratesan interruptrequest.DMA transfersarecontrolledby theUCTXIFG and UCRXIFG flagson deviceswitha DMA controller. 24.3.7.1I2C TransmitInterruptOperation The UCTXIFG interruptflagissetby thetransmittertoindicatethatUCBxTXBUF isreadytoaccept anothercharacter.An interruptrequestisgeneratedifUCTXIE and GIE arealsoset.UCTXIFG is automaticallyresetifa characteriswrittentoUCBxTXBUF orifa NACK isreceived.UCTXIFG isset when UCSWRST = 1 and theI2C mode isselected.UCTXIE isresetaftera PUC orwhen UCSWRST = 1. 24.3.7.2I2C Receive InterruptOperation The UCRXIFG interruptflagissetwhen a characterisreceivedand loadedintoUCBxRXBUF. An interruptrequestisgeneratedifUCRXIE and GIE arealsoset.UCRXIFG and UCRXIE areresetaftera PUC signalorwhen UCSWRST = 1.UCRXIFG isautomaticallyresetwhen UCxRXBUF isread. 653SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI Operation– I2C Mode www.ti.com 24.3.7.3I2C StateChange InterruptOperation Table24-1describestheI2C statechange interruptflags. Table24-1.I2C StateChange InterruptFlags InterruptFlag InterruptCondition UCALIFG Arbitration-lost.Arbitrationcan be lostwhen two ormore transmittersstarta transmissionsimultaneously,or when theUSCI operatesas masterbutisaddressedas a slaveby anothermasterinthesystem.The UCALIFG flagissetwhen arbitrationislost.When UCALIFG isset,theUCMST bitisclearedand theI2C controllerbecomes a slave. UCNACKIFG Not-acknowledgeinterrupt.Thisflagissetwhen an acknowledgeisexpectedbutisnotreceived. UCNACKIFG isautomaticallyclearedwhen a START conditionisreceived. UCSTTIFG START conditiondetectedinterrupt.Thisflagissetwhen theI2C module detectsa START conditiontogether withitsown addresswhileinslavemode. UCSTTIFG isused inslavemode onlyand isautomaticallycleared when a STOP conditionisreceived. UCSTPIFG STOP conditiondetectedinterrupt.Thisflagissetwhen theI2C module detectsa STOP conditionwhilein slavemode. UCSTPIFG isused inslavemode onlyand isautomaticallyclearedwhen a START conditionis received.

654 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI Operation– I2C Mode 24.3.7.4UCBxIV, InterruptVectorGenerator The USCI interruptflagsareprioritizedand combined tosourcea singleinterruptvector.The interrupt vectorregisterUCBxIV isused todeterminewhichflagrequestedan interrupt.The highest-priority enabledinterruptgeneratesa number intheUCBxIV registerthatcan be evaluatedoradded tothePC to automaticallyentertheappropriatesoftwareroutine.Disabledinterruptsdo notaffecttheUCBxIV value. Any access,readorwrite,oftheUCBxIV registerautomaticallyresetsthehighest-pendinginterruptflag.If anotherinterruptflagisset,anotherinterruptisimmediatelygeneratedafterservicingtheinitialinterrupt. 24.3.7.4.1UCBxIV SoftwareExample The followingsoftwareexample shows therecommended use ofUCBxIV. The UCBxIV valueisadded to thePC toautomaticallyjump totheappropriateroutine.The example isgivenforUSCI_B0. USCI_I2C_ISR ADD &UCB0IV,PC;Addoffsettojumptable RETI ;Vector0:Nointerrupt JMP ALIFG_ISR;Vector2:ALIFG JMP NACKIFG_ISR;Vector4:NACKIFG JMP STTIFG_ISR;Vector6:STTIFG JMP STPIFG_ISR;Vector8:STPIFG JMP RXIFG_ISR;Vector10:RXIFG TXIFG_ISR ;Vector12 ... ;Taskstartshere RETI ;Return ALIFG_ISR ;Vector2 ... ;Taskstartshere RETI ;Return NACKIFG_ISR ;Vector4 ... ;Taskstartshere RETI ;Return STTIFG_ISR ;Vector6 ... ;Taskstartshere RETI ;Return STPIFG_ISR ;Vector8 ... ;Taskstartshere RETI ;Return RXIFG_ISR ;Vector10 ... ;Taskstartshere RETI ;Return 655SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI_B I2C Mode Registers www.ti.com

24.4 USCI_B I2C Mode Registers

The USCI registersapplicableinI2C mode arelistedinTable24-2.The base addresscan be foundinthe device-specificdatasheet.The addressoffsetsarelistedinTable24-2. Table24-2.USCI_B Registers Offset Acronym RegisterName Type Access Reset Section 00h UCBxCTLW0 USCI_Bx ControlWord 0 Read/write Word 0101h 00h UCBxCTL1 USCI_Bx Control1 Read/write Byte 01h Section24.4.2 01h UCBxCTL0 USCI_Bx Control0 Read/write Byte 01h Section24.4.1 06h UCBxBRW USCI_Bx BitRate ControlWord Read/write Word 0000h 06h UCBxBR0 USCI_Bx BitRate Control0 Read/write Byte 00h Section24.4.3 07h UCBxBR1 USCI_Bx BitRate Control1 Read/write Byte 00h Section24.4.4 0Ah UCBxSTAT USCI_Bx Status Read/write Byte 00h Section24.4.5 0Bh Reserved-readszero Read Byte 00h 0Ch UCBxRXBUF USCI_Bx ReceiveBuffer Read/write Byte 00h Section24.4.6 0Dh Reserved-readszero Read Byte 00h 0Eh UCBxTXBUF USCI_Bx TransmitBuffer Read/write Byte 00h Section24.4.7 0Fh Reserved-readszero Read Byte 00h 10h UCBxI2COA USCI_Bx I2C Own Address Read/write Word 0000h Section24.4.8 12h UCBxI2CSA USCI_Bx I2C SlaveAddress Read/write Word 0000h Section24.4.9 1Ch UCBxICTL USCI_Bx InterruptControl Read/write Word 0200h 1Ch UCBxIE USCI_Bx InterruptEnable Read/write Byte 00h Section24.4.10 1Dh UCBxIFG USCI_Bx InterruptFlag Read/write Byte 02h Section24.4.11 1Eh UCBxIV USCI_Bx InterruptVector Read Word 0000h Section24.4.12

656 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI_B I2C Mode Registers

24.4.1 UCBxCTL0 Register

USCI_Bx ControlRegister0 Figure24-17.UCBxCTL0 Register 7 6 5 4 3 2 1 0 UCA10 UCSLA10 UCMM Reserved UCMST UCMODEx UCSYNC rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 rw-0 r-1 Modifyonlywhen UCSWRST = 1. Table24-3.UCBxCTL0 RegisterDescription Bit Field Type Reset Description

7 UCA10 RW 0h Own addressingmode select

0b = Own addressisa 7-bitaddress 1b = Own addressisa 10-bitaddress

6 UCSLA10 RW 0h Slaveaddressingmode select

0b = Addressslavewith7-bitaddress 1b = Addressslavewith10-bitaddress

5 UCMM RW 0h Multi-masterenvironmentselect

0b = Singlemasterenvironment.Thereisno othermasterinthesystem.The addresscompare unitisdisabled. 1b = Multi-masterenvironment 4 Reserved R 0h Reserved.Alwaysreadsas 0. 3 UCMST RW 0h Mastermode select.When a masterlosesarbitrationina multi-master environment(UCMM = 1),theUCMST bitisautomaticallyclearedand the module actsas slave. 0b = Slavemode 1b = Mastermode 2-1 UCMODEx RW 0h USCI mode. The UCMODEx bitsselectthesynchronousmode when UCSYNC = 00b = 3-pinSPI 01b = 4-pinSPI (master/slaveenabledifSTE = 1) 10b = 4-pinSPI (master/slaveenabledifSTE = 0) 11b = I2C mode

0 UCSYNC R 1h Synchronousmode enable

0b = Asynchronousmode 1b = Synchronousmode 657SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. USCI_B I2C Mode Registers www.ti.com

24.4.2 UCBxCTL1 Register

USCI_Bx ControlRegister1 Figure24-18.UCBxCTL1 Register 7 6 5 4 3 2 1 0 UCSSELx Reserved UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST rw-0 rw-0 r0 rw-0 rw-0 rw-0 rw-0 rw-1 Modifyonlywhen UCSWRST = 1. Table24-4.UCBxCTL1 RegisterDescription Bit Field Type Reset Description 7-6 UCSSELx RW 0h USCI clocksourceselect.These bitsselecttheBRCLK sourceclock. 00b = UCLKI 01b = ACLK 10b = SMCLK 11b = SMCLK 5 Reserved RW 0h Reserved.Alwaysreadsas 0.

4 UCTR RW 0h Transmitterorreceiver

0b = Receiver 1b = Transmitter 3 UCTXNACK RW 0h Transmita NACK. UCTXNACK isautomaticallyclearedaftera NACK is transmitted. 0b = Acknowledgenormally 1b = GenerateNACK 2 UCTXSTP RW 0h TransmitSTOP conditioninmastermode. Ignoredinslavemode. Inmaster receivermode, theSTOP conditionisprecededby a NACK. UCTXSTP is automaticallyclearedafterSTOP isgenerated. 0b = No STOP generated 1b = GenerateSTOP 1 UCTXSTT RW 0h TransmitSTART conditioninmastermode. Ignoredinslavemode. Inmaster receivermode, a repeatedSTART conditionisprecededby a NACK. UCTXSTT isautomaticallyclearedafterSTART conditionand addressinformationis transmitted.Ignoredinslavemode. 0b = Do notgenerateSTART condition 1b = GenerateSTART condition 0b = Disabled.USCI resetreleasedforoperation. 1b = Enabled.USCI logicheldinresetstate.

658 SLAU259E –May 2009–RevisedJanuary2013UniversalSerialCommunicationInterface– I2C Mode

ECCN 5E002 TSPA -Technology/SoftwarePubliclyAvailable. www.ti.com USCI_B I2C Mode Registers

24.4.3 UCBxBR0 Register

USCI_Bx Baud Rate ControlRegister0 Figure24-19.UCBxBR0 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table24-5.UCBxBR0 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefined Bitclockprescalerlowbyte.The 16-bitvalueof(UCxxBR0 + UCxxBR1 × 256) formstheprescalervalueUCBRx.

24.4.4 UCBxBR1 Register

USCI_Bx Baud Rate ControlRegister1 Figure24-20.UCBxBR1 Register 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw Modifyonlywhen UCSWRST = 1. Table24-6.UCBxBR1 RegisterDescription Bit Field Type Reset Description 7-0 UCBRx RW undefined Bitclockprescalerhighbyte.The 16-bitvalueof(UCxxBR0 + UCxxBR1 × 256) formstheprescalervalueUCBRx. 659SLAU259E –May 2009–RevisedJanuary2013 UniversalSerialCommunicationInterface– I2C Mode SubmitDocumentationFeedback Copyright© 2009–2013,Texas InstrumentsIncorporated

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CC430 specifications and overview.

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ECCN 5E002 TSPA - Technology / Software Publicly Available.

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ECCN 5E002 TSPA - Technology / Software Publicly Available.

Source title CC430 Datasheet(PDF) - Texas Instruments

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