CC3220SF12ARGKT

CC3220R_18 TI1 | Alldatasheet

Document overview

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Technical content

Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 CC3220R,CC3220S,andCC3220SFSimpleLink™ Wi-Fi® Single-ChipWirelessMCUSolutions

1 Device Overview

1.1 Features

• Dual-Core Architecture: – User-Dedicated Application MCU Subsystem – Highly-Integrated Wi-Fi Network Processor
• Rich Set of IoT Security Features: – Enhanced IoT Networking Security – Asymmetric Keys and Unique Device Identity – Software IP Protection and Secure Storage (CC3220S/CC3220SF)
• Advanced Low-Power Modes for Battery Powered

Applications

• Built-In Power Management Subsystem
• Industrial Temperature: –40°C to 85°C
• Chip-Level Wi-Fi Alliance® Wi-Fi CERTIFIED™ Extended Features List:
• Applications Microcontroller Subsystem: – Arm® Cortex®-M4 Core at 80 MHz – Embedded Memory: – 256KB of RAM – Optional 1MB of Executable Flash – External Serial Flash – Peripherals: – McASP Supports Two I2S Channels – SD, SPI, I2C, UART – 8-Bit Synchronous Imager Interface – 4-Channel 12-Bit ADCs – 4 General-Purpose Timers (GPT) With 16-Bit PWM Mode – Watchdog Timer – Up to 27 GPIO Pins – Debug Interfaces: JTAG, cJTAG, SWD
• Wi-Fi Network Processor (NWP) Subsystem: – Wi-Fi Modes: – 802.11b/g/n Station – 802.11b/g Access Point (AP) Supports up to Four Stations – Wi-Fi Direct® Client and Group Owner – WPA2 Personal and Enterprise Security: WEP, WPA™ / WPA2™ PSK, WPA2 Enterprise (802.1x) – IPv4 and IPv6 TCP/IP Stack – Industry-Standard BSD Socket Application Programming Interfaces (APIs): – 16 Simultaneous TCP or UDP Sockets – 6 Simultaneous TLS and SSL Sockets – IP Addressing: Static IP, LLA, DHCPv4, DHCPv6 With Duplicate Address Detection (DAD) – SimpleLink Connection Manager for Autonomous and Fast Wi-Fi Connections – Flexible Wi-Fi Provisioning With SmartConfig™ Technology, AP Mode, and WPS2 Options – RESTful API Support Using the Internal HTTP Server – Wide Set of Security Features: – Hardware Features: – Separate Execution Environments – Device Identity – Hardware Crypto Engine for Advanced Fast Security, Including: AES, DES, 3DES, SHA2, MD5, CRC, and Checksum – Initial Secure Programming: – Debug Security – JTAG and Debug Ports are Locked – Personal and Enterprise Wi-Fi Security – Secure Sockets (SSLv3, TLS1.0, TLS1.1, TLS1.2) – Networking Security: – Personal and Enterprise Wi-Fi Security – Secure Sockets (SSLv3, TLS1.0, TLS1.1, TLS1.2) – HTTPS Server – Trusted Root-Certificate Catalog – TI Root-of-Trust Public Key – Software IP Protection: – Secure Key Storage – File System Security – Software Tamper Detection – Cloning Protection – Secure Boot: Validate the Integrity and Authenticity of the Runtime Binary During Boot

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device Overview Copyright © 2016–2018, Texas Instruments Incorporated – Embedded Network Applications Running on the Dedicated Network Processor: – HTTP/HTTPS Web Server With Dynamic User Callbacks – mDNS, DNS-SD, DHCP Server – Ping – Recovery Mechanism— Can Recover to Factory Defaults or to a Complete Factory Image – Wi-Fi TX Power: – 18.0 dBm at 1 DSSS – 14.5 dBm at 54 OFDM – Wi-Fi RX Sensitivity: – –96 dBm at 1 DSSS – –74.5 dBm at 54 OFDM – Application Throughput: – UDP: 16 Mbps – TCP: 13 Mbps – Peak: 72 Mbps

• Power-Management Subsystem: – Integrated DC/DC Converters Support a Wide Range of Supply Voltage: – VBAT Wide-Voltage Mode: 2.1 V to 3.6 V – VIO is Always Tied With VBAT – Preregulated 1.85-V Mode – Advanced Low-Power Modes: – Shutdown: 1 µA – Hibernate: 4.5 µA – Low-Power Deep Sleep (LPDS): 135 µA (Measured on CC3220R, CC3220S, and CC3220SF With 256KB RAM Retention) – RX Traffic (MCU Active): 59 mA (Measured on CC3220R and CC3220S; CC3220SF Consumes an Additional 10 mA) at 54 OFDM – TX Traffic (MCU Active): 223 mA (Measured on CC3220R and CC3220S; CC3220SF Consumes an Additional 15 mA) at

54 OFDM, Maximum Power

– Idle Connected (MCU in LPDS): 710 µA (Measured on CC3220R and CC3220S With 256KB RAM Retention) at DTIM = 1

• Clock Source: – 40.0-MHz Crystal With Internal Oscillator – 32.768-kHz Crystal or External RTC
• RGK Package – 64-Pin, 9-mm × 9-mm Very Thin Quad Flat Nonleaded (VQFN) Package, 0.5-mm Pitch
• Operating Temperature – Ambient Temperature Range: –40°C to +85°C
• Device Supports SimpleLink™ MCU Platform Developer's Ecosystem

1.2 Applications

• For Internet of Things applications, such as: – Building and Home Automation:
• HVAC Systems & Thermostat
• Video Surveillance, Video Doorbells, and Low-Power Camera
• Building Security Systems & E-locks – Appliances – Asset Tracking – Factory Automation – Medical and Healthcare – Grid Infrastructure

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device OverviewCopyright © 2016–2018, Texas Instruments Incorporated

1.3 Description

The SoC Wireless MCU CC3220x device comes in three variants: CC3220R, CC3220S, and C3220SF.

• CC3220R features 256KB of RAM, IoT networking security and device identity/keys.
• CC3220S builds on the CC3220R and MCU level security such as file system encryption, user IP (MCU image) encryption, secure boot and debug security.
• CC3220SF builds on the CC3220S and integrates a user-dedicated 1MB of executable Flash, in addition to the 256KB of RAM. Start your internet-of-things (IoT) design with a Wi-Fi CERTIFIED™ Wireless Microcontroller. The SimpleLink™ Wi-Fi® CC3220x device family is a system-on-chip (SoC) solution, that integrates two processors within a single-chip:
• The application processor is an Arm® Cortex®-M4 MCU with a user-dedicated 256KB of RAM and an optional 1MB of serial flash.
• The network processor MCU runs all Wi-Fi® and internet logical layers. This ROM-based subsystem includes an 802.11b/g/n radio, baseband, and MAC with a powerful crypto engine. These devices introduce new features and capabilities that further simplify the connectivity of things to the internet. The main new features include the following:
• Optimized low-power management
• Enhanced networking security
• Device identity and Asymmetric keys
• Enhanced file system security (supported only by the CC3220S and CC3220SF variants)
• IPv6 TCP/IP Stack
• AP mode with support of four stations
• Up to 16 concurrent BSD sockets, of which 6 are secure
• HTTPS support
• RESTful API support The CC3220x device family is part of the SimpleLink™ MCU platform, a common, easy-to-use development environment based on a single core software development kit (SDK), rich tool set, reference designs and E2E™ community that supports Wi-Fi®, Bluetooth® low energy, Sub-1 GHz and host MCUs. For more information, visit the SimpleLink™ MCU Platform. (1) For all available packages, see the orderable addendum at the end of the data sheet. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CC3220RM2ARGKR/T VQFN (64) 9.00 mm × 9.00 mm CC3220SM2ARGKR/T VQFN (64) 9.00 mm × 9.00 mm CC3220SF12ARGKR/T VQFN (64) 9.00 mm × 9.00 mm

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device Overview Copyright © 2016–2018, Texas Instruments Incorporated

1.4 Functional Block Diagrams

Figure 1-1 shows the functional block diagram of the CC3220x SimpleLink Wi-Fi solution. Figure 1-1. Functional Block Diagram

CC32xx ± Single-Chip Wireless MCU Arm ® Cortex® -M4 Processor

80 MHz

1MB flash (optional) 256KB RAM ROM Peripherals 1× SPI 2× UART 1× I2C 1× I2S/PCM 1× SD/MMC 8-bit Camera 4× ADC SystemDMA Timers GPIOs Network Processor Application Protocols RAM ROM Crypto Engine Wi-Fi® Driver TCP/IP Stack (Arm® Cortex® Processor) Power Management Oscillators DC/DC RTC Baseband MAC Processor Radio Synthesizer CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device OverviewCopyright © 2016–2018, Texas Instruments Incorporated Figure 1-2 shows the CC3220x hardware overview. Figure 1-2. CC3220x Hardware Overview

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Revision HistoryCopyright © 2016–2018, Texas Instruments Incorporated Table of Contents

4.5 Drive Strength and Reset States for Analog and

4.6 Pad State After Application of Power to Chip But

5.5 Current Consumption Summary (CC3220R,

5.7 TX Power and IBAT versus TX Power Level

5.14 Thermal Resistance Characteristics for RGK

9 Mechanical, Packaging, and Orderable

2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from February 7, 2017 to November 29, 2018 Page

• Added By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW in the
• Deleted "VBAT present and nReset pin pulled low" from the "MCU SHUTDOWN" row in the Current

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Revision History Copyright © 2016–2018, Texas Instruments Incorporated

• Deleted "VBAT present and nReset pin pulled low" from the "MCU SHUTDOWN" row in the Current
• Added the table note "Power of 802.11b rates are reduced to meet ETSI requirements" to the WLAN
• Deleted the Functional Block Diagram subsection in the Detailed Description section. Subsequent subsections

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device ComparisonCopyright © 2016–2018, Texas Instruments Incorporated

3 Device Comparison

Table 3-1 shows the features supported across different CC3220 devices. Table 3-1. Device Features Comparison FEATURE DEVICE CC3220R CC3220S CC3220SF On-Chip Application Memory RAM 256KB 256KB 256KB Flash – – 1MB Security Features Enhanced Application Level Security – File system security Secure key storage Software tamper detection Cloning protection Initial secure programming File system security Secure key storage Software tamper detection Cloning protection Initial secure programming Hardware Acceleration Hardware Crypto Engines Hardware Crypto Engines Hardware Crypto Engines Additional Networking Security Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key Unique Device Identity Trusted Root-Certificate Catalog TI Root-of-Trust Public key Secure Boot No Yes Yes Additional Features Standard 802.11 b/g/n TCP/IP Stack IPv4, IPv6 Package 9 mm × 9 mm VQFN Sockets 16

3.1 Related Products

For information about other devices in this family of products or related products, see the following links: SimpleLink™ MCU Portfolio This portfolio offers a single development environment that delivers flexible hardware, software and tool options for customers developing wired and wireless applications. With 100 percent code reuse across host MCUs, Wi-Fi™ , Bluetooth® low energy, Sub-1 GHz devices and more, choose the MCU or connectivity standard that fits your design. A one-time investment with the SimpleLink software development kit (SDK) allows you to reuse often, opening the door to create unlimited applications. SimpleLink™ Wi-Fi® Family This device platform offers several Internet-on-a chip™ solutions, which address the need of battery operated, security enabled products. Texas instruments offers a single chip wireless microcontroller and a wireless network processor which can be paired with any MCU, to allow developers to design new wi-fi products, or upgrade existing products with wi-fi capabilities. BoosterPack™ Plug-In Modules The BoosterPack Plug-in modules extend the functionality of TI LaunchPad Development Kit. Application-specific BoosterPack Plug-in modules allow you to explore a broad range of applications, including capacitive touch, wireless sensing, LED Lighting control, and more. Stack multiple BoosterPack modules onto a single LaunchPad kit to further enhance the functionality of your design. Reference Designs for CC3200 and CC3220 Devices TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs and design files to speed your time to market. Search and download designs at ti.com/tidesigns. SimpleLink™ Wi-Fi® CC3220 SDK This SDK contains drivers for the CC3220 programmable MCU, sample applications, and documentation required to start development with CC3220 solutions.

VDD_RAM GPIO0 RTC_XTAL_P RTC_XTAL_N GPIO30 VIN_IO2 GPIO1 VDD_DIG2 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDD_ANA1 VDD_ANA2 DCDC_ANA2_SW_N DCDC_ANA2_SW_P VIN_DCDC_DIG DCDC_DIG_SW DCDC_PA_OUT DCDC_PA_SW_N DCDC_PA_SW_P VIN_DCDC_PA DCDC_ANA_SW VIN_DCDC_ANA LDO_IN1 SOP0 SOP1 VDD_PA_IN nRESET RF_BG ANTSEL2 ANTSEL1 NC NC NC LDO_IN2 VDD_PLL WLAN_XTAL_P WLAN_XTAL_N SOP2 TMS TCK GPIO28 TDO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 VDD_DIG1 VIN_IO1 FLASH_SPI_CLK FLASH_SPI_DOUT FLASH_SPI_DIN FLASH_SPI_CS GPIO22 TDI CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows pin assignments for the 64-pin VQFN package. NC = No internal connection Figure 4-1. VQFN 64-Pin Assignments Top View

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated

4.2 Pin Attributes and Pin Multiplexing

The device makes extensive use of pin multiplexing to accommodate the large number of peripheral functions in the smallest possible package. To achieve this configuration, pin multiplexing is controlled using a combination of hardware configuration (at device reset) and register control. NOTE TI highly recommends using Pin Mux Tool to obtain the desired pinout. The board and software designers are responsible for the proper pin multiplexing configuration. Hardware does not ensure that the proper pin multiplexing options are selected for the peripherals or interface mode used. Table 4-1 and Table 4-2 list the pin descriptions and attributes. Table 4-3 lists the signal descriptions. Table 4-4 presents an overall view of pin multiplexing. All pin multiplexing options are configurable using the pin mux registers. The following special considerations apply:

• All I/Os support drive strengths of 2, 4, and 6 mA. The drive strength is individually configurable for each pin.
• All I/Os support 10-µA pullup and pulldown resistors.
• The VIO and VBAT supply must be tied together at all times.
• By default, all I/Os float in the Hibernate state. However, the default state can be changed by SW.
• All digital I/Os are nonfail-safe. NOTE If an external device drives a positive voltage to the signal pads and the CC3220x device is not powered, DC is drawn from the other device. If the drive strength of the external device is adequate, an unintentional wakeup and boot of the CC3220x device can occur. To prevent current draw, TI recommends any one of the following conditions:
• All devices interfaced to the CC3220x device must be powered from the same power rail as the chip.
• Use level shifters between the device and any external devices fed from other independent rails.
• The nRESET pin of the CC3220x device must be held low until the VBAT supply to the device is driven and stable.
• All GPIO pins default to high impedance unless programmed by the MCU. The bootloader sets the TDI, TDO, TCK, TMS, and Flash_SPI pins to mode 1. All the other pins are left in the Hi-Z state. Table 4-1. Pin Descriptions PINS TYPE DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAGNO. NAME

1 GPIO10 I/O General-purpose input or output No No No

2 GPIO11 I/O General-purpose input or output Yes No No

3 GPIO12 I/O General-purpose input or output No No No

4 GPIO13 I/O General-purpose input or output Yes No No

5 GPIO14 I/O General-purpose input or output No No No

6 GPIO15 I/O General-purpose input or output No No No

7 GPIO16 I/O General-purpose input or output No No No

8 GPIO17 I/O General-purpose input or output Yes No No

9 VDD_DIG1 Power Internal digital core voltage N/A N/A N/A

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-1. Pin Descriptions (continued) PINS TYPE DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAGNO. NAME (1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. (2) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities. (3) Device firmware automatically enables the digital path during ROM boot.

10 VIN_IO1 Power I/O power supply (same as

battery voltage) N/A N/A N/A

11 FLASH_SPI_CLK O Serial flash interface: SPI clock N/A N/A N/A

12 FLASH_SPI_DOUT O Serial flash interface: SPI data

13 FLASH_SPI_DIN I Serial flash interface: SPI data in N/A N/A N/A

14 FLASH_SPI_CS O Serial flash interface: SPI chip

15 GPIO22 I/O General-purpose input or output No No No

16 TDI I/O JTAG interface: data input No No Muxed with

17 TDO I/O JTAG interface: data output Yes No Muxed with

18 GPIO28 I/O General-purpose input or output No No No

19 TCK I/O JTAG/SWD interface: clock No No

20 TMS I/O JTAG/SWD interface: mode

21(1) SOP2 I Configuration sense-on-power 2 No No No 22 WLAN_XTAL_N Analog 40-MHz crystal. Pulldown if external TCXO is used. N/A N/A N/A

23 WLAN_XTAL_P Analog 40-MHz crystal or TCXO clock

24 VDD_PLL Power Internal analog voltage N/A N/A N/A

25 LDO_IN2 Power Internal analog RF supply from

analog DC/DC output N/A N/A N/A

26 NC — No connect N/A N/A N/A

27 NC — Reserved N/A N/A N/A

28 NC — Reserved N/A N/A N/A

29(2) ANTSEL1 O Antenna selection control No User configuration not required (3) No 30(2) ANTSEL2 O Antenna selection control No User configuration not required (3) No 31 RF_BG RF RF BG band: 2.4-GHz TX, RX N/A N/A N/A 32 nRESET I Master chip reset input. Active low input. N/A N/A N/A

33 VDD_PA_IN Power Internal RF power amplifier (PA)

input from PA DC/DC output N/A N/A N/A

34 SOP1 I Configuration sense-on-power 1 N/A N/A N/A

35 SOP0 I Configuration sense-on-power 0 N/A N/A N/A

36 LDO_IN1 Power Internal Analog RF supply from

analog DC/DC output N/A N/A N/A

37 VIN_DCDC_ANA Analog DC/DC supply input

(same as battery voltage [VBAT]) N/A N/A N/A

38 DCDC_ANA_SW Power Internal Analog DC/DC converter

switching node N/A N/A N/A

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated Table 4-1. Pin Descriptions (continued) PINS TYPE DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAGNO. NAME (4) Pin 45 is used by an internal DC/DC converter (ANA2_DCDC). This pin will be available automatically if the serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47. (5) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for the RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the device to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions. (6) To use the digital functions, RTC_XTAL_N must be pulled high to the supply voltage using a 100-kΩ resistor. (7) This pin is shared by the ADC inputs and digital I/O pad cells. (8) Requires user configuration to enable the analog switch of the ADC channel (the switch is off by default.) The digital I/O is always connected and must be made Hi-Z before enabling the ADC switch.

39 VIN_DCDC_PA Power PA DC/DC converter input supply

(same as battery voltage [VBAT]) N/A N/A N/A

40 DCDC_PA_SW_P Power Internal PA DC/DC converter

+ve switching node N/A N/A N/A

41 DCDC_PA_SW_N Power Internal PA DC/DC converter

–ve switching node N/A N/A N/A

42 DCDC_PA_OUT Power Internal PA buck DC/DC

converter output N/A N/A N/A

43 DCDC_DIG_SW Power Internal Digital DC/DC converter

switching node N/A N/A N/A

44 VIN_DCDC_DIG Power

Digital DC/DC converter supply input (same as battery voltage [VBAT]) N/A N/A N/A 45(4) DCDC_ANA2_SW_P I/O Analog2 DC/DC converter +ve switching node No User configuration not required (3) No

46 DCDC_ANA2_SW_N Power Internal Analog2 DC/DC

converter –ve switching node N/A N/A N/A

47 VDD_ANA2 Power Internal Analog2 DC/DC output N/A N/A N/A

48 VDD_ANA1 Power

Internal Analog1 power supply fed by analog2 DC/DC converter output N/A N/A N/A

49 VDD_RAM Power Internal SRAM LDO output N/A N/A N/A

50 GPIO0 I/O General-purpose input or output No User configuration

not required (3) No 51 RTC_XTAL_P Analog 32.768-kHz XTAL_P or external CMOS level clock input N/A N/A N/A 52(5) RTC_XTAL_N Analog 32.768-kHz XTAL_N N/A User configuration not required (3)(6) No

53 GPIO30 I/O General-purpose input or output No User configuration

not required (3) No

54 VIN_IO2 Power device supply voltage (VBAT) N/A N/A N/A

55 GPIO1 I/O General-purpose input or output No No No

56 VDD_DIG2 Power internal digital core voltage N/A N/A N/A

57(7) GPIO2 I/O Analog input (up to 1.5-V ) or general-purpose input or output Yes See (8) No 58(7) GPIO3 I/O Analog input (up to 1.5-V ) or general-purpose input or output No See (8) No 59(7) GPIO4 I/O Analog input (up to 1.5-V ) or general-purpose input or output Yes See (8) No 60(7) GPIO5 I/O Analog input (up to 1.5 V) or general-purpose input or output No See (8) No

61 GPIO6 I/O General-purpose input or output No No No

62 GPIO7 I/O General-purpose input or output No No No

63 GPIO8 I/O General-purpose input or output No No No

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-1. Pin Descriptions (continued) PINS TYPE DESCRIPTION SELECT AS WAKEUP SOURCE CONFIGURE ADDITIONAL ANALOG MUX MUXED WITH JTAGNO. NAME

64 GPIO9 I/O General-purpose input or output No No No

GND_TAB — Thermal pad and electrical ground N/A N/A N/A (1) Signals names with (PN) denote the default pin name. (2) Signal Types: I = Input, O = Output, I/O = Input or Output. (3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need. (4) Hibernate mode: The I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need. Table 4-2. Pin Attributes PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 GPIO10 (PN) I/O

0 I/O Hi-Z, Pull, Drive

Hi-Z, Pull, Drive Hi-Z I2C_SCL 1 I/O (open drain) Hi-Z, Pull, Drive GT_PWM06 3 O Hi-Z, Pull, Drive UART1_TX 7 O 1 SDCARD_CLK 6 O 0 GT_CCP01 12 I Hi-Z, Pull, Drive GPIO11 (PN) I/O Hi-Z, Pull, Drive Hi-Z I2C_SDA 1 I/O (open drain) Hi-Z, Pull, Drive GT_PWM07 3 O Hi-Z, Pull, Drive pXCLK (XVCLK) 4 O 0 SDCARD_CMD 6 I/O (open drain) Hi-Z, Pull, Drive UART1_RX 7 I Hi-Z, Pull, Drive GT_CCP02 12 I Hi-Z, Pull, Drive McAFSX 13 O Hi-Z, Pull, Drive GPIO12 (PN) I/O Hi-Z, Pull, Drive Hi-Z McACLK 3 O Hi-Z, Pull, Drive pVS (VSYNC) 4 I Hi-Z, Pull, Drive I2C_SCL 5 I/O (open drain) Hi-Z, Pull, Drive UART0_TX 7 O 1 GT_CCP03 12 I Hi-Z, Pull, Drive GPIO13 (PN) I/O

0 I/O

Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z I2C_SDA 5 I/O (open drain) pHS (HSYNC) 4 I UART0_RX 7 I GT_CCP04 12 I GPIO14 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z I2C_SCL 5 I/O (open drain) GSPI_CLK 7 I/O pDATA8 (CAM_D4) 4 I GT_CCP05 12 I

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated Table 4-2. Pin Attributes (continued) PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 (5) To minimize leakage in some serial flash vendors during LPDS, TI recommends that the user application always enables internal weak pulldown resistors on the FLASH_SPI_DIN, FLASH_SPI_DOUT, and FLASH_SPI_CLK pins. GPIO15 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z I2C_SDA 5 I/O (open drain) GSPI_MISO 7 I/O pDATA9 (CAM_D5) 4 I GT_CCP06 13 I SDCARD_DATA0 8 I/O GPIO16 (PN) I/O Hi-Z, Pull, Drive Hi-Z GSPI_MOSI 7 I/O Hi-Z, Pull, Drive pDATA10 (CAM_D6) 4 I Hi-Z, Pull, Drive UART1_TX 5 O 1 GT_CCP07 13 I Hi-Z, Pull, Drive SDCARD_CLK 8 O 0 GPIO17 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z UART1_RX 5 I GSPI_CS 7 I/O pDATA11 (CAM_D7) 4 I SDCARD_CMD 8 I/O

9 VDD_DIG1 (PN) — N/A N/A N/A N/A N/A

10 VIN_IO1 — N/A N/A N/A N/A N/A

11 FLASH_SPI_CLK O N/A O Hi-Z, Pull,

Drive(5) Hi-Z, Pull, Drive Hi-Z

12 FLASH_SPI_DOUT O N/A O Hi-Z, Pull,

Drive(5) Hi-Z, Pull, Drive Hi-Z

13 FLASH_SPI_DIN I N/A I Hi-Z, Pull,

Drive(5) Hi-Z Hi-Z

14 FLASH_SPI_CS O N/A O 1 Hi-Z, Pull,

GPIO22 (PN) I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-ZMcAFSX O 7 O GT_CCP04 I 5 I TDI (PN) I/O 1 I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GPIO23 0 I/O UART1_TX 2 O 1 I2C_SCL 9 I/O (open drain) Hi-Z, Pull, Drive TDO (PN) I/O 1 O Hi-Z, Pull, Drive Driven high in SWD; driven low in 4-wire JTAG Hi-Z GPIO24 0 I/O PWM0 5 O UART1_RX 2 I I2C_SDA 9 I/O (open drain) GT_CCP06 4 I McAFSX 6 O

18 GPIO28 I/O 0 I/O Hi-Z, Pull, Drive Hi-Z, Pull,

TCK (PN) I/O 1 I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GT_PWM03 8 O

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-2. Pin Attributes (continued) PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 (6) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. (7) For details on proper use, see Section 4.5. (8) This pin is one of three that must have a passive pullup or pulldown resistor onboard to configure the device hardware power-up mode. For this reason, the pin must be output only when used for digital functions. (9) This pin is reserved for WLAN antenna selection, controlling an external RF switch that multiplexes the RF pin of the CC3220x device between two antennas. These pins must not be used for other functionalities. TMS (PN) I/O I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GPIO29 0 21(6) GPIO25 O

0 O Hi-Z, Pull, Drive

GT_PWM02 9 O Hi-Z, Pull, Drive McAFSX 2 O Hi-Z, Pull, Drive TCXO_EN N/A (see (7)) O 0 SOP2 (PN) N/A (see (8)) I Hi-Z, Pull, Drive

22 WLAN_XTAL_N — N/A

(see (7)) N/A N/A N/A N/A

23 WLAN_XTAL_P — N/A N/A N/A N/A N/A

24 VDD_PLL — N/A N/A N/A N/A N/A

25 LDO_IN2 — N/A N/A N/A N/A N/A

26 NC — N/A N/A N/A N/A N/A

27 NC — N/A N/A N/A N/A N/A

28 NC — N/A N/A N/A N/A N/A

29(9) ANTSEL1 O 0 O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z 30(9) ANTSEL2 O 0 O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z

31 RF_BG — N/A N/A N/A N/A N/A

32 nRESET — N/A N/A N/A N/A N/A

33 VDD_PA_IN — N/A N/A N/A N/A N/A

34 SOP1 — N/A N/A N/A N/A N/A

35 SOP0 — N/A N/A N/A N/A N/A

36 LDO_IN1 — N/A N/A N/A N/A N/A

37 VIN_DCDC_ANA — N/A N/A N/A N/A N/A

38 DCDC_ANA_SW — N/A N/A N/A N/A N/A

39 VIN_DCDC_PA — N/A N/A N/A N/A N/A

40 DCDC_PA_SW_P — N/A N/A N/A N/A N/A

41 DCDC_PA_SW_N — N/A N/A N/A N/A N/A

42 DCDC_PA_OUT — N/A N/A N/A N/A N/A

43 DCDC_DIG_SW — N/A N/A N/A N/A N/A

44 VIN_DCDC_DIG — N/A N/A N/A N/A N/A

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated Table 4-2. Pin Attributes (continued) PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 (10) Pin 45 is used by an internal DC/DC (ANA2_DCDC). This pin will be available automatically if serial flash is forced in the CC3220SF device. For the CC3220R and CC3220S devices, pin 45 can be used as GPIO_31 if a supply is provided on pin 47. (11) Pin 52 is used by the RTC crystal oscillator. These devices use automatic configuration sensing. Therefore, some board-level configuration is required to use pin 52 as a digital pad. Pin 52 is used for RTC crystal in most applications. However, in some applications a 32.768-kHz square-wave clock might always be available onboard. When a 32.768-kHz square-wave clock is available, the crystal can be removed to free pin 52 for digital functions. The external clock must then be applied at pin 51. For the chip to automatically detect this configuration, a 100-kΩ pullup resistor must be connected between pin 52 and the supply line. To prevent false detection, TI recommends using pin 52 for output-only functions. 45(10) GPIO31 I/O UART0_RX 9 I McAFSX 12 O UART1_RX 2 I McAXR0 6 I/O GSPI_CLK 7 I/O DCDC_ANA2_SW_P (PN) — N/A (see (7)) N/A N/A N/A N/A

46 DCDC_ANA2_SW_N — N/A N/A N/A N/A N/A

47 VDD_ANA2 — N/A N/A N/A N/A N/A

48 VDD_ANA1 — N/A N/A N/A N/A N/A

49 VDD_RAM — N/A N/A N/A N/A N/A

GPIO0 (PN) I/O Hi-Z, Pull, Drive Hi-Z UART0_CTS 12 I Hi-Z, Pull, Drive McAXR1 6 I/O Hi-Z, Pull, Drive GT_CCP00 7 I Hi-Z, Pull, Drive GSPI_CS 9 I/O Hi-Z, Pull, Drive UART1_RTS 10 O 1 UART0_RTS 3 O 1 McAXR0 4 I/O Hi-Z, Pull, Drive

51 RTC_XTAL_P — N/A N/A N/A N/A N/A

52(11) RTC_XTAL_N (PN) O N/A N/A N/A Hi-Z, Pull, Drive Hi-Z GPIO32 0 O Hi-Z, Pull, DriveMcACLK 2 O McAXR0 4 O UART0_RTS 6 O 1 GSPI_MOSI 8 O Hi-Z, Pull, Drive GPIO30 (PN) I/O Hi-Z, Pull, Drive Hi-Z UART0_TX 9 O 1 McACLK 2 O Hi-Z, Pull, Drive McAFSX 3 O GT_CCP05 4 I GSPI_MISO 7 I/O

54 VIN_IO2 — N/A N/A N/A N/A N/A

GPIO1 (PN) I/O Hi-Z, Pull, Drive Hi-Z UART0_TX 3 O 1 pCLK (PIXCLK) 4 I Hi-Z, Pull, Drive UART1_TX 6 O 1 GT_CCP01 7 I Hi-Z, Pull, Drive

56 VDD_DIG2 — N/A N/A N/A N/A N/A

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-2. Pin Attributes (continued) PIN NO. SIGNAL NAME(1) SIGNAL TYPE(2) PIN MUX ENCODING SIGNAL DIRECTION PAD STATES LPDS(3) Hib(4) nRESET = 0 (12) This pin is shared by the ADC inputs and digital I/O pad cells. 57(12) ADC_CH0 Analog input (up to 1.5 V) or digital I/O N/A (see (7)) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GPIO2 (PN) 0 I/O UART0_RX 3 I UART1_RX 6 I GT_CCP02 7 I 58(12) ADC_CH1 Analog input (up to 1.5 V) or digital I/O N/A (see (7)) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-ZGPIO3 (PN) 0 I/O UART1_TX 6 O 1 pDATA7 (CAM_D3) 4 I Hi-Z, Pull, Drive 59(12) ADC_CH2 Analog input (up to 1.5 V) or digital I/O N/A (see (7)) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-ZGPIO4 (PN) 0 I/O UART1_RX 6 I pDATA6 (CAM_D2) 4 I 60(12) ADC_CH3 Analog input (up to 1.5 V) or digital I/O N/A (see (7)) I Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GPIO5 (PN) 0 I/O pDATA5 (CAM_D1) 4 I McAXR1 6 I/O GT_CCP05 7 I GPIO6 (PN) I/O Hi-Z, Pull, Drive Hi-Z UART0_RTS 5 O 1 pDATA4 (CAM_D0) 4 I Hi-Z, Pull, Drive UART1_CTS 3 I UART0_CTS 6 I GT_CCP06 7 I GPIO7 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z McACLKX 13 O UART1_RTS 3 O 1UART0_RTS 10 O UART0_TX 11 O GPIO8 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z SDCARD_IRQ 6 I McAFSX 7 O GT_CCP06 12 I GPIO9 (PN) I/O Hi-Z, Pull, Drive Hi-Z, Pull, Drive Hi-Z GT_PWM05 3 O SDCARD_DATA0 6 I/O McAXR0 7 I/O GT_CCP00 12 I GND_TAB — N/A N/A N/A N/A N/A

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated NOTE The ADC inputs are tolerant up to 1.8 V (see Table 5-18 for more details about the usable range of the ADC). On the other hand, the digital pads can tolerate up to 3.6 V. Hence, take care to prevent accidental damage to the ADC inputs. TI recommends first disabling the output buffers of the digital I/Os corresponding to the desired ADC channel (that is, converted to Hi-Z state), and thereafter disabling the respective pass switches (S7 [Pin 57], S8 [Pin 58], S9 [Pin 59], and S10 [Pin 60]). For more information about drive strength and reset states for analog-digital multiplexed pins, see Section 4.5.

4.3 Signal Descriptions

Table 4-3. Signal Descriptions FUNCTION SIGNAL NAME PIN NO. PIN TYPE SIGNAL DIRECTION DESCRIPTION ADC ADC_CH0 57 I/O I ADC channel 0 input (maximum of 1.5 V) ADC_CH1 58 I/O I ADC channel 1 input (maximum of 1.5 V) ADC_CH2 59 I/O I ADC channel 2 input (maximum of 1.5 V) ADC_CH3 60 I/O I ADC channel 3 input (maximum of 1.5 V) Antenna selection ANTSEL1 29 O O Antenna selection control 1 ANTSEL2 30 O O Antenna selection control 2 Clock TCX0_EN 21 O O Enable to optional external 40-MHz TCXO WLAN_XTAL_N 22 — — 40-MHz crystal; pull down if external TCXO is used WLAN_XTAL_P 23 — — 40-MHz crystal or TCXO clock input RTC_XTAL_P 51 — — Connect 32.768-kHz crystal or force external CMOS level clock RTC_XTAL_N 52 — — Connect 32.768-kHz crystal or connect 100-kΩ resistor to supply voltage JTAG / SWD TDI 16 I/O I JTAG TDI. Reset default pinout. TDO 17 I/O O JTAG TDO. Reset default pinout. TCK 19 I/O I JTAG/SWD TCK. Reset default pinout. TMS 20 I/O I/O JTAG/SWD TMS. Reset default pinout. I2C I2C_SCL I/O I/O (open drain) I2C clock data I2C_SDA I/O I/O (open drain) I2C data

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. PIN TYPE SIGNAL DIRECTION DESCRIPTION Timers GT_PWM06 1 I/O O Pulse-width modulated O/P GT_CCP01 1 I/O I Timer capture port GT_PWM07 2 I/O O Pulse-width modulated O/P GT_CCP02 2 I/O I Timer capture port GT_CCP03 3 I/O I GT_CCP04

4 I/O I

15 I/O I

GT_CCP05 5 I/O I GT_CCP06

6 I/O I

17 I/O I

61 I/O I

63 I/O I

GT_CCP07 7 I/O I PWM0 17 I/O O Pulse-width modulated outputGT_PWM03 19 I/O O GT_PWM02 21 O O GT_CCP00

50 I/O I

64 I/O I

GT_CCP05 53 I/O I GT_CCP01 55 I/O I GT_CCP02 57 I/O I GT_CCP05 60 I I GT_PWM05 64 I/O O Pulse-width modulated output

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. PIN TYPE SIGNAL DIRECTION DESCRIPTION GPIO GPIO10 1 I/O I/O General-purpose input or output GPIO11 2 I/O I/O GPIO12 3 I/O I/O GPIO13 4 I/O I/O GPIO14 5 I/O I/O GPIO15 6 I/O I/O GPIO16 7 I/O I/O GPIO17 8 I/O I/O GPIO22 15 I/O I/O GPIO23 16 I/O I/O GPIO24 17 I/O I/O GPIO28 18 I/O I/O GPIO29 20 I/O I/O GPIO25 21 O O General-purpose output only GPIO31 45 I/O I/O General-purpose input or output GPIO0 50 I/O I/O GPIO32 52 I/O O General-purpose output only GPIO30 53 I/O I/O General-purpose input or output GPIO1 55 I/O I/O GPIO2 57 I/O I/O GPIO3 58 I/O I/O GPIO4 59 I/O I/O GPIO5 60 I/O I/O GPIO6 61 I/O I/O GPIO7 62 I/O I/O GPIO8 63 I/O I/O GPIO9 64 I/O I/O McASP I2S or PCM McAFSX I/O O I2S audio port frame sync McACLK

3 I/O O

I2S audio port clock output52 O O

53 I/O O

50 I/O I/O

I2S audio port data 1 (RX and TX)

60 I I/O

45 I/O I/O

I2S audio port data 0 (RX and TX)

52 O O I2S audio port data (only output mode is supported on

pin 52)

64 I/O I/O I2S audio port data (RX and TX)

McACLKX 62 I/O O I2S audio port clock

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. PIN TYPE SIGNAL DIRECTION DESCRIPTION Multimedia card (MMC or SD) SDCARD_CLK I/O O SD card clock data SDCARD_CMD

2 I/O I/O (open drain)

8 I/O I/O

SDCARD_DATA0 I/O I/O SD card data SDCARD_IRQ 63 I/O I Interrupt from SD card (future support) Parallel interface (8-bit π) pXCLK (XVCLK) 2 I/O O Free clock to parallel camera pVS (VSYNC) 3 I/O I Parallel camera vertical sync pHS (HSYNC) 4 I/O I Parallel camera horizontal sync pDATA8 (CAM_D4) 5 I/O I Parallel camera data bit 4 pDATA9 (CAM_D5) 6 I/O I Parallel camera data bit 5 pDATA10 (CAM_D6) 7 I/O I Parallel camera data bit 6 pDATA11 (CAM_D7) 8 I/O I Parallel camera data bit 7 pCLK (PIXCLK) 55 I/O I Pixel clock from parallel camera sensor pDATA7 (CAM_D3) 58 I/O I Parallel camera data bit 3 pDATA6 (CAM_D2) 59 I/O I Parallel camera data bit 2 pDATA5 (CAM_D1) 60 I I Parallel camera data bit 1 pDATA4 (CAM_D0) 61 I/O I Parallel camera data bit 0 Power VDD_DIG1 9 — — Internal digital core voltage VIN_IO1 10 — — Device supply voltage (VBAT) VDD_PLL 24 — — Internal analog voltage LDO_IN2 25 — — Internal analog RF supply from analog DC/DC output VDD_PA_IN 33 — — Internal PA supply voltage from PA DC/DC output LDO_IN1 36 — — Internal analog RF supply from analog DC/DC output VIN_DCDC_ANA 37 — — Analog DC/DC input (connected to device input supply [VBAT]) DCDC_ANA_SW 38 — — Internal analog DC/DC switching node VIN_DCDC_PA 39 — — PA DC/DC input (connected to device input supply [VBAT]) Internal PA DC/DC switching node DCDC_PA_OUT 42 — — Internal PA buck converter output DCDC_DIG_SW 43 — — Internal digital DC/DC switching node VIN_DCDC_DIG 44 — — Digital DC/DC input (connected to device input supply [VBAT]) DCDC_ANA2_SW_P 45 — — Analog to DC/DC converter +ve switching node DCDC_ANA2_SW_N 46 — — Internal analog to DC/DC converter –ve switching node VDD_ANA2 47 — — Internal analog to DC/DC output VDD_ANA1 48 — — Internal analog supply fed by ANA2 DC/DC output VDD_RAM 49 — — Internal SRAM LDO output VIN_IO2 54 — — Device supply voltage (VBAT) VDD_DIG2 56 — — Internal digital core voltage

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated Table 4-3. Signal Descriptions (continued) FUNCTION SIGNAL NAME PIN NO. PIN TYPE SIGNAL DIRECTION DESCRIPTION (1) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. SPI GSPI_CLK

5 I/O I/O

GSPI_MISO

6 I/O I/O

53 I/O I/O

GSPI_CS GSPI_MOSI

7 I/O I/O

52 O O

FLASH_SPI_CLK 11 O O Clock to SPI serial flash (fixed default) FLASH_SPI_DOUT 12 O O Data to SPI serial flash (fixed default) FLASH_SPI_DIN 13 I I Data from SPI serial flash (fixed default) FLASH_SPI_CS 14 O O Device select to SPI serial flash (fixed default) UART UART1_TX

1 I/O O

7 I/O O

16 I/O O

55 I/O O

58 I/O O

UART1_RX

2 I/O I

8 I/O I

45 I/O I

57 I/O I

59 I/O I

UART1_RTS

50 I/O O

UART1 request-to-send (active low)

62 I/O O

UART1_CTS 61 I/O I UART1 clear-to-send (active low) UART0_TX UART0_RX UART0_CTS UART0 clear-to-send input (active low) UART0_RTS UART0 request-to-send (active low)

61 I/O O

SOP2 21(1) O I Sense-on-power 2 SOP1 34 — — Configuration sense-on-power 1 SOP0 35 — — Configuration sense-on-power 0 Reset nRESET 32 — — Global master device reset (active low) RF RF_BG 31 — — WLAN analog RF 802.11 b/g bands

Copyright © 2016–2018, Texas Instruments IncorporatedTerminal Configuration and Functions Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com

4.4 Pin Multiplexing

(1) Pin mux encodings with (RD) denote the default encoding after reset release. (2) This pin has dual functions: as a SOP[2] (device operation mode), and as an external TCXO enable. As a TXCO enable, the pin is an output on power up and driven logic high. During hibernate low-power mode, the pin is in a Hi-Z state but is pulled down for SOP mode to disable TCXO. Because of the SOP functionality, the pin must be used as an output only. (3) LPDS state: Unused I/Os are in a Hi-Z state. Software may program the I/Os to be input with pull or drive (regardless of active pin configuration), according to the need. Table 4-4. Pin Multiplexing REGISTER ADDRESS REGISTER NAME PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (XXX FIELD ENCODING)(1) JTAG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0x4402 E0C8 GPIO_PAD_CONFIG_10 1 — GPIO10 I2C_SCL — GT_PWM06 — — SDCARD_ 0x4402 E0CC GPIO_PAD_CONFIG_11 2 — GPIO11 I2C_SDA — GT_PWM07 pXCLK (XVCLK) — SDCARD_ CMD UART1_RX — — — — GT_CCP02 MCAFSX 0x4402 E0D0 GPIO_PAD_CONFIG_12 3 — GPIO12 — — McACLK pVS (VSYNC) I2C_SCL — UART0_TX — — — — GT_CCP03 — 0x4402 E0D4 GPIO_PAD_CONFIG_13 4 — GPIO13 — — — pHS (HSYNC) I2C_SDA — UART0_RX — — — — GT_CCP04 — 0x4402 E0D8 GPIO_PAD_CONFIG_14 5 — GPIO14 — — — pDATA8 0x4402 E0DC GPIO_PAD_CONFIG_15 6 — GPIO15 — — — pDATA9 (CAM_D5) I2C_SDA — GSPI_ MISO SDCARD_ 0x4402 E0E0 GPIO_PAD_CONFIG_16 7 — GPIO16 — — — pDATA10 (CAM_D6) UART1_TX — GSPI_ MOSI SDCARD_ 0x4402 E0E4 GPIO_PAD_CONFIG_17 8 — GPIO17 — — — pDATA11 (CAM_D7) UART1_RX — GSPI_CS SDCARD_ 0x4402 0x4402 E0FC GPIO_PAD_CONFIG_23 16 Muxed with 0x4402 E100 GPIO_PAD_CONFIG_24 17 Muxed with JTAG TDO GPIO24 TDO UART1_RX — GT_CCP06 PWM0 McAFSX — — I2C_SDA — — — — 0x4402 0x4402 E110 GPIO_PAD_CONFIG_28 19 Muxed with JTAG or SWD and TCK 0x4402 E114 GPIO_PAD_CONFIG_29 20 Muxed with JTAG or SWD and TMSC 0x4402 E104 GPIO_PAD_CONFIG_25 21(2) — GPIO25 — McAFSX — — — — — — GT_ PWM02 — — — — 0x4402 0x4402

Copyright © 2016–2018, Texas Instruments Incorporated Terminal Configuration and Functions Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Table 4-4. Pin Multiplexing (continued) REGISTER ADDRESS REGISTER NAME PIN ANALOG OR SPECIAL FUNCTION DIGITAL FUNCTION (XXX FIELD ENCODING)(1) JTAG 0 1 2 3 4 5 6 7 8 9 10 11 12 13 0x4402 E11C GPIO_PAD_CONFIG_31 45 — GPIO31 — UART1_RX — — — McAXR0 GSPI_CLK — UART0_RX — — McAFSX — 0x4402 E0A0 GPIO_PAD_CONFIG_0 50 — GPIO0 — — UART0_ RTS McAXR0 — McAXR1 GT_CCP00 — GSPI_CS UART1_ RTS — UART0_ CTS — 0x4402 E120 GPIO_PAD_CONFIG_32 52 — GPIO32 — McACLK — McAXR0 — UART0 _ RTS — GSPI_ 0x4402 E118 GPIO_PAD_CONFIG_30 53 -— GPIO30 — McACLK McAFSX GT_CCP05 — — GSPI_ 0x4402 E0A4 GPIO_PAD_CONFIG_1 55 — GPIO1 — — UART0_TX pCLK 0x4402 0x4402 E0AC GPIO_PAD_CONFIG_3 58 — GPIO3 — — — pDATA7 0x4402 E0B0 GPIO_PAD_CONFIG_4 59 — GPIO4 — — — pDATA6 0x4402 E0B4 GPIO_PAD_CONFIG_5 60 — GPIO5 — — — pDATA5 0x4402 E0B8 GPIO_PAD_CONFIG_6 61 — GPIO6 — — UART1_ CTS pDATA4 (CAM_D0) UART0_ RTS UART0_ 0x4402 E0BC GPIO_PAD_CONFIG_7 62 — GPIO7 — — UART1_ RTS UART0_TX — McACLKX 0x4402 E0C0 GPIO_PAD_CONFIG_8 63 — GPIO8 — — — — — SDCARD_ 0x4402 E0C4 GPIO_PAD_CONFIG_9 64 -— GPIO9 — — GT_PWM05 — — SDCARD_ DATA0 McAXR0 — — — — GT_CCP00 —

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and Functions Copyright © 2016–2018, Texas Instruments Incorporated

4.5 Drive Strength and Reset States for Analog and Digital Multiplexed Pins

Table 4-5 describes the use, drive strength, and default state of analog and digital multiplexed pins at first- time power up and reset (nRESET pulled low). Table 4-5. Drive Strength and Reset States for Analog and Digital Multiplexed Pins Pin BOARD-LEVEL CONFIGURATION AND USE DEFAULT STATE AT FIRST POWER UP OR FORCED RESET STATE AFTER CONFIGURATION OF ANALOG SWITCHES (ACTIVE, LPDS, AND HIB POWER MODES) MAXIMUM EFFECTIVE DRIVE STRENGTH (mA) Connected to the enable pin of the RF switch (ANTSEL1). Other use is not recommended. Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 Connected to the enable pin of the RF switch (ANTSEL2). Other use is not recommended. Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 VDD_ANA2 (pin 47) must be shorted to the input supply rail. Otherwise, the pin is driven by the ANA2 DC/DC. Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 50 Generic I/O Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 The pin must have an external pullup of 100 kΩ to the supply rail and must be used in output signals only. Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 53 Generic I/O Analog is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 57 Analog signal (1.8-V absolute, 1.46-V full scale) ADC is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 58 Analog signal (1.8-V absolute, 1.46-V full scale) ADC is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 59 Analog signal (1.8-V absolute, 1.46-V full scale) ADC is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4 60 Analog signal (1.8-V absolute, 1.46-V full scale) ADC is isolated. The digital I/O cell is also isolated. Determined by the I/O state, as are other digital I/Os. 4

4.6 Pad State After Application of Power to Chip But Before Reset Release

When a stable power is applied to the CC3220x chip for the first time or when supply voltage is restored to the proper value following a period with supply voltage less than 1.5 V, the level of each digital pad is undefined in the period starting from the release of nRESET and until DIG_DCDC powers up. This period is less than approximately 10 ms. During this period, pads can be internally pulled weakly in either direction. If a certain set of pins is required to have a definite value during this prereset period, an appropriate pullup or pulldown resistor must be used at the board level. The recommended value of this external pull is 2.7 kΩ.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Terminal Configuration and FunctionsCopyright © 2016–2018, Texas Instruments Incorporated

4.7 Connections for Unused Pins

All unused pins must be left as no connect (NC) pins. Table 4-6 provides a list of NC pins. Table 4-6. Connections for Unused Pins PIN DEFAULT FUNCTION STATE AT RESET AND HIBERNATE I/O TYPE DESCRIPTION 26 NC WLAN analog — Unused; leave unconnected. 27 NC WLAN analog — Unused; leave unconnected. 28 NC WLAN analog — Unused; leave unconnected.

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to VSS, unless otherwise noted.

5 Specifications

All measurements are referenced at the device pins, unless otherwise indicated. All specifications are over process and voltage, unless otherwise indicated.

5.1 Absolute Maximum Ratings

All measurements are referenced at the device pins unless otherwise indicated. All specifications are over process, voltage, and operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT VBAT and VIO Pins: 37, 39, 44 –0.5 3.8 V VIO – VBAT (differential) Pins: 10, 54 VBAT and VIO should be tied together V Digital inputs –0.5 VIO + 0.5 V RF pins –0.5 2.1 V Analog pins, crystal Pins: 22, 23, 51, 52 –0.5 2.1 V Operating temperature, TA –40 85 °C Storage temperature, Tstg –55 125 °C (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.2 ESD Ratings

VESD Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±500 (1) The TX duty cycle (power amplifier ON time) is assumed to be 10% of the device POH. Of the remaining 90% of the time, the device can be in any other state.

5.3 Power-On Hours (POH)

This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products. OPERATING CONDITION POWER-ON HOURS [POH] (hours) TA up to 85°C(1) 87,600

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated (1) Operating temperature is limited by crystal frequency variation. (2) When operating at an ambient temperature of over 75°C, the transmit duty cycle must remain below 50% to avoid the auto-protect feature of the power amplifier. If the auto-protect feature triggers, the device takes a maximum of 60 seconds to restart the transmission. (3) To ensure WLAN performance, ripple on the supply must be less than ±300 mV. (4) The minimum voltage specified includes the ripple on the supply voltage and all other transient dips. The brownout condition is also 2.1 V, and care must be taken when operating at the minimum specified voltage. (5) To ensure WLAN performance, ripple on the 1.85-V supply must be less than 2% (±40 mV). (6) TI recommends keeping VBAT above 1.85 V. For lower voltages, use a boost converter.

5.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN TYP MAX UNIT VBAT, VIO (shorted to VBAT) Pins: 10, 37, 39, 44, 54 Direct battery connection(3) 2.1(4) 3.3 3.6 V Preregulated 1.85 V(5)(6) Ambient thermal slew –20 20 °C/minute (1) TX power level = 0 implies maximum power (see Figure 5-1, Figure 5-2, and Figure 5-3). TX power level = 4 implies output power backed off approximately 4 dB. (2) The CC3220x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied. (3) DTIM = 1

5.5 Current Consumption Summary (CC3220R, CC3220S)

TA = 25°C, VBAT = 3.6 V PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT MCU ACTIVE NWP ACTIVE TX

1 DSSS

TX power level = 0 272 mA TX power level = 4 190

6 OFDM

TX power level = 0 248 TX power level = 4 182

54 OFDM

TX power level = 0 223 TX power level = 4 160 RX

1 DSSS 59

54 OFDM 59

NWP idle connected(3) 15.3 MCU SLEEP NWP ACTIVE TX TX power level = 0 269 mA TX power level = 4 187 TX power level = 0 245 TX power level = 4 179 TX power level = 0 220 TX power level = 4 157 RX

1 DSSS 56

54 OFDM 56

NWP idle connected(3) 12.2

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated Current Consumption Summary (CC3220R, CC3220S) (continued) TA = 25°C, VBAT = 3.6 V PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT (4) LPDS current does not include the external serial Flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA. (5) The complete calibration can take up to 17 mJ of energy from the battery over a time of 24 ms. In default mode, calibration is performed sparingly, and typically occurs when re-enabling the NWP and when the temperature has changed by more than 20°C. There are two additional calibration modes that may be used to reduced or completely eliminate the calibration event. For further details, see CC3120, CC3220 SimpleLink™ Wi-Fi® and IoT Network Processor Programmer's Guide. MCU LPDS NWP ACTIVE TX TX power level = 0 266 mA TX power level = 4 184 TX power level = 0 242 TX power level = 4 176 TX power level = 0 217 TX power level = 4 154 RX

1 DSSS 53

54 OFDM 53

NWP LPDS(4) 120 µA at 64KB 135 µA at 256KB 135 µA NWP idle connected(3) 710 µA MCU SHUTDOWN MCU shutdown 1 µA MCU HIBERNATE MCU hibernate 4.5 µA Peak calibration current(5) VBAT = 3.6 V 420 mA VBAT = 3.3 V 450 VBAT = 2.1 V 670 VBAT = 1.85 V 700

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated (1) TX power level = 0 implies maximum power (see Figure 5-1, Figure 5-2, and Figure 5-3). TX power level = 4 implies output power backed off approximately 4 dB. (2) The CC3220x system is a constant power-source system. The active current numbers scale based on the VBAT voltage supplied. (3) DTIM = 1 (4) LPDS current does not include the external serial flash. The LPDS number of reported is with retention of 256KB of MCU SRAM. The CC3220x device can be configured to retain 0KB, 64KB, 128KB, 192KB, or 256KB of SRAM in LPDS. Each 64-KB block of MCU retained SRAM increases LPDS current by 4 µA. (5) The complete calibration can take up to 17 mJ of energy from the battery over a period of 24 ms. Calibration is performed sparingly, typically when coming out of HIBERNATE and only if temperature has changed by more than 20°C. The calibration event can be controlled by a configuration file in the serial Flash..

5.6 Current Consumption Summary (CC3220SF)

TA = 25°C, VBAT = 3.6 V PARAMETER TEST CONDITIONS(1) (2) MIN TYP MAX UNIT MCU ACTIVE NWP ACTIVE TX TX power level = maximum 286 mA TX power level = maximum – 4 202 TX power level = maximum 255 TX power level = maximum – 4 192 TX power level = maximum 232 TX power level = maximum – 4 174 RX

1 DSSS 74

54 OFDM 74

NWP idle connected(3) 25.2 MCU SLEEP NWP ACTIVE TX TX power level = maximum 282 mA TX power level = maximum – 4 198 TX power level = maximum 251 TX power level = maximum – 4 188 TX power level = maximum 228 TX power level = maximum – 4 170 RX

1 DSSS 70

54 OFDM 70

NWP idle connected(3) 21.2 MCU LPDS NWP active TX TX power level = 0 266 mA TX power level = 4 184 TX power level = 0 242 TX power level = 4 176 TX power level = 0 217 TX power level = 4 154 RX NWP LPDS(4) 120 µA at 64KB 135 µA at 256KB 135 µA NWP idle connected(3) 710 MCU SHUTDOWN MCU shutdown 1 MCU HIBERNATE MCU hibernate 4.5 Peak calibration current(5) VBAT = 3.6 V 420 mA VBAT = 3.3 V 450 VBAT = 2.1 V 670 VBAT = 1.85 V 700

TX Power (dBm) 19.00 17.00 15.00 13.00 11.00 9.00 7.00 5.00 3.00 1.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IBAT (VBAT @ 3.6 V)(mAmp) 280.00 264.40 249.00 233.30 218.00 202.00 186.70 171.00 155.60 140.00 TX Power (dBm) IBAT (VBAT @ 3.6 V) TX power level setting TX Power (dBm) 19.00 17.00 15.00 13.00 11.00 9.00 7.00 5.00 3.00 1.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 280.00 264.40 249.00 233.30 218.00 202.00 186.70 171.00 155.60 140.00 IBAT (VBAT @ 3.6 V)(mAmp) Color by TX Power (dBm) IBAT (VBAT @ 3.6 V) CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.7 TX Power and IBAT versus TX Power Level Settings

Figure 5-1, Figure 5-2, and Figure 5-3 show TX Power and IBAT versus TX power level settings for the CC3220R and CC3220S devices at modulations of 1 DSSS, 6 OFDM, and 54 OFDM, respectively. For the CC3220SF device, the IBAT current has an increase of approximately 10 mA to 15 mA depending on the transmitted rate. The TX power level will remain the same. In Figure 5-1, the area enclosed in the circle represents a significant reduction in current during transition from TX power level 3 to level 4. In the case of lower range requirements (14-dBm output power), TI recommends using TX power level 4 to reduce the current. Figure 5-1. TX Power and IBAT vs TX Power Level Settings (1 DSSS) Figure 5-2. TX Power and IBAT vs TX Power Level Settings (6 OFDM)

TX Power (dBm) 19.00 17.00 15.00 13.00 11.00 9.00 7.00 5.00 3.00 1.00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 280.00 264.40 249.00 233.30 218.00 202.00 186.70 171.00 155.60 140.00 IBAT (VBAT @ 3.6 V)(mAmp) Color by TX Power (dBm) IBAT (VBAT @ 3.6 V) CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated Figure 5-3. TX Power and IBAT vs TX Power Level Settings (54 OFDM)

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.8 Brownout and Blackout Conditions

The device enters a brownout condition when the input voltage drops below Vbrownout (see Figure 5-4 and Figure 5-5). This condition must be considered during design of the power supply routing, especially when operating from a battery. High-current operations, such as a TX packet or any external activity (not necessarily related directly to networking) can cause a drop in the supply voltage, potentially triggering a brownout condition. The resistance includes the internal resistance of the battery, the contact resistance of the battery holder (four contacts for 2× AA batteries), and the wiring and PCB routing resistance. NOTE When the device is in HIBERNATE state, brownout is not detected. Only blackout is in effect during HIBERNATE state. Figure 5-4. Brownout and Blackout Levels (1 of 2) Figure 5-5. Brownout and Blackout Levels (2 of 2)

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated In the brownout condition, all sections of the device (including the 32-kHz RTC) shut down except for the Hibernate module, which remains on. The current in this state can reach approximately 400 µA. The blackout condition is equivalent to a hardware reset event in which all states within the device are lost. Table 5-1 lists the brownout and blackout voltage levels. Table 5-1. Brownout and Blackout Voltage Levels CONDITION VOLTAGE LEVEL UNIT Vbrownout 2.1 V Vblackout 1.67 V (1) TI recommends using the lowest possible drive strength that is adequate for the applications. This recommendation minimizes the risk of interference to the WLAN radio and reduces any potential degradation of RF sensitivity and performance. The default drive strength setting is 6 mA. 5.9 Electrical Characteristics (3.3 V, 25°C) GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT CIN Pin capacitance 4 pF VIH High-level input voltage 0.65 × VDD VDD + 0.5 V V VIL Low-level input voltage –0.5 0.35 × VDD V IIH High-level input current 5 nA IIL Low-level input current 5 nA VOH High-level output voltage IL = 2 mA; configured I/O drive strength = 2 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.8 V IL = 4 mA; configured I/O drive strength = 4 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.7 IL = 6 mA; configured I/O drive strength = 6 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.7 IL = 2 mA; configured I/O drive strength = 2 mA; 2.1 V ≤ VDD < 2.4 V VDD × 0.75 IL = 2 mA; configured I/O drive strength = 2 mA; VDD = 1.85 V VDD × 0.7 VOL Low-level output voltage IL = 2 mA; configured I/O drive strength = 2 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 V IL = 4 mA; configured I/O drive strength = 4 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 IL = 6 mA; configured I/O drive strength = 6 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 IL = 2 mA; configured I/O drive strength = 2 mA; 2.1 V ≤ VDD < 2.4 V VDD × 0.25 IL = 2 mA; configured I/O drive strength = 2 mA; VDD = 1.85 V VDD × 0.35 IOH High-level source current 2-mA drive 2 mA4-mA drive 4 6-mA drive 6

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated Electrical Characteristics (3.3 V, 25°C) (continued) GPIO Pins Except 29, 30, 50, 52, and 53 (25°C)(1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT (2) The nRESET pin must be held below 0.6 V for the device to register a reset. IOL Low-level sink current 2-mA drive 2 mA4-mA drive 4 6-mA drive 6 GPIO Pins 29, 30, 50, 52, and 53 (25°C)(1) CIN Pin capacitance 7 pF VIH High-level input voltage 0.65 × VDD VDD + 0.5 V V VIL Low-level input voltage –0.5 0.35 × VDD V IIH High-level input current 50 nA IIL Low-level input current 50 nA VOH High-level output voltage IL = 2 mA; configured I/O drive strength = 2 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.8 V IL = 4 mA; configured I/O drive strength = 4 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.7 IL = 6 mA; configured I/O drive strength = 6 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.7 IL = 2 mA; configured I/O drive strength = 2 mA; 2.1 V ≤ VDD < 2.4 V VDD × 0.75 IL = 2 mA; configured I/O drive strength = 2 mA; VDD = 1.85 V VDD × 0.7 VOL Low-level output voltage IL = 2 mA; configured I/O drive strength = 2 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 V IL = 4 mA; configured I/O drive strength = 4 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 IL = 6 mA; configured I/O drive strength = 6 mA; 2.4 V ≤ VDD < 3.6 V VDD × 0.2 IL = 2 mA; configured I/O drive strength = 2 mA; 2.1 V ≤ VDD < 2.4 V VDD × 0.25 IL = 2 mA; configured I/O drive strength = 2 mA; VDD = 1.85 V VDD × 0.35 IOH High-level source current, VOH = 2.4 2-mA drive 1.5 mA4-mA drive 2.5 6-mA drive 3.5 IOL Low-level sink current 2-mA drive 1.5 mA4-mA drive 2.5 6-mA drive 3.5 VIL nRESET(2) 0.6 V Pin Internal Pullup and Pulldown (25°C)(1) IOH Pullup current, VOH = 2.4 (VDD = 3.0 V) 5 10 µA IOL Pulldown current, VOL = 0.4 (VDD = 3.0 V) 5 µA

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated (1) In preregulated 1.85-V mode, RX sensitivity is 0.25- to 1-dB lower. (2) Sensitivity is 1-dB worse on channel 13 (2472 MHz). (3) Sensitivity for mixed mode is 1-dB worse.

5.10 WLAN Receiver Characteristics

TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters are measured at the SoC pin on channel 6 (2437 MHz). PARAMETER TEST CONDITIONS (Mbps) MIN TYP(1) MAX UNIT Sensitivity (8% PER for 11b rates, 10% PER for 11g/11n rates) (10% PER)(2) 1 DSSS –96.0 dBm 2 DSSS –94.0 11 CCK –88.0 6 OFDM –90.5 9 OFDM –90.0 18 OFDM –86.5 36 OFDM –80.5 54 OFDM –74.5 MCS7 (GF)(3) –71.5 MCS7 (MM)(3) –70.5 Maximum input level (10% PER) 802.11b –4.0 dBm 802.11g –10.0 (1) The edge channels (2412 and 2472 MHz) have reduced TX power to meet FCC emission limits. (2) Power of 802.11b rates are reduced to meet ETSI requirements. (3) In preregulated 1.85-V mode, maximum TX power is 0.25- to 0.75-dB lower for modulations higher than 18 OFDM.

5.11 WLAN Transmitter Characteristics

TA = 25°C, VBAT = 2.1 V to 3.6 V. Parameters measured at SoC pin on channel 6 (2437 MHz).(1)(2)(3) PARAMETER TEST CONDITIONS(3) MIN TYP MAX UNIT Maximum RMS output power measured at 1 dB from IEEE spectral mask or EVM 1 DSSS 18.0 dBm 2 DSSS 18.0 11 CCK 18.3 6 OFDM 17.3 9 OFDM 17.3 18 OFDM 17.0 36 OFDM 16.0 54 OFDM 14.5 MCS7 (MM) 13.0 Transmit center frequency accuracy –25 25 ppm

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.12 WLAN Filter Requirements

The device requires an external band-pass filter to meet the various emission standards, including FCC. Table 5-2 presents the attenuation requirements for the band-pass filter. TI recommends using the same filter used in the reference design to ease the process of certification. (1) Insertion loss directly impacts output power and sensitivity. At customer discretion, insertion loss can be relaxed to meet attenuation requirements. Table 5-2. WLAN Filter Requirements PARAMETER FREQUENCY (MHz) MIN TYP MAX UNIT Return loss 2412 to 2484 10 dB Insertion loss(1) 2412 to 2484 1 1.5 dB Attenuation 800 to 830 30 45 dB 1600 to 1670 20 25 3200 to 3300 30 48 4000 to 4150 45 50 4800 to 5000 20 25 5600 to 5800 20 25 6400 to 6600 20 35 7200 to 7500 35 45 7500 to 10000 20 25 Reference impendence 2412 to 2484 50 Ω Filter type Bandpass

5.13 Thermal Resistance Characteristics

5.14 Thermal Resistance Characteristics for RGK Package

PARAMETER 0 lfm (C/W) 150 lfm (C/W) 250 lfm (C/W) 500 lfm (C/W) θja 23 14.6 12.4 10.8 Ψjt 0.2 0.2 0.3 0.1 Ψjb 2.3 2.3 2.2 2.4 θjc 6.3 θjb 2.4

5.15 Timing and Switching Characteristics

5.15.1 Power Supply Sequencing

For proper operation of the CC3220x device, perform the recommended power-up sequencing as follows: 1. Tie VBAT (pins 37, 39, 44) and VIO (pins 54 and 10) together on the board. 2. Hold the RESET pin low while the supplies are ramping up. TI recommends using a simple RC circuit 3. For an external RTC, ensure that the clock is stable before RESET is deasserted (high). For timing diagrams, see Section 5.15.3.

OFF HW INIT FW INIT APP CODE EXECUTION VBAT VIO nRESET STATE T1 T2 T3 RESET 32-kHz RTC CLK APP CODE LOAD CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated

5.15.2 Device Reset

When a device restart is required, the user may issue a negative pulse to the nRESET pin. The user must follow one of the two alternatives to ensure the reset is properly applied:

• A negative reset pulse (on pin 32) of at least 200-ms duration
• If the above cannot be guaranteed, a pull-down resistor of 2 MΩ should be connected to pin 52 (RTC_XTAL_N). If implemented, a shorter pulse of at least 100 µs can be used. To ensure a proper reset sequence, the user has to call the sl_stop function prior to toggling the reset. It is preferable to use software reset instead of an external trigger when a reset is required.

5.15.3 Reset Timing

5.15.3.1 nRESET (32-kHz Crystal) Figure 5-6 shows the reset timing diagram for the 32-kHz crystal first-time power-up and reset removal. NOTE: T1 should be ≥200 ms without a pulldown resistor on the XTAL_N pin or T1 should be ≥100 µs if there is 2-MΩ pulldown resistor on the XTAL_N pin. Figure 5-6. First-Time Power-Up and Reset Removal Timing Diagram (32-kHz Crystal) Table 5-3 describes the timing requirements for the 32-kHz clock crystal first-time power-up and reset removal. Table 5-3. First-Time Power-Up and Reset Removal Timing Requirements (32-kHz Crystal) ITEM NAME DESCRIPTION MIN TYP MAX UNIT T1 Supply settling time Depends on application board power supply, decoupling capacitor, and so on 3 ms T2 Hardware wake-up time 25 ms Time taken by ROM firmware to initialize hardware Includes 32.768-kHz XOSC settling time 1.1 s App code load time for CC3220R and CC3220S CC3220R Image size (KB) × 0.75 ms CC3220S Image size (KB) × 1.7 ms App code integrity check time for CC3220SF CC3220SF Image size (KB) × 0.06 ms

ACTIVE HIBERNA TE HW WAKEUP FW INIT APP CODE LOAD EXECUTION VBA T VIO nRESET ST A TE 32-kHz RTC CLK THIB_MIN T2 T3 T4 Application software requests entry to HIBERNA TE mode CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated

5.15.4 Wakeup From HIBERNATE Mode

Figure 5-8 shows the timing diagram for wakeup from HIBERNATE mode. Figure 5-8. Wakeup From HIBERNATE Timing Diagram NOTE The 32.768-kHz crystal is kept enabled by default when the chip goes into HIBERNATE mode.

5.15.5 Clock Specifications

The CC3220x device requires two separate clocks for its operation:

• A slow clock running at 32.768 kHz is used for the RTC.
• A fast clock running at 40 MHz is used by the device for the internal processor and the WLAN subsystem. The device features internal oscillators that enable the use of less-expensive crystals rather than dedicated TCXOs for these clocks. The RTC can also be fed externally to provide reuse of an existing clock on the system and to reduce overall cost.

5.15.5.1 Slow Clock Using Internal Oscillator

The RTC crystal connected on the device supplies the free-running slow clock. The accuracy of the slow clock frequency must be 32.768 kHz ±150 ppm. In this mode of operation, the crystal is tied between RTC_XTAL_P (pin 51) and RTC_XTAL_N (pin 52) with a suitable load capacitance to meet the ppm requirement.

RTC_XTAL_P RTC_XTAL_N Host system 32.768 kHz VIO 100 KΩ Copyright © 2017, Texas Instruments Incorporated RTC_XTAL_P RTC_XTAL_N 32.768 kHz 10 pF GND GND 10 pF Copyright © 2017, Texas Instruments Incorporated CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated Figure 5-9 shows the crystal connections for the slow clock. Figure 5-9. RTC Crystal Connections Table 5-5 lists the RTC crystal requirements. Table 5-5. RTC Crystal Requirements CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT Frequency 32.768 kHz Frequency accuracy Initial plus temperature plus aging ±150 ppm Crystal ESR 32.768 kHz 70 kΩ

5.15.5.2 Slow Clock Using an External Clock

When an RTC oscillator is present in the system, the CC3220x device can accept this clock directly as an input. The clock is fed on the RTC_XTAL_P line, and the RTC_XTAL_N line is held to VIO. The clock must be a CMOS-level clock compatible with VIO fed to the device. Figure 5-10 shows the external RTC input connection. Figure 5-10. External RTC Input

WLAN_XTAL_P WLAN_XTAL_N

40 MHz

6.2 pF 6.2 pF SWAS031-030 CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated Table 5-6 lists the external RTC digital clock requirements. Table 5-6. External RTC Digital Clock Requirements CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT Frequency 32768 Hz Frequency accuracy (Initial plus temperature plus aging) ±150 ppm tr, tf Input transition time tr, tf (10% to 90%) 100 ns Frequency input duty cycle 20% 50% 80% Vih Slow clock input voltage limits Square wave, DC coupled 0.65 × VIO VIO V Vil 0 0.35 × VIO Vpeak Input impedance 1 MΩ 5 pF

5.15.5.3 Fast Clock (Fref) Using an External Crystal

The CC3220x device also incorporates an internal crystal oscillator to support a crystal-based fast clock. The crystal is fed directly between WLAN_XTAL_P (pin 23) and WLAN_XTAL_N (pin 22) with suitable loading capacitors. Figure 5-11 shows the crystal connections for the fast clock. NOTE: The crystal capacitance must be tuned to ensure that the PPM requirement is met. See CC31xx & CC32xx Frequency Tuning for information on frequency tuning. Figure 5-11. Fast Clock Crystal Connections Table 5-7 lists the WLAN fast-clock crystal requirements. Table 5-7. WLAN Fast-Clock Crystal Requirements CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT Frequency 40 MHz Frequency accuracy Initial plus temperature plus aging ±25 ppm Crystal ESR 40 MHz 60 Ω

WLAN_XTAL_P WLAN_XTAL_N XO (40 MHz) 82 pF TCXO_EN EN OUT Vcc CC3220x Copyright © 2017, Texas Instruments Incorporated CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.15.5.4 Fast Clock (Fref) Using an External Oscillator

The CC3220x device can accept an external TCXO/XO for the 40-MHz clock. In this mode of operation, the clock is connected to WLAN_XTAL_P (pin 23). WLAN_XTAL_N (pin 22) is connected to GND. The external TCXO/XO can be enabled by TCXO_EN (pin 21) from the device to optimize the power consumption of the system. If the TCXO does not have an enable input, an external LDO with an enable function can be used. Using the LDO improves noise on the TCXO power supply. Figure 5-12 shows the connection. Figure 5-12. External TCXO Input Table 5-8 lists the external Fref clock requirements. Table 5-8. External Fref Clock Requirements (–40°C to +85°C) CHARACTERISTICS TEST CONDITIONS MIN TYP MAX UNIT Frequency 40.00 MHz Frequency accuracy (Initial plus temperature plus aging) ±25 ppm Frequency input duty cycle 45% 50% 55% Vpp Clock voltage limits Sine or clipped sine wave, AC coupled 0.7 1.2 Vpp Phase noise at 40 MHz at 1 kHz –125 dBc/Hzat 10 kHz –138.5 at 100 kHz –143 Input impedance Resistance 12 kΩ Capacitance 7 pF

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated

5.15.6 Peripherals Timing

This section describes the peripherals that are supported by the CC3220x device:

• SPI
• I2S
• GPIOs
• I2C
• IEEE 1149.1 JTAG
• ADC
• Camera parallel port
• UART
• SD Host
• Timers

5.15.6.1 SPI

5.15.6.1.1 SPI Master

The CC3220x microcontroller includes one SPI module, which can be configured as a master or slave device. The SPI includes a serial clock with programmable frequency, polarity, and phase; a programmable timing control between chip select and external clock generation; and a programmable delay before the first SPI word is transmitted. Slave mode does not include a dead cycle between two successive words. Figure 5-13 shows the timing diagram for the SPI master. Figure 5-13. SPI Master Timing Diagram Table 5-9 lists the timing parameters for the SPI master. (1) Timing parameter assumes a maximum load of 20 pF. Table 5-9. SPI Master Timing Parameters PARAMETER NUMBER MIN MAX UNIT F(1) Clock frequency 20 MHz T2 Tclk (1) Clock period 50 ns D(1) Duty cycle 45% 55% T6 tIS(1) RX data setup time 1 ns T7 tIH(1) RX data hold time 2 ns T8 tOD(1) TX data output delay 8.5 ns T9 tOH(1) TX data hold time 8 ns

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.15.6.1.2 SPI Slave

Figure 5-14 shows the timing diagram for the SPI slave. Figure 5-14. SPI Slave Timing Diagram Table 5-10 lists the timing parameters for the SPI slave. (1) Timing parameter assumes a maximum load of 20 pF at 3.3 V. Table 5-10. SPI Slave Timing Parameters PARAMETER NUMBER MIN MAX UNIT F(1) Clock frequency at VBAT = 3.3 V 20 MHz Clock frequency at VBAT ≤ 2.1 V 12 T2 Tclk (1) Clock period 50 ns D(1) Duty cycle 45% 55% T6 tIS (1) RX data setup time 4 ns T7 tIH (1) RX data hold time 4 ns T8 tOD (1) TX data output delay 20 ns T9 tOH (1) TX data hold time 24 ns

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5.15.6.2 I2S

The McASP interface functions as a general-purpose audio serial port optimized for multichannel audio applications and supports transfer of two stereo channels over two data pins. The McASP consists of transmit and receive sections that operate synchronously and have programmable clock and frame-sync polarity. A fractional divider is available for bit-clock generation.

5.15.6.2.1 I2S Transmit Mode

Figure 5-15 shows the timing diagram for the I2S transmit mode. Figure 5-15. I2S Transmit Mode Timing Diagram Table 5-11 lists the timing parameters for the I2S transmit mode. (1) Timing parameter assumes a maximum load of 20 pF. Table 5-11. I2S Transmit Mode Timing Parameters PARAMETER NUMBER MIN MAX UNIT T1 fclk (1) Clock frequency 9.216 MHz T2 tLP(1) Clock low period 1/2 fclk ns T3 tHT (1) Clock high period 1/2 fclk ns T4 tOH (1) TX data hold time 22 ns

5.15.6.2.2 I2S Receive Mode

Figure 5-16 shows the timing diagram for the I2S receive mode. Figure 5-16. I2S Receive Mode Timing Diagram

80% 20% tGPIOFtGPIOR CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated Table 5-12 lists the timing parameters for the I2S receive mode. (1) Timing parameter assumes a maximum load of 20 pF. Table 5-12. I2S Receive Mode Timing Parameters PARAMETER NUMBER MIN MAX UNIT T1 fclk(1) Clock frequency 9.216 MHz T2 tLP(1) Clock low period 1/2 fclk ns T3 tHT(1) Clock high period 1/2 fclk ns T4 tOH(1) RX data hold time 0 ns T5 tOS(1) RX data setup time 15 ns

5.15.6.3 GPIOs

All digital pins of the device can be used as general-purpose input/output (GPIO) pins. The GPIO module consists of four GPIO blocks, each of which provides eight GPIOs. The GPIO module supports 24 programmable GPIO pins, depending on the peripheral used. Each GPIO has configurable pullup and pulldown strength (weak 10 µA), configurable drive strength (2, 4, and 6 mA), and open-drain enable. Figure 5-17 shows the GPIO timing diagram. Figure 5-17. GPIO Timing Diagram Table 5-13 lists the GPIO output transition times for Vsupply = 3.3 V. (1) Vsupply = 3.3 V, T = 25°C, total pin load = 30 pF (2) The transition data applies to the pins except the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53. Table 5-13. GPIO Output Transition Times (Vsupply = 3.3 V)(1)(2) DRIVE STRENGTH (mA) DRIVE STRENGTH CONTROL BITS tr tf UNIT MIN NOM MAX MIN NOM MAX 2MA_EN=1 4MA_EN=0 2MA_EN=0 4MA_EN=1 2MA_EN=1 4MA_EN=1

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated Table 5-14 lists the GPIO output transition times for Vsupply = 1.8 V. (1) Vsupply = 1.8 V, T = 25°C, total pin load = 30 pF (2) The transition data applies to the pins other than the multiplexed analog-digital pins 29, 30, 45, 50, 52, and 53. Table 5-14. GPIO Output Transition Times (Vsupply = 1.85 V)(1)(2) DRIVE STRENGTH (mA) DRIVE STRENGTH CONTROL BITS tr tf UNIT MIN NOM MAX MIN NOM MAX 2MA_EN=1 4MA_EN=0 2MA_EN=0 4MA_EN=1 2MA_EN=1 4MA_EN=1

5.15.6.3.3 GPIO Input Transition Time Parameters

Table 5-15 lists the input transition time parameters. Table 5-15. GPIO Input Transition Time Parameters' MIN MAX UNIT tr Input transition time (tr, tf), 10% to 90% 1 3 ns tf 1 3 ns

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5.15.6.4 I2C

The CC3220x microcontroller includes one I2C module operating with standard (100 kbps) or fast (400 kbps) transmission speeds. Figure 5-18 shows the I2C timing diagram. Figure 5-18. I2C Timing Diagram Table 5-16 lists the I2C timing parameters. (1) All timing is with 6-mA drive and 20-pF load. (2) This value depends on the value programmed in the clock period register of I2C. Maximum output frequency is the result of the minimal value programmed in this register. (3) Because I2C is an open-drain interface, the controller can drive logic 0 only. Logic is the result of external pullup. Rise time depends on the value of the external signal capacitance and external pullup register. Table 5-16. I2C Timing Parameters(1) PARAMETER NUMBER MIN MAX UNIT T2 tLP Clock low period See (2) System clock T3 tSRT SCL/SDA rise time See (3) ns T4 tDH Data hold time NA T5 tSFT SCL/SDA fall time 3 ns T6 tHT Clock high time See (2) System clock T7 tDS Data setup time tLP/2 System clock T8 tSCSR Start condition setup time 36 System clock T9 tSCS Stop condition setup time 24 System clock

2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs 2 µs Repeats Every 16 µs ADC CLOCK = 10 MHz Sampling 4 cycles SAR Conversion 16 cycles Sampling 4 cycles SAR Conversion 16 cycles Sampling 4 cycles SAR Conversion 16 cycles Sampling 4 cycles SAR Conversion 16 cycles EXT CHANNEL 0 INTERNAL CHANNEL EXT CHANNEL 1 INTERNAL CHANNEL Internal Ch CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Specifications Copyright © 2016–2018, Texas Instruments Incorporated

5.15.6.6 ADC

Figure 5-20 shows the ADC clock timing diagram. Figure 5-20. ADC Clock Timing Diagram Table 5-18 lists the ADC electrical specifications. See CC32xx ADC Appnote for further information on using the ADC and for application-specific examples. Table 5-18. ADC Electrical Specifications PARAMETER DESCRIPTION TEST CONDITIONS AND ASSUMPTIONS MIN TYP MAX UNIT Nbits Number of bits 12 Bits INL Integral nonlinearity Worst-case deviation from histogram method over full scale (not including first and last three LSB levels) –2.5 2.5 LSB DNL Differential nonlinearity Worst-case deviation of any step from ideal –1 4 LSB Input range 0 1.4 V Driving source impedance 100 Ω FCLK Clock rate Successive approximation input clock rate 10 MHz Input capacitance 12 pF Input impedance ADC Pin 57 2.15 kΩ ADC Pin 58 0.7 ADC Pin 59 2.12 ADC Pin 60 1.17 Number of channels 4 Fsample Sampling rate of each pin 62.5 KSPS F_input_max Maximum input signal frequency 31 kHz SINAD Signal-to-noise and distortion Input frequency DC to 300 Hz and 1.4 Vpp sine wave input 55 60 dB I_active Active supply current Average for analog-to-digital during conversion without reference current 1.5 mA I_PD Power-down supply current for core supply Total for analog-to-digital when not active (this must be the SoC level test) 1 µA Absolute offset error FCLK = 10 MHz ±2 mV Gain error ±2% Vref ADC reference voltage 1.467 V

pVS, pHS pDATA T3 T2 T4 T6 T7 CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated

5.15.6.7 Camera Parallel Port

The fast camera parallel port interfaces with a variety of external image sensors, stores the image data in a FIFO, and generates DMA requests. The camera parallel port supports 8 bits. Figure 5-21 shows the timing diagram for the camera parallel port. Figure 5-21. Camera Parallel Port Timing Diagram Table 5-19 lists the timing parameters for the camera parallel port. Table 5-19. Camera Parallel Port Timing Parameters PARAMETER NUMBER MIN MAX UNIT pCLK Clock frequency 2 MHz T2 Tclk Clock period 1/pCLK ns T3 tLP Clock low period Tclk/2 ns T4 tHT Clock high period Tclk/2 ns T6 tIS RX data setup time 2 ns T7 tIH RX data hold time 2 ns D Duty cycle 45% 55%

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5.15.6.8 UART

The CC3220x device includes two UARTs with the following features:

• Programmable baud-rate generator allowing speeds up to 3 Mbps
• Separate 16-bit × 8-bit TX and RX FIFOs to reduce CPU interrupt service loading
• Programmable FIFO length, including a 1-byte-deep operation providing conventional double-buffered interface
• FIFO trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8
• Standard asynchronous communication bits for start, stop, and parity
• Generation and detection of line-breaks
• Fully programmable serial interface characteristics: – 5, 6, 7, or 8 data bits – Generation and detection of even, odd, stick, or no-parity bits – Generation of 1 or 2 stop-bits
• RTS and CTS hardware flow support
• Standard FIFO-level and end-of-transmission interrupts
• Efficient transfers using µDMA: – Separate channels for transmit and receive – Receive single request asserted when data is in the FIFO; burst request asserted at programmed FIFO level – Transmit single request asserted when there is space in the FIFO; burst request asserted at programmed FIFO level
• System clock is used to generate the baud clock.

5.15.6.9 SD Host

CC3220x provides an interface between a local host (LH), such as an MCU and an SD memory card, and handles SD transactions with minimal LH intervention. The SD host does the following:

• Provides SD card access in 1-bit mode
• Deals with SD protocol at the transmission level
• Handles data packing
• Adds cyclic redundancy checks (CRC)
• Start and end bit
• Checks for syntactical correctness The application interface sends every SD command and either polls for the status of the adapter or waits for an interrupt request. The result is then sent back to the application interface in case of exceptions or to warn of end-of-operation. The controller can be configured to generate DMA requests and work with minimum CPU intervention. Given the nature of integration of this peripheral on the CC3220x platform, TI recommends that developers use peripheral library APIs to control and operate the block. This section emphasizes understanding the SD host APIs provided in the peripheral library of the CC3220x Software Development Kit (SDK). The SD Host features are as follows:
• Full compliance with SD command and response sets, as defined in the SD memory card – Specifications, v2.0 – Includes high-capacity (size >2 GB) cards HC SD
• Flexible architecture, allowing support for new command structure.
• 1-bit transfer mode specifications for SD cards

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF SpecificationsCopyright © 2016–2018, Texas Instruments Incorporated

• Built-in 1024-byte buffer for read or write – 512-byte buffer for both transmit and receive – Each buffer is 32-bits wide by 128-words deep
• 32-bit-wide access bus to maximize bus throughput
• Single interrupt line for multiple interrupt source events
• Two slave DMA channels (1 for TX, 1 for RX)
• Programmable clock generation
• Integrates an internal transceiver that allows a direct connection to the SD card without external transceiver
• Supports configurable busy and response timeout
• Support for a wide range of card clock frequency with odd and even clock ratio
• Maximum frequency supported is 24 MHz

5.15.6.10 Timers

Programmable timers can be used to count or time external events that drive the timer input pins. The CC3220x general-purpose timer module (GPTM) contains 16- or 32-bit GPTM blocks. Each 16- or 32-bit GPTM block provides two 16-bit timers or counters (referred to as Timer A and Timer B) that can be configured to operate independently as timers or event counters, or they can be concatenated to operate as one 32-bit timer. Timers can also be used to trigger µDMA transfers. The GPTM contains four 16- or 32-bit GPTM blocks with the following functional options:

• Operating modes: – 16- or 32-bit programmable one-shot timer – 16- or 32-bit programmable periodic timer – 16-bit general-purpose timer with an 8-bit prescaler – 16-bit input-edge count- or time-capture modes with an 8-bit prescaler – 16-bit PWM mode with an 8-bit prescaler and software-programmable output inversion of the PWM signal
• Counts up or counts down
• Sixteen 16- or 32-bit capture compare pins (CCP)
• User-enabled stalling when the microcontroller asserts CPU Halt flag during debug
• Ability to determine the elapsed time between the assertion of the timer interrupt and entry into the interrupt service routine
• Efficient transfers using micro direct memory access controller (µDMA): – Dedicated channel for each timer – Burst request generated on timer interrupt
• Runs from system clock (80 MHz)

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated

6 Detailed Description

The CC3220x wireless MCU family has a rich set of peripherals for diverse application requirements. This section briefly highlights the internal details of the CC3220x devices and offers suggestions for application configurations.

6.1 Arm® Cortex®-M4 Processor Core Subsystem

The high-performance Cortex-M4 processor provides a low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts.

• The Cortex-M4 core has low-latency interrupt processing with the following features: – A 32-bit Arm® Thumb® instruction set optimized for embedded applications – Handler and thread modes – Low-latency interrupt handling by automatic processor state saving and restoration during entry and exit – Support for ARMv6 unaligned accesses
• Nested vectored interrupt controller (NVIC) closely integrated with the processor core to achieve low- latency interrupt processing. The NVIC includes the following features: – Bits of priority configurable from 3 to 8 – Dynamic reprioritization of interrupts – Priority grouping that enables selection of preempting interrupt levels and nonpreempting interrupt levels – Support for tail-chaining and late arrival of interrupts, which enables back-to-back interrupt processing without the overhead of state saving and restoration between interrupts – Processor state automatically saved on interrupt entry and restored on interrupt exit with no instruction overhead – Wake-up interrupt controller (WIC) providing ultra-low-power sleep mode support
• Bus interfaces: – Advanced high-performance bus (AHB-Lite) interfaces: system bus interfaces – Bit-band support for memory and select peripheral that includes atomic bit-band write and read operations
• Low-cost debug solution featuring: – Debug access to all memory and registers in the system, including access to memory-mapped devices, access to internal core registers when the core is halted, and access to debug control registers even while SYSRESETn is asserted – Serial wire debug port (SW-DP) or serial wire JTAG debug port (SWJ-DP) debug access – Flash patch and breakpoint (FPB) unit to implement breakpoints and code patches

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6.2 Wi-Fi Network Processor Subsystem

The Wi-Fi network processor subsystem includes a dedicated Arm MCU to completely offload the host MCU along with an 802.11 b/g/n radio, baseband, and MAC with a powerful crypto engine for a fast, secure WLAN and Internet connections with 256-bit encryption. The CC3220x devices support station, AP, and Wi-Fi Direct modes. The device also supports WPA2 personal and enterprise security and WPS 2.0. The Wi-Fi network processor includes an embedded IPv6, IPv4 TCP/IP stack.

6.2.1 WLAN

The WLAN features are as follows:

• 802.11b/g/n integrated radio, modem, and MAC supporting WLAN communication as a BSS station, AP, Wi-Fi Direct client and group owner with CCK and OFDM rates in the 2.4-GHz ISM band, channels 1 to 13. NOTE 802.11n is supported only in Wi-Fi station, Wi-Fi direct, and P2P client modes.
• Autocalibrated radio with a single-ended 50-Ω interface enables easy connection to the antenna without requiring expertise in radio circuit design.
• Advanced connection manager with multiple user-configurable profiles stored in serial Flash allows automatic fast connection to an access point without user or host intervention.
• Supports all common Wi-Fi security modes for personal and enterprise networks with on-chip security accelerators, including: WEP, WPA/WPA2 PSK, WPA2 Enterprise (802.1x).
• Smart provisioning options deeply integrated within the device providing a comprehensive end-to-end solution. With elaborate events notification to the host, enabling the application to control the provisioning decision flow. The wide variety of Wi-Fi provisioning methods include: – Access Point using HTTPS – SmartConfig Technology: a 1-step, 1-time process to connect a CC3220-enabled device to the home wireless network, removing dependency on the I/O capabilities of the host MCU; thus, it is usable by deeply embedded applications
• 802.11 transceiver mode allows transmitting and receiving of proprietary data through a socket without adding MAC or PHY headers. The 802.11 transceiver mode provides the option to select the working channel, rate, and transmitted power. The receiver mode works with the filtering options.

6.2.2 Network Stack

The Network Stack features are as follows:

• Integrated IPv4, IPv6 TCP/IP stack with BSD (BSD adjacent) socket APIs for simple Internet connectivity with any MCU, microprocessor, or ASIC NOTE Not all APIs are 100% BSD compliant. Not all BSD APIs are supported.
• Support of 16 simultaneous TCP, UDP, or RAW sockets
• Support of 6 simultaneous SSL\\TLS sockets
• Built-in network protocols: – Static IP, LLA, DHCPv4, DHCPv6 with DAD and stateless autoconfiguration – ARP, ICMPv4, IGMP, ICMPv6, MLD, ND – DNS client for easy connection to the local network and the Internet

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated

• Built-in network application and utilities: – HTTP/HTTPS
• Web page content stored on serial Flash
• RESTful APIs for setting and configuring application content
• Dynamic user callbacks – Service discovery: Multicast DNS service discovery lets a client advertise its service without a centralized server. After connecting to the access point, the CC3220x device provides critical information, such as device name, IP, vendor, and port number. – DHCP server – Ping Table 6-1 describes the NWP features. Table 6-1. NWP Features Feature Description Wi-Fi standards 802.11b/g/n station 802.11b/g AP supporting up to four stations Wi-Fi Direct client and group owner Wi-Fi channels 1 to 13 Wi-Fi security WEP, WPA/WPA2 PSK, WPA2 enterprise (802.1x) Wi-Fi provisioning SmartConfig technology, Wi-Fi protected setup (WPS2), AP mode with internal HTTP web server IP protocols IPv4/IPv6 IP addressing Static IP, LLA, DHCPv4, DHCPv6 with DAD Cross layer ARP, ICMPv4, IGMP, ICMPv6, MLD, NDP Transport UDP, TCP SSLv3.0/TLSv1.0/TLSv1.1/TLSv1.2 RAW Network applications and utilities Ping HTTP/HTTPS web server mDNS DNS-SD DHCP server Host interface UART/SPI Security Device identity Trusted root-certificate catalog TI root-of-trust public key The CC3220S and CC3220SF variants also support:
• Secure key storage
• File system security
• Software tamper detection
• Cloning protection
• Secure boot
• Validate the integrity and authenticity of the run-time binary during boot
• Initial secure programming
• Debug security
• JTAG and debug Power management Enhanced power policy management uses 802.11 power save and deep-sleep power modes Other Transceiver Programmable RX filters with event-trigger mechanism

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6.3 Security

The SimpleLink™ Wi-Fi® CC3220x Internet-on-a-Chip device enhances the security capabilities available for development of IoT devices, while completely offloading these activities from the MCU to the networking subsystem. The security capabilities include the following key features: Wi-Fi and Internet Security:

• Personal and enterprise Wi-Fi security – Personal standards
• AES (WPA2-PSK)
• TKIP (WPA-PSK)
• WEP – Enterprise standards
• EAP Fast
• EAP PEAPv0/1
• EAP PEAPv0 TLS
• EAP PEAPv1 TLS EAP LS
• EAP TLS
• EAP TTLS TLS
• EAP TTLS MSCHAPv2

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated

• Secure sockets – Protocol versions: SSL v3, TLS 1.0, TLS 1.1, TLS 1.2 – Powerful crypto engine for fast, secure Wi-Fi and internet connections with 256-bit AES encryption for TLS and SSL connections – Ciphers suites
• SL_SEC_MASK_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_ECDHE_RSA_WITH_CHACHA20_POLY1305_SHA256
• SL_SEC_MASK_TLS_DHE_RSA_WITH_CHACHA20_POLY1305_SHA256 – Server authentication – Client authentication – Domain name verification – Runtime socket upgrade to secure socket – STARTTLS
• Secure HTTP server (HTTPS)
• Trusted root-certificate catalog— Verifies that the CA used by the application is trusted and known secure content delivery
• TI root-of-trust public key— Hardware-based mechanism that allows authenticating TI as the genuine origin of a given content using asymmetric keys
• Secure content delivery— Allows encrypted file transfer to the system using asymmetric keys created by the device Code and Data Security:
• Network passwords and certificates are encrypted and signed.
• Cloning protection— Application and data files are encrypted by a unique key per device.
• Access control— Access to application and data files only by using a token provided in file creation time. If an unauthorized access is detected, a tamper protection lockdown mechanism takes effect.
• Encrypted and Authenticated file system (not supported in CC3220R)
• Secured boot— Authentication of the application image on every boot
• Code and data encryption (not supported in CC3220R)— User application and data files are encrypted in serial flash.

1MB Flash (CC3220SF) Peripherals OEM Application Serial Flash Data FilesOEM Application Network Information SPI and I2C GPIO UART PWM ADC Wi-Fi® Radio Baseband MAC Internet HTTPS TLS/SSL TCP/IP Arm ® Cortex® -M4 Processor Internet CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated Figure 6-2 shows the high-level structure of the CC3220S and CC3220SF devices. The application image, user data, and network information files (passwords, certificates) are encrypted using a device-specific key. Figure 6-2. CC3220S and CC3220SF High-Level Structure

6.4 Power-Management Subsystem

The CC3220x power-management subsystem contains DC/DC converters to accommodate the different voltage or current requirements of the system.

• Digital DC/DC (Pin 44) – Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V
• ANA1 DC/DC (Pin 37) – Input: VBAT wide voltage (2.1 to 3.6 V) – In preregulated 1.85-V mode, the ANA1 DC/DC converter is bypassed.
• PA DC/DC (Pin 39) – Input: VBAT wide voltage (2.1 to 3.6 V) – In preregulated 1.85-V mode, the PA DC/DC converter is bypassed.
• ANA2 DC/DC (Pin 47) – Input: VBAT wide voltage (2.1 to 3.6 V) or preregulated 1.85 V The CC3220x device is a single-chip WLAN radio solution used on an embedded system with a wide- voltage supply range. The internal power management, including DC/DC converters and LDOs, generates all of the voltages required for the device to operate from a wide variety of input sources. For maximum

6.4.1 VBAT Wide-Voltage Connection

In the wide-voltage battery connection, the device is powered directly by the battery or preregulated 3.3-V supply. All other voltages required to operate the device are generated internally by the DC/DC converters. This scheme supports wide-voltage operation from 2.1 to 3.6 V and is thus the most common mode for the device.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed DescriptionCopyright © 2016–2018, Texas Instruments Incorporated (1) Modes are listed in order of power consumption, with highest power modes listed first. 6.4.2 Preregulated 1.85-V Connection The preregulated 1.85-V mode of operation applies an external regulated 1.85 V directly at pins 10, 25, 33, 36, 37, 39, 44, 48, and 54 of the device. The VBAT and the VIO are also connected to the 1.85-V supply. This mode provides the lowest BOM count version in which inductors used for PA DC/DC and ANA1 DC/DC (2.2 and 1 µH) and a capacitor (22 µF) can be avoided. In the preregulated 1.85-V mode, the regulator providing the 1.85 V must have the following characteristics:

• Load current capacity ≥900 mA
• Line and load regulation with <2% ripple with 500-mA step current and settling time of < 4 µs with the load step NOTE The regulator must be placed as close as possible to the device so that the IR drop to the device is very low.

6.5 Low-Power Operating Mode

From a power-management perspective, the CC3220x device comprises the following two independent subsystems:

• Arm Cortex-M4 application processor subsystem
• Networking subsystem Each subsystem operates in one of several power states. The Cortex-M4 application processor runs the user application loaded from an external serial Flash, or internal Flash (in CC3220SF). The networking subsystem runs preprogrammed TCP/IP and Wi-Fi data link layer functions. The user program controls the power state of the application processor subsystem and can be in one of the five modes described in Table 6-2. Table 6-2. User Program Modes APPLICATION PROCESSOR (MCU) MODE(1) DESCRIPTION MCU active mode MCU executing code at 80-MHz state rate MCU sleep mode The MCU clocks are gated off in sleep mode and the entire state of the device is retained. Sleep mode offers instant wakeup. The MCU can be configured to wake up by an internal fast timer or by activity from any GPIO line or peripheral. MCU LPDS mode State information is lost and only certain MCU-specific register configurations are retained. The MCU can wake up from external events or by using an internal timer. (The wake-up time is less than 3 ms.) Certain parts of memory can be retained while the MCU is in LPDS mode. The amount of memory retained is configurable. Users can choose to preserve code and the MCU-specific setting. The MCU can be configured to wake up using the RTC timer or by an external event on specific GPIOs as the wake-up source. MCU hibernate mode The lowest power mode in which all digital logic is power-gated. Only a small section of the logic directly powered by the input supply is retained. The RTC keeps running and the MCU supports wakeup from an external event or from an RTC timer expiry. Wake-up time is longer than LPDS mode at about 15 ms plus the time to load the application from serial Flash, which varies according to code size. In this mode, the MCU can be configured to wake up using the RTC timer or external event on a GPIO. MCU shutdown mode The lowest power mode system-wise. All device logics are off, including the RTC. The wake-up time in this mode is longer than hibernate at about 1.1 s. To enter or exit the shutdown mode, the state of the nRESET line is changed (low to shut down, high to turn on).

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated The NWP can be active or in LPDS mode and takes care of its own mode transitions. When there is no network activity, the NWP sleeps most of the time and wakes up only for beacon reception (see Table 6-3). Table 6-3. Networking Subsystem Modes NETWORK PROCESSOR MODE DESCRIPTION Network active mode (processing layer 3, 2, and 1) Transmitting or receiving IP protocol packets Network active mode (processing layer 2 and 1) Transmitting or receiving MAC management frames; IP processing not required. Network active listen mode Special power optimized active mode for receiving beacon frames (no other frames supported) Network connected Idle A composite mode that implements 802.11 infrastructure power save operation. The CC3220x NWP automatically goes into LPDS mode between beacons and then wakes to active listen mode to receive a beacon and determine if there is pending traffic at the AP. If not, the NWP returns to LPDS mode and the cycle repeats. Network LPDS mode Low-power state between beacons in which the state is retained by the NWP, allowing for a rapid wake up. Network disabled The network is disabled The operation of the application and network processor ensures that the device remains in the lowest power mode most of the time to preserve battery life. The following examples show the use of the power modes in applications:

• A product that is continuously connected to the network in the 802.11 infrastructure power-save mode but sends and receives little data spends most of the time in connected idle, which is a composite of receiving a beacon frame and waiting for the next beacon.
• A product that is not continuously connected to the network but instead wakes up periodically (for example, every 10 minutes) to send data, spends most of the time in hibernate mode, jumping briefly to active mode to transmit data.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed DescriptionCopyright © 2016–2018, Texas Instruments Incorporated (1) Including fail-safe. (2) For maximum MCU size.

6.6 Memory

6.6.1 External Memory Requirements

The CC3220x device maintains a proprietary file system on the serial flash. The CC3220x file system stores the MCU binary, service pack file, system files, configuration files, certificate files, web page files, and user files. By using a format command through the API, users can provide the total size allocated for the file system. The starting address of the file system cannot be set and is always at the beginning of the serial flash. The applications microcontroller must access the serial flash memory area allocated to the file system directly through the CC3220x file system. The applications microcontroller must not access the serial flash memory area directly. The file system manages the allocation of serial flash blocks for stored files according to download order, which means that the location of a specific file is not fixed in all systems. Files are stored on serial flash using human-readable filenames rather than file IDs. The file system API works using plain text, and file encryption and decryption is invisible to the user. Encrypted files can be accessed only through the file system. All file types can have a maximum of 100 supported files in the file system. All files are stored in 4-KB blocks and thus use a minimum of 4KB of Flash space. Fail-safe files require twice the original size and use a minimum of 8KB. Encrypted files are counted as fail-safe in terms of space. The maximum file size is 1MB. Table 6-4 lists the minimum required memory consumption under the following assumptions:

• System files in use consume 64 blocks (256KB).
• Vendor files are not taken into account.
• MCU code is taken as the maximal possible size for the CC3220 with fail-safe enabled to account for future updates, such as through OTA.
• Gang image: – Storage for the gang image is rounded up to 32 blocks (meaning 128KB resolution). – Gang image size depends on the actual content size of all components. Additionally, the image should be 128KB aligned so unaligned memory is considered lost. Service pack, system files, and the 128KB aligned memory are assumed to occupy 256KB.
• All calculations consider that the restore-to-default is enabled. Table 6-4. Recommended Flash Size ITEM CC3220R and CC3220S [KB] CC3220SF [KB] File system allocation table 20 20 System and configuration files(1) 256 256 Service Pack(1) 264 264 MCU Code(1) 512 2048 Gang image size 256 + MCU 256 + MCU Total 1308 + MCU 2844 + MCU Minimal Flash size(2) 16MBit 32MBit Recommended Flash size(2) 16MBit 32MBit NOTE The maximum supported serial flash size is 32MB (256Mb). See the Using Serial Flash on CC3120/CC3220 SimpleLink™ Wi-Fi® and Internet-of-Things Devices application report.

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated

6.6.2 Internal Memory

The CC3220x device includes on-chip SRAM to which application programs are downloaded and executed. The application developer must share the SRAM for code and data. The micro direct memory access (μDMA) controller can transfer data to and from SRAM and various peripherals. The CC3220x ROM holds the rich set of peripheral drivers, which saves SRAM space. For more information on drivers, see the CC3220x API list.

6.6.2.1 SRAM

The CC3220x family provides 256KB of on-chip SRAM. Internal RAM is capable of selective retention during LPDS mode. This internal SRAM is at offset 0x2000 0000 of the device memory map. Use the µDMA controller to transfer data to and from the SRAM. When the device enters low-power mode, the application developer can choose to retain a section of memory based on need. Retaining the memory during low-power mode provides a faster wakeup. The application developer can choose the amount of memory to retain in multiples of 64KB. For more information, see the API guide.

6.6.2.2 ROM

The internal zero-wait-state ROM of the CC3220x device is at address 0x0000 0000 of the device memory and is programmed with the following components:

• Bootloader
• Peripheral driver library (DriverLib) release for product-specific peripherals and interfaces The bootloader is used as an initial program loader (when the serial Flash memory is empty). The CC3220x DriverLib software library controls on-chip peripherals with a bootloader capability. The library performs peripheral initialization and control functions, with a choice of polled or interrupt-driven peripheral support. The DriverLib APIs in ROM can be called by applications to reduce Flash memory requirements and free the Flash memory for other purposes.

6.6.2.3 Flash Memory

The CC3220SF device comes with an on-chip Flash memory of 1MB that allows application code to execute in place while freeing SRAM exclusively for read-write data. The Flash memory is used for code and constant data sections and is directly attached to the ICODE/DCODE bus of the Cortex-M4 core. A 128-bit-wide instruction prefetch buffer allows maintenance of maximum performance for linear code or loops that fit inside the buffer. The Flash memory is organized as 2-KB sectors that can be independently erased. Reads and writes can be performed at word (32-bit) level.

6.6.2.4 Memory Map

Table 6-5 describes the various MCU peripherals and how they are mapped to the processor memory. For more information on peripherals, see the API document.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed DescriptionCopyright © 2016–2018, Texas Instruments Incorporated Table 6-5. Memory Map START ADDRESS END ADDRESS DESCRIPTION COMMENT 0x0000 0000 0x0007 FFFF On-chip ROM (bootloader + DriverLib) 0x0100 0000 0x010F FFFF On-chip Flash (for user application code) CC3220SF device only 0x2000 0000 0x2003 FFFF Bit-banded on-chip SRAM 0x2200 0000 0x23FF FFFF Bit-band alias of 0x2000 0000 to 0x200F FFFF 0x4000 0000 0x4000 0FFF Watchdog timer A0 0x4000 4000 0x4000 4FFF GPIO port A0 0x4000 5000 0x4000 5FFF GPIO port A1 0x4000 6000 0x4000 6FFF GPIO port A2 0x4000 7000 0x4000 7FFF GPIO port A3 0x4000 C000 0x4000 CFFF UART A0 0x4000 D000 0x4000 DFFF UART A1 0x4002 0000 0x4000 07FF I2C A0 (master) 0x4002 4000 0x4002 4FFF GPIO group 4 0x4002 0800 0x4002 0FFF I2C A0 (slave) 0x4003 0000 0x4003 0FFF General-purpose timer A0 0x4003 1000 0x4003 1FFF General-purpose timer A1 0x4003 2000 0x4003 2FFF General-purpose timer A2 0x4003 3000 0x4003 3FFF General-purpose timer A3 0x400F7000 0x400F 7FFF Configuration registers 0x400F E000 0x400F EFFF System control 0x400F F000 0x400F FFFF µDMA 0x4200 0000 0x43FF FFFF Bit band alias of 0x4000 0000 to 0x400F FFFF 0x4401 0000 0x4401 0FFF SDIO master 0x4401 8000 0x4401 8FFF Camera Interface 0x4401 C000 0x4401 DFFF McASP 0x4402 0000 0x4402 1FFF SSPI Used for external serial Flash 0x4402 1000 0x4402 2FFF GSPI Used by application processor 0x4402 5000 0x4402 5FFF MCU reset clock manager 0x4402 6000 0x4402 6FFF MCU configuration space 0x4402 D000 0x4402 DFFF Global power, reset, and clock manager (GPRCM) 0x4402 E000 0x4402 EFFF MCU shared configuration 0x4402 F000 0x4402 FFFF Hibernate configuration 0x4403 0000 0x4403 FFFF Crypto range (includes apertures for all crypto-related blocks as follows) 0x4403 0000 0x4403 0FFF DTHE registers and TCP checksum 0x4403 5000 0x4403 5FFF MD5/SHA 0x4403 7000 0x4403 7FFF AES 0x4403 9000 0x4403 9FFF DES 0xE000 0000 0xE000 0FFF Instrumentation trace Macrocell™ 0xE000 1000 0xE000 1FFF Data watchpoint and trace (DWT) 0xE000 2000 0xE000 2FFF Flash patch and breakpoint (FPB) 0xE000 E000 0xE000 EFFF NVIC 0xE004 0000 0xE004 0FFF Trace port interface unit (TPIU) 0xE004 1000 0xE004 1FFF Reserved for embedded trace macrocell (ETM) 0xE004 2000 0xE00F FFFF Reserved

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Detailed Description Copyright © 2016–2018, Texas Instruments Incorporated

6.7 Restoring Factory Default Configuration

The device has an internal recovery mechanism that allows rolling back the file system to its predefined factory image or restoring the factory default parameters of the device. The factory image is kept in a separate sector on the serial flash in a secure manner and cannot be accessed from the host processor. The following restore modes are supported:

• None— no factory restore settings
• Enable restore of factory default parameters
• Enable restore of factory image and factory default parameters The restore process is performed by calling SW APIs, or by pulling or forcing SOP[2:0] = 110 pins and toggling the nRESET pin from low to high. The process is fail-safe and resumes operation if a power failure occurs before the restore is finished. The restore process typically takes about 8 seconds, depending on the attributes of the serial Flash vendor.

6.8 Boot Modes

6.8.1 Boot Mode List

The CC3220x device implements a sense-on-power (SoP) scheme to determine the device operation mode. SoP values are sensed from the device pin during power up. This encoding determines the boot flow. Before the device is taken out of reset, the SoP values are copied to a register and used to determine the device operation mode while powering up. These values determine the boot flow as well as the default mapping for some of the pins (JTAG, SWD, UART0). Table 6-6 lists the pull configurations. Table 6-6. CC3220x Functional Configurations NAME SOP[2] SOP[1] SOP[0] SoP MODE COMMENT UARTLOAD Pullup Pulldown Pulldown LDfrUART Factory, lab Flash, and SRAM loads through the UART. The device waits indefinitely for the UART to load code. The SOP bits then must be toggled to configure the device in functional mode. Also puts JTAG in 4-wire mode. FUNCTIONAL_2WJ Pulldown Pulldown Pullup Fn2WJ Functional development mode. In this mode, 2-pin SWD is available to the developer. TMS and TCK are available for debugger connection. FUNCTIONAL_4WJ Pulldown Pulldown Pulldown Fn4WJ Functional development mode. In this mode, 4-pin JTAG is available to the developer. TDI, TMS, TCK, and TDO are available for debugger connection. UARTLOAD_FUNCTIONAL_4WJ Pulldown Pullup Pulldown LDfrUART_Fn4WJ Supports Flash and SRAM load through UART and functional mode. The MCU bootloader tries to detect a UART break on UART receive line. If the break signal is present, the device enters the UARTLOAD mode, otherwise, the device enters the functional mode. TDI, TMS, TCK, and TDO are available for debugger connection. RET_FACTORY_IMAGE Pulldown Pullup Pullup RetFactDef When device reset is toggled, the MCU bootloader kickstarts the procedure to restore factory default images.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Applications, Implementation, and LayoutCopyright © 2016–2018, Texas Instruments Incorporated The recommended values of pull resistors are 100 kΩ for SOP0 and SOP1 and 2.7 kΩ for SOP2. The application can use SOP2 for other functions after chip has powered up. However, to avoid spurious SOP values from being sensed at power up, TI strongly recommends using the SOP2 pin only for output signals. The SOP0 and SOP1 pins are multiplexed with the WLAN analog test pins and are not available for other functions.

7 Applications, Implementation, and Layout

Information in the following Applications section is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

7.1.1 Typical Application— CC3220x Wide-Voltage Mode

Figure 7-1 shows the schematic for an application using the CC3220x device in the wide-voltage mode of operation. For a full operation reference design, refer to CC3220 SimpleLink™ and Internet of Things Hardware Design Files. NOTE For complete reference schematics and BOM, see the CC3220x product page. Table 7-1 lists the bill of materials for an application using the CC3220x device in wide-voltage mode.

VBAT_CC VBAT_CC VBAT_CC G ND 10µF C20 10µF C17 10µF C10 100k 100k 100k 0.1µF C190.1µF C18 0.1µF 0.1µF 0.1µF C21 0.1µF C22 0.1µF C11 0.1µF 0.1µF C12 0.1µF C13 4.7µF 4.7µF 4.7µF 22µF C14 22µF C15 6.2pF C25 6.2pF C26 IN1 GND 2 OUT 3 GND 4 FL1 10uH 2.2uH 2.2uH 10pF C24 10pF C23 1uH VBAT_CCVBAT_CC 100k G ND 4 2 GG 32.768kHz 1µF CC_GPIO_00 CC_GPIO_01 CC_GPIO_02 CC_GPIO_03 CC_GPIO_04 CC_GPIO_05 CC_GPIO_06 CC_GPIO_07 CC_GPIO_08 CC_GPIO_09 CC_GPIO_10 CC_GPIO_11 CC_GPIO_12 CC_GPIO_13 CC_GPIO_16 CC_GPIO_17 CC_GPIO_22 CC_GPIO_28 CC_GPIO_30 CC_GPIO_14 CC_GPIO_15 CC_JTAG_TDO CC_JTAG_TDI CC_JTAG_TMS CC_JTAG_TCK 1µF C16 10k 2.7k GPIO11 2 GPIO28 18 VDD_PA_IN33 DCDC_PA_OUT42 GPIO0 50 GPIO4 59 GPIO13 4 FLASH_SPI_DOUT 12 GPIO6 61 GPIO15 6 FLASH_SPI_CS 14 WLAN_XTAL_N 22 ANTSEL2 30 DCDC_ANA2_SW_N46 GPIO8 63 GPIO17 8 VDD_PLL24 RESET 32 VDD_ANA148 VDD_DIG256 GPIO10 1 VDD_DIG19 LDO_IN225 DCDC_PA_SW_N41 VDD_RAM49 GPIO2 57 GPIO12 3 FLASH_SPI_CLK 11 LDO_IN136 DCDC_DIG_SW43 GPIO5 60 GPIO14 5 FLASH_SPI_DIN 13 ANTSEL1 29 DCDC_ANA_SW38 DCDC_ANA2_SW_P45 GPIO30 53 GPIO7 62 GPIO16 7 GPIO22 15 WLAN_XTAL_P 23 RF_BG 31 DCDC_PA_SW_P40 VDD_ANA247 GPIO1 55 GPIO9 64 GPIO3 58 GND_TAB 65 SOP035 SOP134 SOP221 TMS20 TDI16 TDO17 TCK19 NC26 NC28 NC27 VIN_IO110 VIN_DCDC_DIG44 VIN_DCDC_ANA37 VIN_IO254 VIN_DCDC_PA39 RTC_XTAL_N 52 RTC_XTAL_P 51 CC3220SF12RGK G ND CS1 SO/SIO12 WP/SIO23 GND 4 SI/SIO05 SCLK6 RESET/SIO37 VCC8 JTAG G ND G NDG ND 1 2 3.3nH 0.5pF Antenna match. Pi network might be required depending on type of antenna. VBAT_CC CC_nReset CC_GPIO_01 CC_GPIO_02 SOP0 SOP2 TP1 TP1 TP1 TP1 TP1 FLASH PROGRAMMING INTERFACE Add provision on the board to isolate GPIO_01 and GPIO_02 while programming G ND G ND VBAT_CC 100µF 100µF Optional: Consider adding extra decoupling capacitors if the battery cannot source the peak currents. PIN 45, 46, and 47: Refer to the BOM in the following table for notes on device-dependent configurations. 270 Copyright © 2016–2018, Texas Instruments IncorporatedApplications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Figure 7-1. CC3220x Wide-Voltage Mode Application Circuit

Copyright © 2016–2018, Texas Instruments Incorporated Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 (1) For CC3220SF device, L5 is populated. For CC3220R and CC3220S devices, L5 is not populated. (2) For CC3220SF device, R8 is not populated. For CC3220R and CC3220S devices if R8 is populated, Pin 47 can be used as GPIO_31. Table 7-1. Bill of Materials for CC3220x in Wide-Voltage Mode QUANTITY DESIGNATOR VALUE MANUFACTURER PART NUMBER DESCRIPTION

1 C1 1 µF MuRata GRM155R61A105KE15D Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402

10 C2, C6, C10, C12, C13,

C14, C19, C20, C22, C23 0.1 µF TDK C1005X5R1A104K050BA Capacitor, Ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402 3 C3, C4, C5 4.7 µF TDK C1005X5R0J475M050BC Capacitor, Ceramic, 4.7 µF, 6.3 V, ±20%, X5R, 0402 2 C7, C8 100 µF Taiyo Yuden LMK325ABJ107MMHT Capacitor, Ceramic, 100 µF, 10 V, ±20%, X5R, AEC-Q200 Grade 3, 1210 1 C9 0.5 pF MuRata GRM1555C1HR50BA01D Capacitor, Ceramic, 0.5 pF, 50 V, ±20%, C0G/NP0, 0402 3 C11, C18, C21 10 µF MuRata GRM188R60J106ME47D Capacitor, Ceramic, 10 µF, 6.3 V, ±20%, X5R, 0603

1 C15 1 µF TDK C1005X5R1A105K050BB Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402

2 C16, C17 22 µF TDK C1608X5R0G226M080AA Capacitor, Ceramic, 22 µF, 4 V, ±20%, X5R, 0603

2 C24, C25 10 pF MuRata GRM1555C1H100JA01D Capacitor, Ceramic, 10 pF, 50 V, ±5%, C0G/NP0, 0402

2 C26, C27 6.2 pF MuRata GRM1555C1H6R2CA01D Capacitor, Ceramic, 6.2 pF, 50 V, ±5%, C0G/NP0, 0402 1 E1 2.45-GHz Antenna Taiyo Yuden AH316M245001-T ANT Bluetooth W-LAN Zigbee® WiMAX™ , SMD 1 FL1 1.02 dB TDK DEA202450BT-1294C1-H Multilayer Chip Band Pass Filter For 2.4 GHz W-LAN/Bluetooth, SMD 1 L1 3.3 nH MuRata LQG15HS3N3S02D Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17 ohm, SMD 2 L2, L4 2.2 µH MuRata LQM2HPN2R2MG0L Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm, SMD 1 L3 1 µH MuRata LQM2HPN1R0MG0L Inductor, Multilayer, Ferrite, 1 µH, 1.6 A, 0.055 ohm, SMD 1 L5(1) 10 µH Taiyo Yuden CBC2518T100M Inductor, Wirewound, Ceramic, 10 µH, 0.48 A, 0.36 ohm, SMD 1 R1 10 k Vishay-Dale CRCW040210K0JNED Resistor, 10 k, 5%, 0.063 W, 0402 4 R2, R3, R4, R5 100 k Vishay-Dale CRCW0402100KJNED Resistor, 100 k, 5%, 0.063 W, 0402 1 R6 2.7 k Vishay-Dale CRCW04022K70JNED Resistor, 2.7 k, 5%, 0.063 W, 0402 1 R7 270 Vishay-Dale CRCW0402270RJNED Resistor, 270, 5%, 0.063 W, 0402 1 R8(2) 0 Panasonic ERJ-2GE0R00X Resistor, 0, 5% 0.063W, 0402

1 U1 MX25R Macronix International

Co., LTD MX25R3235FM1IL0 Ultra-Low Power, 32-Mbit [x 1/x 2/x 4] CMOS MXSMIO (Serial Multi I/O) Flash Memory, SOP-8 1 U2 CC3220 Texas Instruments CC3220SF12RGK SimpleLink™ Wi-Fi® and internet-of-things Solution, a Single-Chip Wireless MCU, RGK0064B 1 Y1 Crystal Abracon Corportation ABS07-32.768KHZ-9-T Crystal, 32.768 KHz, 9PF, SMD

1 Y2 Crystal Epson Q24FA20H0039600 Crystal, 40 MHz, 8pF, SMD

1.85V 1.85V 1.85V G ND 10µF C19 10µF C16 100k 100k 100k 0.1µF C180.1µF C17 0.1µF 0.1µF 0.1µF C20 0.1µF C21 0.1µF C11 0.1µF C10 0.1µF C12 0.1µF C13 4.7µF 4.7µF 4.7µF 22µF C15 6.2pF C24 6.2pF C25 IN1 GND 2 OUT 3 GND 4 FL1 10uH 2.2uH 10pF C23 10pF C22 1.85V1.85V 100k G ND 4 2 GG 32.768kHz 1µF CC_GPIO_00 CC_GPIO_01 CC_GPIO_02 CC_GPIO_03 CC_GPIO_04 CC_GPIO_05 CC_GPIO_06 CC_GPIO_07 CC_GPIO_08 CC_GPIO_09 CC_GPIO_10 CC_GPIO_11 CC_GPIO_12 CC_GPIO_13 CC_GPIO_16 CC_GPIO_17 CC_GPIO_22 CC_GPIO_28 CC_GPIO_30 CC_GPIO_14 CC_GPIO_15 CC_JTAG_TDO CC_JTAG_TDI CC_JTAG_TMS CC_JTAG_TCK 1µF C14 10k 2.7k GPIO11 2 GPIO28 18 VDD_PA_IN33 DCDC_PA_OUT42 GPIO0 50 GPIO4 59 GPIO13 4 FLASH_SPI_DOUT 12 GPIO6 61 GPIO15 6 FLASH_SPI_CS 14 WLAN_XTAL_N 22 ANTSEL2 30 DCDC_ANA2_SW_N46 GPIO8 63 GPIO17 8 VDD_PLL24 RESET 32 VDD_ANA148 VDD_DIG256 GPIO10 1 VDD_DIG19 LDO_IN225 DCDC_PA_SW_N41 VDD_RAM49 GPIO2 57 GPIO12 3 FLASH_SPI_CLK 11 LDO_IN136 DCDC_DIG_SW43 GPIO5 60 GPIO14 5 FLASH_SPI_DIN 13 ANTSEL1 29 DCDC_ANA_SW38 DCDC_ANA2_SW_P45 GPIO30 53 GPIO7 62 GPIO16 7 GPIO22 15 WLAN_XTAL_P 23 RF_BG 31 DCDC_PA_SW_P40 VDD_ANA247 GPIO1 55 GPIO9 64 GPIO3 58 GND_TAB 65 SOP035 SOP134 SOP221 TMS20 TDI16 TDO17 TCK19 NC26 NC28 NC27 VIN_IO110 VIN_DCDC_DIG44 VIN_DCDC_ANA37 VIN_IO254 VIN_DCDC_PA39 RTC_XTAL_N 52 RTC_XTAL_P 51 CC3220SF12RGK G ND CS1 SO/SIO12 WP/SIO23 GND 4 SI/SIO05 SCLK6 RESET/SIO37 VCC8 JTAG G ND G NDG ND 1 2 3.3nH 0.5pF Antenna match. Pi network might be required depending on type of antenna. 1.85V CC_nReset CC_GPIO_01 CC_GPIO_02 SOP0 SOP2 TP1 TP2 TP3 TP4 TP5 FLASH PROGRAMMING INTERFACE Add provision on the board to isolate GPIO_01 and GPIO_02 while programming G ND G ND 1.85V 100µF 100µF Optional: Consider adding extra decoupling capacitors if the battery cannot source the peak currents. 1.85V PIN 45, 46, and 47: Refer to the BOM in the following table for notes on device-dependent configurations. 270 Copyright © 2016–2018, Texas Instruments IncorporatedApplications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com 7.1.2 Typical Application Schematic— CC3220x Preregulated, 1.85-V Mode Figure 7-2 shows the typical application schematic using the CC3220x in preregulated, 1.85-V mode of operation. For addition information on this mode of operation please contact your TI representative. Figure 7-2. CC3220x Preregulated 1.85-V Mode Application Circuit

Copyright © 2016–2018, Texas Instruments Incorporated Applications, Implementation, and Layout Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 (1) For CC3220SF device, L3 is populated. For CC3220R and CC3220S devices, L3 is not populated and Pin 47 can be used as GPIO_31. Table 7-2 lists the bill of materials for an application using the CC3120R device in preregulated 1.85-V mode. Table 7-2. Bill of Materials for CC3220x Preregulated, 1.85-V Mode QUANTITY DESIGNATOR VALUE MANUFACTURER PART NUMBER DESCRIPTION

10 C2, C6, C10, C11, C12,

C13, C17, C18, C20, C21 0.1 µF TDK C1005X5R1A104K050BA Capacitor, Ceramic, 0.1 µF, 10 V, ±10%, X5R, 0402 3 C3, C4, C5 4.7 µF TDK C1005X5R0J475M050BC Capacitor, Ceramic, 4.7 µF, 6.3 V, ±20%, X5R, 0402 2 C7, C8 100 µF Taiyo Yuden LMK325ABJ107MMHT Capacitor, Ceramic, 100 µF, 10 V, ± 20%, X5R, AEC-Q200 Grade 3, 1210 1 C9 0.5 pF MuRata GRM1555C1HR50BA01D Capacitor, Ceramic, 0.5 pF, 50 V, ±20%, C0G/NP0, 0402

1 C14 1 µF TDK C1005X5R1A105K050BB Capacitor, Ceramic, 1 µF, 10 V, ±10%, X5R, 0402

1 C15 22 µF TDK C1608X5R0G226M080AA Capacitor, Ceramic, 22 µF, 4 V, ±20%, X5R, 0603

2 C16, C19 10 µF MuRata GRM188R60J106ME47D Capacitor, Ceramic, 10 µF, 6.3 V, ±20%, X5R, 0603

2 C22, C23 10 pF MuRata GRM1555C1H100JA01D Capacitor, Ceramic, 10 pF, 50 V, ±5%, C0G/NP0, 0402

2 C24, C25 6.2 pF MuRata GRM1555C1H6R2CA01D Capacitor, Ceramic, 6.2 pF, 50 V, ±5%, C0G/NP0, 0402 Co. LTD MX25R3235FM1IL0 Ultra-low power, 32-Mbit [x 1/x 2/x 4] CMOS MXSMIO (Serial Multi I/O) Flash Memory, SOP-8 1 E1 2.45-GHz Antenna Taiyo Yuden AH316M245001-T ANT Bluetooth W-LAN Zigbee® WiMAX™ , SMD 1 FL1 1.02 dB TDK DEA202450BT-1294C1-H Multilayer Chip Band Pass Filter For 2.4GHz W-LAN/Bluetooth, SMD 1 L1 3.3 nH MuRata LQG15HS3N3S02D Inductor, Multilayer, Air Core, 3.3 nH, 0.3 A, 0.17 ohm, SMD 1 L2 2.2 µH MuRata LQM2HPN2R2MG0L Inductor, Multilayer, Ferrite, 2.2 µH, 1.3 A, 0.08 ohm, SMD 1 L3(1) 10 µH Taiyo Yuden CBC2518T100M Inductor, Wirewound, Ceramic, 10 µH, 0.48 A, 0.36 ohm, SMD 1 R1 10 k Vishay-Dale CRCW040210K0JNED Resistor, 10 k, 5%, 0.063 W, 0402 4 R2, R3, R4, R6 100 k Vishay-Dale CRCW0402100KJNED Resistor, 100 k, 5%, 0.063 W, 0402 1 R5 2.7 k Vishay-Dale CRCW04022K70JNED Resistor, 2.7 k, 5%, 0.063 W, 0402 1 R7 270 Vishay-Dale CRCW0402270RJNED Resistor, 270, 5%, 0.063 W, 0402 1 U2 CC3220 Texas Instruments CC3220SF12RGK SimpleLink™ Wi-Fi® and internet-of-things solution, a Single-Chip Wireless MCU, RGK0064B 1 Y1 Crystal Abracon Corporation ABS07-32.768KHZ-9-T Crystal, 32.768 kHZ, 9PF, SMD

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated

7.2 PCB Layout Guidelines

This section details the PCB guidelines to speed up the PCB design using the CC3220x VQFN device. Follow these guidelines ensures that the design will minimize the risk with regulatory certifications including FCC, ETSI, and CE. For more information, see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.

7.2.1 General PCB Guidelines

Use the following PCB guidelines:

• Verify the recommended PCB stackup in the PCB design guidelines, as well as the recommended layers for signals and ground.
• Ensure that the PCB footprint of the VQFN follows the information in Section 9.
• Ensure that the GND and solder paste of the VQFN PCB follow the recommendations provided in CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines.
• Decoupling capacitors must be as close as possible to the VQFN device.

7.2.2 Power Layout and Routing

Three critical DC/DC converters must be considered for the CC3220x device.

• Analog DC/DC converter
• PA DC/DC converter
• Digital DC/DC converter Each converter requires an external inductor and capacitor that must be laid out with care. DC current loops are formed when laying out the power components.

7.2.2.1 Design Considerations

The following design guidelines must be followed when laying out the CC3220x device:

• Route all of the input decoupling capacitors (C11, C13, and C18) on L2 using thick traces, to isolate the RF ground from the noisy supply ground. This step is also required to meet the IEEE spectral mask specifications.
• Maintain the thickness of power traces to be greater than 12 mils. Take special consideration for power amplifier supply lines (pins 33, 40, 41, and 42), and all input supply pins (pins 37, 39, and 44).
• Ensure the shortest grounding loop for the PLL supply decoupling capacitor (pin 24).
• Place all decoupling capacitors as close to the respective pins as possible.
• Power budget: The CC3220x device can consume up to 450 mA for 3.3 V, 670 mA for 2.1 V, and 700 mA for 1.85 V, for 24 ms during the calibration cycle.
• Ensure the power supply is designed to source this current without any issues. The complete calibration (TX and RX) can take up to 17 mJ of energy from the battery over a time of 24 ms.
• The CC3220x device contains many high-current input pins. Ensure the trace feeding these pins is capable of handling the following currents: – VIN_DCDC_PA input (pin 39) maximum is 1 A – VIN_DCDC_ANA input (pin 37) maximum is 600 mA – VIN_DCDC_DIG input (pin 44) maximum is 500 mA – DCDC_PA_SW_P (pin 40) and DCDC_PA_SW_N (pin 41) switching nodes maximum is 1 A – DCDC_PA_OUT output node (pin 42) maximum 1 A – DCDC_ANA_SW switching node (pin 38) maximum is 600 mA – DCDC_DIG_SW switching node (pin 43) maximum is 500 mA – VDD_PA_IN supply (pin 33) maximum is 500 mA

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Applications, Implementation, and LayoutCopyright © 2016–2018, Texas Instruments Incorporated Figure 7-3 shows the ground routing for the input decoupling capacitors. Figure 7-3. Ground Routing for the Input Decoupling Capacitors The ground return for the input capacitors are routed on L2 to reduce the EMI and improve the spectral mask. This routing must be strictly followed because it is critical for the overall performance of the device.

7.2.3 Clock Interfaces

The following guidelines are for the slow clock.

• The 32.768-kHz crystal must be placed close to the VQFN package.
• Ensure that the load capacitance is tuned according to the board parasitics to the frequency tolerance is within ±150 ppm.
• The ground plane on layer two is solid below the trace lanes and there is ground around these traces on the top layer. The following guidelines are for the fast clock.
• The 40-MHz crystal must be placed close to the VQFN package.
• Ensure that he load capacitance is tuned according to the board parasitics to the frequency tolerance is within ±100 ppm at room temperature. The total frequency across parts, temperature, and with aging, must be ±25 ppm to meet the WLAN specification.
• Ensure that no high-frequency lines are routed close to the crystal routing to avoid noise degradation.
• Ensure that crystal tuning capacitors are close to the crystal pads.
• Make both traces (XTAL_N and XTAL_P) as close to parallel as possible and approximately the same length.
• The ground plane on layer two is solid below the trace lines and that there is ground around these traces on the top layer.
• See CC31xx & CC32xx Frequency Tuning for frequency tuning.

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Applications, Implementation, and Layout Copyright © 2016–2018, Texas Instruments Incorporated

7.2.4 Digital Input and Output

The following guidelines are for the digital I/O.

• Route SPI and UART lines away from any RF traces.
• Keep the length of the high-speed lines as short as possible to avoid transmission line effects.
• Keep the line lower than 1/10 of the rise time of the signal to ignore transmission line effects. This is required if the traces cannot be kept short. Place the resistor at the source end, closer to the device that is driving the signal.
• Add a series-terminating resistor for each high-speed line (such as SPI_CLK or SPI_DATA) to match the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line impedance.
• Route high-speed lines with a ground reference plane continuously below it to offer good impedance throughout. This routing also helps shield the trace against EMI.
• Avoid stubs on high-speed lines to minimize the reflections. If the line must be routed to multiple locations, use a separate line driver for each line.
• If the lines are longer compared to the rise time, add series-terminating resistors near the driver for each high-speed line to match the driver impedance to the line. Typical terminating-resistor values range from 27 to 36 Ω for a 50-Ω line impedance.

7.2.5 RF Interface

The following guidelines are for the RF interface. Follow guidelines specified in the vendor-specific antenna design guides (including placement of the antenna). Also see CC3120 and CC3220 SimpleLink™ Wi-Fi® and IoT Solution Layout Guidelines for general antenna guidelines.

• Ensure that the antenna is matched for 50-Ω. TI recommends using a Pi-matching network.
• Ensure that the area underneath the BPF pads is grounded on layer one and layer two, and ensure that the minimum filter requirements are met.
• Verify that the Wi-Fi RF trace is a 50-Ω, impedance-controlled trace with a reference to solid ground.
• The RF trace bends must be made with gradual curves. Avoid using 90-degree bends.
• The RF traces must not have sharp corners.
• Do not place traces or ground under the antenna section.
• The RF traces must have via stitching on the ground plane beside the RF trace on both sides.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation SupportCopyright © 2016–2018, Texas Instruments Incorporated

8 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed in this section.

8.1 Development Tools and Software

For the most up-to-date list of development tools and software, see the CC3220 Tools & Software product page. Users can also click the "Alert Me" button on the top right corner of the CC3220 Tools & Software page to stay informed about updates related to the CC3220MOD device. Development Tools Pin Mux Tool The supported devices are: CC3200 and CC3220x. The Pin Mux Tool is a software tool that provides a graphical user interface (GUI) for configuring pin multiplexing settings, resolving conflicts and specifying I/O cell characteristics for MPUs from TI. Results are output as C header/code files that can be imported into software development kits (SDKs) or used to configure customers' custom software. Version 3 of the Pin Mux Tool adds the capability of automatically selecting a mux configuration that satisfies the entered requirements. SimpleLink™ Wi-Fi® Starter Pro The supported devices are: CC3100, CC3200, CC3120R, and CC3220x. The SimpleLink™ Wi-Fi® Starter Pro mobile App is a new mobile application for SimpleLink provisioning. The app goes along with the embedded provisioning library and example that runs on the device side (see SimpleLink™ Wi-Fi® CC3120 SDK plugin and TI SimpleLink™ Wi-Fi® CC3220 Software Development Kit (SDK)). The new provisioning release is a TI recommendation for Wi-Fi provisioning using SimpleLink Wi-Fi products. The provisioning release implements advanced AP mode and SmartConfig™ technology provisioning with feedback and fallback options to ensure successful process has been accomplished. Customers can use both embedded library and the mobile library for integration to their end products. SimpleLink™ Wi-Fi® Radio Testing Tool The supported devices are: CC3100, CC3200, and CC3220x. The SimpleLink™ Wi-Fi® Radio Testing Tool is a Windows-based software tool for RF evaluation and testing of SimpleLink Wi-Fi CC3120 and CC3220 designs during development and certification. The tool enables low-level radio testing capabilities by manually setting the radio into transmit or receive modes. Using the tool requires familiarity and knowledge of radio circuit theory and radio test methods. Created for the Internet of Things (IoT), the SimpleLink Wi-Fi CC31xx and CC32xx family of devices include on-chip Wi-Fi, Internet, and robust security protocols with no prior Wi-Fi experience needed for faster development. For more information on these devices, visit SimpleLink™ Wi-Fi® family, Internet-on-a chip™ solutions. CC3220 Software Development Kit (SDK) The CC3220x device is supported. The CC3220 SDK contains drivers, many sample applications for Wi-Fi features and Internet, as well as documentation needed to use the CC3220 Internet-on-a-chip solution. This SDK can be used with TI’s MSP432P401R LaunchPad™ development kit, or with the SimpleLink Studio, a PC tool that allows MCU development with CC3220. You can also use the SDK as example code for any platform. All sample applications in the SDK are supported on TI’s MSP432P401R ultra-low-power MCUs with Code Composer Studio™ IDE and TI- RTOS. In addition, many of the applications support IAR. Uniflash Standalone Flash Tool for TI Microcontrollers (MCU), Sitara Processors & SimpleLink Devices CCS Uniflash is a standalone tool used to program on-chip flash memory on TI MCUs and on-board flash memory for Sitara processors. Uniflash has a GUI, command line, and scripting interface. CCS Uniflash is available free of charge.

M2 = 256KB RAM 12 = 1MB flash and 256KB RAM PREFIX CC 3220 x xx x xxx x DEVICE FAMILY CC = wireless connectivity SERIES NUMBER 3 = Wi-Fi Centric PACKAGE RGK = 9-mm × 9-mm VQFN PACKAGING R = tape/reel T = small reel MEMORY SIZE A = Revision A REVISION R = ROM S = Secured SF = Secured flash MEMORY X = preproduction device no prefix = production device CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation Support Copyright © 2016–2018, Texas Instruments Incorporated TI Designs and Reference Designs The TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor, and connectivity. Created by TI experts to help you jumpstart your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

8.2 Firmware Updates

TI updates features in the service pack for this module with no published schedule. Due to the ongoing changes, TI recommends that the user has the latest service pack in their module for production. To stay informed, click the SDK “Alert me” button the top right corner of the product page, or visit SimpleLink™ Wi-Fi® CC3120 SDK plugin.

8.3 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of the CC3220x device and support tools (see Figure 8-1). Figure 8-1. CC3220x Device Nomenclature

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation SupportCopyright © 2016–2018, Texas Instruments Incorporated

8.4 Documentation Support

To receive notification of documentation updates— including silicon errata— go to the product folder for your device on ti.com (CC3220). In the upper right corner, click the "Alert me" button. This registers you to receive a weekly digest of product information that has changed (if any). For change details, check the revision history of any revised document. The current documentation that describes the processor, related peripherals, and other technical collateral follows. The following documents provide support for the CC3220 device. Errata CC3220R, CC3220S Silicon Errata This document describes the known exceptions to the functional specifications for the CC3220R and the CC3220S SimpleLink™ Wi-Fi® Wireless and Internet-of-Things Solution, a Single-Chip Wireless MCU. CC3220SF Silicon Errata This document describes the known exception to the functional specifications for the CC3220SF SimpleLink™ Wi-Fi® Wireless and Internet-of-Things Solution, a Single- Chip Wireless MCU. Application Reports CC3120 and CC3220 SimpleLink™ Wi-Fi® Embedded Programming CC3120 and CC3220 SimpleLink™ Wi-Fi® Embedded Programming SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Networking Sub-System Power Management This application report describes the best practices for power management and extended battery life for embedded low-power Wi-Fi devices such as the SimpleLink™ Wi-Fi® Internet- on-a chip™ solution from Texas Instruments™ . SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Solution Built-In Security Features The SimpleLink™ Wi-Fi® CC3120 and CC3220 Internet-on-a chip™ family of devices from Texas Instruments™ offer a wide range of built-in security features to help developers address a variety of security needs, which is achieved without any processing burden on the main microcontroller (MCU). This document describes these security-related features and provides recommendations for leveraging each in the context of practical system implementation. SimpleLink™ CC3120, CC3220 Wi-Fi® and Internet of Things Over-the-Air Update This document describes the OTA library for the SimpleLink™ Wi-Fi® CC3x20 family of devices from Texas Instruments™ and explains how to prepare a new cloud-ready update to be downloaded by the OTA library. SimpleLink™ CC3120, CC3220 Wi-Fi® Internet-on-a chip™ Solution Device Provisioning This guide describes the provisioning process, which provides the SimpleLink™ Wi-Fi® device with the information (network name, password, and so forth) needed to connect to a wireless network. Transfer of TI's Wi-Fi® Alliance Certifications to Products Based on SimpleLink™ This document explains how to employ the Wi-Fi® Alliance (WFA) derivative certification transfer policy to transfer a WFA certification, already obtained by Texas Instruments, to a system you have developed. Using Serial Flash on SimpleLink™ CC3120 and CC3220 Wi-Fi® and Internet-of-Things Devices This application note is divided into two parts. The first part provides important guidelines and best- practice design techniques to consider when choosing and embedding a serial Flash paired with the CC3120 and CC3220 (CC3x20) devices. The second part describes the file system, along with guidelines and considerations for system designers working with the CC3x20 devices.

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation Support Copyright © 2016–2018, Texas Instruments Incorporated User's Guides SimpleLink™ Wi-Fi® and Internet of Things CC3120 and CC3220 Network Processor This document provides software (SW) programmers with all of the required knowledge for working with the networking subsystem of the SimpleLink™ Wi-Fi® devices. This guide provides basic guidelines for writing robust, optimized networking host applications, and describes the capabilities of the networking subsystem. The guide contains some example code snapshots, to give users an idea of how to work with the host driver. More comprehensive code examples can be found in the formal software development kit (SDK). This guide does not provide a detailed description of the host driver APIs. SimpleLink™ Wi-Fi® CC3120 and CC3220 and IoT Solution Layout Guidelines This document provides the design guidelines of the 4-layer PCB used for the CC3120 and CC3220 SimpleLink™ Wi-Fi® family of devices from Texas Instruments™ . The CC3120 and CC3220 devices are easy to lay out and are available in quad flat no-leads (QFNS) packages. When designing the board, follow the suggestions in this document to optimize performance of the board. SimpleLink™ Wi-Fi® and Internet of Things Solution CC3220, a Single-Chip Wireless MCUThis guide is intended to assist users in the initial setup and demonstration of running their first sample application for the CC3220, CC3220S, CC3220SF SimpleLink™ Wi-Fi® and Internet of Things Solution, a Single-Chip Wireless MCU from Texas Instruments™ . The guide explains how to install the software development kit (SDK) and various other tools required to get started with the first application. SimpleLink™ CC3220 Wi-Fi® LaunchPad™ Development Kit HardwareThe CC3220 SimpleLink LaunchPad™ Development Kit (CC3220-LAUNCHXL) is a low-cost evaluation platform for Arm® Cortex®-M4-based MCUs. The LaunchPad design highlights the CC3220 Internet-on-a chip™ solution and Wi-Fi capabilities. The CC3220 LaunchPad also features temperature and accelerometer sensors, programmable user buttons, three LEDs for custom applications, and onboard emulation for debugging. The stackable headers of the CC3220 LaunchPad XL interface demonstrate how easy it is to expand the functionality of the LaunchPad when interfacing with other peripherals on many existing BoosterPack™ Plug-in Module add-on boards, such as graphical displays, audio codecs, antenna selection, environmental sensing, and more. SimpleLink™ Wi-Fi® and Internet of Things CC3220This document introduces the user to the environment setup for the CC3220x device, along with some reference examples from the software development kit (SDK). This document explains both the platform and the framework available to enable further application development. SimpleLink™ Wi-Fi® CC3220 Out-of-Box ApplicationThis guide demonstrates the out-of-box experience for the CC3220 LaunchPad™ Development Kit, highlighting the easy connection to the CC3220 LaunchPad using the SimpleLink™ Wi-Fi® Starter Pro application, and the over-the-air update. SimpleLink™ Wi-Fi® and Internet-on-a-chip™ CC3120 and CC3220 Solution Radio Tool The Radio Tool serves as a control panel for direct access to the radio, and can be used for both the radio frequency (RF) evaluation and for certification purposes. This guide describes how to have the tool work seamlessly on Texas Instruments™ evaluation platforms such as the BoosterPack™ plus FTDI emulation board for CC3120 devices, and the LaunchPad™ for CC3220 devices. SimpleLink™ Wi-Fi® CC3120 and CC3220 Provisioning for Mobile ApplicationsThis guide describes TI’s SimpleLink™ Wi-Fi® provisioning solution for mobile applications, specifically on the usage of the Android™ and iOS® building blocks for UI requirements, networking, and provisioning APIs required for building the mobile application. SimpleLink™ Wi-Fi® CC3220 Out-of-Box ApplicationThis guide details the out-of-box (OOB) experience with the CC3220 LaunchPad™ Development Kit from Texas Instruments™ . UniFlash CC3120 and CC3220 SimpleLink™ Wi-Fi® and Internet-on-a chip™ Solution ImageCreator and Programming Tool This document describes the installation, operation, and usage of the SimpleLink ImageCreator tool as part of the UniFlash.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation SupportCopyright © 2016–2018, Texas Instruments Incorporated More Literature CC3220, CC3220S, CC3220SF SimpleLink™ Wi-Fi® and Internet of ThingsThis technical reference manual details the modules and peripherals of the SimpleLink™ CC32xx wireless MCU. Each description presents the module or peripheral in a general sense. Not all features and functions of all modules or peripherals may be present on all devices. Pin functions, internal signal connections, and operational parameters differ from device to device. The user should consult the device-specific data sheet for these details. RemoTI Manifest CC3120, CC3220 SimpleLink™ Wi-Fi® and Internet of Things Design Checklist CC3220 SimpleLink™ Wi-Fi® and Internet of Things CC3220 hardware design files.

8.5 Related Links

The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to order now. Table 8-1. Related Links PARTS PRODUCT FOLDER ORDER NOW TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY CC3220R Click here Click here Click here Click here Click here CC3220S Click here Click here Click here Click here Click here CC3220SF Click here Click here Click here Click here Click here

8.6 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community The TI engineer-to-engineer (E2E) community was created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

8.7 Trademarks

SmartConfig, SimpleLink, LaunchPad, Code Composer Studio, E2E are trademarks of Texas Instruments. Arm, Cortex, Thumb are registered trademarks of Arm Limited. Macrocell is a trademark of Kappa Global Inc. Wi-Fi CERTIFIED, WPA, WPA2 are trademarks of Wi-Fi Alliance. Wi-Fi Alliance, Wi-Fi Direct are registered trademarks of Wi-Fi Alliance. WiMAX is a trademark of WiMAX Forum. Zigbee is a registered trademark of Zigbee Alliance. All other trademarks are the property of their respective owners.

CC3220R, CC3220S, CC3220SF SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 www.ti.com Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Device and Documentation Support Copyright © 2016–2018, Texas Instruments Incorporated

8.8 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.9 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from disclosing party under nondisclosure obligations (if any), or any direct product of such technology, to any destination to which such export or re-export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

8.10 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

CC3220R, CC3220S, CC3220SF www.ti.com SWAS035B –SEPTEMBER 2016–REVISED NOVEMBER 2018 Submit Documentation Feedback Product Folder Links: CC3220R CC3220S CC3220SF Mechanical, Packaging, and Orderable InformationCopyright © 2016–2018, Texas Instruments Incorporated

9 Mechanical, Packaging, and Orderable Information

9.1 Packaging Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

www.ti.com 6-Mar-2017 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CC3220RM2ARGKR ACTIVE VQFN RGK 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220R M2A CC3220RM2ARGKT ACTIVE VQFN RGK 64 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220R M2A CC3220SF12ARGKR ACTIVE VQFN RGK 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220SF 12A CC3220SF12ARGKT ACTIVE VQFN RGK 64 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220SF 12A CC3220SM2ARGKR ACTIVE VQFN RGK 64 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220S M2A CC3220SM2ARGKT ACTIVE VQFN RGK 64 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-3-260C-168 HR -40 to 85 CC3220S M2A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 6-Mar-2017 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC3220RM2ARGKR VQFN RGK 64 2500 367.0 367.0 38.0 CC3220RM2ARGKT VQFN RGK 64 250 210.0 185.0 35.0 CC3220SF12ARGKR VQFN RGK 64 2500 367.0 367.0 38.0 CC3220SF12ARGKT VQFN RGK 64 250 210.0 185.0 35.0 CC3220SM2ARGKR VQFN RGK 64 2500 367.0 367.0 38.0 CC3220SM2ARGKT VQFN RGK 64 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2017 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 9.1 8.9 9.1 8.9 1.0 0.8 0.05 0.00 2X 7.5 60X 0.5 2X 7.5 64X 0.5 0.3 64X 0.30 0.18 6.3 0.1 (0.2) TYP VQFN - 1 mm max heightRGK0064B PLASTIC QUAD FLATPACK - NO LEAD 4222201/B 03/2018 0.08 C

0.1 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM EXPOSED THERMAL PAD SYMM 17 32 4964 SCALE 1.500 AB

www.ti.com EXAMPLE BOARD LAYOUT 60X (0.5) ( 0.2) TYP VIA (R0.05) TYP

0.07 MAX

0.07 MIN

64X (0.6) 64X (0.24) (8.8) (8.8) ( 6.3) (0.6) TYP 18X (1.2) 8X (1.1) (0.6) TYP 18X (1.2) (1.1) VQFN - 1 mm max heightRGK0064B PLASTIC QUAD FLATPACK - NO LEAD 4222201/B 03/2018 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SEE SOLDER MASK DETAIL 17 32 4964 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 64X (0.6) 64X (0.24) 60X (0.5) (8.8) (8.8) 25X ( 1) (R0.05) TYP (1.2) TYP (1.2) TYP VQFN - 1 mm max heightRGK0064B PLASTIC QUAD FLATPACK - NO LEAD 4222201/B 03/2018 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 MM THICK STENCIL SCALE: 10X EXPOSED PAD 65 63% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SYMM SYMM 17 32 4964 METAL TYP

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