CC2650F128RGZR

CC2650_16 TI1 | Alldatasheet

Document overview

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Technical content

Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 CC2650SimpleLink™ MultistandardWirelessMCU

1 Device Overview

1.1 Features

– Very Few External Components• Microcontroller – Seamless Integration With the SimpleLink™– Powerful ARM® Cortex®-M3 CC2590 and CC2592 Range Extenders– EEMBC CoreMark® Score: 142 – Active-Mode Sensor Controller: 8.2 µA/MHz• Efficient Code Size Architecture, Placing Drivers, – Standby: 1 µA (RTC Running and RAM/CPUBluetooth® Low Energy Controller, IEEE 802.15.4 Retention)MAC, and Bootloader in ROM – Shutdown: 100 nA (Wake Up on External• RoHS-Compliant Packages Events)– 4-mm × 4-mm RSM VQFN32 (10 GPIOs)

• RF Section– 5-mm × 5-mm RHB VQFN32 (15 GPIOs) An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

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1.2 Applications

• Consumer Electronics • Alarm and Security
• Mobile Phone Accessories • Electronic Shelf Labeling
• Sports and Fitness Equipment • Proximity Tags
• HID Applications • Medical
• Home and Building Automation • Remote Controls
• Lighting Control • Wireless Sensor Networks

1.3 Description

The CC2650 device is a wireless MCU targeting Bluetooth Smart, ZigBee® and 6LoWPAN, and ZigBee RF4CE remote control applications. The device is a member of the CC26xx family of cost-effective, ultralow power, 2.4-GHz RF devices. Very low active RF and MCU current and low-power mode current consumption provide excellent battery lifetime and allow for operation on small coin cell batteries and in energy-harvesting applications. The CC2650 device contains a 32-bit ARM Cortex-M3 processor that runs at 48 MHz as the main processor and a rich peripheral feature set that includes a unique ultralow power sensor controller. This sensor controller is ideal for interfacing external sensors and for collecting analog and digital data autonomously while the rest of the system is in sleep mode. Thus, the CC2650 device is ideal for applications within a whole range of products including industrial, consumer electronics, and medical. The Bluetooth Low Energy controller and the IEEE 802.15.4 MAC are embedded into ROM and are partly running on a separate ARM Cortex-M0 processor. This architecture improves overall system performance and power consumption and frees up flash memory for the application. The Bluetooth Smart and ZigBee stacks are available free of charge from www.ti.com. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CC2650F128RGZ VQFN (48) 7.00 mm × 7.00 mm CC2650F128RHB VQFN (32) 5.00 mm × 5.00 mm CC2650F128RSM VQFN (32) 4.00 mm × 4.00 mm (1) For more information, see Section 9, Mechanical Packaging and Orderable Information.

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1.4 Functional Block Diagram

Figure 1-1 shows a block diagram for the CC2650. Figure 1-1. Block Diagram Copyright © 2015, Texas Instruments Incorporated Device Overview 3 Submit Documentation Feedback Product Folder Links: CC2650

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4 Table of Contents Copyright © 2015, Texas Instruments Incorporated

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from February 21, 2015 to October 15, 2015 Page Copyright © 2015, Texas Instruments Incorporated Revision History 5 Submit Documentation Feedback Product Folder Links: CC2650

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3 Device Comparison

Table 3-1. Device Family Overview FLASHDEVICE PHY SUPPORT RAM (KB) GPIO PACKAGE(1) (KB) CC2650F128xxx Multi-Protocol(2) 128 20 31, 15, 10 RGZ, RHB, RSM CC2640F128xxx Bluetooth low energy 128 20 31, 15, 10 RGZ, RHB, RSM CC2630F128xxx IEEE 802.15.4 Zigbee(/6LoWPAN) 128 20 31, 15, 10 RGZ, RHB, RSM CC2620F128xxx IEEE 802.15.4 (RF4CE) 128 20 31, 10 RGZ, RSM (1) Package designator replaces the xxx in device name to form a complete device name, RGZ is 7-mm × 7-mm VQFN48, RHB is 5-mm × 5-mm VQFN32, and RSM is 4-mm × 4-mm VQFN32. (2) The CC2650 device supports all PHYs and can be reflashed to run all the supported standards.

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DIO_25 38 DIO_24 37 DCDC_SW33 DIO_18 RESET_N35 DIO_2336 X32K_Q2 4 X32K_Q1 3 RF_N 2 RF_P 1 DIO_2232 DIO_2131 DIO_2030 DIO_1929 DIO_0 5 DIO_1 6 DIO_2 7 JTAG_TCKC25 CC26xx QFN48 7x7 RGZ DIO_15 DIO_14 VDDR 45 VDDR_RF 48 DIO_17 DIO_16 VDDS_DCDC DIO_26 DIO_12 DIO_13 VDDS2 DIO_11 DIO_10 DIO_5 DIO_6 DIO_7 DIO_3 DIO_4 X24M_P X24M_N DIO_8 DIO_9 DIO_28 VDDS3 DCOUPL JTAG_TMSC DIO_29 DIO_30 DIO_27 VDDS CC2650 www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

4 Terminal Configuration and Functions

4.1 Pin Diagram – RGZ Package

Note: I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities. Figure 4-1. RGZ (7-mm × 7-mm) Pinout, 0.5-mm Pitch

4.2 Signal Descriptions – RGZ Package

Table 4-1. Signal Descriptions – RGZ Package NAME NO. TYPE DESCRIPTION DCDC_SW 33 Power Output from internal DC-DC(1) DCOUPL 23 Power 1.27-V regulated digital-supply decoupling capacitor(2) DIO_0 5 Digital I/O GPIO, Sensor Controller DIO_1 6 Digital I/O GPIO, Sensor Controller DIO_2 7 Digital I/O GPIO, Sensor Controller DIO_3 8 Digital I/O GPIO, Sensor Controller DIO_4 9 Digital I/O GPIO, Sensor Controller DIO_5 10 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_6 11 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_7 12 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_8 14 Digital I/O GPIO DIO_9 15 Digital I/O GPIO DIO_10 16 Digital I/O GPIO DIO_11 17 Digital I/O GPIO (1) See Section 8.2, technical reference manual for more details. (2) Do not supply external circuitry from this pin. Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 7 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Table 4-1. Signal Descriptions – RGZ Package (continued) NAME NO. TYPE DESCRIPTION DIO_12 18 Digital I/O GPIO DIO_13 19 Digital I/O GPIO DIO_14 20 Digital I/O GPIO DIO_15 21 Digital I/O GPIO DIO_16 26 Digital I/O GPIO, JTAG_TDO, high-drive capability DIO_17 27 Digital I/O GPIO, JTAG_TDI, high-drive capability DIO_18 28 Digital I/O GPIO DIO_19 29 Digital I/O GPIO DIO_20 30 Digital I/O GPIO DIO_21 31 Digital I/O GPIO DIO_22 32 Digital I/O GPIO DIO_23 36 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_24 37 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_25 38 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_26 39 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_27 40 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_28 41 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_29 42 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_30 43 Digital/Analog I/O GPIO, Sensor Controller, Analog JTAG_TMSC 24 Digital I/O JTAG TMSC, high-drive capability JTAG_TCKC 25 Digital I/O JTAG TCKC RESET_N 35 Digital input Reset, active-low. No internal pullup. Positive RF input signal to LNA during RXRF_P 1 RF I/O Positive RF output signal to PA during TX Negative RF input signal to LNA during RXRF_N 2 RF I/O Negative RF output signal to PA during TX VDDR 45 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(3)(2) VDDR_RF 48 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(4)(2) VDDS 44 Power 1.8-V to 3.8-V main chip supply(1) VDDS2 13 Power 1.8-V to 3.8-V DIO supply(1) VDDS3 22 Power 1.8-V to 3.8-V DIO supply(1) VDDS_DCDC 34 Power 1.8-V to 3.8-V DC-DC supply X32K_Q1 3 Analog I/O 32-kHz crystal oscillator pin 1 X32K_Q2 4 Analog I/O 32-kHz crystal oscillator pin 2 X24M_N 46 Analog I/O 24-MHz crystal oscillator pin 1 X24M_P 47 Analog I/O 24-MHz crystal oscillator pin 2 EGP Power Ground – Exposed Ground Pad (3) If internal DC-DC is not used, this pin is supplied internally from the main LDO. (4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.

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30 QFN32 5x5

DIO_10 DIO_7 DIO_9 DIO_8 DCDC_SW RESET_N VDDS_DCDC DIO_11 VDDR_RF X24M_N X24M_P VDDR VDDS DIO_13 DIO_14 DIO_12 DIO_3 JTAG_TMSC DIO_4 DCOUPL VDDS2 JTAG_TCKC DIO_5 DIO_6 RF_P RF_N RX_TX DIO_0 DIO_1 DIO_2 X32K_Q1 X32K_Q2 CC2650 www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

4.3 Pin Diagram – RHB Package

Note: I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities. Figure 4-2. RHB (5-mm × 5-mm) Pinout, 0.5-mm Pitch

4.4 Signal Descriptions – RHB Package

Table 4-2. Signal Descriptions – RHB Package NAME NO. TYPE DESCRIPTION DCDC_SW 17 Power Output from internal DC-DC(1) DCOUPL 12 Power 1.27-V regulated digital-supply decoupling(2) DIO_0 6 Digital I/O GPIO, Sensor Controller DIO_1 7 Digital I/O GPIO, Sensor Controller DIO_2 8 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_3 9 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_4 10 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_5 15 Digital I/O GPIO, High drive capability, JTAG_TDO DIO_6 16 Digital I/O GPIO, High drive capability, JTAG_TDI DIO_7 20 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_8 21 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_9 22 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_10 23 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_11 24 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_12 25 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_13 26 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_14 27 Digital/Analog I/O GPIO, Sensor Controller, Analog JTAG_TMSC 13 Digital I/O JTAG TMSC, high-drive capability JTAG_TCKC 14 Digital I/O JTAG TCKC RESET_N 19 Digital input Reset, active-low. No internal pullup. (1) See Section 8.2, technical reference manual for more details. (2) Do not supply external circuitry from this pin. Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 9 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Table 4-2. Signal Descriptions – RHB Package (continued) NAME NO. TYPE DESCRIPTION Negative RF input signal to LNA during RXRF_N 2 RF I/O Negative RF output signal to PA during TX Positive RF input signal to LNA during RXRF_P 1 RF I/O Positive RF output signal to PA during TX RX_TX 3 RF I/O Optional bias pin for the RF LNA VDDR 29 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(3)(2) VDDR_RF 32 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(4)(2) VDDS 28 Power 1.8-V to 3.8-V main chip supply(1) VDDS2 11 Power 1.8-V to 3.8-V GPIO supply(1) VDDS_DCDC 18 Power 1.8-V to 3.8-V DC-DC supply X32K_Q1 4 Analog I/O 32-kHz crystal oscillator pin 1 X32K_Q2 5 Analog I/O 32-kHz crystal oscillator pin 2 X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1 X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2 EGP Power Ground – Exposed Ground Pad (3) If internal DC-DC is not used, this pin is supplied internally from the main LDO. (4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.

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30 QFN32 4x4

DIO_6 VSS DIO_5 RESET_N VSS VDDS_DCDC DCDC_SW DIO_7 VDDR_RF X24M_N X24M_P VSS VDDR DIO_9 VDDS DIO_8 DIO_1 JTAG_TMSC DIO_2 DCOUPL VDDS2 JTAG_TCKC DIO_3 DIO_4 RF_P RF_N VSS X32K_Q2 VSS DIO_0 RX_TX X32K_Q1 CC2650 www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

4.5 Pin Diagram – RSM Package

Note: I/O pins marked in bold have high drive capabilities. I/O pins marked in italics have analog capabilities. Figure 4-3. RSM (4-mm × 4-mm) Pinout, 0.4-mm Pitch

4.6 Signal Descriptions – RSM Package

Table 4-3. Signal Descriptions – RSM Package NAME NO. TYPE DESCRIPTION Output from internal DC-DC. (1). Tie to ground for external regulator modeDCDC_SW 18 Power (1.7-V to 1.95-V operation) DCOUPL 12 Power 1.27-V regulated digital-supply decoupling capacitor(2) DIO_0 8 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_1 9 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_2 10 Digital I/O GPIO, Sensor Controller, high-drive capability DIO_3 15 Digital I/O GPIO, High drive capability, JTAG_TDO DIO_4 16 Digital I/O GPIO, High drive capability, JTAG_TDI DIO_5 22 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_6 23 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_7 24 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_8 25 Digital/Analog I/O GPIO, Sensor Controller, Analog DIO_9 26 Digital/Analog I/O GPIO, Sensor Controller, Analog JTAG_TMSC 13 Digital I/O JTAG TMSC JTAG_TCKC 14 Digital I/O JTAG TCKC RESET_N 21 Digital Input Reset, active-low. No internal pullup. Negative RF input signal to LNA during RXRF_N 2 RF I/O Negative RF output signal to PA during TX Positive RF input signal to LNA during RXRF_P 1 RF I/O Positive RF output signal to PA during TX RX_TX 4 RF I/O Optional bias pin for the RF LNA (1) See Section 8.2, technical reference manual for more details. (2) Do not supply external circuitry from this pin. Copyright © 2015, Texas Instruments Incorporated Terminal Configuration and Functions 11 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Table 4-3. Signal Descriptions – RSM Package (continued) NAME NO. TYPE DESCRIPTION VDDR 28 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC. (3)(2) VDDR_RF 32 Power 1.7-V to 1.95-V supply, typically connect to output of internal DC-DC(4)(2) VDDS 27 Power 1.8-V to 3.8-V main chip supply(1) VDDS2 11 Power 1.8-V to 3.8-V GPIO supply(1) 3, 7, 17, 20, GroundVSS Power29 X32K_Q1 5 Analog I/O 32-kHz crystal oscillator pin 1 X32K_Q2 6 Analog I/O 32-kHz crystal oscillator pin 2 X24M_N 30 Analog I/O 24-MHz crystal oscillator pin 1 X24M_P 31 Analog I/O 24-MHz crystal oscillator pin 2 EGP Power Ground – Exposed Ground Pad (3) If internal DC-DC is not used, this pin is supplied internally from the main LDO. (4) If internal DC-DC is not used, this pin must be connected to VDDR for supply from the main LDO.

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2) MIN MAX UNIT VDDR supplied by internal DC-DC regulator orSupply voltage, VDDS(3) –0.3 4.1 Vinternal GLDO Supply voltage, VDDS(3) and External regulator mode (VDDS and VDDR pins –0.3 2.25 VVDDR connected on PCB) Voltage on any digital pin(4) –0.3 VDDS + 0.3, max 4.1 V Voltage on crystal oscillator pins, X32K_Q1, X32K_Q2, X24M_N and X24M_P –0.3 VDDR + 0.3, max 2.25 V Voltage scaling enabled –0.3 VDDS Voltage on ADC input (Vin) Voltage scaling disabled, internal reference –0.3 1.49 V Voltage scaling disabled, VDDS as reference –0.3 VDDS / 2.9 Input RF level 5 dBm Tstg Storage temperature –40 150 °C (1) All voltage values are with respect to ground, unless otherwise noted. (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (3) VDDS2 and VDDS3 must be at the same potential as VDDS. (4) Including analog-capable DIO.

5.2 ESD Ratings

Human body model (HBM), per ANSI/ESDA/JEDEC All pins ±2500JS001(1) Electrostatic dischargeVESD V(ESD) performance RF pins ±750 Charged device model (CDM), per JESD22-C101(2) Non-RF pins ±750 (1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT Ambient temperature range –40 85 °C Operating supply voltage For operation in 1.8-V systems (VDDS and VDDR), external (VDDS and VDDR pins connected on PCB, internal DC-DC 1.7 1.95 V regulator mode cannot be used) Operating supply voltage For operation in battery-powered and 3.3-V systems 1.8 3.8 V(VDDS) (internal DC-DC can be used to minimize power consumption) Copyright © 2015, Texas Instruments Incorporated Specifications 13 Submit Documentation Feedback Product Folder Links: CC2650

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5.4 Power Consumption Summary

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V with internal DC-DC converter, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Reset. RESET_N pin asserted or VDDS below 100Power-on-Reset threshold nA Shutdown. No clocks running, no retention 150 Standby. With RTC, CPU, RAM and (partial) 1register retention. RCOSC_LF Standby. With RTC, CPU, RAM and (partial) 1.2register retention. XOSC_LF Standby. With Cache, RTC, CPU, RAM and µA2.5(partial) register retention. RCOSC_LF Icore Core current consumption Standby. With Cache, RTC, CPU, RAM and 2.7(partial) register retention. XOSC_LF Idle. Supply Systems and RAM powered. 550 1.45 mA +Active. Core running CoreMark 31 µA/MHz Radio RX (1) 5.9 Radio RX(2) 6.1 mA Radio TX, 0-dBm output power(1) 6.1 Radio TX, 5-dBm output power(2) 9.1 Peripheral Current Consumption (Adds to core current Icore for each peripheral unit activated)(3) Peripheral power domain Delta current with domain enabled 20 µA Serial power domain Delta current with domain enabled 13 µA Delta current with power domain enabled, clockRF Core 237 µAenabled, RF core idle µDMA Delta current with clock enabled, module idle 130 µA Iperi Timers Delta current with clock enabled, module idle 113 µA I2C Delta current with clock enabled, module idle 12 µA I2S Delta current with clock enabled, module idle 36 µA SSI Delta current with clock enabled, module idle 93 µA UART Delta current with clock enabled, module idle 164 µA (1) Single-ended RF mode is optimized for size and power consumption. Measured on CC2650EM-4XS. (2) Differential RF mode is optimized for RF performance. Measured on CC2650EM-5XD. (3) Iperi is not supported in Standby or Shutdown.

5.5 General Characteristics

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT FLASH MEMORY Supported flash erase cycles before 100 k Cyclesfailure Flash page/sector erase current Average delta current 12.6 mA Flash page/sector size 4 KB Flash write current Average delta current, 4 bytes at a time 8.15 mA Flash page/sector erase time(1) 8 ms Flash write time(1) 4 bytes at a time 8 µs (1) This number is dependent on Flash aging and will increase over time and erase cycles.

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 5.6 1-Mbps GFSK (Bluetooth Low Energy) – RX Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, fRF = 2440 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential mode. Measured at the CC2650EM-5XDReceiver sensitivity –97 dBmSMA connector, BER = 10–3 Single-ended mode. Measured on CC2650EM-4XS,Receiver sensitivity –96 dBmat the SMA connector, BER = 10–3 Differential mode. Measured at the CC2650EM-5XDReceiver saturation 4 dBmSMA connector, BER = 10–3 Single-ended mode. Measured on CC2650EM-4XS,Receiver saturation 0 dBmat the SMA connector, BER = 10–3 Difference between the incoming carrier frequencyFrequency error tolerance –350 350 kHzand the internally generated carrier frequency Difference between incoming data rate and theData rate error tolerance –750 750 ppminternally generated data rate Wanted signal at –67 dBm, modulated interferer in Co-channel rejection (1) channel, –6 dB BER = 10–3 Wanted signal at –67 dBm, modulated interferer at Selectivity, ±1 MHz (1) ±1 MHz, 7 / 3(2) dB BER = 10–3 Wanted signal at –67 dBm, modulated interferer at Selectivity, ±2 MHz (1) ±2 MHz, 34 / 25(2) dB BER = 10–3 Wanted signal at –67 dBm, modulated interferer at Selectivity, ±3 MHz (1) ±3 MHz, 38 / 26(2) dB BER = 10–3 Wanted signal at –67 dBm, modulated interferer at Selectivity, ±4 MHz (1) ±4 MHz, 42 / 29(2) dB BER = 10–3 Wanted signal at –67 dBm, modulated interferer at ≥Selectivity, ±5 MHz or more(1) 32 dB±5 MHz, BER = 10–3 Wanted signal at –67 dBm, modulated interferer at Selectivity, Image frequency(1) image frequency, 25 dB BER = 10–3 Selectivity, Image frequency Wanted signal at –67 dBm, modulated interferer at 3 / 26(2) dB±1 MHz(1) ±1 MHz from image frequency, BER = 10–3 Out-of-band blocking (3) 30 MHz to 2000 MHz –20 dBm Out-of-band blocking 2003 MHz to 2399 MHz –5 dBm Out-of-band blocking 2484 MHz to 2997 MHz –8 dBm Out-of-band blocking 3000 MHz to 12.75 GHz –8 dBm Wanted signal at 2402 MHz, –64 dBm. Two Intermodulation interferers at 2405 and 2408 MHz respectively, at –34 dBm the given power level Conducted measurement in a 50-Ω single-ended Spurious emissions, load. Suitable for systems targeting compliance with –71 dBm30 to 1000 MHz EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 Conducted measurement in a 50 Ω single-ended Spurious emissions, load. Suitable for systems targeting compliance with –62 dBm1 to 12.75 GHz EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 RSSI dynamic range 70 dB RSSI accuracy ±4 dB (1) Numbers given as I/C dB. (2) X / Y, where X is +N MHz and Y is –N MHz. (3) Excluding one exception at Fwanted / 2, per Bluetooth Specification. Copyright © 2015, Texas Instruments Incorporated Specifications 15 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com 5.7 1-Mbps GFSK (Bluetooth Low Energy) – TX Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, fRF = 2440 MHz, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential mode, delivered to a single-ended 50-Ω loadOutput power, highest setting 5 dBmthrough a balun Measured on CC2650EM-4XS, delivered to a single-endedOutput power, highest setting 2 dBm50-Ω load Output power, lowest setting Delivered to a single-ended 50-Ω load through a balun –21 dBm f < 1 GHz, outside restricted bands –43 dBm f < 1 GHz, restricted bands ETSI –65 dBmSpurious emission conducted measurement(1) f < 1 GHz, restricted bands FCC –76 dBm f > 1 GHz, including harmonics –46 dBm (1) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan). 5.8 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Differential mode. Measured at the CC2650EM-5XDReceiver sensitivity –100 dBmSMA connector, PER = 1% Single-ended mode. Measured on CC2650EM-4XS,Receiver sensitivity –97 dBmat the SMA connector, PER = 1% Measured at the CC2650EM-5XD SMA connector,Receiver saturation +4 dBmPER = 1% Wanted signal at –82 dBm, modulated interferer atAdjacent channel rejection 39 dB±5 MHz, PER = 1% Wanted signal at –82 dBm, modulated interferer atAlternate channel rejection 52 dB±10 MHz, PER = 1% Wanted signal at –82 dBm, undesired signal is IEEEChannel rejection, ±15 MHz or 802.15.4 modulated channel, stepped through all 57 dBmore channels 2405 to 2480 MHz, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 64 dB5 MHz from upper band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 64 dB10 MHz from upper band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 65 dB20 MHz from upper band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 68 dB50 MHz from upper band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 63 dB–5 MHz from lower band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 63 dB–10 MHz from lower band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 65 dB–20 MHz from lower band edge sensitivity level), CW jammer, PER = 1% Blocking and desensitization, Wanted signal at –97 dBm (3 dB above the 67 dB–50 MHz from lower band edge sensitivity level), CW jammer, PER = 1% Conducted measurement in a 50 Ω single-ended Spurious emissions, 30 MHz to load. Suitable for systems targeting compliance with –71 dBm1000 MHz EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 Conducted measurement in a 50 Ω single-ended Spurious emissions, 1 GHz to load. Suitable for systems targeting compliance with –62 dBm12.75 GHz EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66 Difference between the incoming carrier frequencyFrequency error tolerance >200 ppmand the internally generated carrier frequency

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – RX (continued) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Difference between incoming symbol rate and theSymbol rate error tolerance >1000 ppminternally generated symbol rate RSSI dynamic range 100 dB RSSI accuracy ±4 dB 5.9 IEEE 802.15.4 (Offset Q-PSK DSSS, 250 kbps) – TX Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Output power, highest setting Delivered to a single-ended 50-Ω load through a balun 5 dBm Measured on CC2650EM-4XS, delivered to a single-Output power, highest setting 2 dBmended 50-Ω load Output power, lowest setting Delivered to a single-ended 50-Ω load through a balun –21 dBm Error vector magnitude At maximum output power 2% f < 1 GHz, outside restricted bands –43 f < 1 GHz, restricted bands ETSI –65 dBm Spurious emission conducted f < 1 GHz, restricted bands FCC –76 measurement f > 1 GHz, including harmonics –46 Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) 5.10 24-MHz Crystal Oscillator (XOSC_HF) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ESR Equivalent series resistance 20 60 Ω Relates to load capacitanceLM Motional inductance < 1.6 × 10–24 / CL

2 H(CL in Farads)

CL Crystal load capacitance 5 9 pF Crystal frequency 24 MHz Crystal frequency tolerance(2) –40 40 ppm Start-up time(3) 150 µs (1) Probing or otherwise stopping the XTAL while the DC-DC converter is enabled may cause permanent damage to the device. (2) Includes initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per Bluetooth and IEEE 802.15.4 specification. (3) Kick-started based on a temperature and aging compensated RCOSC_HF using precharge injection. 5.11 32.768-kHz Crystal Oscillator (XOSC_LF) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Crystal frequency 32.768 kHz Crystal frequency tolerance, Bluetooth low- –500 500 ppmenergy applications(1) ESR Equivalent series resistance 30 100 kΩ CL Crystal load capacitance 6 12 pF (1) Includes initial tolerance of the crystal, drift over temperature, ageing and frequency pulling due to incorrect load capacitance. As per Bluetooth and IEEE 802.15.4 specification. Copyright © 2015, Texas Instruments Incorporated Specifications 17 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com 5.12 48-MHz RC Oscillator (RCOSC_HF) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Frequency 48 MHz Uncalibrated frequency accuracy ±1% Calibrated frequency accuracy(1) ±0.25% Start-up time 5 µs (1) Accuracy relative to the calibration source (XOSC_HF). 5.13 32-kHz RC Oscillator (RCOSC_LF) Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Calibrated frequency 32.8 kHz Temperature coefficient 50 ppm/°C

5.14 ADC Characteristics

Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 0 VDDS V Resolution 12 Bits Sample rate 200 ksps Offset Internal 4.3-V equivalent reference(2) 2 LSB Gain error Internal 4.3-V equivalent reference(2) 2.4 LSB DNL(3) Differential nonlinearity >–1 LSB INL(4) Integral nonlinearity ±3 LSB Internal 4.3-V equivalent reference(2), 200 ksps, 9.89.6-kHz input tone ENOB Effective number of bits VDDS as reference, 200 ksps, 9.6-kHz input tone 10 Bits Internal 1.44-V reference, voltage scaling disabled, 11.132 samples average, 200 ksps, 300-Hz input tone Internal 4.3-V equivalent reference(2), 200 ksps, –659.6-kHz input tone THD Total harmonic distortion VDDS as reference, 200 ksps, 9.6-kHz input tone –69 dB Internal 1.44-V reference, voltage scaling disabled, –7132 samples average, 200 ksps, 300-Hz input tone Internal 4.3-V equivalent reference(2), 200 ksps, 609.6-kHz input toneSignal-to-noiseSINAD, and VDDS as reference, 200 ksps, 9.6-kHz input tone 63 dBSNDR Distortion ratio Internal 1.44-V reference, voltage scaling disabled, 6932 samples average, 200 ksps, 300-Hz input tone Internal 4.3-V equivalent reference(2), 200 ksps, 679.6-kHz input tone Spurious-free dynamicSFDR VDDS as reference, 200 ksps, 9.6-kHz input tone 72 dBrange Internal 1.44-V reference, voltage scaling disabled, 7332 samples average, 200 ksps, 300-Hz input tone clock-Conversion time Serial conversion, time-to-output, 24-MHz clock 50 cycles Current consumption Internal 4.3-V equivalent reference(2) 0.66 mA Current consumption VDDS as reference 0.75 mA (1) Using IEEE Std 1241™ -2010 for terminology and test methods. (2) Input signal scaled down internally before conversion, as if voltage range was 0 to 4.3 V. (3) No missing codes. Positive DNL typically varies from +0.3 to +3.5, depending on device (see Figure 5-24). (4) For a typical example, see Figure 5-25.

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 ADC Characteristics (continued) Tc = 25°C, VDDS = 3.0 V and voltage scaling enabled, unless otherwise noted.(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Equivalent fixed internal reference (input voltage scalingReference voltage 4.3(2)(5) Venabled) Reference voltage Fixed internal reference (input voltage scaling disabled) 1.44 ±1% V VDDS as reference (Also known as RELATIVE) (inputReference voltage VDDS Vvoltage scaling enabled) VDDS as reference (Also known as RELATIVE) (input VDDS /Reference voltage Vvoltage scaling disabled) 2.82(5) 200 ksps, voltage scaling enabled. Capacitive input, Input Input Impedance impedance depends on sampling frequency and sampling >1 MΩ time (5) Applied voltage must be within absolute maximum ratings (Section 5.1) at all times.

5.15 Temperature Sensor

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 4 °C Range –40 85 °C Accuracy ±5 °C Supply voltage coefficient(1) 3.2 °C/V (1) Automatically compensated when using supplied driver libraries.

5.16 Battery Monitor

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 50 mV Range 1.8 3.8 V Accuracy 13 mV

5.17 Continuous Time Comparator

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 0 VDDS V External reference voltage 0 VDDS V Internal reference voltage DCOUPL as reference 1.27 V Offset 3 mV Hysteresis <2 mV Decision time Step from –10 mV to 10 mV 0.72 µs Current consumption when enabled(1) 8.6 µA (1) Additionally, the bias module must be enabled when running in standby mode. Copyright © 2015, Texas Instruments Incorporated Specifications 19 Submit Documentation Feedback Product Folder Links: CC2650

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5.18 Low-Power Clocked Comparator

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 0 VDDS V Clock frequency 32 kHz Internal reference voltage, VDDS / 2 1.49 – 1.51 V Internal reference voltage, VDDS / 3 1.01 – 1.03 V Internal reference voltage, VDDS / 4 0.78 – 0.79 V Internal reference voltage, DCOUPL / 1 1.25 – 1.28 V Internal reference voltage, DCOUPL / 2 0.63 – 0.65 V Internal reference voltage, DCOUPL / 3 0.42 – 0.44 V Internal reference voltage, DCOUPL / 4 0.33 – 0.34 V Offset <2 mV Hysteresis <5 mV Decision time Step from –50 mV to 50 mV <1 clock-cycle Current consumption when enabled 362 nA

5.19 Programmable Current Source

Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Current source programmable output range 0.25 – 20 µA Resolution 0.25 µA Including current source at maximumCurrent consumption(1) 23 µAprogrammable output (1) Additionally, the bias module must be enabled when running in standby mode.

5.20 DC Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C, VDDS = 1.8 V GPIO VOH at 8-mA load IOCURR = 2, high-drive GPIOs only 1.32 1.54 V GPIO VOL at 8-mA load IOCURR = 2, high-drive GPIOs only 0.26 0.32 V GPIO VOH at 4-mA load IOCURR = 1 1.32 1.58 V GPIO VOL at 4-mA load IOCURR = 1 0.21 0.32 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 71.7 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 21.1 µA GPIO high/low input transition, IH = 0, transition between reading 0 and reading 1 0.88 Vno hysteresis GPIO low-to-high input transition, IH = 1, transition voltage for input read as 0 → 1 1.07 Vwith hysteresis GPIO high-to-low input transition, IH = 1, transition voltage for input read as 1 → 0 0.74 Vwith hysteresis GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.33 V

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 DC Characteristics (continued) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C, VDDS = 3.0 V GPIO VOH at 8-mA load IOCURR = 2, high-drive GPIOs only 2.68 V GPIO VOL at 8-mA load IOCURR = 2, high-drive GPIOs only 0.33 V GPIO VOH at 4-mA load IOCURR = 1 2.72 V GPIO VOL at 4-mA load IOCURR = 1 0.28 V TA = 25°C, VDDS = 3.8 V GPIO pullup current Input mode, pullup enabled, Vpad = 0 V 277 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 113 µA GPIO high/low input transition, IH = 0, transition between reading 0 and reading 1 1.67 Vno hysteresis GPIO low-to-high input transition, IH = 1, transition voltage for input read as 0 → 1 1.94 Vwith hysteresis GPIO high-to-low input transition, IH = 1, transition voltage for input read as 1 → 0 1.54 Vwith hysteresis GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.4 V TA = 25°C Lowest GPIO input voltage reliably interpreted as aVIH 0.8 VDDS(1) «High» Highest GPIO input voltage reliably interpreted as aVIL 0.2 VDDS(1) «Low» (1) Each GPIO is referenced to a specific VDDS pin. See the technical reference manual listed in Section 8.2 for more details.

5.21 Thermal Characteristics

NAME DESCRIPTION RSM (°C/W)(1) (2) RHB (°C/W)(1) (2) RGZ (°C/W)(1) (2) RθJA Junction-to-ambient thermal resistance 36.9 32.8 29.6 RθJC(top) Junction-to-case (top) thermal resistance 30.3 24.0 15.7 RθJB Junction-to-board thermal resistance 7.6 6.8 6.2 PsiJT Junction-to-top characterization parameter 0.4 0.3 0.3 PsiJB Junction-to-board characterization parameter 7.4 6.8 6.2 RθJC(bot) Junction-to-case (bottom) thermal resistance 2.1 1.9 1.9 (1) °C/W = degrees Celsius per watt. (2) These values are based on a JEDEC-defined 2S2P system (with the exception of the Theta JC [RθJC] value, which is based on a JEDEC-defined 1S0P system) and will change based on environment as well as application. For more information, see these EIA/JEDEC standards:

• JESD51-2, Integrated Circuits Thermal Test Method Environmental Conditions - Natural Convection (Still Air).
• JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-7, High Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages.
• JESD51-9, Test Boards for Area Array Surface Mount Package Thermal Measurements. Power dissipation of 2 W and an ambient temperature of 70ºC is assumed. Copyright © 2015, Texas Instruments Incorporated Specifications 21 Submit Documentation Feedback Product Folder Links: CC2650

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5.22 Timing Requirements

Rising supply-voltage slew rate 0 100 mV/µs Falling supply-voltage slew rate 0 20 mV/µs Falling supply-voltage slew rate, with low-power flash settings(1) 3 mV/µs No limitation for negative Positive temperature gradient in standby(2) temperature gradient, or 5 °C/s outside standby mode CONTROL INPUT AC CHARACTERISTICS(3) RESET_N low duration 1 µs SYNCHRONOUS SERIAL INTERFACE (SSI) (4) systemS1 (SLAVE) (5) tclk_per SSIClk period 12 65024 clocks S2 (5) tclk_high SSIClk high time 0.5 tclk_per S3(5) tclk_low SSIClk low time 0.5 tclk_per (1) For smaller coin cell batteries, with high worst-case end-of-life equivalent source resistance, a 22-µF VDDS input capacitor (see Figure 7-1) must be used to ensure compliance with this slew rate. (2) Applications using RCOSC_LF as sleep timer must also consider the drift in frequency caused by a change in temperature (see Section 5.13). (3) TA = –40°C to 85°C, VDDS = 1.7 V to 3.8 V, unless otherwise noted. (5) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3.

5.23 Switching Characteristics

Measured on the TI CC2650EM-5XD reference design with Tc = 25°C, VDDS = 3.0 V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT WAKEUP AND TIMING Idle → Active 14 µs Standby → Active 151 µs Shutdown → Active 1015 µs SYNCHRONOUS SERIAL INTERFACE (SSI) (1) systemS1 (TX only)(2) tclk_per (SSIClk period) One-way communication to SLAVE 4 65024 clocks systemS1 (TX and RX)(2) tclk_per (SSIClk period) Normal duplex operation 8 65024 clocks S2 (2) tclk_high (SSIClk high time) 0.5 tclk_per S3 (2) tclk_low(SSIClk low time) 0.5 tclk_per (1) Device operating as MASTER. For SSI SLAVE operation, see Section 5.22. (2) Refer to SSI timing diagrams Figure 5-1, Figure 5-2, and Figure 5-3. Figure 5-1. SSI Timing for TI Frame Format (FRF = 01), Single Transfer Timing Measurement

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Frequency (MHz) Sensitivity Level (dBm) 2400 2410 2420 2430 2440 2450 2460 2470 2480 -101 -100 -99 -98 -97 -96 -95 D019 Sensitivity 4XS Sensitivity 5XD Frequency (MHz) Sensitivity Level (dBm) 2400 2410 2420 2430 2440 2450 2460 2470 2480 -99 -98.5 -98 -97.5 -97 -96.5 -96 -95.5 -95 D020 Sensitivity 5XD Sensitivity 4XS VDDS (V) Sensitivity (dBm) -101 -100 -99 -98 -97 -96 -95 D004 BLE 5XD Sensitivity BLE 4XS Sensitivity VDDS (V) Sensitivity (dBm) -101 -100 -99 -98 -97 -96 -95 D005 IEEE 802.15.4 5XD Sensitivity IEEE 802.15.4 4XS Sensitivity Temperature (qC) Sensitivity (dBm) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -99 -98 -97 -96 -95 -94 Sensitivity 4XS Sensitivity 5XD Temperature (qC) Sensitivity (dBm) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 -103 -102 -101 -100 -99 -98 -97 -96 -95 Sensitivity 4XS Sensitivity 5XD CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com

5.24 Typical Characteristics

Figure 5-4. BLE Sensitivity vs Temperature Figure 5-5. IEEE 802.15.4 Sensitivity vs Temperature Figure 5-6. BLE Sensitivity vs Supply Voltage (VDDS) Figure 5-7. IEEE 802.15.4 Sensitivity vs Supply Voltage (VDDS) Figure 5-8. IEEE 802.15.4 Sensitivity vs Channel Frequency Figure 5-9. BLE Sensitivity vs Channel Frequency

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Input Frequency (Hz) Effective Number of Bits 200300 500 1000 2000 5000 10000 20000 100000 9.4 9.6 9.8 10.2 10.4 10.6 10.8 11.2 11.4 D009 Fs= 200 kHz, No Averaging Fs= 200 kHz, 32 samples averaging VDDS (V) ADC Code 1004.8 1005 1005.2 1005.4 1005.6 1005.8 1006 1006.2 1006.4 D012 VDDS (V) Current Consumption (mA) 2.5 3.5 4.5 D007 Active Mode Current Temperature (qC) Current (uA) -20 -10 0 10 20 30 40 50 60 70 80 0.5 1.5 2.5 3.5 D008 Standby Mode Current Temperature (qC) Active Mode Current Consumpstion (mA) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 2.85 2.9 2.95 3.05 3.1 D006 Active Mode Current Temperature (qC) TX Current (mA) -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 D002 5XD 5dBm Setting 4XS 2dBm Setting CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) Figure 5-16. TX Mode Current Consumption vs Temperature Figure 5-17. Active Mode (MCU Running, No Peripherals) Current Consumption vs Temperature Figure 5-18. Active Mode (MCU Running, No Peripherals) Current Figure 5-19. Standby Mode Current Consumption With RCOSC Consumption vs Supply Voltage (VDDS) RTC vs Temperature Figure 5-20. SoC ADC Effective Number of Bits vs Input Figure 5-21. SoC ADC Output vs Supply Voltage (Fixed Input, Frequency (Internal Reference, No Scaling) Internal Reference, No Scaling)

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0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2400 2600 2800 3000 3200 3400 3600 3800 4000 4200 D011 CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Typical Characteristics (continued) Figure 5-25. SoC ADC INL vs ADC Code (Internal Reference, No Scaling)

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6 Detailed Description

6.1 Overview

The core modules of the CC26xx product family are shown in the Section 6.2.

6.2 Functional Block Diagram

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6.3 Main CPU

The SimpleLink CC2650 Wireless MCU contains an ARM Cortex-M3 (CM3) 32-bit CPU, which runs the application and the higher layers of the protocol stack. The CM3 processor provides a high-performance, low-cost platform that meets the system requirements of minimal memory implementation, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. CM3 features include the following:

• 32-bit ARM Cortex-M3 architecture optimized for small-footprint embedded applications
• Outstanding processing performance combined with fast interrupt handling
• ARM Thumb®-2 mixed 16- and 32-bit instruction set delivers the high performance expected of a 32-bit ARM core in a compact memory size usually associated with 8- and 16-bit devices, typically in the range of a few kilobytes of memory for microcontroller-class applications: – Single-cycle multiply instruction and hardware divide – Atomic bit manipulation (bit-banding), delivering maximum memory use and streamlined peripheral control – Unaligned data access, enabling data to be efficiently packed into memory
• Fast code execution permits slower processor clock or increases sleep mode time
• Harvard architecture characterized by separate buses for instruction and data
• Efficient processor core, system, and memories
• Hardware division and fast digital-signal-processing oriented multiply accumulate
• Saturating arithmetic for signal processing
• Deterministic, high-performance interrupt handling for time-critical applications
• Enhanced system debug with extensive breakpoint and trace capabilities
• Serial wire trace reduces the number of pins required for debugging and tracing
• Migration from the ARM7™ processor family for better performance and power efficiency
• Optimized for single-cycle flash memory use
• Ultralow-power consumption with integrated sleep modes
• 1.25 DMIPS per MHz

6.4 RF Core

The RF Core contains an ARM Cortex-M0 processor that interfaces the analog RF and base-band circuitries, handles data to and from the system side, and assembles the information bits in a given packet structure. The RF core offers a high level, command-based API to the main CPU. The RF core is capable of autonomously handling the time-critical aspects of the radio protocols (802.15.4 RF4CE and ZigBee, Bluetooth Low Energy) thus offloading the main CPU and leaving more resources for the user application. The RF core has a dedicated 4-KB SRAM block and runs initially from separate ROM memory. The ARM Cortex-M0 processor is not programmable by customers.

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6.5 Sensor Controller

The Sensor Controller contains circuitry that can be selectively enabled in standby mode. The peripherals in this domain may be controlled by the Sensor Controller Engine which is a proprietary power-optimized CPU. This CPU can read and monitor sensors or perform other tasks autonomously, thereby significantly reducing power consumption and offloading the main CM3 CPU. The Sensor Controller is set up using a PC-based configuration tool, called Sensor Controller Studio, and potential use cases may be (but are not limited to):

• Analog sensors using integrated ADC
• Digital sensors using GPIOs, bit-banged I2C, and SPI
• UART communication for sensor reading or debugging
• Capacitive sensing
• Waveform generation
• Pulse counting
• Keyboard scan
• Quadrature decoder for polling rotation sensors
• Oscillator calibration NOTE Texas Instruments provides application examples for some of these use cases, but not for all of them. The peripherals in the Sensor Controller include the following:
• The low-power clocked comparator can be used to wake the device from any state in which the comparator is active. A configurable internal reference can be used in conjunction with the comparator. The output of the comparator can also be used to trigger an interrupt or the ADC.
• Capacitive sensing functionality is implemented through the use of a constant current source, a time- to-digital converter, and a comparator. The continuous time comparator in this block can also be used as a higher-accuracy alternative to the low-power clocked comparator. The Sensor Controller will take care of baseline tracking, hysteresis, filtering and other related functions.
• The ADC is a 12-bit, 200-ksamples/s ADC with eight inputs and a built-in voltage reference. The ADC can be triggered by many different sources, including timers, I/O pins, software, the analog comparator, and the RTC.
• The Sensor Controller also includes a SPI–I2C digital interface.
• The analog modules can be connected to up to eight different GPIOs. The peripherals in the Sensor Controller can also be controlled from the main application processor. Copyright © 2015, Texas Instruments Incorporated Detailed Description 31 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com Table 6-1. GPIOs Connected to the Sensor Controller(1) 7 × 7 RGZ 5 × 5 RHB 4 × 4 RSMANALOG CAPABLE DIO NUMBER DIO NUMBER DIO NUMBER Y 30 14 Y 29 13 Y 28 12 Y 27 11 9 Y 26 9 8 Y 25 10 7 Y 24 8 6 Y 23 7 5 N 7 4 2 N 6 3 1 N 5 2 0 N 4 1 N 3 0 N 2 N 1 N 0 (1) Depending on the package size, up to 16 pins can be connected to the Sensor Controller. Up to 8 of these pins can be connected to analog modules.

6.6 Memory

The flash memory provides nonvolatile storage for code and data. The flash memory is in-system programmable. The SRAM (static RAM) can be used for both storage of data and execution of code and is split into two 4-KB blocks and two 6-KB blocks. Retention of the RAM contents in standby mode can be enabled or disabled individually for each block to minimize power consumption. In addition, if flash cache is disabled, the 8-KB cache can be used as a general-purpose RAM. The ROM provides preprogrammed embedded TI RTOS kernel, Driverlib and lower layer protocol stack software (802.15.4 MAC and Bluetooth Low Energy Controller). It also contains a bootloader that can be used to reprogram the device using SPI or UART.

6.7 Debug

The on-chip debug support is done through a dedicated cJTAG (IEEE 1149.7) or JTAG (IEEE 1149.1) interface.

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6.8 Power Management

To minimize power consumption, the CC2650 device supports a number of power modes and power management features (see Table 6-2). Table 6-2. Power Modes SOFTWARE CONFIGURABLE POWER MODES RESET PINMODE HELDACTIVE IDLE STANDBY SHUTDOWN CPU Active Off Off Off Off Flash On Available Off Off Off SRAM On On On Off Off Radio Available Available Off Off Off Supply System On On Duty Cycled Off Off Current 1.45 mA + 31 µA/MHz 550 µA 1 µA 0.15 µA 0.1 µA Wake-up Time to CPU Active(1) – 14 µs 151 µs 1015 µs 1015 µs Register Retention Full Full Partial No No SRAM Retention Full Full Full No No XOSC_HF or XOSC_HF orHigh-Speed Clock Off Off OffRCOSC_HF RCOSC_HF XOSC_LF or XOSC_LF or XOSC_LF orLow-Speed Clock Off OffRCOSC_LF RCOSC_LF RCOSC_LF Peripherals Available Available Off Off Off Sensor Controller Available Available Available Off Off Wake up on RTC Available Available Available Off Off Wake up on Pin Edge Available Available Available Available Off Wake up on Reset Pin Available Available Available Available Available Brown Out Detector (BOD) Active Active Duty Cycled(2) Off N/A Power On Reset (POR) Active Active Active Active N/A (1) Not including RTOS overhead (2) The Brown Out Detector is disabled between recharge periods in STANDBY. Lowering the supply voltage below the BOD threshold between two recharge periods while in STANDBY may cause the BOD to lock the device upon wake-up until a Reset/POR releases it. To avoid this, it is recommended that STANDBY mode is avoided if there is a risk that the supply voltage (VDDS) may drop below the specified operating voltage range. For the same reason, it is also good practice to ensure that a power cycling operation, such as a battery replacement, triggers a Power-on-reset by ensuring that the VDDS decoupling network is fully depleted before applying supply voltage again (for example, inserting new batteries). In active mode, the application CM3 CPU is actively executing code. Active mode provides normal operation of the processor and all of the peripherals that are currently enabled. The system clock can be any available clock source (see Table 6-2). In idle mode, all active peripherals can be clocked, but the Application CPU core and memory are not clocked and no code is executed. Any interrupt event will bring the processor back into active mode. In standby mode, only the always-on domain (AON) is active. An external wake event, RTC event, or sensor-controller event is required to bring the device back to active mode. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode. In shutdown mode, the device is turned off entirely, including the AON domain and the Sensor Controller. The I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from Shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between a reset in this way, a reset-by-reset pin, or a power-on-reset by reading the reset status register. The only state retained in this mode is the latched I/O state and the Flash memory contents. Copyright © 2015, Texas Instruments Incorporated Detailed Description 33 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com The Sensor Controller is an autonomous processor that can control the peripherals in the Sensor Controller independently of the main CPU, which means that the main CPU does not have to wake up, for example, to execute an ADC sample or poll a digital sensor over SPI. The main CPU saves both current and wake-up time that would otherwise be wasted. The Sensor Controller Studio enables the user to configure the sensor controller and choose which peripherals are controlled and which conditions wake up the main CPU.

6.9 Clock Systems

The CC2650 supports two external and two internal clock sources. A 24-MHz crystal is required as the frequency reference for the radio. This signal is doubled internally to create a 48-MHz clock. The 32-kHz crystal is optional. Bluetooth low energy requires a slow-speed clock with better than ±500 ppm accuracy if the device is to enter any sleep mode while maintaining a connection. The internal 32-kHz RC oscillator can in some use cases be compensated to meet the requirements. The low-speed crystal oscillator is designed for use with a 32-kHz watch-type crystal. The internal high-speed oscillator (48-MHz) can be used as a clock source for the CPU subsystem. The internal low-speed oscillator (32.768-kHz) can be used as a reference if the low-power crystal oscillator is not used. The 32-kHz clock source can be used as external clocking reference through GPIO.

6.10 General Peripherals and Modules

The I/O controller controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a flexible manner. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull or open-drain. Five GPIOs have high drive capabilities (marked in bold in Section 4). The SSIs are synchronous serial interfaces that are compatible with SPI, MICROWIRE, and Texas Instruments synchronous serial interfaces. The SSIs support both SPI master and slave up to 4 MHz. The UART implements a universal asynchronous receiver/transmitter function. It supports flexible baud- rate generation up to a maximum of 3 Mbps and is compatible with the Bluetooth HCI specifications. Timer 0 is a general-purpose timer module (GPTM), which provides two 16-bit timers. The GPTM can be configured to operate as a single 32-bit timer, dual 16-bit timers or as a PWM module. Timer 1, Timer 2, and Timer 3 are also GPTMs. Each of these timers is functionally equivalent to Timer 0. In addition to these four timers, the RF core has its own timer to handle timing for RF protocols; the RF timer can be synchronized to the RTC. The I2C interface is used to communicate with devices compatible with the I2C standard. The I2C interface is capable of 100-kHz and 400-kHz operation, and can serve as both I2C master and I2C slave. The TRNG module provides a true, nondeterministic noise source for the purpose of generating keys, initialization vectors (IVs), and other random number requirements. The TRNG is built on 24 ring oscillators that create unpredictable output to feed a complex nonlinear combinatorial circuit. The watchdog timer is used to regain control if the system fails due to a software error after an external device fails to respond as expected. The watchdog timer can generate an interrupt or a reset when a predefined time-out value is reached.

34 Detailed Description Copyright © 2015, Texas Instruments Incorporated

Submit Documentation Feedback Product Folder Links: CC2650

www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data transfer tasks from the CM3 CPU, allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory as the peripheral is ready to transfer more data. Some features of the µDMA controller include the following (this is not an exhaustive list):

• Highly flexible and configurable channel operation of up to 32 channels
• Transfer modes: – Memory-to-memory – Memory-to-peripheral – Peripheral-to-memory – Peripheral-to-peripheral
• Data sizes of 8, 16, and 32 bits The AON domain contains circuitry that is always enabled, except for in Shutdown (where the digital supply is off). This circuitry includes the following:
• The RTC can be used to wake the device from any state where it is active. The RTC contains three compare and one capture registers. With software support, the RTC can be used for clock and calendar operation. The RTC is clocked from the 32-kHz RC oscillator or crystal. The RTC can also be compensated to tick at the correct frequency even when the internal 32-kHz RC oscillator is used instead of a crystal.
• The battery monitor and temperature sensor are accessible by software and give a battery status indication as well as a coarse temperature measure.

6.11 System Architecture

Depending on the product configuration, CC26xx can function either as a Wireless Network Processor (WNP— an IC running the wireless protocol stack, with the application running on a separate MCU), or as a System-on-Chip (SoC), with the application and protocol stack running on the ARM CM3 core inside the device. In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack. Copyright © 2015, Texas Instruments Incorporated Detailed Description 35 Submit Documentation Feedback Product Folder Links: CC2650

(50 Ohm) 1 pF 1 pF 2.4 nH 2.4-2.7 nH 6.8 pF 6.2-6.8 nH Antenna (50 Ohm) 1.2 pF 15 nH 2 nH 1.2 pF Antenna (50 Ohm) 1.2 pF 2 nH 1.2 pF Antenna (50 Ohm) 1.2 pF 2 nH 1.2 pF Pin 1 (RF P) Pin 2 (RF N) Pin 3 (RXTX) Pin 1 (RF P) Pin 2 (RF N) Pin 1 (RF P) Pin 2 (RF N) Red = Not necessary if internal bias is used Red = Not necessary if internal bias is used Differential operation Single ended operation Single ended operation with 2 antennas Pin 3 (RXTX) 15 nH 15 nH CC 26 xx ( GND exposed die attached pad ) Pin 3/4 (RXTX) Pin 1 (RF P) Pin 2 (RF N) 24MHz XTAL (Load caps on chip) 10uF 10uH Optional inductor. Only needed for DCDC operation 12 pF 12 pF 12 pF 12 pF 2 nH 2 nH 1 pF input decoupling 10uF ± 22uF To VDDR pins VDDS_DCDC DCDC_SW Red = Not necessary if internal bias is used CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com

7 Application, Implementation, and Layout

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

7.1 Application Information

Very few external components are required for the operation of the CC2650 device. This section provides some general information about the various configuration options when using the CC2650 in an application, and then shows two examples of application circuits with schematics and layout. Complete reference designs are available in the product folder on www.ti.com. Figure 7-1 shows the various RF front-end configuration options. The RF front end can be used in differential- or single-ended configurations with the options of having internal or external biasing. These options allow for various trade- offs between cost, board space, and RF performance. Differential operation with external bias gives the best performance while single-ended operation with internal bias gives the least amount of external components and the lowest power consumption. Reference designs exist for each of these options. Figure 7-1. CC2650 Application Circuit Submit Documentation Feedback Product Folder Links: CC2650

Internal DC-DC Regulator External RegulatorInternal LDO Regulator (GND Exposed Die Attached Pad) Pin 3/4 (RXTX) Pin 1 (RF P) Pin 2 (RF N)

24 MHz XTAL

(Load Caps on Chip) F H VDDS_DCDC Input Decoupling F±22 F To All VDDR Pins VDDS_DCDC Pin DCDC_SW Pin 1.8 V±3.8 V to All VDDS Pins VDDR VDDR VDDS VDDS CC26xx (GND Exposed Die Attached Pad) Pin 3/4 (RXTX) Pin 1 (RF P) Pin 2 (RF N) (Load Caps on Chip) VDDS_DCDC Input Decoupling F±22 F To All VDDR Pins VDDS_DCDC Pin NC 1.8 V±3.8 V Supply Voltage VDDR VDDR VDDS VDDS CC26xx F To All VDDS Pins (GND Exposed Die Attached Pad) Pin 3/4 (RXTX) Pin 1 (RF P) Pin 2 (RF N) (Load Caps on Chip) VDDS_DCDC Pin CC26xx 2.2 F DCDC_SW Pin 1.7 V±1.95 V to All VDDR- and VDDS Pins Except VDDS_DCDCExt. Regulator CC2650 www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 Figure 7-2 shows the various supply voltage configuration options. Not all power supply decoupling capacitors or digital I/Os are shown. Exact pin positions will vary between the different package options. For a detailed overview of power supply decoupling and wiring, see the TI reference designs and the CC26xx technical reference manual (Section 8.2). Figure 7-2. Supply Voltage Configurations Copyright © 2015, Texas Instruments Incorporated Application, Implementation, and Layout 37 Submit Documentation Feedback Product Folder Links: CC2650

VDDR Decoupling Capacitors Pin 32Pin 29 50-Ω Antenna VDDS 10 uH 32.768 kHz C18 12 pF C17 12 pF Place L1 and C8 close to pin 17 C23 DNM C22 DNM 10 µF C10 DNM C16 100 nF 10 µF CC2650F128RHB VSS33 DIO_06 DIO_17 DIO_28 DIO_39 DIO_410 DIO_515 DIO_616 DIO_720 DIO_821 DIO_922 DIO_1023 DIO_1124 DIO_1225 DIO_1326 DIO_1427 VDDR 29 VDDR 32 VDDS 28 VDDS2 11 VDDS_DCDC 18 DCOUPL12 RESET_N19 JTAG_TMSC13 JTAG_TCKC14 X32K_Q1 4X32K_Q2 X24M_N 30X24M_P RF_P 1RF_N 2RX_TX DCDC_SW

24 MHz

X24M_N X24M_P VDDS VDDR DCDC_SW DCDC_SW C31 6.8 pF VDDS nRESET C19 1 µF JTAG_TCK JTAG_TMS DIO_1 DIO_0 DIO_3 DIO_2 DIO_5/JTAG_TDO DIO_4 DIO_7 DIO_6/JTAG_TDI DIO_10 DIO_9 DIO_8 DIO_12 DIO_11 DIO_14 DIO_13 RX_TX RFP RFN L11 2.7 nH 1 2 L21 2.4 nH VDD_EB FL1 BLM18HE152SN1 100 nF 100 nF 100 nF VDDS Decoupling Capacitors Pin 18Pin 28Pin 11 100 nF L10 6.2 nH 100 k VDDR CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com 7.2 5 × 5 External Differential (5XD) Application Circuit Figure 7-3. 5 × 5 External Differential (5XD) Application Circuit Submit Documentation Feedback Product Folder Links: CC2650

www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

7.2.1 Layout

Figure 7-4. 5 × 5 External Differential (5XD) Layout Copyright © 2015, Texas Instruments Incorporated Application, Implementation, and Layout 39 Submit Documentation Feedback Product Folder Links: CC2650

RF_P C14 12 pF

10 F µ

VDDS Decoupling CapacitorsVDDS Pin 11 Pin 27 Pin 19 32.768 kHz C18 12 pF C17 12 pF 100 nF 100 nF 100 nF C12 1.2 pF VDDS 100 k VDDR Place L1 and C8 close to pin 18 C20 100 nF nRESET DIO_8 DIO_0 DIO_7 DIO_9 Pin 28 Pin 32 100 nF VDDR Decoupling Capacitors VDDR

10 H µ

1 2DCDC_SW C19 1 µF 50-Ω Antenna FL1 BLM18HE152SN1 RF_N used for RX biasing. L21 may be removed at the cost of 1 dB degraded sensitivity VDD_EB C13 1.2 pF L12 2 nH 1 2 CC26XX_4X4 DIO_08 DIO_19 DIO_210 DIO_315 DIO_416 DIO_522 DIO_623 DIO_724 DIO_825 DIO_926 RESET_N21 JTAG_TCKC14 JTAG_TMSC13 X24M_P X24M_N DCOUPL VSS29 VSS3 EGP33 VDDS 27 VDDS2 11 VDDS_DCDC 19 VDDR 28 VDDR 32 DCDC_SW RX/TX RF_N RF_P X32K_Q2 X32K_Q1 VSS7 VSS17 VSS20 DIO_1 DIO_3/JTAG_TDO DIO_2 DIO_6 DIO_5 DIO_4/JTAG_TDI DCDC_SW JTAG_TCK nRESET JTAG_TMS C23 DNM C22 DNM X24M_N X24M_P CC2650 SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com 7.3 4 × 4 External Single-ended (4XS) Application Circuit Figure 7-5. 4 × 4 External Single-ended (4XS) Application Circuit Submit Documentation Feedback Product Folder Links: CC2650

www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

7.3.1 Layout

Figure 7-6. 4 × 4 External Single-ended (4XS) Layout Copyright © 2015, Texas Instruments Incorporated Application, Implementation, and Layout 41 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com

8 Device and Documentation Support

8.1 Device Support

8.1.1 Development Support

TI offers an extensive line of development tools, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. The following products support development of the CC2650 device applications: Software Tools: SmartRF Studio 7: SmartRF Studio is a PC application that helps designers of radio systems to easily evaluate the RF-IC at an early stage in the design process.

• Test functions for sending and receiving radio packets, continuous wave transmit and receive
• Evaluate RF performance on custom boards by wiring it to a supported evaluation board or debugger
• Can also be used without any hardware, but then only to generate, edit and export radio configuration settings
• Can be used in combination with several development kits for Texas Instruments’CCxxxx RF-ICs Sensor Controller Studio: Sensor Controller Studio provides a development environment for the CC26xx Sensor Controller. The Sensor Controller is a proprietary, power-optimized CPU in the CC26xx, which can perform simple background tasks autonomously and independent of the System CPU state.
• Allows for Sensor Controller task algorithms to be implemented using a C-like programming language
• Outputs a Sensor Controller Interface driver, which incorporates the generated Sensor Controller machine code and associated definitions
• Allows for rapid development by using the integrated Sensor Controller task testing and debugging functionality. This allows for live visualization of sensor data and algorithm verification. IDEs and Compilers: Code Composer Studio:
• Integrated development environment with project management tools and editor
• Code Composer Studio (CCS) 6.1 and later has built-in support for the CC26xx device family
• Best support for XDS debuggers; XDS100v3, XDS110 and XDS200
• High integration with TI-RTOS with support for TI-RTOS Object View IAR Embedded Workbench for ARM
• Integrated development environment with project management tools and editor
• IAR EWARM 7.30.3 and later has built-in support for the CC26xx device family
• Broad debugger support, supporting XDS100v3, XDS200, IAR I-Jet and Segger J-Link
• Integrated development environment with project management tools and editor
• RTOS plugin available for TI-RTOS For a complete listing of development-support tools for the CC2650 platform, visit the Texas Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field sales office or authorized distributor.

42 Device and Documentation Support Copyright © 2015, Texas Instruments Incorporated

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

8.1.2 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, CC2650 is in production; therefore, no prefix/identification is assigned). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Production devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RSM). For orderable part numbers of the CC2650 device in the RSM, RHB or RGZ package types, see the Package Option Addendum of this document, the TI website (www.ti.com), or contact your TI sales representative. Copyright © 2015, Texas Instruments Incorporated Device and Documentation Support 43 Submit Documentation Feedback Product Folder Links: CC2650

SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015 www.ti.com

8.2 Documentation Support

The following documents describe the CC2650. Copies of these documents are available on the Internet at www.ti.com. SWCU117 CC26xx SimpleLink™ Wireless MCU Technical Reference Manual SWRZ058 CC26xx SimpleLink™ Wireless MCU Errata

8.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. TI Embedded Processors Wiki Texas Instruments Embedded Processors Wiki. Established to help developers get started with Embedded Processors from Texas Instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices.

8.4 Texas Instruments Low-Power RF Website

Texas Instruments' Low-Power RF website has all the latest products, application and design notes, FAQ section, news and events updates. Go to www.ti.com/lprf.

8.5 Low-Power RF Online Community

• Forums, videos, and blogs
• RF design help
• E2E interaction Join at: www.ti.com/lprf-forum.

8.6 Texas Instruments Low-Power RF Developer Network

Texas Instruments has launched an extensive network of low-power RF development partners to help customers speed up their application development. The network consists of recommended companies, RF consultants, and independent design houses that provide a series of hardware module products and design services, including:

• RF circuit, low-power RF, and ZigBee design services
• Low-power RF and ZigBee module solutions and development tools
• RF certification services and RF circuit manufacturing For help with modules, engineering services or development tools: Search the Low-Power RF Developer Network to find a suitable partner. www.ti.com/lprfnetwork

8.7 Low-Power RF eNewsletter

The Low-Power RF eNewsletter is up-to-date on new products, news releases, developers’news, and other news and events associated with low-power RF products from TI. The Low-Power RF eNewsletter articles include links to get more online information. Sign up at: www.ti.com/lprfnewsletter

44 Device and Documentation Support Copyright © 2015, Texas Instruments Incorporated

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www.ti.com SWRS158A –FEBRUARY 2015–REVISED OCTOBER 2015

8.8 Additional Information

Texas Instruments offers a wide selection of cost-effective, low-power RF solutions for proprietary and standard-based wireless applications for use in industrial and consumer applications. The selection includes RF transceivers, RF transmitters, RF front ends, and Systems-on-Chips as well as various software solutions for the sub-1-GHz and 2.4-GHz frequency bands. In addition, Texas Instruments provides a large selection of support collateral such as development tools, technical documentation, reference designs, application expertise, customer support, third-party and university programs. The Low-Power RF E2E Online Community provides technical support forums, videos and blogs, and the chance to interact with engineers from all over the world. With a broad selection of product solutions, end-application possibilities, and a range of technical support, Texas Instruments offers the broadest low-power RF portfolio.

8.9 Trademarks

SimpleLink, SmartRF, Code Composer Studio, E2E are trademarks of Texas Instruments. ARM7 is a trademark of ARM Limited (or its subsidiaries). ARM, Cortex, ARM Thumb are registered trademarks of ARM Limited (or its subsidiaries). Bluetooth is a registered trademark of Bluetooth SIG, Inc. CoreMark is a registered trademark of Embedded Microprocessor Benchmark Consortium. IAR Embedded Workbench is a registered trademark of IAR Systems AB. IEEE Std 1241 is a trademark of Institute of Electrical and Electronics Engineers, Incorporated. ZigBee is a registered trademark of ZigBee Alliance, Inc.

8.10 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

8.11 Export Control Notice

Recipient agrees to not knowingly export or re-export, directly or indirectly, any product or technical data (as defined by the U.S., EU, and other Export Administration Regulations) including software, or any controlled product restricted by other applicable national regulations, received from Disclosing party under this Agreement, or any direct product of such technology, to any destination to which such export or re- export is restricted or prohibited by U.S. or other applicable laws, without obtaining prior authorization from U.S. Department of Commerce and other competent Government authorities to the extent required by those laws.

8.12 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms and definitions.

9 Mechanical Packaging and Orderable Information

9.1 Packaging Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. Copyright © 2015, Texas Instruments Incorporated Mechanical Packaging and Orderable Information 45 Submit Documentation Feedback Product Folder Links: CC2650

www.ti.com 5-Sep-2015 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CC2650F128RGZR ACTIVE VQFN RGZ 48 2500 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 CC2650F128RGZT ACTIVE VQFN RGZ 48 250 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 CC2650F128RHBR ACTIVE VQFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 CC2650F128RHBT ACTIVE VQFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 CC2650F128RSMR ACTIVE VQFN RSM 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 CC2650F128RSMT ACTIVE VQFN RSM 32 250 Green (RoHS & no Sb/Br) CU NIPDAU | Call TI Level-3-260C-168 HR -40 to 85 CC2650 F128 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.

www.ti.com 5-Sep-2015 Addendum-Page 2 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2015 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CC2650F128RGZR VQFN RGZ 48 2500 367.0 367.0 38.0 CC2650F128RGZT VQFN RGZ 48 250 210.0 185.0 35.0 CC2650F128RHBR VQFN RHB 32 3000 367.0 367.0 35.0 CC2650F128RHBT VQFN RHB 32 250 210.0 185.0 35.0 CC2650F128RSMR VQFN RSM 32 3000 367.0 367.0 35.0 CC2650F128RSMT VQFN RSM 32 250 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 3-Aug-2015 Pack Materials-Page 2

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