CC2480

CC2480 TI | Alldatasheet

Document overview

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Technical content

Z-Accel 2.4 GHz ZigBee® Processor Accelerate your ZigBee Development

Applications

• ZigBee™ systems
• Home/Building automation
• Industrial control and monitoring
• Low power wireless sensor networks
• Set-top boxes and remote controls
• Automated Meter Reading

Description

The CC2480 (form erly kn own a s CCZA CC06) is a cost-effective, low power, Z-Accel ZigBee Processor that provid es full ZigBee functionality with a minimal development effort. Z-Accel is a solution where TI’s ZigBee stack, Z-Stack, runs on a ZigBee Processor and the application runs on an external microcontroller. The CC2480 handles all the timing criti cal and processing i ntensive Zi gBee proto col tasks, and le aves t he re sources of the appli cation microcontroller free to ha ndle the ap plication. Z-Accel makes it easy to add ZigBee to new or existing p roducts at the sam e time as it provides great flexibility in choi ce of microcontroller. CC2480 interf aces any mi crocontroller thro ugh an SPI or UART interface. There is no need to learn a ne w micro controller or ne w tools. CC2480 can for example be combined with an MSP430. CC2480 s upports TI’s SimpleAPI. SimpleAPI has only 10 API calls to learn, which drastically simplifies t he d evelopment of ZigBee applications. Key Features

• Simple integ ration of Zi gBee into any design
• Running the mature an d stable Zi gBee 2006 compliant TI Z-Stack
• SPI or UART int erface to any microcontroller running the application
• Simple API and full ZigBee API supported
• Can implement any type of ZigBee device: Coordinator, Router or End Device
• Automatically enters low power mode (<0.5 uA) in idle periods when configured as End Device
• Radi o o Fully integra ted and ro bust IEEE 802.15.4-compliant 2.4 G Hz DSSS RF transceiver o E xcellent receiver se nsitivity and best in class ro bustness to interferers
• Powe r Supply o Wide supply voltage ran ge (2.0V – 3.6V) o Low current con sumption (RX: 27 mA, TX: 27 mA) and fast transition times.
• External System o Very few external components o RoHS compliant 7x7 mm QLP4 8 package
• Peripherals and Supporting Functions o Port expander with 4 general I/O pins, t wo with in creased sink/source capability o Battery mon itor and te mperature sensor o 7-12 bits ADC with two channels o Robust po wer-on-reset a nd brown- out-reset circuitry
• Tool s and Development o Packet sniffer PC software o R eference designs CC2480 Data Sheet SWRS074A Page 1 of 43

CC2480 Data Sheet SWRS074A Page 2 of 43

CC2480 Data Sheet SWRS074A Page 3 of 43

1 Abbreviations

ADC Analog to Digital Converter AES Advanced Encryption Standard AGC Automatic Gain Control ARIB Association of Radio Industries and Businesses BOD Brown Out Detector BOM Bill of Materials CCA Clear Channel Assessment CFR Code of Federal Regulations CPU Central Processing Unit CRC Cyclic Redundancy Check CSMA-CA Carrier Sense Multiple Access with Collision Avoidance CW Continuous Wave DAC Digital to Analog Converter DC Direct Current DNL Differential Nonlinearity DSM Delta Sigma Modulator DSSS Direct Sequence Spread Spectrum EM Evaluation Module ENOB Effective Number of bits ESD Electro Static Discharge ESR Equivalent Series Resistance ETSI European Telecommunications Standards Institute EVM Error Vector Magnitude FCC Federal Communications Commission FCF Frame Control Field FCS Frame Check Sequence I/O Input / Output I/Q In-phase / Quadrature-phase IEEE Institute of Electrical and Electronics Engineers IF Intermediate Frequency INL Integral Nonlinearity ISM Industrial, Scientific and Medical JEDEC Joint Electron Device Engineering Council KB 1024 bytes kbps kilo bits per second LFSR Linear Feedback Shift Register LNA Low-Noise Amplifier LO Local Oscillator LQI Link Quality Indication LSB Least Significant Bit / Byte LSB Least Significant Byte MAC Medium Access Control MISO Master In Slave Out MOSI Master Out Slave In MPDU MAC Protocol Data Unit MSB Most Significant Byte MUX Multiplexer NA Not Available NC Not Connected O-QPSK Offset - Quadrature Phase Shift Keying PA Power Amplifier PCB Printed Circuit Board PER Packet Error Rate PHY Physical Layer PLL Phase Locked Loop PM{0-3} Power Mode 0-3 POR Power On Reset PWM Pulse Width Modulator QLP Quad Leadless Package RAM Random Access Memory RC Resistor-Capacitor RCOSC RC Oscillator RF Radio Frequency RoHS Restriction on Hazardous Substances RSSI Receive Signal Strength Indicator RX Receive SCK Serial Clock SFD Start of Frame Delimiter SHR Synchronization Header SINAD Signal-to-noise and distortion ratio SPI Serial Peripheral Interface SRAM Static Random Access Memory ST Sleep Timer T/R Tape and reel T/R Transmit / Receive TBD To Be Decided / To Be Defined THD Total Harmonic Distortion TI Texas Instruments TX Transmit UART Universal Asynchronous Receiver/Transmitter USART Universal Synchronous/Asynchronous Receiver/Transmitter VGA Variable Gain Amplifier XOSC Crystal Oscillator CC2480 Data Sheet SWRS074A Page 4 of 43

2 References

[1] IEEE std. 802.15.4 - 2006: Wireless Medium Access Control (MAC) and Physical Layer (PHY) specifications for Low Rate Wireless Personal Area Networks (LR-WPANs). [2] CC2480 Interface Specification http://www.ti.com/lit/pdf/swra175 CC2480 Data Sheet SWRS074A Page 5 of 43

3 Absolute Maximum Ratings

Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Table 1: Absolute Maximum Ratings Parameter Min Max Units Condition Supply voltage, VDD –0.3 3.9 V All supply pins must have the same voltage Voltage on any digital pin –0.3 VDD+0.3, max 3.9 V Voltage on the 1.8V pins (pin no. 22, 25-40 and 42) –0.3 2.0 V Input RF level 10 dBm Storage temperature range –50 150 °C Device not programmed Reflow soldering temperature 260 °C According to IPC/JEDEC J-STD-020C <500 V On RF pads (RF_P, RF_N, AVDD_RF1, and AVDD_RF2), according to Human Body Model, JEDEC STD 22, method A114

700 V All other pads, according to Human Body

Model, JEDEC STD 22, method A114 ESD

200 V According to Charged Device Model,

JEDEC STD 22, method C101 Caution! ESD sensitive device. Precaution should be used when handling the device in order to prevent permanent damage.

4 Operating Conditions

The operating conditions for CC2480 are listed in Table 2. Table 2: Operating Conditions Parameter Min Max Unit Condition Operating ambient temperature range, TA -40 85 °C Operating supply voltage 2.0 3.6 V The supply pins to the radio part must be driven by the 1.8 V on-chip regulator CC2480 Data Sheet SWRS074A Page 6 of 43

5 Electrical Specifications

Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 3: Electrical Specifications Parameter Min Typ Max Unit Condition Current Consumption CPU Active Mode, 16 MHz, low CPU activity 4.3 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. Low CPU activity: no flash access (i.e. only cache hit), no RAM access. CPU Active Mode, 16 MHz, medium CPU activity 5.1 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. Medium CPU activity: normal flash access , minor RAM access. CPU Active Mode, 16 MHz, high CPU activity 5.7 mA Digital regulator on. 16 MHz RCOSC running. No radio, crystals, or peripherals active. High CPU activity: normal flash access, extensive RAM access and heavy CPU load. CPU Active Mode, 32 MHz, low CPU activity 9.5 mA 32 MHz XOSC running. No radio or peripherals active. Low CPU activity : no flash access (i.e. only cache hit), no RAM access CPU Active Mode, 32 MHz, medium CPU activity 10.5 mA 32 MHz XOSC running. No radio or peripherals active. Medium CPU activity: normal flash access , minor RAM access. CPU Active Mode, 32 MHz, high CPU activity 12.3 mA 32 MHz XOSC running. No radio or peripherals active. High CPU activity: normal flash access , extensive RAM access and heavy CPU load. CPU Active and RX Mode 26.7 mA CPU running at full speed (32MHz), 32MHz XOSC running, radio in RX mode, -50 dBm input power. No peripherals active. Low CPU activity. CPU Active and TX Mode, 0dBm 26.9 mA CPU running at full speed (32MHz), 32MHz XOSC running, radio in TX mode, 0dBm output power. No peripherals active. Low CPU activity. Power mode 1 190 µA Digital regulator on, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. Power mode 2 0.5 µA Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off. 32.768 kHz XOSC, POR and ST active. RAM retention. Power mode 3 0.3 µA No clocks. RAM retention. POR active. Peripheral Current Consumption Adds to the figures above if the peripheral unit is activated Sleep Timer 0.2 µA Including 32.753 kHz RCOSC. ADC 1.2 mA When converting. Flash write 3 mA Estimated value Flash erase 3 mA Estimated value

1 Normal Flash access means that the code used exceeds the cache storage so cache misses will

happen frequently. CC2480 Data Sheet SWRS074A Page 7 of 43

5.1 Gener al Characteristics

Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 4: General Characteristics Parameter Min Typ Max Unit Condition/Note Wake-Up and Timing Power mode 1 Æ power mode 0 4.1 µs Digital regulator on, 16 MHz RCOSC and 32 MHz crystal oscillator off. Start-up of 16 MHz RCOSC. Power mode 2 or 3 Æ power mode 0 120 µs Digital regulator off, 16 MHz RCOSC and 32 MHz crystal oscillator off. Start-up of regulator and 16 MHz RCOSC. Active Æ TX or RX 32MHz XOSC initially OFF. Voltage regulator initially OFF 525 µs Time from enabling radio part in power mode 0, until TX or RX starts. Includes start-up of voltage regulator and crystal oscillator in parallel. Crystal ESR=16Ω. Active Æ TX or RX Voltage regulator initially OFF 320 µs Time from enabling radio part in power mode 0, until TX or RX starts. Includes start-up of voltage regulator. Active Æ RX or TX 192 µs Radio part already enabled. Time until RX or TX starts. RX/TX turnaround 192 µs Radio part RF Frequency Range 2400 2483.5 MHz Programmable in 1 MHz steps, 5 MHz between channels for compliance with [1] Radio bit rate 250 kbps As defined by [1] Radio chip rate

2.0 MChip/s As defined by [1]

CC2480 Data Sheet SWRS074A Page 8 of 43

5.2 RF Receive Section

Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 5: RF Receive Parameters Parameter Min Typ Max Unit Condition/Note Receiver sensitivity -92 dBm PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –85 dBm Saturation (maximum input level) 10 dBm PER = 1%, as specified by [1] Measured in 50 Ω single endedly through a balun. [1] requires –20 dBm Adjacent channel rejection + 5 MHz channel spacing dB Wanted signal -88dBm, adjacent modulated channel at +5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Adjacent channel rejection - 5 MHz channel spacing dB Wanted signal -88dBm, adjacent modulated channel at -5 MHz, PER = 1 %, as specified by [1]. [1] requires 0 dB Alternate channel rejection + 10 MHz channel spacing dB Wanted signal -88dBm, adjacent modulated channel at +10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Alternate channel rejection - 10 MHz channel spacing dB Wanted signal -88dBm, adjacent modulated channel at -10 MHz, PER = 1 %, as specified by [1] [1] requires 30 dB Channel rejection ≥ + 15 MHz ≤ - 15 MHz dB dB Wanted signal @ -82 dBm. Undesired signal is an 802.15.4 modulated channel, stepped through all channels from 2405 to 2480 MHz. Signal level for PER = 1%. Values are estimated. Co-channel rejection -6 dB Wanted signal @ -82 dBm. Undesired signal is 802.15.4 modulated at the same frequency as the desired signal. Signal level for PER = 1%. Blocking / Desensitization + 5 MHz from band edge + 10 MHz from band edge + 20 MHz from band edge + 50 MHz from band edge - 5 MHz from band edge - 10 MHz from band edge - 20 MHz from band edge - 50 MHz from band edge -42 -29 -26 -22 -31 -36 -24 -25 dBm dBm dBm dBm dBm dBm dBm dBm Wanted signal 3 dB above the sensitivity level, CW jammer, PER = 1%. Measured according to EN 300 440 class 2. Spurious emission 30 – 1000 MHz 1 – 12.75 GHz −64 −75 dBm dBm Conducted measurement in a 50 Ω single ended load. Complies with EN 300 328, EN 300 440 class 2, FCC CFR47, Part 15 and ARIB STD-T-66. Frequency error tolerance ±140 ppm Difference between centre frequency of the received RF signal and local oscillator frequency. [1] requires minimum 80 ppm Symbol rate error tolerance ±900 ppm Difference between incoming symbol rate and the internally generated symbol rate [1] requires minimum 80 ppm

5.3 RF Transmit Section

Measured on Texa s In struments CC2480 EM refe rence design with T A=25°C, VDD=3.0V, an d nominal output power unless stated otherwise. CC2480 Data Sheet SWRS074A Page 9 of 43

Table 6: RF Transmit Parameters Parameter Min Typ Max Unit Condition/Note Nominal output power 0 dBm Delivered to a single ended 50 Ω load through a balun. [1] requires minimum –3 dBm Harmonics nd harmonic rd harmonic th harmonic th harmonic -50.7 -55.8 -54.2 -53.4 dBm dBm dBm dBm Measurement conducted with 100 kHz resolution bandwidth on spectrum analyzer. Output Delivered to a single ended 50 Ω load through a balun. Spurious emission 30 - 1000 MHz 1– 12.75 GHz 1.8 – 1.9 GHz 5.15 – 5.3 GHz -47 -43 -58 -56 dBm dBm dBm dBm Maximum output power. Texas Instruments CC2480 EM reference design complies with EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD- T-66. Transmit on 2480MHz under FCC is supported by duty-cycling The peak conducted spurious emission is -47 dBm @ 192 MHz which is in an EN 300 440 restricted band limited to -54 dBm. All radiated spurious emissions are within the limits of ETSI/FCC/ARIB. Conducted spurious emission (CSE) can be reduced with a simple band pass filter connected between matching network and RF connector (1.8 pF in parallel with 1.6 nH reduces the CSE by 20 dB), this filter must be connected to good RF ground. EVM 11 % Measured as defined by [1] [1] requires max. 35 % Optimum load impedance + j164 Ω Differential impedance as seen from the RF-port (RF_P and RF_N) towards the antenna 5.4 32 MHz Crystal Oscillator Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 7: 32 MHz Crystal Oscillator Parameters Parameter Min Typ Max Unit Condition/Note Crystal frequency 32 MHz Crystal frequency accuracy requirement - 40 40 ppm Including aging and temperature dependency, as specified by [1] ESR 6 16 60 Ω Simulated over operating conditions C0 1 1.9 7 pF Simulated over operating conditions CL 10 13 16 pF Simulated over operating conditions Start-up time 212 µs 5.5 32.768 kHz Crystal Oscillator Measured o n Texa s In struments CC2480 EM refe rence design with T A=25°C a nd V DD=3.0V unless stated otherwise.

2 This is for 2440MHz

CC2480 Data Sheet SWRS074A Page 10 of 43

Table 8: 32.768 kHz Crystal Oscillator Parameters Parameter Min Typ Max Unit Condition/Note Crystal frequency 32.768 kHz Crystal frequency accuracy requirement –40 40 ppm Including aging and temperature dependency, as specified by [1] ESR 40 130 kΩ Simulated over operating conditions C0 0.9 2.0 pF Simulated over operating conditions CL 12 16 pF Simulated over operating conditions Start-up time 400 ms Value is simulated. 5.6 32 kHz RC Oscillator Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 9: 32 kHz RC Oscillator parameters Parameter Min Typ Max Unit Condition/Note Calibrated frequency 32.753 kHz The calibrated 32 kHz RC Oscillator frequency is the 32 MHz XTAL frequency divided by 977 Frequency accuracy after calibration ±0.2 % Value is estimated. Temperature coefficient +0.4 % / °C Frequency drift when temperature changes after calibration. Value is estimated. Supply voltage coefficient +3 % / V Frequency drift when supply voltage changes after calibration. Value is estimated. Initial calibration time 1.7 ms When the 32 kHz RC Oscillator is enabled, calibration is continuously done in the background as long as the 32 MHz crystal oscillator is running. 5.7 16 MHz RC Oscillator Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 10: 16 MHz RC Oscillator parameters Parameter Min Typ Max Unit Condition/Note Frequency 16 MHz The calibrated 16 MHz RC Oscillator frequency is the 32 MHz XTAL frequency divided by 2 Uncalibrated frequency accuracy ±18 % Calibrated frequency accuracy ±0.6 ±1 % Start-up time 10 µs Temperature coefficient -325 ppm / °C Frequency drift when temperature changes after calibration Supply voltage coefficient 28 ppm / mV Frequency drift when supply voltage changes after calibration Initial calibration time 50 µs When the 16 MHz RC Oscillator is enabled it will be calibrated continuously when the 32MHz crystal oscillator is running. CC2480 Data Sheet SWRS074A Page 11 of 43

5.8 Frequency Synthesizer Characteristics

Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 11: Frequency Synthesizer Parameters Parameter Min Typ Max Unit Condition/Note Phase noise −116 −117 −118 dBc/Hz dBc/Hz dBc/Hz Unmodulated carrier At ±1.5 MHz offset from carrier At ±3 MHz offset from carrier At ±5 MHz offset from carrier PLL lock time 192 µs The startup time until RX/TX turnaround. The crystal oscillator is running.

5.9 Analog Temperature Sensor

Measured o n Texas In struments CC2480 EM reference de sign with T A=25°C an d VDD=3.0V unless stated otherwise. Table 12: Analog Temperature Sensor Parameters Parameter Min Typ Max Unit Condition/Note Output voltage at –40°C 0.648 V Value is estimated Output voltage at 0°C 0.743 V Value is estimated Output voltage at +40°C 0.840 V Value is estimated Output voltage at +80°C 0.939 V Value is estimated Temperature coefficient 2.45 mV/°C Fitted from –20°C to +80°C on estimated values. Absolute error in calculated temperature –8 °C From –20°C to +80°C when assuming best fit for absolute accuracy on estimated values: 0.743V at 0°C and 2.45mV / °C. Error in calculated temperature, calibrated -2 0 2 °C From –20°C to +80°C when using 2.45mV / °C, after 1-point calibration at room temperature. Values are estimated. Indicated min/max with 1- point calibration is based on simulated values for typical process parameters Current consumption increase when enabled 280 µA

5.10 ADC

Measured wi th TA=25°C and V DD=3.0V. Note tha t other d ata may re sult when u sing T exas Instruments’ CC2480 EM reference design. Table 13: ADC Characteristics Parameter Min Typ Max Unit Condition/Note Input voltage 0 VDD V VDD is voltage on AVDD_SOC pin Input resistance, signal 197 kΩ Simulated using 4 MHz clock speed. Full-Scale Signal

2.97 V Peak-to-peak, defines 0dBFS

3 Measured with 300 Hz Sine input and VDD as reference. CC2480 Data Sheet SWRS074A Page 12 of 43

Parameter Min Typ Max Unit Condition/Note ENOB 5.7 bits 7-bits setting. Single ended input 7.5 9-bits setting. 9.3 10-bits setting. 10.8 12-bits setting. ENOB Error! Bookmark not defined. 6.5 bits 7-bits setting. Differential input 8.3 9-bits setting. 10.0 10-bits setting. 11.5 12-bits setting. Useful Power Bandwidth 0-20 kHz 7-bits setting THD -Single ended input -75.2 dB 12-bits setting, -6dBFS -Differential input -86.6 dB 12-bits setting, -6dBFS Signal To Non-Harmonic Ratio -Single ended input 70.2 dB 12-bits setting -Differential input 79.3 dB 12-bits setting Spurious Free Dynamic Range -Single ended input 78.8 dB 12-bits setting, -6dBFS -Differential input 88.9 dB 12-bits setting, -6dBFS CMRR, differential input <-84 dB 12- bit setting, 1 kHz Sine (0dBFS), limited by ADC resolution Crosstalk, single ended input <-84 dB 12- bit setting, 1 kHz Sine (0dBFS), limited by ADC resolution Offset -3 mV Mid. Scale Gain error 0.68 % DNL

0.05 LSB 12-bits setting, mean

0.9 LSB 12-bits setting, max

4.6 LSB 12-bits setting, mean

13.3 LSB 12-bits setting, max

35.4 dB 7-bits setting. Single ended input 46.8 dB 9-bits setting. (-THD+N) 57.5 dB 10-bits setting. 66.6 dB 12-bits setting. SINAD Error! Bookmark not defined. 40.7 dB 7-bits setting. Differential input 51.6 dB 9-bits setting. (-THD+N) 61.8 dB 10-bits setting. 70.8 dB 12-bits setting. Conversion time 20 µs 7-bits setting. 36 µs 9-bits setting. 68 µs 10-bits setting. 132 µs 12-bits setting. Power Consumption 1.2 mA CC2480 Data Sheet SWRS074A Page 13 of 43

5.11 Control AC Characteristics

TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 14: Control Inputs AC Characteristics Parameter Min Typ Max Unit Condition/Note System clock, fSYSCLK tSYSCLK= 1/ fSYSCLK 16 32 MHz System clock is 32 MHz when crystal oscillator is used. System clock is 16 MHz when calibrated 16 MHz RC oscillator is used. RESET_N low width 250 ns See item 1, Figure 1. This is the shortest pulse that is guaranteed to be recognized as a complete reset pin request. Note that shorter pulses may be recognized but will not lead to complete reset of all modules within the chip. Interrupt pulse width tSYSCLK ns See item 2, Figure 1.This is the shortest pulse that is guaranteed to be recognized as an interrupt request. In PM2/3 the internal synchronizers are bypassed so this requirement does not apply in PM2/3. RESET_N GPIOx GPIOx Figure 1: Control Inputs AC Characteristics CC2480 Data Sheet SWRS074A Page 14 of 43

5.12 SPI AC Characteristics

TA= -40°C to 85°C, VDD=2.0V to 3.6V if nothing else stated. Table 15: SPI AC Characteristics Parameter Min Typ Max Unit Condition/Note SSN low to SCK 2*tSYSCLK See item 5 Figure 2 SCK to SSN high 30 ns See item 6 Figure 2 SCK period 100 ns See item 1 Figure 2 SCK duty cycle 50% SI setup 10 ns See item 2 Figure 2 SI hold 10 ns See item 3 Figure 2 SCK to SO 25 ns See item 4 Figure 2, load = 10 pF Figure 2: SPI AC Characteristics

5.13 Port Outputs AC Characteristics

TA= 25°C, VDD=3.0V if nothing else stated. Table 16: Port Outputs AC Characteristics Parameter Min Typ Max Unit Condition/Note GPIO/USART output rise time (SC=0/SC=1) 3.15/ 1.34 ns Load = 10 pF Timing is with respect to 10% VDD and 90% VDD levels. Values are estimated fall time (SC=0/SC=1) 3.2/ 1.44 Load = 10 pF Timing is with respect to 90% VDD and 10% VDD. Values are estimated

5.14 DC Characteristics

The DC Characteristics of CC2480 are listed in Table 17 below. TA=25°C, VDD=3.0V if nothing else stated. Table 17: DC Characteristics CC2480 Data Sheet SWRS074A Page 15 of 43

Digital Inputs/Outputs Min Typ Max Unit Condition Logic "0" input voltage 30 % Of VDD supply (2.0 – 3.6 V) Logic "1" input voltage 70 % Of VDD supply (2.0 – 3.6 V) Logic "0" input current per pin NA 12 nA Input equals 0V Logic "1" input current NA 12 nA Input equals VDD Total logic “0” input current all pins 70 nA Total logic “1” input current all pins 70 nA I/O pin pull-up and pull-down resistor 20 kΩ CC2480 Data Sheet SWRS074A Page 16 of 43

6 Pin and I/O Port Configuration

The CC2480 pinout is shown in Figure 3 with details in Table 18. Figure 3: Pinout top view Note: The exposed di e attach pad must be connected to a solid gro und plane a s this i s the ground connection for the chip. CC2480 Data Sheet SWRS074A Page 17 of 43

Table 18: Pinout overview Pin Pin name Pin type Description - GND Ground The exposed die attach pad must be connected to a solid ground plane

1 NC N/A

2 NC N/A

3 GPIO3 Digital I/O General I/O pin 3

4 GPIO2 Digital I/O General I/O pin 2

5 SRDY Digital Output Slave ready. Mandatory for SPI, optional for UART. 6 MRDY Digital Input Master ready. Optional for SPI and UART. 7 DVDD Power (Digital) 2.0V-3.6V digital power supply for digital I/O

8 GPIO1 Digital I/O General I/O pin 1 – increased drive capability

9 GPIO0 Digital I/O General I/Opin 0 – increased drive capability

10 RESET_N Digital input Reset, active low

11 CFG0 Digital Input Configuration input 0

12 CFG1 Digital Input Configuration input 1

13 SO/RX Digital Input SPI slave output or UART RX data

14 SI/TX Digital Output SPI slave input or UART TX data

15 SS/CT Digital I/O SPI slave select (in) or UART CTS (out)

16 C/RT Digital Input SPI clock or UART RTS

17 A0 Analog Input ADC input A0

18 A1 Analog Input ADC input A1

19 XOSC_Q2 Analog I/O 32 MHz crystal oscillator pin 2

20 AVDD_SOC Power (Analog) 2.0V-3.6V analog power supply connection

21 XOSC_Q1 Analog I/O 32 MHz crystal oscillator pin 1, or external clock input

22 RBIAS1 Analog I/O External precision bias resistor for reference current

23 AVDD_RREG Power (Analog) 2.0V-3.6V analog power supply connection 24 RREG_OUT Power output 1.8V Voltage regulator power supply output. Only intended for supplying the analog 1.8V part (power supply for pins 25, 27-31, 35-40). 25 AVDD_IF1 Power (Analog) 1.8V Power supply for the receiver band pass filter, analog test module, global bias and first part of the VGA

26 RBIAS2 Analog output External precision resistor, 43 kΩ, ±1 %

27 AVDD_CHP Power (Analog) 1.8V Power supply for phase detector, charge pump and first part of loop filter

28 VCO_GUARD Power (Analog) Connection of guard ring for VCO (to AVDD) shielding

29 AVDD_VCO Power (Analog) 1.8V Power supply for VCO and last part of PLL loop filter 30 AVDD_PRE Power (Analog) 1.8V Power supply for Prescaler, Div-2 and LO buffers 31 AVDD_RF1 Power (Analog) 1.8V Power supply for LNA, front-end bias and PA 32 RF_P RF I/O Positive RF input signal to LNA during RX. Positive RF output signal from PA during TX

33 TXRX_SWITCH Power (Analog) Regulated supply voltage for PA

34 RF_N RF I/O Negative RF input signal to LNA during RX

Negative RF output signal from PA during TX 35 AVDD_SW Power (Analog) 1.8V Power supply for LNA / PA switch 36 AVDD_RF2 Power (Analog) 1.8V Power supply for receive and transmit mixers 37 AVDD_IF2 Power (Analog) 1.8V Power supply for transmit low pass filter and last stages of VGA 38 AVDD_ADC Power (Analog) 1.8V Power supply for analog parts of ADCs and DACs 39 DVDD_ADC Power (Digital) 1.8V Power supply for digital parts of ADCs

40 AVDD_DGUARD Power (Digital) Power supply connection for digital noise isolation

41 AVDD_DREG Power (Digital) 2.0V-3.6V digital power supply for digital core voltage regulator 42 DCOUPL Power (Digital) 1.8V digital power supply decoupling. Do not use for supplying external circuits. 43 32K_XOSC_Q2 Analog I/O 32.768 kHz XOSC 44 32K_XOSC_Q1 Analog I/O 32.768 kHz XOSC

45 NC N/A

46 NC N/A

47 DVDD Power (Digital) 2.0V-3.6V digital power supply for digital I/O

48 NC N/A

CC2480 Data Sheet SWRS074A Page 18 of 43

7 Circuit Description

Figure 4: CC2480 Block Diagram own in Figure 4. The mo dules can be rough es: CPU-relate distribution, and radio-related modules. CC2480 IEEE 802.15.4 compli ant radio r. See MEMORY ARBITRATOR

8051 CPU

RESETRESET_N GPIO3 GPIO2 GPIO1 GPIO0 SI/TX SO/RX SS/CT C/RT SRDY MRDY 32.768 kHz CRYSTAL OSC

32 MHz

CLOCK MUX & CALIBRATION USART IEEE 802.15.4 MAC TIMER AES ENCRYPTION DECRYPTION IRQ CTRL FIFO AND FRAME CONTROL AGC RF_P RF_N MODULATORDEMODULATOR POWER ON RESET BROWN OUT SLEEP MODE CONTROLLER SLEEP TIMERXOSC_Q2 XOSC_Q1 ∆Σ ADC AUDIO / DC

2 CHANNELS

VDD (2.0 - 3.6 V) DCOUPL ON-CHIP VOLTAGE REGULATOR RECEIVE CHAIN TRANSMIT CHAIN FREQUENCY SYNTHESIZER DIGITAL ANALOG MIXED GP I/O 32K_XOSC_Q2 32K_XOSC_Q1 A block di agram of CC2480 is sh ly divide d into features an one of three categori d modules, modules related to p ower an d clock based on the leading CC2420 transceive Section 10 for details. CC2480 Data Sheet SWRS074A Page 19 of 43

8 Application Circuit

Few external components are requi red for the operation of CC2480. A typical app lication circuit is shown in Figure 5. Typical values and description of external components are sho wn in Table 19.

8.1 Input / output matching

The RF inp ut/output is hi gh imp edance and differential. T he optimum differential lo ad for the RF port is 60 + j164 Ω4. When using an unbalanced antenna such as a monopole, a balun should be used in o rder to optimize pe rformance. T he bal un can be implemented using low-cost discrete ind uctors and capa citors. The re commended balun shown, co nsists of C34 1, L341, L321 and L331 to gether with a PCB mi crostrip transmission line ( λ/2-dipole), and will match the RF inp ut/output to 50 Ω. An internal T/R switch ci rcuit is used to switch b etween the 4 This is for 2440MHz. LNA (RX) and the PA (T X). See In put/output matching section on page 33 for more details. If a bala nced antenna such as a folded dipole is used, the balun can be omitted. If the antenna also provid es a DC pa th from TXRX_SWITCH pin to the RF pin s, in ductors are not needed for DC bias. Figure 5 shows a suggested application circuit using a differential antenna. The antenna type is a sta ndard folded dip ole. The dip ole has a virtual groun d point; hen ce bi as i s p rovided without deg radation in a ntenna performance. Also refer to the se ction Antenna Considerations on page 35.

8.2 Bias resistors

The bia s resistors a re R2 21 an d R2 61. The bias resistor R221 is u sed to set a n accurate bias current for the 32 MHz crystal oscillator.

8.3 Cr ystal

An external 32 M Hz crystal, XTAL1, with two loading cap acitors (C 191 and C2 11) is used for the 32 MHz crystal oscillator. See page 10 for details. The load capacitance seen by the

32 MHz crystal is given by:

XTAL2 is a n optional 32.768 kHz cryst al, with two loading capacitors (C441 and C431), used for the 32.768 kHz crys tal oscillator. The 32.768 kHz crystal o scillator is u sed in applications where yo u n eed both ve ry lo w sleep current consumption and accurate wake up time s. T he lo ad capacitance seen by the 32.768 kHz crystal is given by: parasiticL C CC C + 431441 A series resistor may be used to comply with the ESR requirement.

8.4 Voltage regulators

The on chip voltage regulators supply all 1.8 V power supply pins and internal power supplies. C241 and C421 are required for stability of the regulators. CC2480 Data Sheet SWRS074A Page 20 of 43

8.5 Power supply decoupling and filtering

Proper power supply decoupling must be used for optimum performance. The pla cement and size of the de coupling ca pacitors and th e power supply filtering a re very imp ortant to achieve th e be st p erformance in an application. TI provides a compact refere nce design that should b e fo llowed very closely. Refer to the section PCB Layout Recommendation on page 35. Figure 5: CC2480 Applicatio n Circuit. (Digital I/O and ADC interface not connected Decouplin g capacitors shownot n. QL P 4 8 7x7CC2480 R261 2.0 - 3.6V Power Supply C341 Antenna (50 Ohm) L331 L321 RESET_N NC GPIO3 GPIO2 SRDY DVDD MRDY GPIO1 GPIO0 CFG0 CFG1 NC SO/RX SI/TX SS/CT C/RT XOSC_Q2 AVDD_SOC XOSC_Q1 RBIAS1 AVDD_RREG RREG_OUT AVDD_PRE RF_P RF_N AVDD_SW AVDD_RF1 TXRX_SWITCH AVDD_RF2 AVDD_IF1 AVDD_CHP VCO_GUARD RBIAS2 AVDD_VCO 32K_XOSC_Q2 NC DVDD NC 32K_XOSC_Q1 AVDD_DREG DCOUPL AVDD_DGUARD DVDD_ADC AVDD_ADC AVDD_IF2 NC R221 C241 XTAL2 C441 C431 or L321 Folded Dipole PCB AntennaL331 XTAL1 C211C191 C421 L341 optional λ/4λ/4 CC2480 Data Sheet SWRS074A Page 21 of 43

Table 19: Overview of external components (excluding supply decoupling capacitors) Component Description Single Ended 50Ω Output Differential Antenna C191 32 MHz crystal load capacitor 33 pF, 5%, NP0, 0402 33 pF, 5%, NP0, 0402 C211 32 MHz crystal load capacitor 27 pF, 5%, NP0, 0402 27 pF, 5%, NP0, 0402 C241 Load capacitance for analogue power supply voltage regulators 220 nF, 10%, 0402 220 nF, 10%, 0402 C421 Load capacitance for digital power supply voltage regulators 1 µF, 10%, 0402 1 µF, 10%, 0402 5.6 pF, 5%, NP0, 0402 Not used C341 DC block to antenna and match Note: For RF connector a LP filter can be connected between this C, the antenna and good ground in order to remove conducted spurious emission by using 1.8pF in parallel with 1.6nH 1.8 pF, Murata COG 0402, GRM15 1.6 nH, Murata 0402, LQG15HS1N6S02 C431, C441 32.768 kHz crystal load capacitor (if low- frequency crystal is needed in application) 15 pF, 5%, NP0, 0402 15 pF, 5%, NP0, 0402 L321 Discrete balun and match 6.8 nH, 5%, Monolithic/multilayer, 0402 12 nH 5%, Monolithic/multilayer, 0402 L331 Discrete balun and match 22 nH, 5%, Monolithic/multilayer, 0402 27 nH, 5%, Monolithic/multilayer, 0402 L341 Discrete balun and match 1.8 nH, +/-0.3 nH, Monolithic/multilayer, 0402 Not used R221 Precision resistor for current reference generator to system-on-chip part 56 kΩ, 1%, 0402 56 kΩ, 1%, 0402 R261 Precision resistor for current reference generator to RF part 43 kΩ, 1%, 0402 43 kΩ, 1%, 0402 XTAL1 32 MHz Crystal 32 MHz crystal, ESR < 60 Ω

32 MHz crystal,

ESR < 60 Ω XTAL2 Optional 32.768 kHz watch crystal (if low- frequency crystal is needed in application) 32.768 kHz crystal, Epson MC 306. 32.768 kHz crystal, Epson MC 306. CC2480 Data Sheet SWRS074A Page 22 of 43

9 Peripherals

In th e fo llowing su b-sections th e u ser- accessible CC2480 peri pheral modul es a re described in detail.

9.1 Res et

The CC2480 has four reset source s. The following events generate a reset:

• Forcing RESET_N input pin low
• A power-on reset condition
• A brown-out reset condition
• A firmwa re-generated re set (SYS_RESET_REQ [2]) The initial condition s after a reset are as follows:
• I/O pins are configured as inputs with pull- up
• See the CC2480 Interface Specification [2] for a description of the interaction between CC2480 an d the ho st processor after reset.

9.1.1 Power On Reset and Brown Out Detector

The CC2480 includes a Power On Reset (POR) providing co rrect initialization du ring device power-on. Also in cludes is a Brown Out Detector (B OD) ope rating on the re gulated 1.8V digital p ower supply only, The BOD will protect the memory con tents d uring su pply voltage variations whi ch cau se the re gulated 1.8V power to dro p belo w the minimu m level required by flash memory and SRAM. When power is initially applied to the CC2480 the Power On Re set (POR) and B rown Out Detector (BO D) will hol d the devi ce in re set state u ntil th e supply volt age reaches above the Power On Reset and Brown Out voltages. Figure 6 shows th e PO R/BOD o peration wit h the 1.8V (ty pical) regulated supply voltage together with the active low re set sign als BOD_RESET and POR_RESET shown in the bottom of the figure (n ote that signal s are not available, just for illustration of events). UNREGULATED 1.8V REGULATED POR RESET ASSERT FALLING VDD BOD RESET ASSERT POR RESET DEASSERT RISING VDD VOLT POR OUTPUT BOD RESET POR RESET X X X X X X Figure 6 : Power On Reset and Brown Out Detector Operation

9.2 I/O ports

The CC2480 has digital in put/output pi ns th at have the following key features:

• General purpose I/O or peripheral I/O
• Pull-up or pull-down capability on inputs
• External interrupt capability Two of the I /O pins h ave external int errupts that can be used to wake up the device from sleep modes. CC2480 Data Sheet SWRS074 Page 23 of 43

9.2.1 Unused I/O pins

Unused I/O pins shoul d have a d efined level and not be left floating. One way to do this is to leave the pin unconnected and configured with pull-up resistor. This is also the state of all pins after reset.

9.2.2 Low I/O Supply Voltage

In applicatio ns where the digital I/O powe r supply voltage pin DVDD is belo w 2.6 V, the SC bit sh ould be set to 1 in order to obtain output DC characte ristics spe cified in section 5.14. See the CC2480 user guid e [2] for a description of how to do this.

9.2.3 General Purpose I/O

See the CC2480 user guide [2] for a description of how to configure and use the GPIO pins. The outp ut drive st rength is 4 mA on all outputs, except for the tw o high-drive outputs, GPIO0 and GPIO1, whi ch each have ~20 mA output drive strength. When u sed as a n inp ut, the gen eral purpose I/O port pins can be configured to have a pull- up, pull-down or tri-state mode of operation. By default, after a reset, inputs are configured as inputs with pull-up. Plea se note th at GPIO0 and GPIO 1 do not h ave pull-up o r p ull-down capabilities. In powe r mo des PM2 and PM3 the I/O pins retain the I/ O mo de and out put va lue (if applicable) that was set when PM2/ 3 was entered CC2480 Data Sheet SWRS074 Page 24 of 43

9.3 ADC

9.3.1 ADC Introduction

The ADC supports up to 12-bit ana log-to- digital conversion. The ADC in cludes a n analog multip lexer with up to two individually configurable channels a nd refe rence voltage generator. The main features of the ADC are as follows:

• Selectable d ecimation r ates w hich al so sets the resolution (7 to 12 bits).
• Two i ndividual in put channels, single- ended or differential
• Internal voltage reference
• T emperature sensor input
• Battery measurement capability input mux Sigma-delta modulator Decimation filter Clock generation and control input mux VDD/3 TMP_SENSOR Int 1.25V Figure 7: ADC block diagram.

9.3.2 ADC Operation

This section describes the gen eral setu p an d operation of the ADC.

9.3.2.1 ADC Core

The ADC inclu des an ADC cap able of converting a n analo g in put into a digital representation with up to 12 bits re solution. The ADC uses a sel ectable positive ref erence voltage.

9.3.2.2 ADC Inputs

The si gnals from inp ut pi ns A0 a nd A1 are used as single-ended ADC input s. Th e ADC automatically perfo rms a seq uence of conversions when the SYS_ADC_READ command is issued. In addition to the input pins A0-1, the output of an on -chip temperatu re sen sor can b e selected as an input to the A DC for temperature measurements. It is also possible to sele ct a voltage corresponding to AVDD_ SOC/3 as a n ADC input. This i nput allows the imple mentation of e.g. a battery monitor in appli cations wh ere this feature is req uired.

9.3.2.3 ADC conversion sequences

The CC2480 has t wo ADC chan nels that are connected to extern al pi ns. Additio nally, the ADC can measure the chi p volta ge a nd temperature. The ADC co nversions are done channel by channel incrementally. The two external pin inputs A0 and A1 can be used as single-ended or differential inputs. In the ca se whe re diff erential inpu ts are selected, the differential inputs consist of the input p air A0 -1. Note th at no negative su pply can be a pplied to the se pins, n or a supply larger than VDD (unregulated power). It is the difference b etween the pairs tha t are converted in differential mode. CC2480 Data Sheet SWRS074 Page 25 of 43

In addition to the input pins A0-1, the output of an on -chip temperatu re sen sor can b e selected a s an input to the ADC fo r temperature measurements. It is al so possible to sel ect a voltage corresponding to AVDD_ SOC/3 a s an ADC input. Thi s input allows the implementation of e.g. a battery monitor in application s where this feature is required.

9.3.2.4 ADC Operating Modes

This se ction d escribes th e op erating mo des and initialization of conversions. The A DC u ses an i nternal voltage re ference for single-ended conversions. The d ecimation rate (an d thereby al so th e resolution an d time req uired to comp lete a conversion a nd sampl e rate) is confi gurable from 7-12 bits.

9.3.2.5 ADC Conversion Results

The digital conversion result is rep resented in two's co mplement form. The re sult i s always positive. Thi s is be cause the re sult is the difference b etween ground and in put sign al which is always posivitely signe d (Vconv=Vinp-Vinn, whe re Vinn =0V). The maximum value is re ached wh en th e input amplitude is equal VREF, the internal voltage reference. For differenti al config urations the difference between th e pin s i s converted a nd this difference can be negatively signed. For 12-bit resolution the digital co nversion result is 2047 when the a nalog inp ut, Vco nv, is equal to VREF, and the conversi on result is -20 48 when the analog input is equal to –VREF.

9.3.2.6 ADC Reference Voltage

The po sitive referen ce voltage for anal og-to- digital conversions i s an i nternally ge nerated 1.25V voltage.

9.3.2.7 ADC Conversion Timing

The A DC i s run on t he 3 2MHz system clo ck, which is divided by 8 to give a 4 MHz clock. The time re quired to pe rform a con version depends on the sele cted de cimation rate. When the decimation rate is set to for instance 128, the decimation filter use s exactly 128 of the 4 MHz clock periods to calculate the result. When a conversion i s starte d, th e inp ut multiplexer is allowed 16 4 MHz clock cycles to settle in case the chan nel has be en changed since the p revious conversion. The 1 6 clo ck cycles settling t ime a pplies t o all d ecimation rates. Thus in general, the conversion time is given by: Tconv = (decimation rate + 16) x 0.25 µs. CC2480 Data Sheet SWRS074 Page 26 of 43

9.4 Random Number Generator

9.4.1 Introdu ction

The rand om numb er g enerator has the following features.

• Generate pseudo-random bytes which can be read by the external microprocessor. The random num ber g enerator i s a 16 -bit Linear Feedback Shift Registe r (LFS R) with polynomial 121516 +++ XXX (i.e. CRC16). It uses different levels of unrolling d epending on the operation it performs. The basic version (no unrolling) is shown in Figure 8. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0+ + +in_bit Figure 8: Basic structure of the Random Number Generator

9.4.2 Semi random sequence generation

The operation is to clock the LFSR once (13x unrolling) each time the external microprocessor read s the random value. This leads to the availabilit y of a fresh pseudo- random byte from the LSB end of the LFSR. CC2480 Data Sheet SWRS074 Page 27 of 43

9.5 USART

The USART is a seri al commu nications interface that c an be operated in e ither asynchronous UART mode or in synchronous SPI mode.

9.5.1 UART mode

For asynchronous serial interfaces, the UART mode i s pro vided. In the UART m ode the interface uses a two-wire or four-wire interface consisting of the pins RXD, TXD and optionally RTS and CTS. The UART mode of o peration is as follows:

• Baud rate: 115200.
• Hardware (RTS/CTS) flow control.
• 8N1 byte format.
• DCE signal connection. The UART mode provides f ull duplex asynchronous tr ansfers, a nd th e synchronization of bits in the receiver does not interfere with the tran smit function. A UART byte transfer consists of a start bit, eight data bits, a parity bit, and one stop bit.

9.5.2 SPI Mode

This sectio n describ es the SPI mo de of operation fo r synchro nous co mmunication. In SPI mode, th e USART communicates with an external sy stem throu gh a 3-wi re o r 4-wire interface. The interface consists of the pins SI, SO, SCK and SS_N. Th e SPI mode is as follows:

• SPI slave.
• Clock speed up to 4 MHz.
• Clock po larity 0 an d clock p hase 0 o n CC2480 .
• Bit order: MSB first.

9.5.2.1 SPI Slave Operation

An SPI byte tran sfer i n slave mo de is controlled by the external system. The d ata on the SI input is shifted i nto the receive registe r controlled by the serial clock SCK which is an input in slave mode. At the same time the byte in the tran smit register is shifted out onto the SO output.

9.5.3 SSN Slave Select Pin

When the USART is operating i n SPI mode, configured as an SPI slave, a 4 -wire interface is used with t he Slave Select (SSN) pin as an input to the SPI (edge controlled). At falling edge of SS N the SPI slave i s active and receives data on the SI in put and outputs data on the SO output. At rising edge of SSN, the SPI slave is inactive and will not receive data. Note that the SO output is not tri-state d after rising e dge on SSn. Thi s coul d be a chieved using an external buffer. Also note that release of SSn (rising edge) must be aligned to end of byte recived or sent. If released in a b yte the next re ceived byte will not be receive d properly as information about previous byte is present in SPI system. CC2480 Data Sheet SWRS074 Page 28 of 43

10 Radio

• Digital RSSI - Gain Control - Image Suppression - Channel Filtering - Demodulation - Frame synchronization DIGITAL MODULATOR - Data spreading - ModulationΣ AUTOMATIC GAIN CONTROL TX POWER CONTROL TXRX SWITCH ADC ADC DAC DAC FREQ SYNTH Power Control PA FFCTRL Register bus CSMA/CA STROBE PROCESSOR RADIO REGISTER BANK RADIO DATA INTERFACE CONTROL LOGIC IRQ HANDLING SFR bus Figure 9: CC2480 Radio Module A simplified block dia gram of the IEEE 802.15.4 co mpliant radio in side CC2480 is shown in Figure 9. The radio core is based on the industry leading CC2420 RF transceiver. CC2480 feature s a lo w-IF re ceiver. The received RF sign al i s a mplified by t he lo w- noise am plifier (LNA ) a nd do wn-converted i n quadrature (I and Q) t o the intermediate frequency (IF). At IF (2 MHz), the complex I/Q signal is filt ered and amplified, an d then digitized by the RF receiver ADCs. The CC2480 transmitter is based on direct up- conversion. The preambl e and sta rt of frame delimiter are gene rated in ha rdware. Each symbol (4 b its) is spread usin g the IEEE 802.15.4 spreading sequence to 32 chips and output to the digital -to-analog converters (DACs). An analog low pass filter passes the signal to the quadrature (I and Q) up-conversion mixers. The RF signal is am plified in the powe r amplifier (PA) and fed to the antenna. The int ernal T/ R switch cir cuitry ma kes t he antenna interface an d matching easy. The RF connection is differential. A balun may be used for single-ended antennas. The biasing of th e PA and LNA is do ne by connecting TXRX_SWITCH to RF_P and RF_N through an external DC path. The fre quency synth esizer i ncludes a completely on-chip LC VCO and a 90 degrees phase splitter for generating the I a nd Q LO signals to the do wn-conversion mi xers in receive mod e and up -conversion mix ers in transmit mo de. The VCO ope rates in the frequency ra nge 48 00 – 4966 M Hz, and the frequency is divided by t wo when spli t into I and Q signals. An on-chi p voltage re gulator deliv ers the regulated 1.8 V supply voltage. CC2480 Data Sheet SWRS074 Page 29 of 43

10.1 IEEE 802.15.4 Modulation Format This section is meant as an introduction to the

2.4 GHz di rect sequ ence sp read sp ectrum

(DSSS) RF modulation format defined in IEEE 802.15.4. F or a complete de scription, please refer to [1]. The mo dulation an d sp reading fu nctions a re illustrated at block level in Figure 10 [1] . Each byte is divide d into two symbols, 4 bits each. The least significant symbol is transmitted first. For multi-byte fields, th e least significant byte is transmitted first. Each symbol is mapp ed to one out of 16 pseudo-random sequ ences, 3 2 chip s e ach. The symbol to chip mapping is shown in Table 20. The chip sequence is then transmitted at 2 MChips/s, wi th the le ast significant chip (C 0) transmitted first for each symbol. Bit-to- Symbol Symbol- to-Chip O-QPSK Modulator Transmitted bit-stream (LSB first) Modulated Signal Figure 10: Modulation and spreading functions [1] The modulation format i s Offset – Qua drature Phase Shift Keying (O-QPSK) with half-s ine chip shaping. This is equivalent to MSK modulation. Each chip is shap ed a s a half- sine, tra nsmitted altern ately in the I and Q channels with one h alf chip period offset. This is illustrated for the zero-symbol in Figure 11. Table 20: IEEE 802.15.4 symbol-to-chip mapping [1] Symbol Chip sequence (C0, C1, C2, … , C31) 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 2 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 3 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 4 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 0 0 1 1 5 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 1 1 0 0 6 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 1 0 0 1 7 1 0 0 1 1 1 0 0 0 0 1 1 0 1 0 1 0 0 1 0 0 0 1 0 1 1 1 0 1 1 0 1 8 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 9 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 10 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 11 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 12 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 0 1 1 0 13 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 14 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 15 1 1 0 0 1 0 0 1 0 1 1 0 0 0 0 0 0 1 1 1 0 1 1 1 1 0 1 1 1 0 0 0 CC2480 Data Sheet SWRS074 Page 30 of 43

Figure 11: I / Q Phases when transmitting a zero-symbol chip sequence, TC = 0.5 µs

10.2 Demodulator, Symbol Synchronizer and Data Decision

The block diagram for the CC2480 demodulator is sh own in Figure 12. Channel filteri ng an d frequency offset comp ensation is performed digitally. The sign al level in the cha nnel i s estimated to gen erate th e RSSI level . Data filtering is also in cluded fo r enhanced performance. With the ±40 ppm freque ncy a ccuracy requirement from [1], a com pliant re ceiver must be able to compensate for up to 80 ppm or 200 kHz. The CC2480 demodulator tolerates up to 300 kHz offset without si gnificant degradation of the receiver performance. Soft decision is use d at the chip level, i .e. the demodulator doe s n ot make a d ecision fo r each chip, on ly for each re ceived symbol. De- spreading i s perfo rmed using over-samplin g symbol correlators. Symbol synchronization is achieved by a continu ous sta rt of frame delimiter (SFD) search. The CC2480 demodulator also han dles symbol rate erro rs i n exce ss of 120 ppm without performance degradati on. Resyn chronization is performed continuously to adjust for error in the incoming symbol rate. Digital IF Channel Filtering ADC Digital Data Filtering Frequency Offset Compensation Symbol Correlators and Synchronisation RSSI Generator I / Q Analog IF signal Data Symbol Output RSSI Average Correlation Value (may be used for LQI) Figure 12: Demodulator Simplified Block Diagram

10.3 Frame Format

CC2480 has hardware support for pa rts of the IEEE 802.15.4 frame format. This section gives a brief s ummary to the IEEE 802.15.4 frame fo rmat, and describes ho w CC2480 is set up to comply with this. Figure 1 3 [1] sh ows a schemati c view of the IEEE 802.15.4 frame format. Similar figures describing spe cific fra me format s (data frames, bea con frame s, ackno wledgment frames an d MAC co mmand frame s) a re included in [1]. CC2480 Data Sheet SWRS074 Page 31 of 43

10.4 Sy nchronization header

sequence is defined to be four bytes of 0x00. The SFD is one byte, set to 0xA7. transmitted first in all transmit modes. used for byte synchronization.

10.5 MAC protocol data unit

Figure 13. Together wit h the MAC data form the MAC Protocol Data Unit (MPDU). The format o f the FCF is sho wn in Fig ure 14. Please refer to [1] for details.

10.6 Frame check sequence

1. The FCS is calculated over the MPDU, i.e.

the length field is not part of the FCS. correct position defined by the length field. frame is correct and low otherwise.

10.7 Linear IF and AGC Settings

CC2480 is based on a linear IF chain where the signal amplification is do ne in an analog VGA (variable gain amplifier). T he gain of the VGA is digitally controlled. The AGC (Automatic G ain Co ntrol) loop ensures th at the ADC operates in side its dynamic range by u sing a n a nalog/digital feedback loop.

10.8 Clear Channel Assessment

The clear channel assessment signal is based on the measured RSSI value and a programmable threshold. The clear channel assessment function is u sed to implem ent the CSMA-CA functionality specified in [1]. CCA is valid when the receiver has been enabled for at least 8 symbol periods.

10.9 VCO and PLL Self-Calibration

10.9.1 VCO

The VCO is co mpletely integrated and operates at 4800 – 4966 M Hz. The VCO frequency is divided b y 2 to generate frequencies in the d esired band (2400-2483.5 MHz).

10.9.2 PLL self-calibration

The VCO's characteri stics will vary with temperature, changes in supply voltages, and the desired operating frequency. In order to ensure reliable operation the VCO’s bias current an d t uning rang e a re automatically calib rated every time the RX mode or TX mode is enabled.

10.10 Input / Output Matching

The RF input / output is di fferential (RF_N and RF_P). In addition there is supply switch output pin ( TXRX_SWITCH) that must h ave an external DC path to RF_N and RF_P. In RX mode the TXRX_SWITCH pi n is at ground and will bias the LNA. In TX mode the TXRX_SWITCH pin is at supply rail voltage and will properly bias the internal PA. The RF output and DC bias can be done using different topologies. Some are shown in Figure 5 on page 21. Component values are gi ven in Ta ble 19 o n page 22. If a differential a ntenna i s implemented, no balun is required. If a si ngle ended output is required (for a single en ded con nector or a single ende d antenna), a balun should be used for optimum performance. CC2480 Data Sheet SWRS074 Page 33 of 43

10.11 System Considerations and Guidelines

10.11.1 SRD regulations

International regulatio ns and nation al laws regulate the use of ra dio re ceivers an d transmitters. SRDs (Short Range Devices) for license free operation are allowed to o perate in the 2.4 GHz ba nd worldwide. T he mo st important re gulations a re ETSI EN 300 32 8 and EN 300 440 (Eu rope), FCC CFR-47 part 15.247 and 15.249 (USA), and ARIB STD-T66 (Japan).

10.11.2 Frequency hopping and multi-channel systems

The 2.4 GHz band is shared by many systems both in i ndustrial, o ffice and home environments. CC2480 uses direct se quence spread spectrum (DSSS) as defined by [1] to spread the o utput po wer, there by maki ng th e communication lin k more robu st ev en in a noisy environment.

10.11.3 Crystal accuracy and drift

A crystal accuracy of ±40 ppm i s required for compliance with IEEE 802.15.4 [1] . This accuracy m ust al so t ake ag eing and temperature drift into consideration. A crystal with low temp erature drift a nd low aging coul d be u sed with out furthe r compensation. A trimmer capacitor in the crystal oscillator circuit (in parallel with C191 in Figure 5) could be u sed to set the initial frequency accurately. For no n-IEEE 802.15.4 systems, the robu st demodulator in CC2480 allows up to 14 0 ppm total frequenc y offset bet ween the trans mitter and receiver. This could e.g. rel ax the accuracy req uirement to 60 ppm fo r each of the devices. Optionally in a star network topology, the full- function device (FFD) could be equipped with a mo re a ccurate crystal thereby relaxi ng the requirement on the red uced-function device (RFD). This can make sense in systems where the re duced-function devices ship i n higher volumes than the full-function devices.

10.11.4 Com munication robustness

CC2480 provides very good adjacent, alternate and co ch annel reje ction, image fre quency suppression and blo cking p roperties. Th e CC2480 performance is significantly better than the re quirements im posed by [1]. Th ese are highly impo rtant pa rameters for reliabl e operation in the 2.4 GHz b and, si nce a n increasing n umber of d evices/systems are using this license free frequency band.

10.11.5 Com munication security

The hardware en cryption and auth entication operations in CC2480 e nable se cure communication, which is req uired fo r many applications. Secu rity operations requi re a lot of data processing, which is costly in an 8-bit microcontroller system. The hardware support within CC2480 enables a hi gh level of secu rity with minimum CPU processing requirements.

10.11.6 Low cost systems

As the CC2480 provides 250 kb ps multi- channel performance wit hout any e xternal filters, a v ery low cost system can be mad e (e.g. two layer P CB with single-sided component mounting). A differential anten na will elimin ate th e ne ed for a balun, and the DC bia sing can be achieved in the antenna topology.

10.11.7 Battery operated systems

In low po wer appli cations, the CC2480 sho uld be pla ced in the low-po wer mod es PM2 or PM3 whe n not active. Ultra low powe r consumption may b e achieved since the voltage regulators are turned off. CC2480 Data Sheet SWRS074 Page 34 of 43

10.12 PCB Layout Recommendation

In the Texas Instruments reference design, the top layer is used for sig nal routin g, and the open a reas are filled with metallization connected to grou nd u sing seve ral via s. The area under the chip is u sed for g rounding and must be well con nected to the groun d plane with several vias. The groun d pins sh ould be con nected to ground a s close as p ossible to the p ackage pin u sing in dividual via s. The d e-coupling capacitors should also be placed as close as possible to the su pply pi ns an d conn ected to the gro und plane by se parate vias. Supply power filtering is very important. The external com ponents sho uld b e a s small as po ssible (0402 is re commended) and surface mount devices must be used. If using an y external high-speed digital devices, caution should be used when placing these i n ord er to avoid i nterference with the RF circuitry. It is strongly advised that this reference layout is followed v ery closely in order to obt ain the best performance. The schematic, BOM and layout G erber file s for the reference designs are all available from the TI website.

10.13 Antenna Considerations

CC2480 ca n be u sed tog ether with v arious types of antennas. A differential antenna like a dipole would be the easi est to interfa ce not needing a b alun (balanced to u n-balanced transformation network). The len gth of the λ/2-dipole anten na i s given by: L = 14250 / f where f i s in MHz, giving t he length in cm. An antenna for 2450 MHz should be 5.8 cm. Each arm is therefore 2.9 cm. Other comm only use d antenna s for short - range com munication are monopole, helical and l oop anten nas. The si ngle-ended monopole an d helical wo uld req uire a balun network bet ween the dif ferential o utput and the antenna. Monopole a ntennas a re resona nt a ntennas with a lengt h corresponding to one q uarter of the electrical wavelength (λ/4). They a re very easy to de sign and can be im plemented simply as a “piece of wire ” or even integrated into the PCB. The length of the λ/4-monopole ante nna is given by: L = 7125 / f where f i s in MHz, giving t he length in cm. An antenna for 2450 MHz should be 2.9 cm. Non-resonant monopole antennas shorter than λ/4 can also be u sed, bu t at the expe nse of range. In si ze and cost critical a pplications such an a ntenna may very well be integrated into the PCB. Enclosing the antenn a in high die lectric constant mat erial redu ces the overall size of the anten na. Many vendo rs offer su ch antennas intended for PCB mounting. Helical ante nnas can b e tho ught of as a combination of a mon opole and a loop antenna. They are a good compromise in size critical appli cations. Heli cal antennas tend to be more difficult to optimiz e than the simple monopole. Loop ante nnas are ea sy to integrate i nto the PCB, but a re le ss effect ive due to difficult impedance matching because of their very low radiation resistance. For lo w po wer appli cations the diff erential antenna is recommended giving th e best range and because of its simplicity. The antenna should be connected as close as possible to the IC. If the antenn a is l ocated away from the RF pi ns the antenna should be matched to the feedin g tran smission lin e (50Ω). CC2480 Data Sheet SWRS074 Page 35 of 43

11 Voltage Regulators

The CC2480 includes two l ow drop-out voltage regulators. These are used to provide a 1.8 V power supply to the CC2480 analog and digital power supplies. Note: It is recommended that the voltage regulators are not u sed t o provi de power to external circuits. Thi s is becau se of lim ited power sourcing ca pability and du e to noise considerations. External circuitry can be powered if t hey can be used when i nternal power consumption is low and can be set I PD mode when internal power consumption I high. The a nalog voltage regulato r in put pin AVDD_RREG is to be co nnected to the unregulated 2.0 to 3.6 V powe r su pply. The regulated 1.8 V voltage o utput to the analog parts, is available on the RREG_OUT pin. The digital re gulator inp ut pin AVDD_DREG is also to be con nected to the unreg ulated 2.0 to 3.6 V power supply. The o utput of the digital regulator is connected internally within the CC2480 to the digital power supply. The voltag e reg ulators req uire external components as described in section 8 on page 20.

11.1 Voltage Regulators Power-on

When the analog voltage regulator is powered- on befo re u se of the ra dio, there will be a delay before the regulator is enabled. The digital v oltage regulator is di sabled when the CC2480 is p laced in lo w po wer modes to reduce power consumption. CC2480 Data Sheet SWRS074 Page 36 of 43

All dimensions are in millimeters, angles in de grees. NOTE: Th e CC2480 is available in RoHS lead- free package only. Compliant with JEDEC MS-020. Table 21: Package dimensions Quad Leadless Package (QLP) D D1 E E1 e b L D2 E2 QLP 48 Min Max 6.9 7.0 7.1 6.65 6.75 6.85 6.9 7.0 7.1 6.65 6.75 6.85 0.5 0.18 0.30 0.3 0.4 0.5 5.05 5.10 5.15 5.05 5.10 5.15 The overall package height is 0.85 +/- 0.05 All dimensions in mm Figure 16: Package dimensions drawing CC2480 Data Sheet SWRS074 Page 37 of 43

12.1 Recommended PCB layout for package (QLP 48)

Figure 17: Recommended PCB layout for QLP 48 package Note: T he fig ure is an illu stration o nly and not to scale. The re are nine 14 mil diameter via holes distributed symmetrically in the g round pad u nder the package. See al so the CC2480 EM referenc e design

12.2 Package thermal properties

Table 22: Thermal properties of QLP 48 package Thermal resistance Air velocity [m/s] 0 Rth,j-a [K/W] 25.6

12.3 Soldering information

The recommendations for lead-free solder reflow in IPC/JEDEC J-STD-020C should be followed.

12.4 Tra y specification

Table 23: Tray specification Tray Specification Package Tray Width Tray Height Tray Length Units per Tray

12.5 Carrier tape and reel specification

Carrier tape and reel is in accordance with EIA Specification 481. CC2480 Data Sheet SWRS074 Page 38 of 43

Table 24: Carrier tape and reel specification Tape and Reel Specification Package Tape Width Component Pitch Hole Pitch Reel Diameter Units per Reel QLP 48 16mm 12mm 4mm 13 inches 2500 CC2480 Data Sheet SWRS074 Page 39 of 43

Table 25: Ordering Information Ordering part number Description MOQ CC2480A1RTC CC2480, QLP48 package, RoHS compliant Pb-free assembly, trays with 260 pcs per tray, ZigBee 2006 Network Processor. 260 CC2480A1RTCR CC2480, QLP48 package, RoHS compliant Pb-free assembly, T&R with 2500 pcs per reel, ZigBee 2006 Network Processor. 2,500 eZ430-RF2480 CC2480 Demonstration Board based on the eZ430-RF platform 1 MOQ = Minimum Order Quantity T&R = tape and reel CC2480 Data Sheet SWRS074 Page 40 of 43

14 General Information

14.1 Docum ent History

Table 26: Document History Revision Date Description/Changes 1.0 2008-04-02 First data sheet for released product.

15 Address Information

Texas Instruments Norway AS Gaustadalléen 21 N-0349 Oslo NORWAY Tel: +47 22 95 85 44 Fax: +47 22 95 85 46 Web site: http://www.ti.com/lpw

16 TI Worldwide Technical Support

TI Semiconductor Product Information Center Home Page: support.ti.com TI Semiconductor KnowledgeBase Home Page: support.ti.com/sc/knowledgebase Product Information Centers Americas Phone: +1(972) 644-5580 Fax: + 1(972) 927-6377 Internet/Email: support.ti.com/sc/pic/americas.htm Europe, Middle East and Africa Phone: Belgium (English) +32 (0) 27 45 54 32 Finland (English) +358 (0) 9 25173948 France +33 (0) 1 30 70 11 64 Germany +49 (0) 8161 80 33 11 Israel (English) 180 949 0107 Italy 800 79 11 37 Netherlands (English) +31 (0) 546 87 95 45 Russia +7 (0) 95 363 4824 Spain +34 902 35 40 28 Sweden (English) +46 (0) 8587 555 22 United Kingdom +44 (0) 1604 66 33 99 Fax: +49 (0) 8161 80 2045 Internet: support.ti.com/sc/pic/euro.htm CC2480 Data Sheet SWRS074 Page 41 of 43

Fax International + 81-3-3344-5317 Domestic 0120-81-0036 Internet/Email International support.ti.com/sc/pic/japan.htm Domestic www.tij.co.jp/pic Asia Phone International + 886-2-23786800 Domestic Toll-Free Number Australia 1-800-999-084 Chin a 800-820-8682 Hong Kon 800-96-5941 India +91-80-51381665 (Toll) Indon esia 001-803-8861-1006 Korea 080-551-2804 Mala ysia 1-800-80-3973 Ne w Zealand 0800-446-934 Phili ppines 1-800-765-7404 Sing apore 800-886-1028 T aiwan 0800-006800 T hailand 001-800-886-0010 Fax + 886-2-2378-6808 Email tiasia@ti.com or ti-china@ti.com Internet support.ti.com/sc/pic/asia.htm CC2480 Data Sheet SWRS074 Page 42 of 43

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