Microcontroller

CC2340R53-Q1

Texas Instruments

CC2340R5-Q1 SimpleLink™ Bluetooth® Low Energy Wireless MCU REVISED JULY 2025

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Technical content

CC2340R5-Q1 SimpleLink™ Bluetooth® Low Energy Wireless MCU

1 Features

AEC-Q100 Grade 2 qualified for automotive

applications

Optimized 48MHz Arm® Cortex®-M0+ processor
512KB of in-system programmable flash
12KB of ROM for bootloader and drivers
2.4GHz RF transceiver compatible with Bluetooth®

5.4 Low Energy

Up to 64KB of ultra-low leakage SRAM. Full RAM retention in standby mode
Integrated balun
Supports over-the-air upgrade (OTA)
Serial wire debug (SWD) Low power consumption
MCU consumption: – 2.6mA active mode, CoreMark® – 53μA/MHz running CoreMark® – < 710nA standby mode, RTC, 64KB RAM – 165nA shutdown mode, wake-up on pin
Radio consumption: – 5.3mA RX – 5.1mA TX at 0dBm – < 11.0mA TX at +8dBm Wireless protocol support
Bluetooth® 5.4 Low Energy High-performance radio
–102dBm for Bluetooth® Low Energy 125kbps
–96.5dBm for Bluetooth® Low Energy 1Mbps
Output power up to +8dBm with temperature compensation Regulatory compliance
Suitable for systems targeting compliance with these standards: – EN 300 328 (Europe) – FCC CFR47 Part 15 – ARIB STD-T66 (Japan) MCU peripherals
19 I/O Pads – 2 IO pads SWD, muxed with GPIOs – 2 IO pads LFXT, muxed with GPIOs – 15 DIOs (analog or digital IOs)
3 × 16-bit and 1× 24-bit general-purpose timers, quadrature decode mode support
12-bit ADC, 1.2Msps with external reference, 267ksps with internal reference, eight external ADC inputs
1× low-power comparator
1× UART
1× SPI
1× I2C
Real-time clock (RTC)
Integrated temperature and battery monitor
Watchdog timer Security enablers
AES 128-bit cryptographic accelerator
Random number generator from on-chip analog noise Product Cybersecurity Compliance
ISO 21434 compliant (Cybersecurity Assurance Level 2)
Developed for cybersecurity-relevant applications
Documentation available to aid cybersecurity system design Development tools and software
LP-EM-CC2340R5 LaunchPad Development Kit
SimpleLink™ CC23xx Software Development Kit (SDK)
SmartRF™ Studio for simple radio configuration
SysConfig system configuration tool Operating range
On-chip buck DC/DC converter
1.71V to 3.8V single supply voltage
Tj: –40 to +125°C
HBM ESD Classification Level 2 (ESD CDM level 1C on RF pin, per AEC-Q100 Rev. J)
CDM ESD Classification Level 2A (ESD CDM level C1 on RF pin, per AEC-Q100 Rev. J) RoHS-compliant package
5mm × 5mm RHB QFN32 with wettable flanks (19 GPIOs) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

2 Applications

Automotive – Car access and security systems
Passive entry passive start (PEPS)
Remote keyless entry (RKE) – Advanced driver assistance systems (ADAS) – Tire pressure monitoring systems (TPMS)

3 Description

The SimpleLink™ CC2340R5-Q1 device is an AEC-Q100 compliant wireless microcontroller (MCU) targeting Bluetooth 5 Low Energy automotive applications. The device is optimized for low-power wireless communication in applications such as tire pressure monitoring systems (TPMS), car access, including key fobs used in passive entry passive start (PEPS) and remote keyless entry (RKE) , cable replacement, and smartphone connectivity. The highlighted features of this device include:

Support for Bluetooth 5 features: high-speed mode (2Mbps PHY), long-range (LE Coded 125kbps and 500kbps PHYs), privacy 1.2.1 and channel selection algorithm #2, as well as backward compatibility and support for key features from the Bluetooth 4.2 and earlier Low Energy specifications.
Fully qualified Bluetooth 5.4 software protocol stack included with the SimpleLink™ CC23xx Software Development Kit (SDK)
Ultra-low standby current less than 0.71μA with RTC operational and full RAM retention that enables significant battery life extension, especially for applications with longer sleep intervals.
Integrated balun for reduced bill-of-material (BOM) board layout
Excellent radio sensitivity and robustness (selectivity and blocking) performance for Bluetooth Low Energy (–102dBm for 125kbps LE Coded PHY, with integrated balun) The CC2340R5-Q1 device is part of the SimpleLink ™ MCU platform, which consists of Wi-Fi, Bluetooth Low Energy, Thread, Zigbee, Sub1GHz MCUs, and host MCUs that all share a common, easy-to-use development environment with a single core software development kit (SDK) and rich tool set. A one-time integration of the SimpleLink™ platform enables you to add any combination of the portfolio’s devices into your design, allowing 100 percent code reuse when your design requirements change. For more information, visit SimpleLink™ MCU platform. Device Information PART NUMBER(1) FLASH RAM TEMPERATURE RANGE PACKAGE PACKAGE SIZE CC2340R52E0WRHBRQ1 512KB 36KB –40°C–125°C QFN32 5.00mm × 5.00mm CC2340R53E0WRHBRQ1 512KB 64KB –40°C–125°C QFN32 5.00mm × 5.00mm (1) For more information, see Section 12. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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4 Functional Block Diagram

48 MHz

B A L U N 2.4GHz Radio Transceiver RF RAM Radio Digital Modem Accelerators PWR & CLK Mgmt. 1x UARTTimers LGPT0-LGPT3 1x SPI 1x I2C RTC WDT Battery Monitor Temperature Sensor IOMUX | 19 GPIOs System Buses AES-128 System Buses µDMA (8 channel)

2.4 GHz

50 Ω 32.768 kHz LFXT 32.768 kHz LFOSC DC/DC Global LDO POR BOD ADC ADC Digital PLL PA LNA 12-bit ADC

1.2 Msps

Shutdown* RNG 1. * Refer to the Device Comparison table for availability of the thermal shutdown feature. Figure 4-1. CC2340R5-Q1 Block Diagram www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CC2340R5-Q1

6.3 Connections for Unused Pins and Modules—

12 Mechanical, Packaging, and Orderable

SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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5 Device Comparison

FLASH (KB) RAM + Cache (KB) GPIO Thermal Shutdown PACKAGE SIZE Bluetooth® LE +20dBm PA 5mm × 5mm VQFN (32) CC2340R52-Q1 X 512 36 19 X X CC2340R53-Q1 X 512 64 19 X www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CC2340R5-Q1

6 Pin Configuration and Functions

6.1 Pin Diagram—RHB Package (Top View)

DIO4_X32N21 DIO5_A223 DCDC24 DIO12 4 DIO11 3 DIO8 2 VDDR 1 DIO3_X32P20 RSTN19 DIO1_A418 DIO24_A717 DIO13 5 DIO14 7 DIO23_A8 VDDD VDDS DIO22_A9 DIO17_SWDCK DIO21_A10 DIO20_A11 DIO16_SWDIO DIO18 DIO19 X48N RFGND ANT VDDS VDDS DIO6_A1 VDDR X48P VDDS Figure 6-1. RHB (5mm × 5mm) Pinout, 0.5mm Pitch (Top View) The following I/O pins marked in Figure 6-1 in bold have high-drive capabilities:

Pin 4, DIO12
Pin 8, DIO16_SWDIO
Pin 9, DIO17_SWDCK
Pin 10, DIO18
Pin 11, DIO19
Pin 17, DIO24_A7 The following I/O pins marked in Figure 6-1 in italics have analog capabilities:
Pin 12, DIO20_A11
Pin 13, DIO21_A10
Pin 15, DIO22_A9
Pin 16, DIO23_A8
Pin 17, DIO24_A7
Pin 18, DIO1_A4
Pin 23, DIO5_A2
Pin 26, DIO6_A1 CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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6.2 Signal Descriptions—RHB Package

Table 6-1. Signal Descriptions—RHB Package PIN I/O TYPE DESCRIPTION NAME NO. EGP — — GND Ground—exposed ground pad(1) VDDR 1 — Power Internal 1.5V supply, must be powered from the internal DC/DC converter or the internal LDO(2) (3) (4) DIO8 2 I/O Digital GPIO DIO11 3 I/O Digital GPIO DIO12 4 I/O Digital GPIO, high-drive capability DIO13 5 I/O Digital GPIO VDDS 6 — Power 1.71V to 3.8V DIO supply(5) DIO14 7 I/O Digital GPIO DIO16_SWDIO 8 I/O Digital GPIO, SWD interface: mode select or SWDIO, high-drive capability DIO17_SWDCK 9 I/O Digital GPIO, SWD interface: clock, high-drive capability DIO18 10 I/O Digital GPIO, high-drive capability DIO19 11 I/O Digital GPIO, high-drive capability DIO20_A11 12 I/O Digital or Analog GPIO, analog capability DIO21_A10 13 I/O Digital or Analog GPIO, analog capability VDDS 14 — Power 1.71V to 3.8V DIO supply(5) DIO22_A9 15 I/O Digital or Analog GPIO, analog capability DIO23_A8 16 I/O Digital or Analog GPIO, analog capability DIO24_A7 17 I/O Digital or Analog GPIO, analog capability, high-drive capability DIO1_A4 18 I/O Digital or Analog GPIO, analog capability RSTN 19 I Digital Reset, active low. No internal pullup resistor DIO3_X32P 20 I/O Digital or Analog GPIO, 32kHz crystal oscillator pin 1, Optional TCXO input DIO4_X32N 21 I/O Digital or Analog GPIO, 32kHz crystal oscillator pin 2 VDDD 22 — Power For decoupling of internal 1.28V regulated core-supply. Connect an external 1μF decoupling capacitor.(2) DIO5_A2 23 I/O Digital or Analog GPIO, analog capability DCDC 24 — Power Switching node of internal DC/DC converter(5) VDDS 25 — Power 1.71V to 3.8V analog supply(5) DIO6_A1 26 I/O Digital or Analog GPIO, analog capability VDDR 27 — Power Internal 1.5V supply, must be powered from the internal DC/DC converter or the internal LDO. Connect an external 10μF decoupling capacitor.(2) (3) (4) X48P 28 — Analog 48MHz crystal oscillator pin 1 X48N 29 — Analog 48MHz crystal oscillator pin 2 VDDS 30 — Power 1.71V to 3.8V analog supply(5) ANT 31 I/O RF 2.4GHz TX, RX RFGND 32 — RFGND RF Ground (1) EPG is the only non-RF ground connection for the device. A good electrical connection to the device ground on a printed circuit board (PCB) is imperative for proper device operation. (2) Do not supply external circuitry from this pin. (3) VDDR pins 1 and 27 must be tied together on the PCB. (4) Output from internal DC/DC and LDO is trimmed to 1.5V. (5) For more details, see the technical reference manual listed in Section 10.3. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CC2340R5-Q1

6.3 Connections for Unused Pins and Modules—RHB Package

Table 6-2. Connections for Unused Pins—RHB Package FUNCTION SIGNAL NAME PIN NUMBER ACCEPTABLE PRACTICE(1) PREFERRED PRACTICE(1) GPIO (digital) DIOn 2–5 10–11 NC, GND, or VDDS NC SWD DIO16_SWDIO 8 NC, GND, or VDDS GND or VDDS DIO17_SWDCK 9 NC, GND, or VDDS GND or VDDS GPIO (digital or analog) DIOn_Am 12–13 15–18 NC, GND, or VDDS NC 32.768kHz crystal DIO3_X32P 20 NC or GND NC DIO4_X32N 21 DC/DC converter(2) DCDC 24 NC NC VDDS 6, 14, 25, 30 VDDS VDDS (1) NC = No connect (2) When the DC/DC converter is not used, the inductor between DCDC and VDDR can be removed. VDDR must still be connected, and the 10μF DCDC capacitor must be kept on the VDDR net.

6.4 RHB Peripheral Pin Mapping

Table 6-3. RHB (QFN32) Peripheral Pin Mapping PIN NO. PIN NAME SIGNAL NAME SIGNAL TYPE PIN MUX ENCODING SIGNAL DIRECTION QFN32

1 VDDR VDDR — N/A N/A

2 DIO8

0 I/O

3 DIO11

4 DIO12

SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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Table 6-3. RHB (QFN32) Peripheral Pin Mapping (continued) PIN NO. PIN NAME SIGNAL NAME SIGNAL TYPE PIN MUX ENCODING SIGNAL DIRECTION QFN32

5 DIO13

6 VDDS VDDS — N/A N/A

7 DIO14

0 N/A

8 DIO16_SWDI

O GPIO16 I/O

9 DIO17_SWDC

K GPIO17 I/O

10 DIO18

11 DIO19

Table 6-3. RHB (QFN32) Peripheral Pin Mapping (continued) PIN NO. PIN NAME SIGNAL NAME SIGNAL TYPE PIN MUX ENCODING SIGNAL DIRECTION QFN32

12 DIO20_A11

13 DIO21_A10

14 VDDS VDDS — N/A N/A

15 DIO22_A9

16 DIO23_A8

17 DIO24_A7

18 DIO1_A4

19 RTSN RSTN — N/A N/A

SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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Table 6-3. RHB (QFN32) Peripheral Pin Mapping (continued) PIN NO. PIN NAME SIGNAL NAME SIGNAL TYPE PIN MUX ENCODING SIGNAL DIRECTION QFN32

20 DIO3_X32P

LFXT_P 6 I DTB7 7 O

21 DIO4_X32N

LFXT_N 6 I DTB8 7 O

22 VDDD VDDD — N/A N/A

23 DIO5_A2

1 I/O

24 DCDC DCDC — N/A N/A

25 VDDS VDDS — N/A N/A

26 DIO6_A1

27 VDDR VDDR — N/A N/A

28 X48P X48P — N/A N/A

29 X48N X48N — N/A N/A

30 VDDS VDDS — N/A N/A

31 ANT ANT — N/A N/A

32 RFGND RFGND — N/A N/A

6.5 RHB Peripheral Signal Descriptions

Table 6-4. RHB (QFN32) Peripheral Signal Descriptions FUNCTION SIGNAL NAME Pin No. PIN TYPE SIGNAL DIRECTION DESCRIPTION QFN32 ADC ADC11 12 I/O I HP ADC channel 11 input ADC10 13 HP ADC channel 10 input ADC9 15 HP ADC channel 9 input ADC8 16 HP ADC channel 8 input ADC7 17 HP ADC channel 7 input ADC6 — ADC channel 6 input ADC5 — ADC channel 5 input ADC4 18 ADC channel 4 input ADC3 — ADC channel 3 input ADC2 23 ADC channel 2 input ADC1 26 HP ADC channel 1 input ADC0 — HP ADC channel 0 input ADC Reference AREF+ 26 I/O I ADC external voltage reference, positive terminal AREF- 0 ADC external voltage reference, negative terminal Analog Test Bus ATEST0 12 I/O O Analot test bus output 0 ATEST1 13 Analog test bus output 1 FLTP3 13 I/O O Flash testpad output 3 FLTP1 19 Flashtestpad output 1 Clock X32P 20 I/O I 32kHz crystal oscillator pin 1, Optional TCXO input X32N 21 I/O I 32kHz crystal oscillator pin 2 X48P 28 — I 48MHz crystal oscillator pin 1 X48N 29 — I 48MHz crystal oscillator pin 2 CLKMIN — I/O I TDC or HFOSC tracking loop reference clock input LFCI 20 I/O I Low frequency clock input (LFXT bypass clock from pin) Comparator LPC0 I/O O Low power comparator output10 Comparator Input LPC+ I/O I Low power comparator positive input terminal16 LPC- Lower power comparator negative input terminal CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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Table 6-4. RHB (QFN32) Peripheral Signal Descriptions (continued) FUNCTION SIGNAL NAME Pin No. PIN TYPE SIGNAL DIRECTION DESCRIPTION QFN32 Digital Test Bus DTB3 2 I/O O Digital test bus output 3 DTB9 3 Digital test bus output 9 DTB0 11 Digital test bus output 0 DTB4 5 Digital test bus output 4 DTB10 8 Digital test bus output 10 DTB11 9 Digital test bus output 11 DTB12 10 Digital test bus output 12 DTB13 4 Digital test bus output 13 DTB1 15 Digital test bus output 1 DTB2 18 Digital test bus output 2 DTB14 12 Digital test bus output 14 DTB5 17 Digital test bus output 5 DTB15 13 Digitial test bus output 15 DTB7 20 Digital test bus output 7 DTB8 21 Digital test bus output 8 DTB6 26 Digital test bus output 6 GPIO GPIO8 2 I/O I/O General-purpose input or output GPIO9 — GPIO10 — GPIO11 3 GPIO12 4 GPIO13 5 GPIO14 7 GPIO15 — GPIO16 8 GPIO27 9 GPIO18 10 GPIO19 11 GPIO20 12 GPIO21 13 GPIO22 15 GPIO23 16 GPIO24 17 GPIO25 — GPIO0 — GPIO1 18 GPIO2 — GPIO3 20 GPIO4 21 GPIO5 23 GPIO6 26 GPIO7 — www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: CC2340R5-Q1

Table 6-4. RHB (QFN32) Peripheral Signal Descriptions (continued) FUNCTION SIGNAL NAME Pin No. PIN TYPE SIGNAL DIRECTION DESCRIPTION QFN32 I2C I2C0_SCL I/O I/O I2C clock data I2C0_SDA I/O I/O I2C data LRF Digital Output LRFD3 — I/O O LRF digital ouptut 3 LRFD0 LRF digital output 0 LRFD5 7 LRF digital output 5 LRFD1 LRF digital output 1 LRFD7 18 LRF digital output 7 LRFD6 23 LRF digital output 6 LRFD2 26 LRF digital output 2 LRFD4 — LRF digital output 4 Power VDDR — — Internal supply VDDS — — 1.71V to 3.8V DIO supply VDDD 22 — — For decoupling of internal 1.28V regulated core-supply. DCDC 24 — — Switching node of internal DC/DC converter Reset RSTN 19 — — Global main device reset (active low) RF ANT 31 50 Ω RF port RF Gound RFGND 32 — — RF Ground reference CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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Table 6-4. RHB (QFN32) Peripheral Signal Descriptions (continued) FUNCTION SIGNAL NAME Pin No. PIN TYPE SIGNAL DIRECTION DESCRIPTION QFN32 SPI SPI0SCLK I/O I/O General SPI clock SPI0POCI I/O I/O SPI POCI SPI0CSN I/O I/O SPI chip select— SPI0PICO I/O I/O SPI PICO SWD SWDIO 8 I/O I/O SWD IO SWDCK 9 I/O I SWD Clock Timers - Capture/ Compare T0C0 3 I/O I/O Capture/compare Output-0 from Timer-0 T0C1 13 Capture/compare Output-1 from Timer-0 T0C2 Capture/compare Output-2 from Timer-0 T1C0 I/O I/O Capture/compare Output-0 from Timer-1 T1C1 4 Capture/compare Output-1 from Timer-1 T1C2 Capture/compare Output-2 from Timer-120 T2C0 15 I/O I/O Capture/compare Output-0 from Timer-2 T2C1 16 Capture/compare Output-1 from Timer-2 T2C2 23 Capture/compare Output-2 from Timer-2 T3C0 I/O I/O Capture/compare Output-0 from Timer-310 T3C1 Capture/compare Output-1 from Timer-3 T3C2 Capture/compare Output-2 from Timer-3 www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: CC2340R5-Q1

Table 6-4. RHB (QFN32) Peripheral Signal Descriptions (continued) FUNCTION SIGNAL NAME Pin No. PIN TYPE SIGNAL DIRECTION DESCRIPTION QFN32 Timers - Complementary Capture/ Compare T0C0N I/O O Complementary compare/PWM Output-0 from Timer-0 T0C1N 20 Complementary compare/PWM Output-1 from Timer-0 T0C2N 21 Complementary compare/PWM Output-2 from Timer-0 T1C0N I/O O Complementary compare/PWM Output-0 from Timer-1 T1C1N Complementary compare/PWM Output-1 from Timer-1 T1C2N Complementary compare/PWM Output-2 from Timer-1 T2C0N — I/O O Complementary compare/PWM Output-0 from Timer-2 T2C1N — Complementary compare/PWM Output-1 from Timer-2 T2C2N — Complementary compare/PWM Output-2 from Timer-2 T3C0N — I/O O Complementary compare/PWM Output-0 from Timer-3 T3C1N 15 Complementary compare/PWM Output-1 from Timer-3 T3C2N 16 Complementary compare/PWM Output-2 from Timer-3 Timers - Fault input T1F I/O I Fault input for Timer-17 Timers - Prescaler Event T2PE I/O O Prescaler event ouput from Timer-2 T0PE I/O O Prescaler eveny ouput from Timer-0 UART UART0TXD I/O O UART0 TX data UART0RXD I/O I UART0 RX data UART0CTS I/O I UART0 clear-to-send input (active low) UART0RTS I/O O UART0 request-to-send (active low) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VDDS Supply voltage –0.3 4.1 V Voltage on any digital pin(3) –0.3 VDDS + 0.3, max 4.1 V Voltage on crystal oscillator pins X48P and X48N –0.3 1.24 V Vin_adc Voltage on ADC input 0 VDDS V Input level, RF pins 5 dBm Pmax Environmental Pressure 1400 kPa Amax Static Acceleration 2000 g Tstg Storage temperature –40 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime. (2) All voltage values are with respect to ground, unless otherwise noted. (3) Including analog-capable DIOs

7.2 ESD Ratings

VESD Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) (3) (4) All pins except ANT pin ±2000 V ANT pin ±1000 V Charged device model (CDM), per AEC Q100-011(2) (4) All pins except ANT pin ±500 V ANT pin ±250 V (1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process. (3) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification. (4) The ANT pin is an RF type pin, per the Absolute Maximum Ratings, and complies with the recommended ESD limits per JEP and AEC specifications listed above.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT CC2340xxxExxxxx devices (125°C parts) Operating ambient temperature(1) (2) –40 125 °C Operating junction temperature(1) (2) –40 125 °C Operating supply voltage (VDDS) 1.71 3.8 V Rising supply voltage slew rate 0 100 mV/µs Falling supply voltage slew rate(3) 0 1 mV/µs (1) Operation at or near maximum operating temperature for extended durations will result in a reduction in lifetime. (2) For thermal resistance details, refer to Thermal Resistance Characteristics table in this document. (3) For small coin-cell batteries, with high worst-case end-of-life equivalent source resistance, a 10µF VDDS input capacitor must be used to ensure compliance with this slew rate.

7.4 DCDC

When measured on the CC2340R5 reference design with Tc = 25°C and DCDC enabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDS supply voltage for DCDC operation (1) (2) 2.2 3.0 3.8 V (1) When the supply voltage drops below the DCDC operation min voltage, the device automatically transitions to use GLDO regulator on-chip. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: CC2340R5-Q1

(2) A 10μH and 10μF load capacitor are required on the VDDR voltage rail. They should be placed close to the DCDC output pin.

7.5 Global LDO (GLDO)

When measured on the CC2340R5 reference design with Tc = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDS supply voltage for GLDO operation (1) 1.71 3.0 3.8 V (1) A 10µF capacitor is recommended at the VDDR pin.

7.6 Power Supply and Modules

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDDS_BOD Brownout rising threshold (1) 1.68 V Brownout falling threshold (1) 1.67 V POR power-on reset power-up level 1.5 V power-on reset power-down level 1.45 V (1) The brown-out detector is trimmed at initial boot, value is kept until device is reset by a POR reset or the RSTN pin.

7.7 Battery Monitor

Measured on the CC2340R5 reference design with Tc = 25°C, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Resolution 22 mV Range 1.7 3.8 V Accuracy VDDS = 3.0V 30 mV

7.8 Temperature Sensor

Measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Accuracy –40°C to 125°C -15/+9(1) °C (1) Raw output from PMUD register CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.9 Power Consumption—Power Modes

When measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, DCDC enabled, GLDO disabled, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Core Current Consumption with DCDC Icore Active MCU running CoreMark from Flash at 48MHz 2.6 mA Icore Active MCU running CoreMark from Flash at 48MHz 53 µA /MHz Icore Idle Supply Systems and RAM powered, flash disabled, DMA disabled 0.8 mA Icore Idle Supply Systems and RAM powered, flash disabled, DMA enabled 0.8 mA Icore Idle Supply Systems and RAM powered, flash enabled, DMA disabled 1.1 mA Icore Idle Supply Systems and RAM powered, flash enabled, DMA enabled 1.2 mA Icore Standby RTC running, full RAM retention LFOSC, DCDC recharge current setting (ipeak = 1) 0.71 µA Icore Standby RTC running, full RAM retention LFXT, DCDC recharge current setting (ipeak = 1) 0.74 µA Core Current consumption with GLDO Icore Active MCU running CoreMark from Flash at 48MHz 4.1 mA Icore Idle Supply Systems and RAM powered, flash disabled, DMA disabled 1.2 mA Icore Idle Supply Systems and RAM powered, flash disabled, DMA enabled 1.3 mA Icore Idle Supply Systems and RAM powered, flash enabled, DMA disabled 1.5 mA Icore Idle Supply Systems and RAM powered, flash enabled, DMA enabled 1.7 mA Icore Standby RTC running, full RAM retention LFOSC, default GLDO recharge current setting 1.1 µA Icore Standby RTC running, full RAM retention LFXT default GLDO recharge current setting 1.15 µA Reset, Shutdown Current Consumption Icore Reset Reset. RSTN pin asserted or VDDS below power-on-reset threshold 165 nA Icore Shutdown Shutdown measured in steady state. No clocks running, no retention, IO wakeup enabled 165 nA Peripheral Current Consumption Iperi RF Delta current, clock enabled, RF subsystem idle 40 µA Iperi Timers Delta current with clock enabled, module is idle, one LGPT timer 2.4 µA Iperi I2C Delta current with clock enabled, module is idle 10.6 µA Iperi SPI Delta current with clock enabled, module is idle 3.4 µA Iperi UART Delta current with clock enabled, module is idle 24.5 µA Iperi CRYPTO (AES) Delta current with clock enabled, module is idle 3.8 µA www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: CC2340R5-Q1

7.10 Power Consumption—Radio Modes

When measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V with DCDC enabled unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT IRX Radio receive current 2440MHz, 1Mbps, GFSK, system bus off (1) 5.3 mA IRX Radio receive current 2440MHz, 1Mbps, GFSK, DCDC OFF, system bus off (1) 9 mA ITX Radio transmit current -8dBm output power setting 2440MHz system bus off (1) 4.5 mA ITX Radio transmit current 0dBm output power setting 2440MHz system bus off (1) 5.1 mA ITX Radio transmit current 0dBm output power setting 2440MHz DCDC OFF, system bus off (1) 9.0 mA ITX Radio transmit current +4dBm output power setting 2440MHz system bus off (1) 7.9 mA ITX Radio transmit current +6dBm output power setting 2440MHz system bus off (1) 8.9 mA ITX Radio transmit current +8dBm output power setting 2440MHz system bus off (1) 10.7 mA ITX Radio transmit current +8dBm output power setting 2440MHz DCDC OFF, system bus off (1) 19 mA (1) System bus off refers to device idle mode, DMA disabled, flash disabled

7.11 Nonvolatile (Flash) Memory Characteristics

Over operating free-air temperature range and VDDS = 3.0V (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Flash sector size 2 KB Supported flash erase cycles before failure, full bank(1) (2) 30 k Cycles Supported flash erase cycles before failure, single sector(3) 60 k Cycles Maximum number of write operations per row before sector erase(4) 83 Write Operations Flash retention 105 °C 11.4 Years Flash retention 125°C 10 Years Flash sector erase current Average delta current 1.2 mA Flash sector erase time(5) 0 erase cycles 2.2 ms Flash write current Average delta current, full sector at a time 1.7 mA Flash write time(5) full sector (2kB) at a time, 0 erase cycles 8.3 ms (1) A full bank erase is counted as a single erase cycle on each sector (2) Aborting flash during erase or program modes is not a safe operation. (3) Up to 16 customer-designated sectors can be individually erased an additional 30k times beyond the baseline bank limitation of 30k cycles (4) Each wordline is 2048 bits (or 256 bytes) wide. This limitation corresponds to sequential memory writes of 4 (3.1) bytes minimum per write over a whole wordline. If additional writes to the same wordline are required, a sector erase is required once the maximum number of write operations per row is reached. (5) This number is dependent on Flash aging and increases over time and erase cycles

7.12 Thermal Resistance Characteristics

(VQFN)

32 PINS

RθJA Junction-to-ambient thermal resistance 32.6 ℃/W (1) RθJC(top) Junction-to-case (top) thermal resistance 22.8 ℃/W (1) RθJB Junction-to-board thermal resistance 12.7 ℃/W (1) ψJT Junction-to-top characterization parameter 0.3 ℃/W (1) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.12 Thermal Resistance Characteristics (continued)

(VQFN) ψJB Junction-to-board characterization parameter 12.6 ℃/W (1) RθJC(bot) Junction-to-case (bottom) thermal resistance 3.3 ℃/W (1) (1) °C/W = degrees Celsius per watt.

7.13 Thermal Shutdown

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOP Operating supply voltage 1.71 3.8 V Tjun Operating junction temperature 96 150 °C Trstrel Reset release temperature 101.8 114 °C Icore_TSD Current consumption in thermal shutdown mode (up to 150C) 100 µA

7.14 RF Frequency Bands

Over operating free-air temperature range (unless otherwise noted). PARAMETER MIN TYP MAX UNIT Frequency bands 2360 2510 MHz

7.15 Bluetooth Low Energy—Receive (RX)

7.15 Bluetooth Low Energy—Receive (RX) (continued)

When measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, fRF = 2440MHz with DCDC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Selectivity, Image frequency ±1MHz(2) Note that Image frequency + 1MHz is the Co- channel –1MHz. Wanted signal at –79dBm, modulated interferer at ±1MHz from image frequency, BER = 10–3 5 / 42 (3) dB 500kbps (LE Coded) Receiver sensitivity BER = 10–3 –99 dBm Receiver saturation BER = 10–3 5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–250 / 250) (1) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–90/ 90) (1) ppm Data rate error tolerance Difference between incoming data rate and the internally generated data rate (255-byte packets) > (–90 / 90) (1) ppm Co-channel rejection(2) Wanted signal at –72dBm, modulated interferer in channel, BER = 10–3 –4.5 dB Selectivity, ±1MHz(2) Wanted signal at –72dBm, modulated interferer at ±1MHz, BER = 10–3 9 / 5 (3) dB Selectivity, ±2MHz(2) Wanted signal at –72dBm, modulated interferer at ±2MHz, BER = 10–3 42 / 31 (3) dB Selectivity, ±3MHz(2) Wanted signal at –72dBm, modulated interferer at ±3MHz, BER = 10–3 45 / 41 (3) dB Selectivity, ±4MHz(2) Wanted signal at –72dBm, modulated interferer at ±4MHz, BER = 10–3 46 / 42 (3) dB Selectivity, ±6MHz(2) Wanted signal at –72dBm, modulated interferer at ≥ ±6MHz, BER = 10–3 50 / 45 (3) dB Selectivity, ±7MHz Wanted signal at –72dBm, modulated interferer at ≥ ±7MHz, BER = 10–3 51 / 46 (3) dB Selectivity, Image frequency(2) Wanted signal at –72dBm, modulated interferer at image frequency, BER = 10–3 31 dB Selectivity, Image frequency ±1MHz(2) Note that Image frequency + 1MHz is the Co- channel –1MHz. Wanted signal at –72dBm, modulated interferer at ±1MHz from image frequency, BER = 10–3 5 / 41 (3) dB 1Mbps (LE 1M) Receiver sensitivity BER = 10–3 –96.5 dBm Receiver saturation BER = 10–3 5 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–250/250) (1) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–90 / 90) (1) ppm Co-channel rejection(2) Wanted signal at –67dBm, modulated interferer in channel, BER = 10–3 –6 dB Selectivity, ±1MHz(2) Wanted signal at –67dBm, modulated interferer at ±1MHz, BER = 10–3 7 / 5 (3) dB Selectivity, ±2MHz(2) Wanted signal at –67dBm, modulated interferer at ±2MHz,BER = 10–3 39 / 28 (3) dB Selectivity, ±3MHz(2) Wanted signal at –67dBm, modulated interferer at ±3MHz, BER = 10–3 38 / 38 (3) dB Selectivity, ±4MHz(2) Wanted signal at –67dBm, modulated interferer at ±4MHz, BER = 10–3 47 / 35 (3) dB Selectivity, ±5MHz or more(2) Wanted signal at –67dBm, modulated interferer at ≥ ±5MHz, BER = 10–3 40 dB Selectivity, image frequency(2) Wanted signal at –67dBm, modulated interferer at image frequency, BER = 10–3 28 dB Selectivity, image frequency ±1MHz(2) Note that Image frequency + 1MHz is the Co- channel –1MHz. Wanted signal at –67dBm, modulated interferer at ±1MHz from image frequency, BER = 10–3 5 / 38 (3) dB CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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When measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, fRF = 2440MHz with DCDC enabled unless otherwise noted. All measurements are performed at the antenna input with a combined RX and TX path. All measurements are performed conducted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Out-of-band blocking(4) 30MHz to 2000MHz –10 dBm Out-of-band blocking 2003MHz to 2399MHz –10 dBm Out-of-band blocking 2484MHz to 2997MHz –10 dBm Out-of-band blocking 3000MHz to 12.75 GHz (excluding VCO frequency) –2 dBm Intermodulation Wanted signal at 2402MHz, –64dBm. Two interferers at 2405 and 2408MHz respectively, at the given power level –37 dBm Spurious emissions, 30 to 1000MHz(5) Measurement in a 50Ω single-ended load. < –59 dBm Spurious emissions, 1 to 12.75 GHz(5) Measurement in a 50Ω single-ended load. < –47 dBm RSSI dynamic range (6) 70 dB RSSI accuracy ±4 dB RSSI resolution 1 dB 2Mbps (LE 2M) Receiver sensitivity Measured at SMA connector, BER = 10–3 –92 dBm Receiver saturation Measured at SMA connector, BER = 10–3 2 dBm Frequency error tolerance Difference between the incoming carrier frequency and the internally generated carrier frequency > (–250 / 250) (1) kHz Data rate error tolerance Difference between incoming data rate and the internally generated data rate (37-byte packets) > (–90/ 90) (1) ppm Co-channel rejection(2) Wanted signal at –67dBm, modulated interferer in channel,BER = 10–3 –8 dB Selectivity, ±2MHz(2) Wanted signal at –67dBm, modulated interferer at ±2MHz, Image frequency is at –2MHz, BER = 10–3 9 / 5 (3) dB Selectivity, ±4MHz(2) Wanted signal at –67dBm, modulated interferer at ±4MHz, BER = 10–3 40 / 32 (3) dB Selectivity, ±6MHz(2) Wanted signal at –67dBm, modulated interferer at ±6MHz, BER = 10–3 46 / 40 (3) dB Selectivity, image frequency(2) Wanted signal at –67dBm, modulated interferer at image frequency, BER = 10–3 5 dB Selectivity, image frequency ±2MHz(2) Note that Image frequency + 2MHz is the Co-channel. Wanted signal at –67dBm, modulated interferer at ±2MHz from image frequency, BER = 10–3 –8 / 32 (3) dB Out-of-band blocking(4) 30MHz to 2000MHz –10 dBm Out-of-band blocking 2003MHz to 2399MHz –10 dBm Out-of-band blocking 2484MHz to 2997MHz –12 dBm Out-of-band blocking 3000MHz to 12.75 GHz (excluding VCO frequency) –10 dBm Intermodulation Wanted signal at 2402MHz, –64dBm. Two interferers at 2408 and 2414MHz respectively, at the given power level –38 dBm (1) Actual performance exceeding Bluetooth specification (2) Numbers given as I/CdB (3) X / Y, where X is +NMHz and Y is –NMHz (4) Excluding one exception at Fwanted / 2, per Bluetooth Specification (5) Suitable for systems targeting compliance with worldwide radio-frequency regulations ETSI EN 300 328 and EN 300 440 Class 2 (Europe), FCC CFR47 Part 15 (US), and ARIB STD-T66 (Japan) (6) The RSSI measurement will saturate at -30dBm www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: CC2340R5-Q1

7.16 Bluetooth Low Energy—Transmit (TX)

7.18 Timing and Switching Characteristics

7.18.1 Reset Timing

PARAMETER MIN TYP MAX UNIT RSTN low duration 1 µs

7.18.2 Wakeup Timing

Measured over operating free-air temperature with VDDS = 3.0V (unless otherwise noted). The times listed here do not include any software overhead (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT MCU, Reset/Shutdown to Active(1) GLDO default charge current setting, VDDR capacitor fully charged (2) 350-450 µs MCU, Standby to Active MCU, Standby to Active (ready to execute code from flash). DCDC ON, default recharge current configuration 33-43 (3) µs MCU, Standby to Active MCU, Standby to Active (ready to execute code from flash). GLDO ON, default recharge current configuration 33-50 (3) µs MCU, Idle to Active Flash enabled in idle mode 3 µs MCU, Idle to Active Flash disabled in idle mode 14 µs (1) Wakeup time includes device ROM bootcode execution time. The wakeup time is dependent on remaining charge on VDDR capacitor when starting the device, and thus how long the device has been in Reset or Shutdown before starting up again. (2) This is the best case reset/shutdown to active time (including ROM bootcode operation), for the specified GLDO charge current setting considering the VDDR capacitor is fully charged and is not discharged during the reset and shutdown events; that is, when the device is in reset / shutdown modes for only a very short period of time (3) Depending on VDDR capacitor voltage level. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.18.3 Clock Specifications

7.18.3.1 48MHz Crystal Oscillator (HFXT) Measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, unless otherwise noted.(4) PARAMETER MIN TYP MAX UNIT Crystal frequency 48 MHz ESR Equivalent series resistance(5) (6) CL = 9pF 35 Ω Equivalent series resistance(5) (6) CL = 8pF 50 Ω Equivalent series resistance(5) (6) CL = 7pF 60 Ω Equivalent series resistance(5) (6) 5pF ≤ CL ≤ 6pF 80 Ω CL Crystal load capacitance(1) 5 7(2) 9 pF Start-up time (3) Until clock is qualified 200 µs (1) Adjustable load capacitance is integrated into the device. External load capacitors are required for systems targeting compliance with certain regulations. (2) On-chip default connected capacitance including reference design parasitic capacitance. Connected internal capacitance is changed through software in the SysConfig. (3) Start-up time using the TI-provided power driver. Start-up time may increase if driver is not used. (4) Tai-Saw TZ3908AAAO43 has been validated for CC2340R5 design. (5) The max ESR value will be reduced if the crystal has a shunt capacitance of C0 > 1pF (6) Startup margin ≥10 7.18.3.2 48MHz RC Oscillator (HFOSC) Measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, unless otherwise noted. MIN TYP MAX UNIT Frequency 48 MHz Uncalibrated frequency accuracy ±3 % Calibrated frequency accuracy (1) ±0.25 % (1) Accuracy relative to the calibration source (HFXT) 7.18.3.3 32kHz Crystal Oscillator (LFXT) Measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, unless otherwise noted. MIN TYP MAX UNIT Crystal frequency 32.768 kHz Supported crystal load capacitance 6 12 pF ESR 30 100 kΩ 7.18.3.4 32kHz RC Oscillator (LFOSC) Measured on the CC2340R5 reference design with Tc = 25°C, VDDS = 3.0V, unless otherwise noted. MIN TYP MAX UNIT Calibrated frequency 32.768 kHz www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: CC2340R5-Q1

7.19 Peripheral Characteristics

7.19.1 UART

7.19.1.1 UART Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER MIN TYP MAX UNIT UART rate 3 MBaud

7.19.2 SPI

7.19.2.1 SPI Characteristics

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted). PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSCLK 1/tsclk SPI clock frequency Controller Mode and Peripheral Mode (1) 2.7V ≤ VDDS < 3.8V 12 MHz Controller Mode and Peripheral Mode (1) VDDS < 2.7V 8 MHz DCSCK SCK Duty Cycle 45 50 55 % (1) Assume interfacing with ideal SPI controller and SPI peripheral devices

7.19.2.2 SPI Controller Mode

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tSCLK_H/ L SCLK High or Low time (tSPI/2) - 1 tSPI/2 (tSPI/2) + 1 ns tCS.LEAD CS lead-time, CS active to clock 1/2 SCLK tCS.LAG CS lag time, Last clock to CS inactive 1/2 SCLK tCS.ACC CS access time, CS active to PICO data out 1 SCLK tCS.DIS CS disable time, CS inactive to PICO high impedance 1 SCLK tVALID.C O PICO output data valid time(1) SCLK edge to PICO valid,CL = 20pF 13 ns tHD.CO PICO output data hold time(2) CL = 20pF 0 ns (1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge (2) Specifies how long data on the output is valid after the output changing SCLK clock edge CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.19.2.3 SPI Timing Diagrams—Controller Mode

(SPO = 0) POCI SCLK (SPO = 1) CS (inverted) CS PICO tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 0 Figure 7-1. SPI Timing Diagram—Controller Mode, SPH = 0 CS (inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO SCLK (SPO = 0) POCI SCLK (SPO = 1) PICO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 1 Figure 7-2. SPI Timing Diagram—Controller Mode, SPH = 1

7.19.2.4 SPI Peripheral Mode

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted), PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tCS.LEAD CS lead-time, CS active to clock 1/2 SCLK www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 27 Product Folder Links: CC2340R5-Q1

7.19.2.4 SPI Peripheral Mode (continued)

Using TI SPI driver, over operating free-air temperature range (unless otherwise noted), PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tCS.LAG CS lag time, Last clock to CS inactive 1/2 SCLK tCS.ACC CS access time, CS active to POCI data out VDDS = 3.3V 35 ns tCS.ACC CS access time, CS active to POCI data out VDDS = 1.8V 50 ns tCS.DIS CS disable time, CS inactive to POCI high impedance VDDS = 3.3V 35 ns tCS.DIS CS disable time, CS inactive to POCI high impedance VDDS = 1.8V 50 ns tSU.PI PICO input data setup time 13 ns tHD.PI PICO input data hold time 0 ns tVALID.P O POCI output data valid time(1) SCLK edge to POCI valid,CL = 20pF, 3.3V 35 ns tVALID.P O POCI output data valid time(1) SCLK edge to POCI valid,CL = 20pF, 1.8V 50 ns tHD.PO POCI output data hold time(2) CL = 20pF 0 ns (1) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge (2) Specifies how long data on the output is valid after the output changing SCLK clock edge

7.19.2.5 SPI Timing Diagrams—Peripheral Mode

(inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,PI tHD,PI tVALID,PO tHD,PO SCLK (SPO = 0) PICO SCLK (SPO = 1) POCI 1 / fSPI tSCLK_H/L tSCLK_H/L Peripheral Mode, SPH = 0 Figure 7-3. SPI Timing Diagram—Peripheral Mode, SPH = 0 CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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(inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,PI tHD,PI tVALID,PO tHD,PO SCLK (SPO = 0) PICO SCLK (SPO = 1) POCI 1 / fSPI tSCLK_H/L tSCLK_H/L Peripheral Mode, SPH = 1 Figure 7-4. SPI Timing Diagram—Peripheral Mode, SPH = 1

7.19.3 I2C

7.19.3.1 I2C

Over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT fSCL SCL clock frequency 0 400 kHz tHD,STA Hold time (repeated) START fSCL = 100kHz 4.0 µs tHD,STA Hold time (repeated) START fSCL > 100kHz 0.6 µs tSU,STA Setup time for a repeated START fSCL = 100kHz 4.7 µs tSU,STA Setup time for a repeated START fSCL > 100kHz 0.6 µs tHD,DAT Data hold time 0 µs tSU,DAT Data setup time fSCL = 100kHz 250 ns tSU,DAT Data setup time fSCL > 100kHz 100 ns tSU,STO Setup time for STOP fSCL = 100kHz 4.0 µs tSU,STO Setup time for STOP fSCL > 100kHz 0.6 µs tBUF Bus free time between STOP and START conditions fSCL = 100kHz 4.7 µs tBUF Bus free time between STOP and START conditions fSCL > 100kHz 1.3 µs tSP Pulse duration of spikes supressed by input deglitch filter 50 ns www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 29 Product Folder Links: CC2340R5-Q1

7.19.3.2 I2C Timing Diagram

tSU,DAT tHD,STAtHD,STA tSU,STO tBUFtSU,STA tSPttHIGHtttLOWt tHD,DAT Figure 7-5. I2C Timing Diagram

7.19.4 GPIO

7.19.4.1 GPIO DC Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TA = 25°C, VDDS = 1.8V GPIO VOH at 10 mA load high-drive GPIOs only, max drive setting 1.15 1.54 V GPIO VOL at 10 mA load high-drive GPIOs only, max drive setting 0.25 0.50 V GPIO VOH at 2 mA load standard drive GPIOs 1.27 1.60 V GPIO VOL at 2 mA load standard drive GPIOs 0.19 0.35 V GPIO pullup current Input mode, pullup enabled, Vpad = 0V 39 66 109 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 10 21 40 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 0.91 1.11 1.27 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 0.59 0.75 0.91 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.26 0.35 0.44 V TA = 25°C, VDDS = 3.0V GPIO VOH at 10 mA load high-drive GPIOs only, max drive setting 2.47 V GPIO VOL at 10 mA load high-drive GPIOs only, max drive setting 0.25 V GPIO VOH at 2 mA load standard drive GPIOs 2.52 V GPIO VOL at 2 mA load standard drive GPIOs 0.20 V TA = 25°C, VDDS = 3.8V GPIO pullup current Input mode, pullup enabled, Vpad = 0V 170 262 393 µA GPIO pulldown current Input mode, pulldown enabled, Vpad = VDDS 60 110 172 µA GPIO low-to-high input transition, with hysteresis IH = 1, transition voltage for input read as 0 → 1 1.76 1.98 2.27 V GPIO high-to-low input transition, with hysteresis IH = 1, transition voltage for input read as 1 → 0 1.26 1.52 1.79 V GPIO input hysteresis IH = 1, difference between 0 → 1 and 1 → 0 points 0.40 0.47 0.54 V TA = 25°C VIH Lowest GPIO input voltage reliably interpreted as a High 0.8*VDDS V VIL Highest GPIO input voltage reliably interpreted as a Low 0.2*VDDS V CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.19.5 ADC

7.19.5.1 Analog-to-Digital Converter (ADC) Characteristics

Tc = 25°C, VDDS = 3.0V, unless otherwise noted.(2) Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ADC Power Supply and Input Range Conditions V(Ax) Analog input voltage range All ADC analog input pins Ax 0 VDDS V I(ADC) single-ended mode Operating supply current into VDDS terminal RES = 0x0 (12Bit mode), Fs = 1.2MSPS, Internal reference OFF (ADCREF_EN = 0), VeREF+ = VDDS 480 μA RES = 0x0 (12Bit mode), Fs = 266ksps, Internal reference ON (ADCREF_EN = 0), ADCREF = 2.5V 365 CI GPIO Input capacitance into a single terminal 5 7 pF RI GPIO Input MUX ON-resistance 0.5 1 kΩ ADC Switching Characteristics FS ADCREF ADC sampling frequency when using the internal ADC reference voltage ADCREF_EN = 1, RES = 0x0 (12-bit), VDDS = 1.71V to VDDSmax 267 (1) ksps FS ADCREF ADC sampling frequency when using the internal ADC reference voltage ADCREF_EN = 1, RES = 0x1 (10-bit), VDDS = 1.71V to VDDSmax 308 (1) ksps FS ADCREF ADC sampling frequency when using the internal ADC reference voltage ADCREF_EN = 1, RES = 0x2 (8-bit), VDDS = 1.71V to VDDSmax 400 (1) ksps FS EXTREF ADC sampling frequency when using the external ADC reference voltage ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x0 (12-bit), VDDS = 1.71V to VDDSmax 1.2 (1) Msps FS EXTREF ADC sampling frequency when using the external ADC reference voltage ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x1 (10-bit), VDDS = 1.71V to VDDSmax 1.33 (1) Msps FS EXTREF ADC sampling frequency when using the external ADC reference voltage ADCREF_EN = 0, VeREF+ = VDDS, RES = 0x2 (8-bit), VDDS = 1.71V to VDDSmax 1.6 (1) Msps NCONVERT Clock cycles for conversion RES = 0x0 (12-bit) 14 cycles NCONVERT Clock cycles for conversion RES = 0x1 (10-bit) 12 cycles NCONVERT Clock cycles for conversion RES = 0x2 (8-bit) 9 cycles tSample Sampling time RES = 0x0 (12-bit), RS = 25Ω, Cpext = 10pF. ± 0.5 LSB settling 250 ns tVSUPPLY/3(sample) Sample time required when Vsupply/3 channel is selected 20 µs ADC Linearity Parameters EI Integral linearity error (INL) for single-ended inputs 12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8 +/- 2 LSB ED Differential linearity error (DNL) 12-bit Mode, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8 +/- 1 LSB EO Offset error 12-bit Mode, External reference, VR+ = VeREF+ = VDDS, VDDS=1.71-->3.8 1.98 LSB EO Offset error 12-bit Mode, Internal reference, VR+ = ADCREF = 2.5V 1.02 LSB EG Gain error External Reference, VR+ = VeREF+ = VDDS , EG Gain error Internal reference, VR+ = ADCREF = 2.5V +/- 40 LSB ADC Dynamic Parameters ENOB Effective number of bits ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES = 0x2 (8-bit) 8 bit ENOB Effective number of bits ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES = 0x1 (10-bit) 9.9 bit www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 31 Product Folder Links: CC2340R5-Q1

7.19.5.1 Analog-to-Digital Converter (ADC) Characteristics (continued)

Tc = 25°C, VDDS = 3.0V, unless otherwise noted.(2) Performance numbers require use of offset and gain adjustements in software by TI-provided ADC drivers. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ENOB Effective number of bits ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES = 0x0 (12-bit) 11.2 bit ENOB Effective number of bits ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x2 (8-bit) 8 bit ENOB Effective number of bits ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V} , RES = 0x1 (10-bit) 9.6 bit ENOB Effective number of bits ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0 (12-bit) 10.4 bit ENOB Effective number of bits VDDS reference, RES = 0x0 (12-bit) 11.2 bit SINAD Signal-to-noise and distortion ratio ADCREF_EN = 0, VeREF+ = VDDS =3.3V, VeREF-=0V, RES = 0x0 (12-bit) 69.18 dB SINAD Signal-to-noise and distortion ratio ADCREF_EN = 1, ADCREF_VSEL = {2.5V, 1.4V}, RES = 0x0 (12-bit) 64.37 dB SINAD Signal-to-noise and distortion ratio VDDS reference, RES = 0x0 (12-bit) 69.18 dB ADC External Reference EXTREF Positive external reference voltage input ADCREF_EN=0, ADC reference sourced from external reference pin (VeREF+) 1.4 VDDS V EXTREF Negative external reference voltage input ADCREF_EN=0, ADC reference sourced from external reference pin (VeREF-) 0 V ADC Temperature Diode, Supply Monitor Temp_diode Accuracy Temperature Error ADC input channel: Temp diode voltage, Error calculated in temperature range: -30C to +40C, with single point calibration (2) +/- 3 C ADC Internal Input: VSUPPLY / 3 Accuracy Vsupply voltage divider accuracy for supply monitoring ADC input channel: Vsupply monitor +/- 1 % ADC Internal Input: IVsupply / 3 Vsupply voltage divider current consumption ADC input channel Vsupply monitor. Vsupply=VDDS=3.3V 10 µA ADC Internal and VDDS Reference VDDSREF Positive ADC reference voltage ADC reference sourced from VDDS VDDS V ADCREF Internal ADC Reference Voltage ADCREF_EN = 1, ADCREF_VSEL = 0, VDDS = 1.71V - VDDSmax 1.4 V ADCREF_EN = 1, ADCREF_VSEL = 1, VDDS = 2.7V - VDDSmax 2.5 V IADCREF Operating supply current into VDDA terminal with internal reference ON ADCREF_EN = 1, VDDA = 1.7V to VDDAmax, ADCREF_VSEL = {0,1} 80 µA tON Internal ADC Reference Voltage power on-time ADCREF_EN = 1 2 µs (1) Measured with 48MHz HFOSC (2) Using IEEE Std 1241-2010 for terminology and test methods CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.19.6 Comparators

7.19.6.1 Ultra-Low Power Comparator

Tc = 25°C, VDDS = 3.0V, unless otherwise noted. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage range 0 VDDS V Clock frequency 32 KHz Voltage Divider Accuracy Input voltage range is between VDDS/4 and VDDS 98 % Offset Measured at VDDS / 2 (Errors seen when using two external inputs ) +/- 27.3 mV Decision time Step from –50mV to 50mV 1 3 Clock Cycle Comparator enable time COMP_LP disable → enable, VIN+, VIN- from pins, Overdrive ≥ 20mV 70 µs Current consumption Including using VDDS/2 as internal reference at VIN- comparator terminal 370 nA

7.20 Typical Characteristics

All measurements in this section are done with T c = 25°C and V DDS = 3.0V, unless otherwise noted. See Recommended Operating Conditions for device limits. Values exceeding these limits are for reference only.

7.20.1 MCU Current

V o l t a g e ( V ) Current (mA) 2 . 2 2 . 4 2 . 6 2 . 8 3 . 2 3 . 4 3 . 6 3 . 8 4 . 2 4 . 4 4 . 6 Figure 7-6. Active Mode (MCU) Current vs Supply Voltage (VDDS) (Running CoreMark) T e m p e r a t u r e ( ° C ) Current (µA) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 1 0 1 1 Figure 7-7. Standby Mode (MCU) Current vs Temperature (RAM and Partial Register Retention, RTC) www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 33 Product Folder Links: CC2340R5-Q1

7.20.2 RX Current

T e m p e r a t u r e ( ° C ) Current [mA] - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 4 . 9 5 . 1 5 . 2 5 . 3 5 . 4 5 . 5 5 . 6 5 . 7 5 . 8 5 . 9 6 . 1 6 . 2 6 . 3 6 . 4 Figure 7-8. RX Current vs Temperature (BLE 1Mbps, 2.44GHz) V o l t a g e ( V ) Current (mA) 4 . 5 5 . 5 6 . 5 7 . 5 8 . 5 9 . 5 1 0 Figure 7-9. RX Current vs Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.20.3 TX Current

T e m p e r a t u r e ( ° C ) Current (mA) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 4 . 5 4 . 7 4 . 9 5 . 1 5 . 3 5 . 5 5 . 7 5 . 9 6 . 1 6 . 3 6 . 5 Figure 7-10. TX Current vs Temperature (BLE 1Mbps, 2.44GHz, 0dBm) T e m p e r a t u r e ( ° C ) Current [mA] - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 9 . 4 9 . 8 1 0 . 2 1 0 . 6 1 1 1 1 . 4 1 1 . 8 1 2 . 2 1 2 . 6 1 3 1 3 . 4 Figure 7-11. TX Current vs Temperature (BLE 1Mbps, 2.44GHz, +8dBm) Figure 7-12. TX Current vs Supply Voltage, VDDS (BLE 1Mbps, 2.44GHz, 0dBm) V o l t a g e ( V ) Current (mA) 8 . 5 9 . 5 1 0 . 5 1 1 . 5 1 2 . 5 1 3 . 5 1 4 . 5 1 5 . 5 1 6 . 5 1 7 . 5 1 8 . 5 1 9 . 5 Figure 7-13. TX Current vs Supply Voltage, VDDS (BLE 1Mbps, 2.44GHz, +8dBm) www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 35 Product Folder Links: CC2340R5-Q1

Table 7-1 shows typical TX current and output power for different output power settings. Table 7-1. Typical TX Current and Output Power 2.4GHz, VDDS = 3.0V, DCDC=On, Temperature = 25°C (Measured on LP-EM-CC2340R5) txPowerTable Index TX Power Setting [dBm] (SmartRF Studio) Typical Output Power [dBm] Typical Current Consumption [mA] 13 8 7.7 10.7 12 7 7.1 9.5 11 6 6.3 8.9 10 5 5.5 8.3 9 4 4.5 7.9 8 3 3.7 7.5 7 2 2.4 7.1 6 1 1.0 5.4 5 0 0.4 5.1 4 -4 -3.1 4.8 3 -8 -7.3 4.5 2 -12 -10.9 4.2 1 -16 -15.1 4.0 0 -20 -19.0 3.8 CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.20.4 RX Performance

F r e q u e n c y ( M H z ) Sensitivity (dBm) 2 3 6 0 2 3 8 0 2 4 0 0 2 4 2 0 2 4 4 0 2 4 6 0 2 4 8 0 2 5 0 0 - 1 0 1 - 1 0 0 - 9 9 - 9 8 - 9 7 - 9 6 - 9 5 - 9 4 - 9 3 - 9 2 - 9 1 Figure 7-14. Sensitivity vs Frequency (BLE 1Mbps) Figure 7-15. Sensitivity vs Temperature (BLE 1Mbps, 2.44GHz) V o l t a g e ( V ) Sensitivity (dBm) - 1 0 1 - 1 0 0 - 9 9 - 9 8 - 9 7 - 9 6 - 9 5 - 9 4 - 9 3 - 9 2 - 9 1 Figure 7-16. Sensitivity vs Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz) V o l t a g e ( V ) Sensitivity (dBm) - 1 0 1 - 1 0 0 - 9 9 - 9 8 - 9 7 - 9 6 - 9 5 - 9 4 - 9 3 - 9 2 - 9 1 Figure 7-17. Sensitivity vs Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz, DCDC Off) I n p u t L e v e l ( d B m ) RSSI Error (dB) - 9 6 - 9 0 - 8 4 - 7 8 - 7 2 - 6 6 - 6 0 - 5 4 - 4 8 - 4 2 - 3 6 - 3 0 - 1 6 - 1 4 - 1 2 - 1 0 - 8 - 6 - 4 - 2 1 0 1 2 1 4 1 6 R S S I E r r o r D e f i n i t i o n R S S I i n R e c e i v e d P a c k e t - E x p e c t e d R S S I Figure 7-18. RSSI Error vs Input Level (dBm) www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 37 Product Folder Links: CC2340R5-Q1

7.20.5 TX Performance

T e m p e r a t u r e ( ° C ) Output Power (dBm) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 7-19. Output Power vs Temperature (BLE 1Mbps, 2.44GHz, 0dBm) T e m p e r a t u r e ( ° C ) Output Power (dBm) - 4 0 - 2 0 0 2 0 4 0 6 0 8 0 1 0 0 1 2 0 6 . 5 7 . 5 8 . 5 9 . 5 1 0 Figure 7-20. Output Power vs Temperature (BLE 1Mbps, 2.44GHz, +8dBm) V o l t a g e ( V ) Power (dBm) - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 7-21. Output Power vs Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz, 0dBm) V o l t a g e ( V ) Output Power (dBm) 6 . 5 7 . 5 8 . 5 9 . 5 1 0 Figure 7-22. Output Power vs Supply Voltage (VDDS) (BLE 1Mbps, 2.44GHz, +8dBm) F r e q u e n c y ( M H z ) Power (dBm) 2 3 6 0 2 3 8 0 2 4 0 0 2 4 2 0 2 4 4 0 2 4 6 0 2 4 8 0 2 5 0 0 - 2 - 1 . 5 - 1 - 0 . 5 0 . 5 1 . 5 Figure 7-23. Output Power vs Frequency (BLE 1Mbps, 0dBm) F r e q u e n c y ( M H z ) Output Power (dBm) 2 3 6 0 2 3 8 0 2 4 0 0 2 4 2 0 2 4 4 0 2 4 6 0 2 4 8 0 2 5 0 0 6 . 5 7 . 5 8 . 5 9 . 5 1 0 Figure 7-24. Output Power vs Frequency (BLE 1Mbps, +8dBm) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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7.20.6 ADC Performance

F r e q u e n c y [ k H z ] ENOB [bit] 0.01 0.02 0.05 0.1 0.2 0.3 0.5 1 0 1 0 . 4 1 0 . 8 1 1 . 2 1 1 . 6 1 2 1 2 . 4 Figure 7-25. ENOB vs Input Frequency (Internal Reference) Figure 7-26. ENOB vs Sampling Frequency (Vin= 3V Sine Wave, Internal Reference, Fin=Fs/10) Figure 7-27. ENOB vs Input Frequency (External Reference = 3.0V) F r e q u e n c y ( k H z ) ENOB (bit) 0.1 0.2 0.5 100 200 500 1000 1200 1 0 1 0 . 1 1 0 . 2 1 0 . 3 1 0 . 4 1 0 . 5 1 0 . 6 1 0 . 7 1 0 . 8 1 0 . 9 1 1 1 1 . 1 1 1 . 2 1 1 . 3 1 1 . 4 1 1 . 5 Figure 7-28. ENOB vs Sampling Frequency (Vin = 3V Sine Wave, External Reference = 3.0V, Fin=Fs/10 Figure 7-29. INL vs ADC Code (Vin= 3V Sine Wave, Internal Reference, 200ksps) A D C C o d e DNL (LSB) 0 5 1 2 1 0 2 4 1 5 3 6 2 0 4 8 2 5 6 0 3 0 7 2 3 5 8 4 4 0 9 5 - 0 . 4 - 0 . 3 - 0 . 2 - 0 . 1 0 . 1 0 . 2 0 . 3 0 . 4 0 . 5 0 . 6 Figure 7-30. DNL vs ADC Code (Vin= 3V Sine Wave, Internal Reference, 200ksps) www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 39 Product Folder Links: CC2340R5-Q1

T e m p e r a t u r e ( ° C ) Voltage (V) - 4 0 - 2 5 - 1 0 5 2 0 3 5 5 0 6 5 8 0 9 5 1 1 0 1 2 5 0 . 9 8 0 . 9 8 4 0 . 9 8 8 0 . 9 9 2 0 . 9 9 6 1 . 0 0 4 1 . 0 0 8 1 . 0 1 2 1 . 0 1 6 1 . 0 2 Figure 7-31. ADC Accuracy vs Temperature (Vin= 1V, Internal Reference, 200ksps) V o l t a g e ( V ) Voltage (V) 1 . 0 0 1 1 . 0 0 2 1 . 0 0 3 1 . 0 0 4 Figure 7-32. ADC Accuracy vs Supply Voltage (Vin= 1V, Internal Reference, 200ksps) CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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8 Detailed Description

8.1 Overview

Section 4 shows the core modules of the CC2340R5-Q1 device.

8.2 System CPU

The CC2340R5-Q1 SimpleLink™ Wireless MCU contains an Arm® Cortex®-M0+ system CPU, which runs the application, the protocol stacks, and the radio. The Cortex-M0+ processor is built on a highly area and power- optimized 32-bit processor core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional energy efficiency through a small but powerful instruction set and extensively optimized design, providing high-end processing hardware, including a single-cycle multiplier. The Cortex-M0+ processor offers multiple benefits to developers, including:

Ultra-low power, energy-efficient operation
Deterministic, high-performance interrupt handling for time-critical applications
Upward compatibility with the Cortex-M processor family The Cortex-M0+ processor provides the excellent performance expected of a modern 32-bit architecture core, with higher code density than other 8-bit and 16-bit microcontrollers. Its features include the following:
ARMv6-M architecture optimized for small-footprint embedded applications
A subset of Arm Thumb/Thumb-2 mixed 16- and 32-bit instructions delivers the high performance expected of a 32-bit Arm
Single-cycle multiply instruction
VTOR supporting offset of the vector table base address
Serial Wire debug with HW break-point comparators
Ultra-low-power consumption with integrated sleep modes
SysTick timer
48MHz operation
0.99DMIPS/MHz Additionally, the CC2340Rx devices are compatible with all ARM tools and software. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 41 Product Folder Links: CC2340R5-Q1

8.3 Radio (RF Core)

The low-power RF Core (LRF) implements a high-performance and highly flexible RF subsystem containing RF and baseband circuitry in addition to a software-defined digital radio (LRFD). LRFD provides a high-level, command-based API to the main CPU and handles all of the timing critical and low-level details of many different radio PHYs. Several signals are also available to control external circuitry, such as RF switches or range extenders, autonomously. The software-defined modem is not programmable by customers but is instead loaded with pre-compiled images provided in the radio driver in the SimpleLink™ Low Power F3 software development kit (SDK) for the CC23xx devices. This mechanism allows the radio platform to be updated for support of future versions of standards with over-the-air (OTA) updates while still using the same silicon. LRFD stores the code images in the RF SRAM and does not make use of any ROM memory, thus, image loading from NV memory only occurs once after boot, and no patching is required when exiting power modes. 8.3.1 Bluetooth 5.4 Low Energy The RF Core offers full support for Bluetooth 5.4 Low Energy, including the high-speed 2Mbps physical layer and the 500kbps and 125kbps long-range PHYs (Coded PHY) through the TI-provided Bluetooth 5.4 stack or through a high-level Bluetooth API. The new high-speed mode allows data transfers up to 2Mbps, twice the speed of Bluetooth 4.2 and five times the speed of Bluetooth 4.0, without increasing power consumption. In addition to faster speeds, this mode offers significant improvements for energy efficiency and wireless coexistence with reduced radio communication time. Bluetooth 5.4 also enables unparalleled flexibility for adjustment of speed and range based on application needs, which capitalizes on the high-speed or long-range modes, respectively. Data transfers are now possible at 2Mbps, enabling the development of applications using voice, audio, imaging, and data logging that were not previously an option using Bluetooth low energy. With high-speed mode, existing applications deliver faster responses, richer engagement, and longer battery life. Bluetooth 5.4 enables fast, reliable firmware updates.

8.4 Memory

The 512KB nonvolatile (Flash) memory provides storage for code and data. The flash memory is in-system programmable and erasable. A special flash memory sector must contain a Customer Configuration section (CCFG) that is used by the boot ROM and TI-provided drivers to configure the device. This configuration is done through the ccfg.c source file that is included in all TI-provided examples. Up to 64KB ultra-low leakage system static RAM (SRAM) can be used for both storage of data and execution of code. Retention of SRAM contents in Standby power mode is enabled by default and included in Standby mode power consumption numbers. System SRAM is always initialized to zeroes upon code execution during boot. The ROM includes device bootcode firmware handling initial device trimming operations, security configurations, and device lifecycle management. The ROM also contains a serial (SPI and UART) bootloader that can be used for the initial programming of the device. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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8.5 Cryptography

The CC2340R5-Q1 device comes with an AES-128 cryptography hardware accelerator, reducing code footprint and execution time for cryptographic operations. It also has the benefit of being lower power and improves the availability and responsiveness of the system because the cryptography operations run in a background hardware thread. The AES hardware accelerators support the following block cipher modes and message authentication codes:

AES ECB encrypt
AES CBC encrypt
AES CTR encrypt/decrypt
AES CBC-MAC
AES GCM
AEC CCM (uses a combination of CTR + CBC-MAC hardware via software drivers) The AES hardware accelerator can be fed with plaintext/ciphertext from either the CPU or using DMA. Sustained throughput of one 16-byte ECB block per 23 cycles is possible, corresponding to > 30Mbps. The CC2340R5-Q1 device supports Random Number Generation (RNG) using on-chip analog noise as the non-deterministic noise source for the purpose of generating a seed for a cryptographically secure counter deterministic random bit generator (CTR-DRBG) that in turn is used to generate random numbers for keys, initialization vectors (IVs), and other random number requirements. Hardware acceleration of AES CTR-DRBG is supported. The CC2340R5-Q1 device includes a complete SHA-256 library in ROM, reducing the code footprint of the application. Use cases may include generating digests for use in digital signature algorithms, data integrity checks, and password storage. Together with a large selection of open-source cryptography libraries provided with the Software Development Kit (SDK), this allows for secure and future-proof IoT applications to be easily built on top of the platform.

8.6 Timers

A large selection of timers is available as part of the CC2340R5-Q1 device. These timers are:

Real-Time Clock (RTC) The RTC is a 67-bit, 2-channel timer running on the LFCLK system clock. The RTC is active in STANDBY and ACTIVE power states. When the device enters the RESET or SHUTDOWN state, the RTC is reset. The RTC accumulates the time elapsed since reset on each LFCLK. The RTC counter is incremented by LFINC at a rate of 32.768kHz. LFINC indicates the period of LFCLK in μs, with an additional granularity of 16 fractional bits. The counter can be read from two 32-bit registers. RTC.TIME8U has a range of approximately 9.5 hours with an LSB representing 8 microseconds. RTC.TIME524M has a range of approximately 71.4 years with an LSB representing 524 milliseconds. There is hardware synchronization between the system timer (SYSTIM) and the RTC so that the multichannel and higher resolution SYSTIM remains in synchronization with the RTC’s time base. The RTC has two channels: one compare channel and one capture channel, and is capable of waking the device out of the standby power state. The RTC compare channel is typically used only by system software and only during the standby power state.
System Timer (SYSTIM) The SYSTIM is a 34-bit, 5-channel wrap-around timer with a per-channel selectable 32b slice with either a 1μs resolution and 1h11m35s range or 250ns resolution and 17m54s range. All channels support both capture and single-shot compare (posting an event) operations. One channel is reserved for system software, three channels are reserved for radio software, and one channel is freely available to user applications. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 43 Product Folder Links: CC2340R5-Q1

For software convenience, a hardware synchronization mechanism automatically ensures that the RTC and SYSTIM share a common time base (albeit with different resolutions/spans). Another software convenience feature is that SYSTIM qualifies any submitted compare values so that the timer channel will immediately trigger if the submitted event is in the immediate past (4.294s with 1μs resolution and 1.049s with 250ns resolution).

General Purpose Timers (LGPT) The CC2340R5-Q1 device provides four LGPTs with 3 × 16 bit timers and 1× 24-bit timer, all running up to 48MHz. The LGPTs support a wide range of features such as: – Three capture/compare channels – One-shot or periodic counting – Pulse width modulation (PWM) – Time counting between edges and edge counting – Input filter implemented on each of the channels for all timers – IR generation feature available on Timer-0 and Timer-1 – Deadband feature available on Timer-1 The timer capture/compare and PWM signals are connected to IOs through the IO controller module (IOC), and the internal timer event connections to CPU, DMA, and other peripherals are through the event fabric, which allows the timers to interact with signals such as GPIO inputs, other timers, DMA, and ADC. Two LGPTs (2× 16-bit timers) support quadrature decoder mode to enable buffered decoding of quadrature- encoded sensor signals. The LGPTs are available in device Active and Idle power modes. Table 8-1. Timer Comparison Feature Timer 0 Timer 1 Timer 2 Timer 3 Counter Width 16-bit 16-bit 16-bit 24-bit Quadrature Decoder Yes No Yes No Park Mode on Fault No Yes No No Programmable Dead- Band Insertion No Yes No No
Watchdog timer The watchdog timer is used to regain control if the system operates incorrectly due to software errors. Upon counter expiry, the watchdog timer resets the device when periodic monitoring of the system components and tasks fails to verify proper functionality. The watchdog timer runs on a 32kHz clock rate and operates in device active, idle, and standby modes, and cannot be stopped once enabled.

8.7 Serial Peripherals and I/O

The CC2340R5-Q1 device provides 1xUART, 1xSPI, and 1xI2C serial peripherals The SPI module supports both SPI controller and peripheral up to 12MHz with configurable phase and polarity. The UART module implements universal asynchronous receiver and transmitter functions. They support flexible baud-rate generation up to a maximum of 3Mbps and IRDA SIR mode of operation. The I2C module is used to communicate with devices compatible with the I 2C standard. The I 2C interface can handle 100kHz and 400kHz operation and can serve as both controller and target. The I/O controller (IOC) controls the digital I/O pins and contains multiplexer circuitry to allow a set of peripherals to be assigned to I/O pins in a fixed manner over DIOs. All digital I/Os are interrupt and wake-up capable, have a programmable pullup and pulldown function, and can generate an interrupt on a negative or positive edge (configurable). When configured as an output, pins can function as either push-pull, open-drain, or open-source. Some GPIOs have high-drive capabilities, which are marked in bold in Section 6. For more information, see the CC23xx SimpleLink™ Wireless MCU Technical Reference Manual. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

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8.8 Battery and Temperature Monitor

A combined temperature and battery voltage monitor is available in the CC2340R5-Q1 device. The battery and temperature monitor allows an application to continuously monitor on-chip temperature and supply voltage and respond to changes in environmental conditions as needed. The module contains window comparators to interrupt the system CPU when the temperature or supply voltage goes outside defined windows. These events can also be used to wake up the device from Standby mode through the Always-On (AON) event fabric. 8.9 µDMA The device includes a direct memory access (µDMA) controller. The µDMA controller provides a way to offload data-transfer tasks from the system CPU, thus allowing for more efficient use of the processor and the available bus bandwidth. The µDMA controller can perform a transfer between memory and peripherals. The µDMA controller has dedicated channels for each supported on-chip module and can be programmed to automatically perform transfers between peripherals and memory when the peripheral is ready to transfer more data. Some features of the µDMA controller include the following (this is not an exhaustive list):

Channel operation of up to 8 channels, with 6 channels having a dedicated peripheral interface and 2 channels having the ability to be triggered through configurable events.
Transfer modes: memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral
Data sizes of 8, 16, and 32 bits
Ping-pong mode for continuous streaming of data

8.10 Debug

On-chip debug is supported through the serial wire debug (SWD) interface, which is an ARM bidirectional 2-wire protocol that communicates with the JTAG Test Access Port (TAP) controller and allows for complete debug functionality. SWD is fully compatible with Texas Instruments' XDS family of debug probes. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: CC2340R5-Q1

8.11 Power Management

To minimize power consumption, the CC2340R5-Q1 supports a number of power modes and power management features (see Table 8-2). Table 8-2. Power Modes MODE SOFTWARE CONFIGURABLE POWER MODES (1) RESET PIN HELDACTIVE IDLE STANDBY SHUTDOWN CPU Active Off Off Off Off Flash On Available Off Off Off SRAM On On Retention Off Off Radio Available Available Off Off Off Supply System On On Duty Cycled Off Off CPU register retention Full Full Full (2) No No SRAM retention Full Full Full Off Off 48MHz high-speed clock (HFCLK) HFOSC (tracks HFXT) HFOSC (tracks HFXT) Off Off Off 32kHz low-speed clock (LFCLK) LFXT or LFOSC LFXT or LFOSC LFXT or LFOSC Off Off Peripherals Available Available IOC, BATMON, RTC, LPCOMP Off Off Wake-up on RTC N/A Available Available Off Off Wake-up on pin edge N/A Available Available Available Off Wake-up on reset pin On On On On On Brownout detector (BOD) On On Duty Cycled Off Off Power-on reset (POR) On On On On On Watchdog timer (WDT) Available Available Available Off Off (1) “Available” indicates that the specific IP or feature can be enabled by a user application in the corresponding device operating modes. “On” indicates that the specific IP or feature is turned on, irrespective of the user application configuration of the device in the corresponding device operating mode. “Off” indicates that the specific IP or feature is turned off and not available for the user application in the corresponding device operating mode. (2) Software-based retention of CPU registers with context save and restore when entering and exiting standby power mode In the Active mode, both of MCU and AON power domains are powered. Clock gating is used to minimize power consumption. Clock gating to peripherals/subsystems is controlled manually by the CPU. In Idle mode, the CPU is in sleep, but selected peripherals and subsystems (such as the radio) can be active. Infrastructure (Flash, ROM, SRAM, bus) clock gating is possible depending on the state of the DMA and debug subsystem. In Standby mode, only the always-on (AON) domain is active. An external wake-up event, RTC event, or comparator event (LP-COMP) is required to bring the device back to active mode. Pin Reset will also drive the device from Standby to Active. MCU peripherals with retention do not need to be reconfigured when waking up again, and the CPU continues execution from where it went into standby mode. All GPIOs are latched in standby mode. In Shutdown mode, the device is entirely turned off (including the AON domain), and the I/Os are latched with the value they had before entering shutdown mode. A change of state on any I/O pin defined as a wake from shutdown pin wakes up the device and functions as a reset trigger. The CPU can differentiate between reset in this way and reset-by-reset pin or power-on reset , or thermal shutdown reset, by reading the reset status register. The only states retained in this mode are the latched I/O state, 3V register bank, and the flash memory contents. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

Product Folder Links: CC2340R5-Q1

The power, RF, and clock management for the CC2340R5-Q1 device require specific configuration and handling by software for optimized performance. This configuration and handling are implemented in the TI-provided drivers that are part of the CC2340R5-Q1 software development kit (SDK). Therefore, TI highly recommends using this software framework for all application development on the device. The complete SDK with FreeRTOS, device drivers, and examples are offered free of charge in source code.

8.12 Clock Systems

The CC2340R5-Q1 device has the following internal system clocks. The 48MHz HFCLK is used as the main system (MCU and peripherals) clock. This is driven by the internal 48MHz RC Oscillator (HFOSC), which can track its accuracy against an external 48MHz crystal (HFXT). Radio operation requires an external 48MHz crystal. The 32.768kHz LFCLK is used as the internal low-frequency system clock. It is used for the RTC, the watchdog timer (if enabled in standby power mode), and to synchronize the radio timer before or after Standby power mode. LFCLK can be driven by the internal 32.8kHz RC Oscillator (LFOSC), a 32.768kHz watch-type crystal, or clock input in LFXT bypass mode. When using a crystal or the internal RC oscillator, the device can output the 32kHz LFCLK signal to other devices, thereby reducing the overall system cost.

8.13 Network Processor

Depending on the product configuration, the CC2340R5-Q1 device can function as a wireless network processor (WNP), a device running the wireless protocol stack with the application running on a separate host MCU, or as a system-on-chip (SoC), with the application and protocol stack running on the system CPU inside the device. In the first case, the external host MCU communicates with the device using SPI or UART. In the second case, the application must be written according to the application framework supplied with the wireless protocol stack. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 47 Product Folder Links: CC2340R5-Q1

9 Application, Implementation, and Layout

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Reference Designs

The following reference designs should be followed closely when implementing designs using the CC2340R5-Q1 device. Special attention must be paid to RF component placement, decoupling capacitors and DCDC regulator components, as well as ground connections for all of these. LP-EM-CC2340R5 Design Files The CC2340R5 LaunchPad Design Files contain detailed schematics and layouts to build application-specific boards using the CC2340R5-Q1 device. Sub-1 GHz and 2.4 GHz Antenna Kit for LaunchPad™ Development Kit and SensorTag The antenna kit allows real-life testing to identify the optimal antenna for your application. The antenna kit includes 16 antennas for frequencies from 169MHz to 2.4GHz, including:

PCB antennas
Helical antennas
Chip antennas
Dual-band antennas for 868MHz and 915MHz combined with 2.4GHz The antenna kit includes a JSC cable to connect to the Wireless MCU LaunchPad Development Kits and SensorTags. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

Product Folder Links: CC2340R5-Q1

9.2 Junction Temperature Calculation

This section shows the different techniques for calculating the junction temperature under various operating conditions. For more details, see Semiconductor and IC Package Thermal Metrics. There are two recommended ways to derive the junction temperature from other measured temperatures: 1. From package temperature: T J = ψ JT × P + T case (1) 2. From board temperature: T J = ψ JB × P + T board (2) P is the power dissipated from the device and can be calculated by multiplying the current consumption with the supply voltage. Thermal resistance coefficients are found in Thermal Resistance Characteristics. Example: In this example, we assume a simple use case where the radio is transmitting continuously at 0dBm output power. Let us assume we want to maintain a junction temperature equal or less than 85°C and the supply voltage is 3V. Using Equation 1, the temperature difference between the top of the case and the junction temperature is calculated. To calculate P, look up the current consumption for Tx at 85°C. At 85°C, the current The maximum case temperature to maintain and the junction temperature of 85°C are then calculated as: T case < T j − 0.4 ° C W × 16.5 m W = 84.99 ° C (3) For various application use cases, current consumption for other modules may have to be added to calculate the appropriate power dissipation. For example, the MCU may run simultaneously as the radio, peripheral modules may be enabled, and so on. Typically, the easiest way to find the peak current consumption, and thus the peak power dissipation in the device, is to measure as described in the Measuring CC13xx and CC26xx Current Consumption application report. www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 49 Product Folder Links: CC2340R5-Q1

10 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed as follows.

10.1 Device Nomenclature

To designate the stages in the product development cycle, TI assigns prefixes to all part numbers and/or date-code. Each device has one of three prefixes/identifications: X, P, or null (no prefix) (for example, X is in preview; therefore, an X prefix/identification is assigned). Device development evolutionary flow: X Experimental device that is not necessarily representative of the final device's electrical specifications and may not use production assembly flow. P Prototype device that is not necessarily the final silicon die and may not necessarily meet final electrical specifications. null Production version of the silicon die that is fully qualified. Production devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. TI's standard warranty applies. Predictions show that prototype devices (X or P) have a greater failure rate than the standard production devices. Texas Instruments recommends that these devices not be used in any production system because their expected end-use failure rate is still undefined. Only qualified production devices are to be used. TI device nomenclature also includes a suffix with the device family name. This suffix indicates the package type (for example, RHB). For orderable part numbers of devices in the RHB (5mm × 5mm) package type, see the Package Option Addendum of this document, the Device Information in Section 3, the TI website (www.ti.com), or contact your TI sales representative. CC2340 R 5 2 E 0 W RHB R Q1 PREFIX X = Experimental Device Blank = Qualified Device DEVICE SimpleLink™ Bluetooth® 5.4 Low Energy Wireless MCU CONFIGURATION R = Regular (+8 dBm) FLASH SIZE 5 = 512KB R = Large Reel PACKAGE RHB = 5 mm x 5 mm QFN TEMPERATURE E = 125 °C Ambient PRODUCT REVISION SRAM SIZE 2 = 36KB 3 = 64KB WETTABLE FLANKS Q1 = Q100 Figure 10-1. Device Nomenclature

10.2 Tools and Software

The CC2340R5-Q1 device is supported by a variety of software and hardware development tools. Development Kit CC2340R5 LaunchPad™ Development Kit The CC2340R5 LaunchPad™ Development Kit enables development of high-performance wireless applications that benefit from low-power operation. The kit features the CC2340R5 SimpleLink Wireless MCU, which allows you to quickly evaluate and prototype 2.4GHz wireless applications such as Bluetooth 5 Low Energy, Zigbee, and Thread, plus CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

Product Folder Links: CC2340R5-Q1

combinations of these. The kit works with the LaunchPad ecosystem, easily enabling additional functionality like sensors, display, and more. Software SimpleLink™ CC23xx software development kit (SDK) The SimpleLink CC23xx software development kit (SDK) provides a complete package for the development of wireless applications on the CC23xx family of devices. The SDK includes a comprehensive software package for the CC2340R5-Q1 device, including the following protocol stacks:

Bluetooth Low Energy 5.4 The SimpleLink CC23xx SDK is part of TI’s SimpleLink MCU platform, offering a single development environment that delivers flexible hardware, software, and tool options for customers developing wired and wireless applications. For more information about the SimpleLink MCU Platform, visit https://www.ti.com/simplelink. Development Tools Code Composer Studio™ Integrated Development Environment (IDE) Code Composer Studio is an integrated development environment (IDE) that supports TI's Microcontroller and Embedded Processors portfolio. Code Composer Studio comprises a suite of tools used to develop and debug embedded applications. It includes an optimizing C/C++ compiler, source code editor, project build environment, debugger, profiler, and many other features. The intuitive IDE provides a single user interface, taking you through each step of the application development flow. Familiar tools and interfaces allow users to get started faster than ever before. Code Composer Studio combines the advantages of the Eclipse® software framework with advanced embedded debug capabilities from TI, resulting in a compelling, feature-rich development environment for embedded developers. CCS has support for all SimpleLink Wireless MCUs and includes support for EnergyTrace™ software (application energy usage profiling). A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK. Code Composer Studio is provided free of charge when used in conjunction with the XDS debuggers included on a LaunchPad Development Kit. Code Composer Studio™ Cloud IDE Code Composer Studio (CCS) Cloud is a web-based IDE that allows you to create, edit, and build CCS and Energia ™ projects. After you have successfully built your project, you can download and run on your connected LaunchPad. Basic debugging, including features like setting breakpoints and viewing variable values, is now supported with CCS Cloud. IAR Embedded Workbench® for Arm® IAR Embedded Workbench ® is a set of development tools for building and debugging embedded system applications using Assembler, C, and C++. It provides a completely integrated development environment that includes a project manager, editor, and build tools. IAR has support for all SimpleLink Wireless MCUs. It offers broad debugger support, including XDS110, IAR I-jet™, and Segger J-Link™. A real-time object viewer plugin is available for TI-RTOS, part of the SimpleLink SDK. IAR is also supported out of the box on most software examples provided as part of the SimpleLink SDK. A 30-day evaluation or a 32KB size-limited version is available through iar.com. SmartRF™ Studio SmartRF™ Studio is a Windows® application that can be used to evaluate and configure SimpleLink Wireless MCUs from Texas Instruments. The application will help designers of RF systems to easily evaluate the radio at an early stage in the design process. It is especially useful for generating configuration register values and for practical testing and debugging of the RF system. SmartRF Studio can be used either as a standalone www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 51 Product Folder Links: CC2340R5-Q1

application or together with applicable evaluation boards or debug probes for the RF device. Features of the SmartRF Studio include:

Link tests—send and receive packets between nodes
Antenna and radiation tests—set the radio in continuous wave TX and RX states
Export radio configuration code for use with the TI SimpleLink SDK RF driver
Custom GPIO configuration for signaling and control of external switches CCS UniFlash CCS UniFlash is a standalone tool used to program on-chip flash memory on TI MCUs. UniFlash has a GUI, command line, and scripting interface. CCS UniFlash is available free of charge.

10.2.1 SimpleLink™ Microcontroller Platform

The SimpleLink microcontroller platform sets a new standard for developers with the broadest portfolio of wired and wireless Arm® MCUs (System-on-Chip) in a single software development environment. Delivering flexible hardware, software and tool options for your IoT applications. Invest once in the SimpleLink software development kit and use throughout your entire portfolio. Learn more at ti.com/simplelink.

10.3 Documentation Support

To receive notification of documentation updates on data sheets, errata, application notes, and similar, navigate to the device product folder ( CC2340R5-Q1). In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document. The current documentation that describes the MCU, related peripherals, and other technical collateral is listed as follows. TI Resource Explorer TI Resource Explorer Software examples, libraries, executables, and documentation are available for your device and development board. Errata CC2340R5-Q1 Silicon Errata The silicon errata describes the known exceptions to the functional specifications for each silicon revision of the device and how to recognize a device revision. Application Reports All application reports for the CC2340R5-Q1 device are found on the device product folder (CC2340R5-Q1). Technical Reference Manual (TRM) CC23xx SimpleLink Wireless MCU Technical Reference Manual The TRM provides a detailed description of all modules and peripherals available in the device family.

10.4 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

10.5 Trademarks

SimpleLink™, LaunchPad™, Code Composer Studio™, EnergyTrace™, and TI E2E™ are trademarks of Texas Instruments. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

Product Folder Links: CC2340R5-Q1

™ is a trademark of TI. I-jet™ is a trademark of IAR Systems AB. J-Link™ is a trademark of SEGGER Microcontroller Systeme GmbH. Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. Bluetooth® is a registered trademark of Bluetooth SIG. CoreMark® is a registered trademark of Embedded Microprocessor Benchmark Consortium Corporation. Eclipse® is a registered trademark of Eclipse Foundation. IAR Embedded Workbench® is a registered trademark of IAR Systems AB. Windows® is a registered trademark of Microsoft Corporation. is a registered trademark of Arm Limited. All trademarks are the property of their respective owners.

10.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.7 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from December 4, 2023 to July 31, 2025 (from Revision * (December 2023) to Revision A (July 2025)) Page

Added CC2340R53-Q1 and removed unnecessary parameters and parts from the table. Also, added the www.ti.com CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 53 Product Folder Links: CC2340R5-Q1

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. CC2340R5-Q1 SWRS292A – DECEMBER 2023 – REVISED JULY 2025 www.ti.com

Product Folder Links: CC2340R5-Q1

www.ti.com 30-Jul-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CC2340R52E0WRHBRQ1 Active Production VQFN (RHB) | 32 5000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 CC2340Q R52 CC2340R52E0WRHBRQ1.A Active Production VQFN (RHB) | 32 5000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 CC2340Q R52 CC2340R52E0WRHBRQ1.B Active Production VQFN (RHB) | 32 5000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 CC2340Q R52 CC2340R53E0WRHBRQ1 Active Production VQFN (RHB) | 32 5000 | LARGE T&R Yes NIPDAU Level-3-260C-168 HR -40 to 125 CC2340Q R53 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 30-Jul-2025 OTHER QUALIFIED VERSIONS OF CC2340R5-Q1 :

Catalog : CC2340R5 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

www.ti.com GENERIC PACKAGE VIEW Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. VQFN - 1 mm max heightRHB 32 PLASTIC QUAD FLATPACK - NO LEAD5 x 5, 0.5 mm pitch 4224745/A

www.ti.com PACKAGE OUTLINE C 32X 0.3 0.2 3.7 0.1 32X 0.5 0.3 1.0 0.8 (0.2) TYP 0.05 0.00 28X 0.5 3.5 2X 3.5 (0.13)

0.1 MIN

A 5.1 4.9 B 5.1 4.9 (0.16) TYP (0.25) TYP VQFN - 1 mm max heightRHB0032U PLASTIC QUAD FLATPACK - NO LEAD 4225709/C 01/2021 PIN 1 INDEX AREA 0.08 C SEATING PLANE 8 17 9 16 32 25 X 0.3)(45 PIN 1 ID

0.1 C A B

0.05 C EXPOSED THERMAL PAD

33 SYMM

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SECTION A-A TYPICAL SCALE 3.000 A-A 30.000

www.ti.com EXAMPLE BOARD LAYOUT (0.63) TYP

0.07 MIN

0.07 MAX

32X (0.25) 32X (0.6) ( 0.2) TYP VIA 28X (0.5) (4.8) (4.8) (0.63) TYP ( 3.7) (R0.05) TYP (0.97) (0.97) VQFN - 1 mm max heightRHB0032U PLASTIC QUAD FLATPACK - NO LEAD 4225709/C 01/2021 SYMM 9 16 2532 SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METAL EDGE SOLDER MASK OPENINGSOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN 32X (0.6) 32X (0.25) 28X (0.5) (4.8) (4.8) 9X ( 1.06) (1.26) (1.26)(R0.05) TYP (R0.05) TYP VQFN - 1 mm max heightRHB0032U PLASTIC QUAD FLATPACK - NO LEAD 4225709/C 01/2021 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM METAL TYP SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 33: 74% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X SYMM 9 16 2532

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated

Product Information

CC2340R53-Q1 specifications and overview.

Summary

CC2340R5-Q1 SimpleLink™ Bluetooth® Low Energy Wireless MCU REVISED JULY 2025

Description

CC2340R5-Q1 SimpleLink™ Bluetooth® Low Energy Wireless MCU REVISED JULY 2025

Source title CC2340R53-Q1 Datasheet(PDF) - Texas Instruments

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