CBTLV3384

SN74CBTLV3384_07 TI | Alldatasheet

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/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0076/C0086/C0051/C0051/C0056/C0052 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 SCDS059G − MARCH 1998 − REVISED JUNE 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C00685-Ω Switch Connection Between Two Ports /C0068Rail-to-Rail Switching on Data I/O Ports /C0068Ioff Supports Partial-Power-Down Mode Operation /C0068Latch-Up Performance Exceeds 250 mA Per JESD 17 /C0068ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) description/ordering information The SN74CBTLV3384 provides ten bits of high-speed bus switching. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. The device is organized as dual 5-bit bus switches with separate output-enable (OE ) inputs. It can be used as two 5-bit bus switches or one 10-bit bus switch. When OE is low, the associated 5-bit bus switch is on, and A port is connected to B port. When OE is high, the switch is open, and the high-impedance state exists between the two ports. This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off. To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING QSOP − DBQ Tape and reel SN74CBTLV3384DBQR CBTLV3384 SOIC − DW Tube SN74CBTLV3384DW CBTLV3384−40°C to 85°C SOIC − DW Tape and reel SN74CBTLV3384DWR CBTLV3384−40 C to 85C TSSOP − PW Tape and reel SN74CBTLV3384PWR CL384 TVSOP − DGV Tape and reel SN74CBTLV3384DGVR CL384 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE (each 5-bit bus switch) INPUTS INPUTS/OUTPUTS 1OE 2OE 1B1−1B5 2B1−2B5 L L 1A1−1A5 2A1−2A5 L H 1A1−1A5 Z H LZ 2A1−2A5 H H Z Z Copyright  2004, Texas Instruments Incorporated DBQ, DGV, DW, OR PW PACKAGE (TOP VIEW) 1OE 1B1 1A1 1A2 1B2 1B3 1A3 1A4 1B4 1B5 1A5 GND V CC 2B5 2A5 2A4 2B4 2B3 2A3 2A2 2B2 2B1 2A1 2OE Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. /C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046

/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0076/C0086/C0051/C0051/C0056/C0052 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 SCDS059G − MARCH 1998 − REVISED JUNE 2004

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic) 1A1 SW 1B1 1A5 1OE SW 1B5 2A1 SW 2B1 2A5 2OE SW 2B5 simplified schematic, each FET switch A (OE) B absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.

/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0076/C0086/C0051/C0051/C0056/C0052 /C0076/C0079/C0087/C0262/C0086/C0079/C0076/C0084/C0065/C0071/C0069 /C0049/C0048/C0262/C0066/C0073/C0084 /C0070/C0069/C0084 /C0066/C0085/C0083 /C0083/C0087/C0073/C0084/C0067/C0072 SCDS059G − MARCH 1998 − REVISED JUNE 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 2.3 3.6 V VIH High-level control input voltage VCC = 2.3 V to 2.7 V 1.7 VVIH High-level control input voltage VCC = 2.7 V to 3.6 V 2 V VIL Low-level control input voltage VCC = 2.3 V to 2.7 V 0.7 VVIL Low-level control input voltage VCC = 2.7 V to 3.6 V 0.8 V TA Operating free-air temperature −40 85 °C NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 3 V, II = −18 mA −1.2 V II VCC = 3.6 V, VI = VCC or GND ±1 µA Ioff VCC = 0, VI or VO = 0 to 3.6 V 10 µA ICC VCC = 3.6 V, IO = 0, VI = VCC or GND 10 µA ∆ICC ‡ Control inputsVCC = 3.6 V, One input at 3 V, Other inputs at VCC or GND 300 µA C i Control inputsVI = 3 V or 0 4.5 pF C io(OFF) VO = 3 V or 0, OE = VCC 10 pF VCC = 2.3 V, VI = 0 II = 64 mA 5 8 VCC = 2.3 V, TYP at VCC = 2.5 V VI = 0 II = 24 mA 5 8 ron§ TYP at VCC = 2.5 V VI = 1.7 V, II = 15 mA 27 40 Ωron§ VI = 0 II = 64 mA 5 7 Ω VCC = 3 V VI = 0 II = 24 mA 5 7VCC = 3 V VI = 2.4 V, II = 15 mA 10 15 † All typical values are at VCC = 3.3 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by the lower of the voltages of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 2.5 V ± 0.2 V VCC = 3.3 V ± 0.3 V UNITPARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX UNIT tpd¶ A or B B or A 0.15 0.25 ns ten OE A or B 1 5 1 4.3 ns tdis OE A or B 1 5.5 1 5.5 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

0 V0 V

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

3,70 3,50 4,90 5,10 20DIM PINS ** 4073251/E 08/00 1,20 MAX Seating Plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 11 2 24 13 4,30 4,50 0,16 NOM Gage Plane A 7,90 7,70 382416 4,90 5,103,70 3,50 A MAX A MIN 6,60 6,20 11,20 11,40 9,60 9,80 0,08 M0,070,40 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. D. Falls within JEDEC: 24/48 Pins – MO-153 14/16/20/56 Pins – MO-194

/C0077/C0069/C0067/C0072/C0065/C0078/C0073/C0067/C0065/C0076 /C0068/C0065/C0084/C0065 MSOI004E JANUARY 1995 − REVISED MAY 2002 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DBQ (R−PDSO−G) PLASTIC SMALL−OUTLINE PACKAGE 4073301/F 02/2002 0.069 (1,75) MAX Seating Plane 0.004 (0,10) 0.010 (0,25) 0.010 (0,25) 0.016 (0,40) 0.035 (0,89) 0.244 (6,20) 0.228 (5,80) 11 2 24 13 0.150 (3,81) 0°−8° Gauge Plane 0.012 (0,30) 0.008 (0,20) 0.197 (5,00) (4,80) 0.189 A MAX A MIN PINS DIM 16 0.337 (8,56) (8,74) 0.344 20 24 A (8,74) 0.344 (8,56) 0.337 0.394 (10,01) 0.386 (9,80) M0−137 VARIATION AB AD AE AFD 0.004 (0,10) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO−137.

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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