CBT3253

SN74CBT3253 TI | Alldatasheet

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/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0051/C0050/C0053/C0051 /C0068/C0085/C0065/C0076 /C0049/C0262/C0079/C0070/C0262/C0052 /C0070/C0069/C0084 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0047/C0068/C0069/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082 SCDS018O − MAY 1995 − REVISED JANUARY 2004 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068TTL-Compatible Input Levels 1OE 1B4 1B3 1B2 1B1 GND V CC 2OE 2B4 2B3 2B2 2B1 D, DB, DBQ, OR PW PACKAGE (TOP VIEW) RGY PACKAGE (TOP VIEW) 11 6 2OE 2B4 2B3 2B2 2B1 1B4 1B3 1B2 1B1 1OE 2A V GND CC description/ordering information The SN74CBT3253 is a dual 1-of-4 high-speed TTL-compatible FET multiplexer/demultiplexer. The low on-state resistance of the switch allows connections to be made with minimal propagation delay. 1OE , 2OE, S0, and S1 select the appropriate B output for the A-input data.

ORDERING INFORMATION

TA PACKAGE † ORDERABLE PART NUMBER TOP-SIDE MARKING QFN − RGY Tape and reel SN74CBT3253RGYR CU253 SOIC − D Tube SN74CBT3253D CBT3253SOIC − D Tape and reel SN74CBT3253DR CBT3253 −40°C to 85°C SSOP − DB Tape and reel SN74CBT3253DBR CU253−40 C to 85C SSOP (QSOP) − DBQ Tape and reel SN74CBT3253DBQR CU253 TSSOP − PW Tube SN74CBT3253PW CU253TSSOP − PW Tape and reel SN74CBT3253PWR CU253 † Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. FUNCTION TABLE INPUTS FUNCTION1OE 2OE S1 S0 FUNCTION X H X X Disconnect 1A and 2A H X X X Disconnect 1A and 2A L L L L 1A to 1B1 and 2A to 2B1 L L L H 1A to 1B2 and 2A to 2B2 L L H L 1A to 1B3 and 2A to 2B3 L L H H 1A to 1B4 and 2A to 2B4 Copyright  2004, Texas Instruments Incorporated/C0080/C0082/C0079/C0068/C0085/C0067/C0084/C0073/C0079/C0078 /C0068/C0065/C0084/C0065 /C0105/C0110/C0102/C0111/C0114/C0109/C0097/C0116/C0105/C0111/C0110 /C0105/C0115 /C0099/C0117/C0114/C0114/C0101/C0110/C0116 /C0097/C0115 /C0111/C0102 /C0112/C0117/C0098/C0108/C0105/C0099/C0097/C0116/C0105/C0111/C0110 /C0100/C0097/C0116/C0101/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0115 /C0099/C0111/C0110/C0102/C0111/C0114/C0109 /C0116/C0111 /C0115/C0112/C0101/C0099/C0105/C0102/C0105/C0099/C0097/C0116/C0105/C0111/C0110/C0115 /C0112/C0101/C0114 /C0116/C0104/C0101 /C0116/C0101/C0114/C0109/C0115 /C0111/C0102 /C0084/C0101/C0120/C0097/C0115 /C0073/C0110/C0115/C0116/C0114/C0117/C0109/C0101/C0110/C0116/C0115 /C0115/C0116/C0097/C0110/C0100/C0097/C0114/C0100 /C0119/C0097/C0114/C0114/C0097/C0110/C0116/C0121/C0046 /C0080/C0114/C0111/C0100/C0117/C0099/C0116/C0105/C0111/C0110 /C0112/C0114/C0111/C0099/C0101/C0115/C0115/C0105/C0110/C0103 /C0100/C0111/C0101/C0115 /C0110/C0111/C0116 /C0110/C0101/C0099/C0101/C0115/C0115/C0097/C0114/C0105/C0108/C0121 /C0105/C0110/C0099/C0108/C0117/C0100/C0101 /C0116/C0101/C0115/C0116/C0105/C0110/C0103 /C0111/C0102 /C0097/C0108/C0108 /C0112/C0097/C0114/C0097/C0109/C0101/C0116/C0101/C0114/C0115/C0046 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0051/C0050/C0053/C0051 /C0068/C0085/C0065/C0076 /C0049/C0262/C0079/C0070/C0262/C0052 /C0070/C0069/C0084 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0047/C0068/C0069/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082 SCDS018O − MAY 1995 − REVISED JANUARY 2004

2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic) 2B1 1B1 1OE 2OE 1B2 1B3 1B4 2B2 2B3 2B4 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7. 3. The package thermal impedance is calculated in accordance with JESD 51-5.

/C0083/C0078/C0055/C0052/C0067/C0066/C0084/C0051/C0050/C0053/C0051 /C0068/C0085/C0065/C0076 /C0049/C0262/C0079/C0070/C0262/C0052 /C0070/C0069/C0084 /C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082/C0047/C0068/C0069/C0077/C0085/C0076/C0084/C0073/C0080/C0076/C0069/C0088/C0069/C0082 SCDS018O − MAY 1995 − REVISED JANUARY 2004 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 4) MIN MAX UNIT VCC Supply voltage 4 5.5 V VIH High-level control input voltage 2 V VIL Low-level control input voltage 0.8 V TA Operating free-air temperature −40 85 °C NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP † MAX UNIT VIK VCC = 4.5 V, II = −18 mA −1.2 V II VCC = 5 V, VI = 5.5 V or GND ±1 µA ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 3 µA ∆ICC ‡ Control inputs VCC = 5.5 V, One input at 3.4 V,Other inputs at VCC or GND 2.5 mA C i Control inputs VI = 3 V or 0 3.5 pF C io(OFF) A port VO = 3 V or 0, OE = VCC pFC io(OFF) B port VO = 3 V or 0, OE = VCC 4 pF VI = 0 II = 64 mA 5 7 ron§ VCC = 4.5 V VI = 0 II = 30 mA 5 7 Ωron§ VCC = 4.5 V VI = 2.4 V, II = 15 mA 10 15 Ω † All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C. ‡ This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND. § Measured by the voltage drop between the A and the B terminals at the indicated current through the switch. On-state resistance is determined by the lower voltage of the two (A or B) terminals. switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) VCC = 4 V VCC = 5 V ± 0.5 V UNITPARAMETER (INPUT) (OUTPUT) MIN MAX MIN MAX UNIT tpd¶ A or B B or A 0.35 0.25 ns tpd S A or B 6.6 1.6 6.2 ns ten S A or B 7.1 1.3 6.3 nsten OE A or B 7.3 1.4 6.4 ns tdis S A or B 7.9 1.1 7.4 nstdis OE A or B 7.3 2.3 7 ns ¶ The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPHL and tPLH are the same as tpd. H. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) SN74CBT3253D ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DBLE OBSOLETE SSOP DB 16 TBD Call TI Call TI SN74CBT3253DBQR ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBQRE4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBQRG4 ACTIVE SSOP/ QSOP DBQ 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253DBR ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DE4 ACTIVE SOIC D 16 40 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DR ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PW ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWE4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWG4 ACTIVE TSSOP PW 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWLE OBSOLETE TSSOP PW 16 TBD Call TI Call TI SN74CBT3253PWR ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWRE4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253PWRG4 ACTIVE TSSOP PW 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74CBT3253RGYR ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR SN74CBT3253RGYRG4 ACTIVE QFN RGY 16 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1YEAR (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 1

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. PACKAGE OPTION ADDENDUM www.ti.com 18-Jul-2006 Addendum-Page 2

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 4040065 /E 12/01

28 PINS SHOWN

8,20 7,40 0,55 0,95 0,25 12,90 12,30 10,50 8,50 Seating Plane 9,907,90 10,50 9,90 0,38 5,60 5,00 0,22 A 2016 6,506,50 0,05 MIN 5,905,90 DIM A MAX A MIN PINS ** 2,00 MAX 6,90 7,50 0,65 M0,15 0°–/C02578° 0,10 0,09 0,25 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65 M0,10 0,10 0,25 0,50 0,75 0,15 NOM Gage Plane 9,80 9,60 7,90 7,70 2016 6,60 6,40 4040064/F 01/97 0,30 6,60 6,20 0,19 4,30 4,50 0,15 A 1,20 MAX 5,10 4,90 3,10 2,90 A MAX A MIN DIM PINS ** 0,05 4,90 5,10 Seating Plane 0°–8° NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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