AD6645ASQ-105 AD | Alldatasheet
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14-Bit, 80 MSPS/105 MSPS A/D Converter AD6645 Rev. D Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2002–2008 Analog Devices, Inc. All rights reserved.
FEATURES
SNR = 75 dB, fIN 15 MHz, up to 105 MSPS SNR = 72 dB, fIN 200 MHz, up to 105 MSPS SFDR = 89 dBc, fIN 70 MHz, up to 105 MSPS 100 dBFS multitone SFDR IF sampling to 200 MHz Sampling jitter: 0.1 ps
1.5 W power dissipation
Differential analog inputs Pin compatible to AD6644 Twos complement digital output format
3.3 V CMOS compatible
Data-ready for output latching
APPLICATIONS
Multichannel, multimode receivers Base station infrastructures AMPS, IS-136, CDMA, GSM, W-CDMA Single channel digital receivers Antenna array processing Communications instrumentation Radars, infrared imaging Instrumentation GENERAL DESCRIPTION The AD6645 is a high speed, high performance, monolithic 14-bit analog-to-digital converter (ADC). All necessary functions, including track-and-hold (T/H) and reference, are included on the chip to provide a complete conversion solution. The AD6645 provides CMOS-compatible digital outputs. It is the fourth generation in a wideband ADC family, preceded by the AD9042 (12-bit, 41 MSPS), the AD6640 (12-bit, 65 MSPS, IF sampling), and the AD6644 (14-bit, 40 MSPS/65 MSPS). Designed for multichannel, multimode receivers, the AD6645 is part of the Analog Devices, Inc., SoftCell® transceiver chipset. The AD6645 maintains 100 dB multitone, spurious-free dynamic range (SFDR) through the second Nyquist band. This breakthrough performance eases the burden placed on multimode digital receivers (software radios) that are typically limited by the ADC. Noise performance is exceptional; typical signal-to-noise ratio (SNR) is 74.5 dB through the first Nyquist band. The AD6645 is built on the Analog Devices extra fast complementary bipolar (XFCB) process and uses an innovative, multipass circuit architecture. Units are available in thermally enhanced 52-lead PowerQuad 4 (LQFP_PQ4) and 52-lead exposed pad (TQFP_EP) packages specified from −40°C to +85°C at 80 MSPS and −10°C to +85°C at 105 MSPS. PRODUCT HIGHLIGHTS 1. IF Sampling. The AD6645 maintains outstanding ac performance up to input frequencies of 200 MHz, suitable for multicarrier 3G wideband cellular IF sampling receivers. 2. Pin Compatibility. The ADC has the same footprint and pin layout as the AD6644 14-bit, 40 MSPS/65 MSPS ADC. 3. SFDR Performance and Oversampling. Multitone SFDR performance of 100 dBFS can reduce the requirements of high end RF components and allows the use of receive signal processors, such as the AD6620, AD6624/AD6624A, or AD6636. FUNCTIONAL BLOCK DIAGRAM AD6645 AIN AIN VREF ENCODE ENCODE GND DMID OVR DRY D13 MSB D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LSB ADC3TH5TH4 DAC2ADC2 TH3A2 DAC1 DIGITAL ERROR CORRECTION LOGIC TH2 ADC1 TH1A1 2.4V INTERNAL TIMING DVCCAVCC 02647-001 Figure 1.
Rev. D | Page 2 of 24 TABLE OF CONTENTS
REVISION HISTORY
10/08—Rev. C to Rev. D Renamed Thermal Characteristics Section Thermal Resistance 12/06—Rev. B to Rev. C 7/03—Rev. A to Rev. B. 6/02—Rev. 0 to Rev. A.
Rev. D | Page 3 of 24 SPECIFICATIONS DC SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted. Table 1. AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Test Level Min Typ Max Min Typ Max Unit RESOLUTION 14 14 Bits ACCURACY No Missing Codes Full II Guaranteed Guaranteed Offset Error Full II −10 +1.2 +10 −10 +1.2 +10 mV Gain Error Full II −10 0 +10 −10 0 +10 % FS Integral Nonlinearity (INL) Full V ±0.5 ±1.5 LSB TEMPERATURE DRIFT Offset Error Full V 1.5 1.5 ppm/°C Gain Error Full V 48 48 ppm/°C POWER SUPPLY REJECTION RATIO (PSRR) REFERENCE OUT (VREF) 1 Full V 2.4 2.4 V ANALOG INPUTS (AIN, AIN) Differential Input Voltage Range Full V 2.2 2.2 V p-p Differential Input Resistance Full V 1 1 kΩ Differential Input Capacitance 25°C 1.5 1.5 pF POWER SUPPLY Supply Voltages Supply Current IAVCC (AVCC = 5.0 V) Full II 275 320 275 320 mA IDVCC (DVCC = 3.3 V) Full II 32 45 32 45 mA Rise Time2 AVCC Full IV 250 5.0 250 ms POWER CONSUMPTION Full II 1.5 1.75 1.5 1.75 W 1 VREF is provided for setting the common-mode offset of a differential amplifier, such as the AD8138, when a dc-coupled analog input is required. VREF should be buffered if used to drive additional circuit functions. 2 Specified for dc supplies with linear rise time characteristics.
Rev. D | Page 4 of 24 DIGITAL SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; TMIN and TMAX at rated speed grade, unless otherwise noted. Table 2. Test AD6645ASQ-80/AD6645ASV-80 AD6645ASQ-105/AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUTS (ENCODE, ENCODE) Differential Input Voltage1 Full IV 0.4 0.4 V p-p Differential Input Resistance 25°C V 10 10 kΩ Differential Input Capacitance 25°C V 2.5 2.5 pF LOGIC OUTPUTS (D13 to D0, DRY , OVR) Logic Compatibility CMOS CMOS Logic 1 Voltage (DVCC = 3.3 V)2 Full II 2.85 DVCC − 2 2.85 DVCC − 2 V Logic 0 Voltage (DVCC = 3.3 V)2 Full II 0.2 0.5 0.2 0.5 V Output Coding Twos complement Twos complement DMID Full V DVCC/2 DVCC/2 V 1 All ac specifications tested by driving ENCODE and ENCODE differentially. 2 Digital output logic levels: DVCC = 3.3 V, CLOAD = 10 pF. Capacitive loads >10 pF degrades performance. AC SPECIFICATIONS All ac specifications tested by driving ENCODE and ENCODE differentially. AVCC = 5 V , DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted. Table 3. Test AD6645ASQ-80/ AD6645ASV-80 AD6645ASQ-105/ AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions SNR Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz 25°C V 73.0 73.0 dB At 150.0 MHz 25°C V 72.0 72.0 dB At 200.0 MHz SINAD Analog Input @ −1 dBFS 25°C V 75.0 75.0 dB At 15.5 MHz Full II 72.5 74.5 dB At 30.5 MHz 25°C I 72.5 74.5 dB At 37.7 MHz Full V 73.0 73.0 dB At 70.0 MHz 25°C V 68.5 67.5 dB At 150.0 MHz 25°C V 62.5 62.5 dB At 200.0 MHz WORST HARMONIC (SECOND OR THIRD) Analog Input @ −1 dBFS 25°C V 93.0 93.1 dBc At 15.5 MHz Full II 85.0 93.0 dBc At 30.5 MHz 25°C I 85.0 93.0 dBc At 37.7 MHz Full V 89.0 87.0 dBc At 70.0 MHz 25°C V 70.0 70.0 dBc At 150.0 MHz 25°C V 63.5 63.5 dBc At 200.0 MHz
Rev. D | Page 5 of 24 Test AD6645ASQ-80/ AD6645ASV-80 AD6645ASQ-105/ AD6645ASV-105 Parameter Temp Level Min Typ Max Min Typ Max Unit Conditions WORST HARMONIC (FOURTH OR HIGHER) Analog Input @ −1 dBFS 25°C V 96.0 96.0 dBc At 15.5 MHz Full II 85.0 95.0 dBc At 30.5 MHz 25°C I 86.0 95.0 dBc At 37.7 MHz Full V 90.0 90.0 dBc At 70.0 MHz 25°C V 90.0 90.0 dBc At 150.0 MHz 25°C V 88.0 88.0 dBc At 200.0 MHz TWO-TONE SFDR 25°C V 100 98.0 dBFS At 30.5 MHz1, 2 25°C V 100 98.0 dBFS At 55.0 MHz1, 3 25°C V 98.0 dBFS At 70.0 MHz1, 4 TWO-TONE IMD REJECTION2, 3 F1, F2 @ −7 dBFS 25°C V 90 90 dBc ANALOG INPUT BANDWIDTH 25°C V 270 270 MHz 1 Analog input signal power swept from −10 dBFS to −100 dBFS. 2 F1 = 30.5 MHz, F2 = 31.5 MHz. 3 F1 = 55.25 MHz, F2 = 56.25 MHz. 4 F1 = 69.1 MHz, F2 = 71.1 MHz. SWITCHING SPECIFICATIONS AVCC = 5 V , DVCC = 3.3 V; ENCODE, ENCODE, TMIN and TMAX at rated speed grade, unless otherwise noted. Table 4. Test AD6645ASQ-80/ AD6645ASV-80 AD6645ASQ-105/ AD6645ASV-105 Parameter Symbol Temp Level Min Typ Max Min Typ Max Unit ENCODE INPUT PARAMETERS1 Maximum Conversion Rate Full II 80 105 MSPS Minimum Conversion Rate Full IV 30 30 MSPS ENCODE Pulse Width High, tENCH2 Full IV 5.625 4.286 ns Full V 6.25 4.75 ns ENCODE Pulse Width Low, tENCL2 Full IV 5.625 4.286 ns Full V 6.25 4.75 ns ENCODE Period1 tENC Full V 12.5 9.5 ns ENCODE/DATA-READY ENCODE Rising to Data-Ready Rising tE_DR Full V tENCH + tDR tENCH + tDR ns ENCODE/DATA (D13:0), OVR ENCODE to DATA Delay (Setup Time) tS_E Full V tENC − tE_FL(max) tENC − tE_FL(max) ns tENC − tE_FL(typ) tENC − tE_FL(typ) ns tENC − tE_FL(min) tENC − tE_FL(min) ns
1 Several timing parameters are a function of tENC and tENCH. 2 Several timing parameters are a function of tENCL and tENCH. 3 ENCODE TO DATA Delay (Hold Time) is the absolute minimum propagation delay through the ADC, tE_RL = tH_E. 4 DRY is an inverted and delayed version of the encode clock. Any change in the duty cycle of the clock will correspondingly change the duty cycle of DRY. 5 Data-ready to DATA Delay (tH_DR and tS_DR) is calculated relative to rated speed grade and is dependent on tENC and duty cycle. Figure 2. Timing Diagram
Table 6. Thermal Characteristics 1 Per JEDEC JESD51-2 (heat sink soldered to PCB).
3 Values of θJA are provided for package comparison and PCB design
4 Per JEDEC JESD51-6 (heat sink soldered to PCB). traces, throughholes, ground, and power planes, the more θJA is reduced. 6 Per MIL-STD-883, Method 1012.1.
7 Values of θJC are provided for package comparison and PCB design
considerations when an external heat sink is required. TA is the ambient temperature (°C). PD is the power dissipation (W). and characterization at temperature extremes. V . Parameter is a typical value only.
- EXPOSED PAD. CONNECT THE EXPOSED PAD TO GND.
27 GND
28 AVCC
29 GND
30 AVCC
31 DNC
32 OVR
33 DVCC
34 GND
35 DMID
36 D0 (LSB)
Figure 3. Pin Configuration Table 7. Pin Function Descriptions 1, 33, 43 DVCC 3.3 V Power Supply (Digital) Output Stage Only. 3 VREF 2.4 V Reference. Bypass to ground with a 0.1 μF microwave chip capacitor. 5 ENCODE Encode Input. Conversion initiated on rising edge. 6 ENCODE Complement of ENCODE, Differential Input. 12 AIN Complement of AIN, Differential Analog Input. 20 C1 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 24 C2 Internal Voltage Reference. Bypass to ground with a 0.1 μF chip capacitor. 31 DNC Do not connect this pin. 32 OVR Overrange Bit. A logic level high indicates analog input exceeds ±FS. 35 DMID Output Data Voltage Midpoint. Approximately equal to (DVCC)/2. 36 D0 (LSB) Digital Output Bit (Least Significant Bit); Twos Complement. 37 to 41, 44 to 50 D1 to D5, D6 to D12 Digital Output Bits in Twos Complement. 51 D13 (MSB) Digital Output Bit (Most Significant Bit); Twos Complement. 53 (EPAD) Exposed Paddle (EPAD) Exposed Pad. Connect the exposed pad to GND.
Rev. D | Page 15 of 24 TERMINOLOGY Analog Bandwidth The analog input frequency at which the spectral power of the fundamental frequency (as determined by the FFT analysis) is reduced by 3 dB. Aperture Delay The delay between the 50% point of the rising edge of the encode command and the instant at which the analog input is sampled. Aperture Uncertainty (Jitter) The sample-to-sample variation in aperture delay. Differential Analog Input Resistance, Differential Analog Input Capacitance, and Differential Analog Input Impedance The real and complex impedances measured at each analog input port. The resistance is measured statically and the capacitance and differential input impedances are measured with a network analyzer. Differential Analog Input Voltage Range The peak-to-peak differential voltage that must be applied to the converter to generate a full-scale response. The peak differential voltage is computed by observing the voltage on a single pin and subtracting the voltage from the other pin, which is 180° out of phase. The peak-to-peak differential is computed by rotating the inputs’ phase 180°and taking the peak measurement again. The difference is then computed between both peak measurements. Differential Nonlinearity The deviation of any code width from an ideal 1 LSB step. Encode Pulse Width/Duty Cycle Pulse width high is the minimum amount of time that the encode pulse should be left in a high state to achieve rated performance; pulse width low is the minimum time that the encode pulse should be left in a low state. See timing implications of changing t ENCH in Table 4. At a given clock rate, these specifications define an acceptable encode duty cycle. Full-Scale Input Power The full-scale input power is expressed in dBm and can be calculated by using the following equation: ⎡ − =− 001 . 0 log 10 InputZ rms Scale FullV Scale FullPower Harmonic Distortion, Second The ratio of the rms signal amplitude to the rms value of the second harmonic component, reported in dBc. Harmonic Distortion, Third The ratio of the rms signal amplitude to the rms value of the third harmonic component, reported in dBc. Integral Nonlinearity The deviation of the transfer function from a reference line measured in fractions of 1 LSB using a best straight line determined by a least square curve fit. Maximum Conversion Rate The encode rate at which parametric testing is performed. Minimum Conversion Rate The encode rate at which the SNR of the lowest analog signal frequency drops by no more than 3 dB below the guaranteed limit. Noise (for Any Range Within the ADC) ⎛ − −× × = 1010 001 . 0 dBFSdBcdBm NOISE SignalSNRFSZV where: Z is the input impedance. FS is the full scale of the device for the frequency in question. SNR is the value for the particular input level. Signal is the signal level within the ADC reported in dB below full scale. This value includes both thermal noise and quantiza- tion noise. Output Propagation Delay The delay between a differential crossing of ENCODE and ENCODE and the time when all output data bits are within valid logic levels. Power Supply Rejection Ratio (PSSR) The ratio of a change in input offset voltage to a change in power supply voltage. Power Supply Rise Time The time from when the dc supply is initiated until the supply output reaches the minimum specified operating voltage for the ADC. The dc level is measured at the supply pin(s) of the ADC. Signal-to-Noise-and-Distortion (SINAD) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, including harmonics, but excluding dc. Signal-to-Noise Ratio (Without Harmonics) The ratio of the rms signal amplitude (set at 1 dB below full scale) to the rms value of the sum of all other spectral components, excluding the first five harmonics and dc.
Rev. D | Page 16 of 24 Spurious-Free Dynamic Range (SFDR) The ratio of the rms signal amplitude to the rms value of the peak spurious spectral component. The peak spurious component may or may not be a harmonic. May be reported in dBc (that is, degrades as signal level is lowered) or dBFS (always related back to converter full scale). Two-Tone Intermodulation Distortion Rejection The ratio of the rms value of either input tone to the rms value of the worst third-order intermodulation product, reported in dBc. Two-Tone SFDR The ratio of the rms value of either input tone to the rms value of the peak spurious component. The peak spurious component may or may not be an IMD product, and may be reported in dBc (that is, degrades as signal level is lowered) or in dBFS (always related back to converter full scale). Worst Other Spur The ratio of the rms signal amplitude to the rms value of the worst spurious component (excluding the second and third harmonics), reported in dBc.
implementation of high frequency, high resolution design practices. with the inputs on the opposite side for isolation purposes. only one gate should be used for all AD6645 digital outputs. isolated from the digital outputs and the analog inputs. Table 8. Twos Complement Output Coding fANALOG is the analog input frequency. and internal encode circuitry). ε is the average DNL of the ADC (typically 0.41 LSB). n is the number of bits in the ADC. analog input of the ADC (typically 0.9 LSB rms). expected SNR performance of the AD6645 as jitter increases. The chart is derived from the preceding equation. Figure 42. SNR vs. Jitter
Table 9. AD6645/PCB Bill of Materials
80 MSPS
105 MSPS Reference ID Description Manufacturer Supplier Part No.
2 MHz to 775 MHz
Rev. D | Page 21 of 24 Quantity 105 MSPS Reference ID Description Manufacturer Supplier Part No. 0 0 (U8)2, 3 IC, SOIC-8, differential receiver Motorola MC100LVEL16 1 0 Y1 Clock oscillator, 80 MHz CTS Reeves MXO45-80 4 4 Y1 Pin sockets, closed end AMP/Tyco Electronics 5-330808-3 4 4 Circuit board support Richco, Inc. CBSB-14-01 1 AC-coupled AIN is standard: R3, R4, R5, R8, and U3 are not installed. If dc-coupled AIN is required, C30, R15, and T3 are not installed. 2 Reference designators in parentheses are not installed on standard units. 3 AC-coupled encode is standard: C5, C6, C33, C34, R1, R11 to R14, and U8 are not installed. If PECL encode is required, CR1 and T2 are not installed.
- R2 IS INSTALLED FOR INPUT MATCHING ON THE PRIMARY OF T3. R1 5 IS NOT INSTALLED.
R15 IS INSTALLED FOR INPUT MATCHING ON THE SECONDARY OF T3, R2 IS NOT INSTALLED.
- AC-COUPLED ENCODE IS STANDARD. C5, C6, C33, C34, R1, R11 −R14 AND U8 ARE NOT INSTALLED.
- AC-COUPLED AIN IS STANDARD, R3, R4, R5, R8 AND U3 ARE NOT INSTALLED.
IF DC-COUPLED AIN IS REQUIRED, C30, R15 AND T3 ARE NOT INSTALLED. IF PECL ENCODE IS REQUIRED, CR1 AND T2 ARE NOT INSTALLED. Figure 43. Evaluation Board Schematic
0.10 MAX
Figure 48. 52-Lead Low Profile Quad Flat Package, PowerQuad [LQFP_PQ4]
12.00 BSC
6.50 BSC
0.08 MAX
Figure 49. 52-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP] registered trademarks are the prop erty of their respective owners.