CBM53D14

CBM53D14 COREBAI | Alldatasheet

Document overview

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Technical content

Features

 CBM53D14:4 buffered 10-Bit DACs in MSOP10L  CBM53D24:4 buffered 12-Bit DACs in MSOP10L  Low power operation: 500uA @ 3V,  600uA @ 5V  2.5V to 5.5V power supply  Power-down to 80nA @ 3V,200nA @ 5V  Double-buffered input logic  Output range:0V to  Power-on reset to 0V  On-chip, rail-to-rail output buffer amplifiers  Temperature range -40℃ to +105℃

Applications

 Portable battery-powered instruments  Digital gain and offset adjustment  Programmable voltage and current sources  Programmable attenuators  Industrial process controls General Description The CBM53D14/CBM53D24 are quad 10- and 12-bit buffered voltage output DACs in MSOP10L packages that operate from a single 2.5V to 5.5V supply, consuming only 500uA at 3V. They have on-chip rail-to-rail output amplifiers with slew rate of 0.7V/us. A 3-wire serial interface compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards is used, which can operates at clock rates up to 30MHz. The references for the four DACs are derived from one reference pin. The outputs of all DACs can be updated simultaneous. It incorporate a power-on reset circuit, and ensure that the DAC outputs power up to 0V and remains there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption to 200nA @ 5V (80nA @ 3V). A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Absolute Maximum Ratings Table 1 TA=25℃,unless otherwise noted. Parameter1 Sym Rating VDD to GND VDDabs -0.3V to+7V Digital Input Voltage to GND VDigabs -0.3V to VDD+0.3V Reference Input Voltage to GND Vrefabs -0.3V to VDD+0.3V VOUTA through VOUTD to GND Voutabs -0.3V to VDD+0.3V Operating Temperature Range Industrial Storage Temperature Range Junction TemperatureTJ max TP TS TJmax -40℃ to +105℃ -65℃ to +150℃ 150℃ Reflow Soldering Peak Temperature(Pb-free) Peak Temperature(non Pb-free) Time at Peak Temperature 260℃ 220℃ 10 sec to 40 sec Transient currents of up to 100mA do not cause SCR latch-up. Recommended Operation Conditions Table 2 Parameter Sym Rating Unit Min Max Power supply VDD 2.5 5.5 V Current dissipation IDD 400u 600u A Ambient Temperature Ta -40 105 ℃ A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Specifications Table 3 VDD=2.5V to 5.5V; V REF=2V; RL=2KΩ to GND ; C L=200pF to GND; T a=25℃; unless otherwise noted. Parameter Sym Test Condition Min Typ Max Unit DC Performance1,2 CBM53D14 Resolution Relative Accuracy Differential Nonlinearity ResN INL DNL Monotonic Guaranteed ±0.5 ±0.05 Bits LSB LSB CBM53D24 Resolution Relative Accuracy Differential Nonlinearity ResN INL DNL Monotonic Guaranteed ±0.2 Bits LSB LSB Offset Error ±0.4 %of FSR Gain Error ±0.15 %of FSR Lower Dead Band Lower dead band exists only if offset error is negative 20 mV DC Power Supply Rejection Ratio3 PSRR △VDD=±10% -60 dB DC Crosstalk3 RL=2KΩ to GND or V DD 200 Uv Reference Input3 VREF Input Range VREF Input Impedance Reference Feedthrough Frequency=10KHz 0.25 -80 VDD V KΩ dB Output Characteristics3 Minimum Output Voltage4 Maximum Output Voltage4 DC Output Impedance Short Circuit Current Power-Up Time VDD 0.5 V V Ω mA uS Logic Input3 Input Low Voltage VIL VDD=3V 0.6 V A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Input High Voltage Pin Capacitance VIH VDD=3V 2.1 V pF Power Requirements Power supply IDD (Normal Mode)4 VDD IDD 2.5 5.5 V VDD=4.5V to 5.5V VDD=2.5V to 3.6V IDD (Power-Down Mode) VDD=4.5V to 5.5V VDD=2.5V to 3.6V VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND VIH=VDD and VIL=GND 600 500 0.2 0.08 uA uA uA uA 1 DC specifications tested with the outputs unloaded.

2 Linearity is tested using a reduced code range: CBM53D14(Code 28 to Code 995);

CBM53D24(Code 115 to Code 3981). 3 Guaranteed by design and characterization, not production tested. 4 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF=VDD and offset plus gain error must be positive.

5 IDDspecification is valid for all DAC codes; interface inactive; all DACs active; load currents

excluded. AC Characteristics Table 4 VDD=2.5V to 5.5V; V REF=2V; RL=2KΩ to GND ; C L=200pF to GND; T a=25℃; unless otherwise noted. Parameter1 Sym Test Condition Min Typ Max Unit Output Voltage Setting Time CBM53D14 CBM53D24 1/4 scale to 3/4 scale change(0x100 to 0x300) 1/4 scale to 3/4 scale change(0x100 to 0x300) uS uS Slew Rate 0.7 V/uS Major-Code Transition Glitch Energy

1 LSB change around major

Digital Feedthrough 1 nV-sec A ll data sheet.com

1 Guaranteed by design and characterization, not production tested. VDD = 2.5V to 5.5V; all specifications T MIN to TMAX, unless otherwise noted. 1 Guaranteed by design and characterization, not production tested.

2 All input signals are specified with tr = tf = 5ns (10% to 90% of V DD) and timed from a voltage

Figure 3. Serial Interface Timing Diagram

Figure 4. MSOP10L Pin Configuration

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Pin Function Descriptions Table 5 Pin Name Pin No. Function Description VDD 1 Power Power Supply Input. These parts can be operated from 2.5V to 5.5V and the supply can be decoupled to GND. VOUTA 2 O Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation. VOUTB 3 O Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation. VOUTC 4 O Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation. Refin 5 I Reference Input Pin for All Four DACs. It has an input range from 0.25V to V DD. VOUTD 6 O Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation. GND 7 Ground Ground Reference Point for All Circuitry on the Part. Din 8 I Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the serial clock input. The Din input buffer is powered down after each write cycle. Sclk 9 I Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can be transferred at clock speeds up to 30MHz. The Sclk input buffer is powered down after each write cycle. Sync 10 I Active Low Control Input. This is the frame synchronization signal for the input data. When goes low, it enables the input shift register and data is transferred in on the falling edges of the following 16clocks. If SYNC is taken high before the 16 th falling edge of Sclk, the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device. I：Input, O：Output A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Functional Description The CBM53D14/CBM53D24 are quad, resistor-string DACs fabricated on a CMOS process with resolutions of 10 and 12 bits, respectively. Each contains four output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5V to 5.5V, and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of 0.7 V/us. The four DACs share a single reference input pin. The devices have programmable power-down modes, in which all DACs can be turned off completely with a high impedance output. The architecture of one DAC channel consists of a resistor-string DAC followed by an output buffer amplifier. The voltage at the Refin pin provides the reference voltage for the DAC. The input coding to the DAC is straight binary, the ideal output voltage is given by VOUT = VREF×D formula 1 Where D=decimal equivalent of the binary code that is loaded to the DAC register: 0—1023 for CBM53D14(10 bits) 0—4095for CBM53D24(12bits) N=DAC resolution. There is a single reference input pin for the four DACs. The reference input is not buffered. The user can have a reference voltage as low as 0.25V or as high as VDD because there is no restriction due to the headroom or footroom requirements of any reference amplifier. It is recommended to use a buffered reference in the external circuit. The input impedance is typical 45kΩ. The output buffer amplifier is capable of generating rail-to-rail voltages on its output, giving an output range of 0V to V DD when the reference is V DD. It is capable of driving a load of 2kΩ to GND or V DD , in parallel with 500pF to GND or V DD. The slew rate is 0.7V/us with a half-scale settling time to ±0.5 LSB(at 12 bits) of 8us. The CBM53D14/CBM53D24 are provided with a power-on reset function, so that they power up in a defined state. The power-on state uses normal operation and an output voltage set to 0V. Both input and DAC registers are filled with zeros and remain so until a valid write sequence is made to the device. The CBM53D14/CBM53D24 are controlled over a versatile, 3-wire serial interface that operates at clock rates up to 30MHz and are compatible with SPI,QSPI,MICROWIRE, and DSP interface standards. A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION The 3-wire serial interface (a). CBM53D14 Input Shift Register Contents (b). CBM53D24 Input Shift Register Contents Figure42. CBM53D14/CBM53D24 Input Shift Register Contents Input Shift Register The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, Sclk. The 16-bit word consists of four control bits followed by 10 or 12 bits of DAC data, depending on the device type. Data is loaded MSB first (Bit15) and the first two bits determine whether the data is for DAC A , DAC B ,DAC C, or DCA D. Bit 13 and Bit 12 control the operating mode of the DAC. Bit 13 is PD, and determines whether the part is in normal or power-down mode. Bit 12 is LDAC, and controls when DAC registers and outputs are updated. Table 6 Address Bits A1 A0 DAC Addressed 0 0 DAC A 0 1 DAC B 1 0 DAC C 1 1 DAC D Control Bits A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION PD: 0: All four DACs go into power-down mode, consuming only 200nA @ 5V. The DAC outputs enter a high impedance state. 1: Normal operation. LDAC 0: All four DAC registers and, therefore, all DAC outputs updated simultaneously on completion of the write sequence. 1: Only addressed input register is updated. There is no change in the content of the DAC registers. The CBM53D24 uses all 12 bits of DAC data; the CBM53D14 uses 10 bits and ignores the 2 LSB Bits. The data format is straight binary, with all 0s corresponding to 0V output and all 1s corresponding to full-scale output (VREF-1LSB). The Sync input is a level-triggered input that acts as a frame synchronization signal and chip enable. Data can be transferred into the device only while Sync is low. To start the serial data transfer, take Sync low. After Sync goes low, serial data shifts into the device’s input shift register on the falling edges of Sclk for 16 clock pulses. Any data and clock pulses after the 16 th falling edge of Sclk are ignored because the Sclk and Din input buffers are powered down. No further serial data transfer occurs until Sync is taken high and low again.Sync can be taken high after the falling edge of the 16 th Sclk pulse. After the end of the serial data transfer, data automatically transfers from the input shift register to the input register of the selected DAC. If Sync is taken high before the 16 th falling edge of Sclk, the data transfer is aborted and the DAC input registers are not updated. When data has been transferred into three of the DAC input registers, all DAC registers and all DAC outputs are simultaneously updated by setting LDAC low when writing to the remaining DAC input register. Low Power Serial Interface To reduce the power consumption of the device even further, the interface fully powers up only when the device is being written to, that is , on the falling edge of Sync. As soon as the 16-bit control word has been written to the part, the Sclk and Din input buffers are powered down. They power up again only following a falling edge of Sync. A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION Double-Buffered Interface The CBM53D14/CBM53D24 DAC’s have double-buffered interfaces consisting of two banks of registers－ input registers and DAC registers. The input register is directly connected to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC register contains the digital code used by the resistor string. Access to the DAC register is controlled by the LDAC bit. When the LDAC bit is set high, the DAC register is latched and hence the input register can change state without affecting the contents of the DAC register. However, when the LDAC bit is set low, all DAC registers are update after a complete write sequence. This is useful if the user requires simultaneous updating of all DAC outputs. The user can write to three of the input registers individually and then, by setting the LDAC bit low when writing to the remaining DAC input register, all outputs update simultaneously. These parts contain an extra feature whereby the DAC register is not updated unless its input register has been update since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC registers are filled with the contents of the input register. In the case of the CBM53D14/CBM53D24 the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk. Power-Down Mode The CBM53D14/CBM53D24 have low power consumption, dissipation only 1.5mW with a 3V supply and 3mW with a 5V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, selected by a 0 on Bit 13 (PD) of the control word. When the PD bit is set to 1, all DAC’s work normally with a typical power consumption of 600uA at 5V (500uA at 3V ). However, in power-down mode, the supply current falls to 200nA at 5V (80nA at 3V) when all DAC’s are powered down. Not only does the supply current drop, but also the output stage is internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-stated while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The bias generator, the output amplifier, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION registers are unaffected when in power-down. The time to exit power-down is typically 5us. This is the time from the falling edge of the 16 th Sclk pulse to when the output voltage deviates from its power down voltage. Typical Application Circuit The CBM53D14/CBM53D24 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0V to V DD. More typically, these devices are used with a fixed, precision reference voltage. If an output range of 0V to V DD is required, the simplest solution is to connect the reference input to VDD. As this supply is not very accurate and can be noisy, the CBM53D14/CBM53D24 can be powered from the reference voltage; for example, using a 5V reference. The current required is 600uA supply current and approximately 112uA into the reference input. This is with no load on the DAC outputs. When the DAC outputs are loaded, the reference also needs to supply the current to the loads. Decoding Multiple CBM53D14/CBM53D24 The SYNC pin on the CBM53D14/CBM53D24 can be used in applications to decode a number of DACs. In this application, all the DACs in the system receive the same serial clock and serial data, but SYNC can only be active to one of the devices at any one time, allowing access to only one DAC in this system. The 74HC139 can be used as a 2-to-4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input must be brought to its inactive state while the coded address inputs are changing state. Power Supply Bypassing and Grounding In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the CBM53D14/CBM53D24 is mounted is designed so that the analog and digital sections are separated and confined to certain areas of the board. If the CBM53D14/CBM53D24 are in a system where multiple devices require an AGND-to-DGND connection, the connection is made at one point only. The star ground point is established as close as possible to the device. The CBM53D14/CBM53D24 has ample supply bypassing of 10uF in parallel with 0.1uF on the supply located as close to the package as possible, ideally right up against the device. The 10uF capacitors are the tantalum bead type. The 0.1uF capacitor has low effective series resistance A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION (ESR) and effective series inductance (ESI). The power supply lines of the CBM53D14/CBM53D24 use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks are shielded with digital ground to avoid radiating noise to other parts of the board, and are never run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board run at right angles to each other. This reduces the effects of feedthrough through the board. Outline Dimensions Figure 5 MSOP10L Dimensions shown in millimeters SYBMOL MILLIMETER MIN NOM MAX A - - 1.10 A1 0.05 - 0.15 A2 0.75 0.85 0.95 A3 0.30 0.35 0.40 b 0.19 - 0.28 b1 0.18 0.20 0.23 c 0.15 - 0.20 c1 0.14 0.152 0.16 D 2.90 3.00 3.10 E 4.70 4.90 5.10 E1 2.90 3.00 3.10 e 0.50 BSC L 0.40 - 0.70 L1 0.95 BSC θ 0 - 8° L/F 载体尺寸 （mil） 71×96 A ll data sheet.com

www.corebai.com CBM53D14/CBM53D24 OPERATION INSTRUCTION PACKAGE/ORDERING INFORMATION PRODUCT ORDERING NUMBER TEMPRANGE PACKAGE PAKEAGE MARKING TRANSPOT MEDIA,QUANTILY CBM53D14 CBM53D14AMS -40℃~105℃ MSOP-10 53D14A Tape and Reel,1000 CBM53D14BMS -40℃~105℃ MSOP-10 53D14B Tape and Reel,1000 CBM53D14 CBM53D14AQF -40℃~105℃ QFN-10 53D14AQ Tape and Reel,1000 CBM53D14BQF -40℃~105℃ QFN-10 53D14BQ Tape and Reel,1000 CBM53D24 CBM53D24AMS -40℃~105℃ MSOP-10 53D24A Tape and Reel,1000 CBM53D24BMS -40℃~105℃ MSOP-10 53D24B Tape and Reel,1000 CBM53D24 CBM53D24AQF -40℃~105℃ QFN-10 53D24AQ Tape and Reel,1000 CBM53D24BQF -40℃~105℃ QFN-10 53D24BQ Tape and Reel,1000 A ll data sheet.com