CB35000 STMICROELECTRONICS | Alldatasheet
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FEATURES
■ 0.5 micron triple layer metal HCMOS5S pro- cess featuring retrograde well technology, low resistance salicided active areas, polysi- licide gates and thin metal oxide. ■ 3.3 V optimized transistor with 5 V I/O inter- face capability ■ 2 - input NAND delay of 210 ps (typ) with fanout = 2. ■ Broad I/O functionality including LVCMOS, LVTTL, GTL, PECL, and LVDS. ■ High drive I/O; capability of sinking up to 48 mA with slew rate control, current spike sup- pression and impedance matching. ■ Generators to support SPRAM, DPRAM, ROM and MULT with BIST options. ■ Extensive embedded function library includ- ing DSP and ST micros, popular third party micros and Synopsys synthetic libraries. Table 1 Module Generator Library Cell Description SPRAM 256K bits max 16K word max 64 bit max Zero static current Tristate outputs DPRAM 128K bits max 8K word max 64 bit max Zero static current Tristate outputs ROM 2M bits max 32K word max 64 bit max Diffusion programmable Tristate outputs MULT Parallel asynchronous operation 2’s complement product 6 to 64 bits for both inputs Ripple Carry or Fast Carry Look Ahead ■ Fully independent power and ground config- urations for inputs, core and outputs. ■ I/O ring capability up to 800 pads. ■ Output buffers capable of driving ISA, EISA, PCI, MCA, and SCSI interface levels. ■ Active pull up and pull down devices. ■ Buskeeper I/O functions. ■ Oscillators for wide frequency spectrum. ■ Broad range of 300 SSI cells. ■ Low Power / Low Drive library subset. ■ Design For Test includes IEEE 1149.1 JTAG Boundary Scan architecture built in. ■ Cadence and Mentor based design system with interfaces from multiple workstations. ■ Broad ceramic and plastic package range. ■ Latchup trigger current > +/- 500 mA. ESD protection > +/- 4000 volts.
The CB35000 standard cell series uses a high performance, low voltage, triple level metal, HCMOS5S 0.5 micron process to achieve sub- nanosecond internal speeds while offering very low power dissipation and high noise immunity. With an average gate density of 5500 gates/mm the CB35000 family allows the design of highly complex devices. The potential available gate count ranges above 1.5 Million equivalent gates. Devices can operate over a Vdd voltage range of 2.7 to 3.6 volts. The I/O count for this array family ranges to over 600 signals and 800 pins dependent upon the package technology utilized. A Sea of I/O approach has been followed to give a solution to CONVENTIONAL VIA LAYOUT STACKED VIA LAYOUT SUBSTRATEISOLATION GATE CONTACT METAL 1 METAL 2 METAL 3 1st VIA 2nd VIA 3rd DIELECTRIC 2nd DIELECTRIC 1st DIELECTRIC AREA SAVINGS UP TO 20% FOR RANDOM LOGIC SIMPLIFIED ROUTING AND DESIGN RULE CHECKING CONTACT / VIA PLUGS Figure 1 Advantages of stacked contacts and vias today’s problems of drive levels and specialized interface standards. The technology does not utilize a set bond pad spacing but allows for pad spacings from 80 microns upwards. The I/O is fully compatible with that of the ISB35000 Structured Array family. The I/O can be configured for circuits ranging from low voltage CMOS and TTL to 350 mHz plus low swing differential circuits. Standards like GTL, SCSI-2, 3.3 Volt PCI, CTI, and a limited set of 5.0 Volt interfaces are currently being addressed. A specialized set of impedance matched transmission line driver LVTTL type circuits are also available with 25, 35, 45, and 55 Ohm output impedance. These buffers sacrifice direct current capabilities for matching positive and negative voltage and current waveforms.
driving capability are available in the library. a high degree of flexibility to the system designer. Figure 2. ND2 Core Cell 10 horizontal wiring channels using third metal. inverters as compared to previous technologies. some cases, the usage of the first metal layer. resulting in greater overall circuit density.
The following section details the elements which make up the CB35000 Series library. The elements are organized into three categories: 1. Macrocell library with Input, Output, Bidirectional Buffers including JTAG macrocells and Core cells. 2. Macrofunctions 3. Module generators. I/O BUFFERS CB35000 technology does not utilize a standard type I/O cell but is a leader in the emerging Sea of I/O approach to handling the chip interface problem. This approach starts at the bond pad area of the I/O where the pad size and pitch is not determined until the customers choice of packaging, signal interface standards and I/O count is considered. Wire bond pad spacings for 80 micron centres are available where large signal counts are most important. Pad spacing can be increased incrementally. It is expected that most designs will use 100 micron spacings or above. It is also possible to use different spacings for different width output sections when needed within the same device. Along with the variable bond pad spacing the I/O output transistor section does not have a fixed width. Previous technologies utilized a design approach where the desired full function buffer was designed for a maximum current taking one pad location with the usual current in the range of twenty four milliamps. The approach followed in CB35000 is to have identical twenty five micron wide output transistor slices stepped around the die. Each slice contains one set of protection diodes to the external power rails and eight P and eight N transistors. The transistors are specifically laid out and selectively non salicided for ESD protection and latch up prevention. These slices are paralleled to meet the current needs of the user, for example, to construct a 24mA sink and 12mA source LVTTL buffer, a number of slices would be used. The next group of devices that makes up the I/O circuits is again a 25u wide slice of specialized transistors that are utilized to form the slew rate control sections of the I/O. Each of these slices has circuits to control the switching of up two sections of P and N output transistors. These sections are of course created from the output transistor slice above the slew rate section and can be connected as desired by the designer. Many configurations of circuits can be created to supply the desired results with slew rate slices paralleled with multiple output sections. A further function of the I/O circuits is current spike suppression during switching of the I/O transistors. The logic utilized causes the conducting transistors to turn off before the opposing set of transistors turn on. Figure 3 IO Buffer Technology INPUT CONTROL SLEW RATE TRISTATE BUSKEEPER LEVEL SHIFTER PROGRAMMABLE PITCH BOND PADS DIE CORE GUARDRING EDGE OF DIE SEGMENTED OUTPUT RIVER OF DRIVE TRANSISTORS 4mA Selected
have an associated current handling capability. your local SGS-THOMSON design centre. operation, and 25 C temperature conditions. Table 4. A third factor, is associated with process Synthesis and HDL based design techniques.
shift register and adders. Macrofunctions are implemented at layout by utilizing macrocells and interconnecting to create the logic function. MODULE GENERATORS A series of module generators using compiled cell generation techniques, are available to support a range of megacells. These modules enable the designer to choose individual parameters in order to create a compiled cell, which meets the specific application requirements. These include single port RAM, dual port RAM, ROM and MULT. The compiled cell generators construct custom cells, which are implemented using a special leaf cell technique, ensuring predictable layout and accurate module characteristics. In choosing megacells the designer can consider the trade-offs between speed and area to generate a fully customized cell which meets their specific device requirements. These megacell generators are complemented by a group of application specific embedded megacells. These allow access to technologies that have been hitherto the domain of standard products. Examples include mixed mode cells for graphics, DAC/ADC’s (4-9 bit), PLL applications, and Digital Signal Processor functions for cellular comms, fax and high-speed modem.which initially consist of a Triple 8-bit DAC, Graphics RAM, Clock Multiplier PLL and Frequency Synthesis PLL. Table 5 Module Generator Library Cell Description SPRAM 256K bits max 16K word max 64 bit max Zero static current, Tristate outputs DPRAM 128K bits max 8K word max 64 bit max Zero static current, Tristate outputs ROM 2M bits max 32K word max 64 bit max Diffusion programmable, Tristate outputs MULT Parallel asynchronous operation 2’s complement product 6 to 64 bits for both inputs Ripple Carry or Fast Carry Look Ahead
100 Mbps serial transputer links coupled with
large and fast memory can be used for pipelining, caching and synchro circuits in modern RISC computing architectures. Viterbi and Reed Solomon cores aim at the HDTV and satellite transmission markets. To support telecom needs for CCITT standard applications, ADPCM cells supporting CT2 protocol have been developed. DESIGN FOR TESTABILITY The time and cost for ASIC testing increases exponentially as the complexity and size of the ASIC grows. Using a design for testability methodology allows large, more complex ASICs to be efficiently and economically tested. CB35000 supports the JTAG boundary Scan and both edge and level sensitive scan design techniques by providing the necessary macrocells. Scan testing aids device testability by permitting access to internal nodes without requiring a separate external connection for each node accessed. Testability is assured at device level with the close coupling of LSSD latch elements, Automatic Test Pattern Generation (ATPG) and high pattern depth tester architecture. BIST options for memory generators are also available. At system level, SGS-THOMSON fully supports IEEE 1149.1, and the I/O structure utilized in this family is completely compatible. Several types of
core scan cells are provided in the CB35000 Series library. Examples include FDxS/FJKxS cells which are edge sensitive and LSxx cells which are true LSSD cells. Non-overlapping clock generator macros are also available. EVALUATION DEVICE An evaluation device is used to demonstrate the performance of the CB35000 series as well as verify the effectiveness of the design system. The device has path delays, latches, a host of macrocells and memory functions which were Figure 5 Evaluation Device used to verify the simulated characteristics that are supplied in the data book. Characterization of the path delays including interconnect shows typical delays of 210 ps for a 2 input NAND with receivers/drivers operating at frequencies of 200 MHz. The evaluation device is available in a 208 pin plastic quad flat pack.
Ball Grid Array (BGA) packages are available from 160 to 500 pins and SBC types allow the pin count to reach the area of 1000 pins. Pin counts for through board mounting (PGA) range up to 480. The diversity in pin count and package style gives the designer the opportunity to find the best compromise for system size, cost and performance requirements. All packages for the military market are hermetically sealed to meet MIL-STD-883 Method. Prototypes are developed in ceramic packages for fast turnaround evaluation. ❍ Packages in Production ✮ Packages in Development NUMBER OF LEADS (Pins) PACKAGE NAME PQFP TQFP BGA PLCC CPGA POWER PQFP Slug/Spreader 20 ❍ 28 ❍ 44 ❍❍ 64 ❍❍ 68 ❍❍ 80 ❍❍ 84 ❍❍ 100 ❍❍ ❍ 120 ❍❍ ❍ 128 ❍❍ 144 ❍❍ ❍ ❍ 160 ❍❍ 176 ❍ 180 ❍ 208 ❍❍ ❍ 224 ❍ 225 ❍ 256 ❍ 257 ❍ 304 313 ✮✮ 400 ✮✮ 480 ✮✮ PACKAGE AVAILABILITY The CB35000 Series is designed to be compatible with QFP , BGA and SBC package types, in addition to the more traditional types found. The options include Plastic Leaded Chip Carriers (PLCC) from 28 to 84 pins, while the Metric Quad Flat Pack (xQFP) offering ranges up to 208 pins. Both high performance and high power variants are available as well as the TQFP thin types. Figure 6 Packaging Capability
Several interface levels are possible between SGS-THOMSON and the customer in the undertaking of an ASIC design. The four levels of interface are shown in Figure 7. Level 1 is characterized by SGS-THOMSON receiving the system specification and taking the design through to validation and fabrication. At level 2 interface the designer supplies a complete logic design implemented in a standard generic logic family. SGS-THOMSON then takes the design through to layout, validation and fabrication. Level 3 is the most common and preferred interface level. Logic capture and pre-layout INTERFACE LEVELS Figure 7 Customer/SGS-THOMSON Interface Levels SYSTEM SYSTEM SPECIFICATION LOGIC DESIGN SCHEMATIC CAPTURE DESIGN VERIFICATION PRE-LAYOUT SIMULATION LAYOUT POST-LAYOUT SIMULATION LEVEL 1 LEVEL 2 LEVEL 3 LEVEL 4 CUSTOMER CUSTOMER CUSTOMER CUSTOMER SGS-THOMSON SGS-THOMSON SGS-THOMSON SGS-THOMSON MANUFACTURE AND TEST ECR1 ECR2 simulation are performed by the designer using an SGS-THOMSON supported design kit. The design is then taken through layout, validation and fabrication by SGS-THOMSON. The SGS-THOMSON design system validates all designs before fabrication. Design kits are provided that allow schematic capture entry via Mentor Graphics and Cadence products. Simulation is supported for Cadence and Mentor Graphics. Full support is also provided for Cadence Verilog, Synopsys VSS and System Hilo simulators. Figure 8 shows the SGS- THOMSON Design Flow. Test vector development uses TSSI software from Summit and Currentest from CrossCheck.
Note 1. Referenced to Vss. Stresses above those listed under “absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended peri- ods may affect the device reliability. Note 1. Commercial, Industrial, and Military Conditions Note 2. Low Voltage TTL Circuits are NOT functional to specifications below 3.0 Volts Note 3. All circuits will operate to full specifications with a Vdd of 3.0V to 3.6V and a junction temperature of -40 to +125 degrees centi- grade. These junction temperatures are compatible with the Commercial and Industrial T emperature Ranges. Note 4. All circuits will be functional from -55 to +150 degrees centigrade junction temperature (military Ambient T emperature Range) but will not necessary operate to published specifications. Only circuits specified as operational to extended temperature range may be used when operating to Military temperature conditions. Note 1. Commercial, and Industrial Use Only -40 +85 degrees Centigrade Note 2. I/O Circuits Only takes Special External Power Distribution and May NOT be mixed with GTL or CTL circuits on any one side of the die. Only a very limited buffer set is available. Note 3. I/O Circuits Only takes Special External Power Distribution and May NOT be mixed with FVI or CTL circuits on any one side of the die. Only a very limited buffer set is available. Note 4. I /O Circuits Only takes Special External Power Distribution and May NOT be mixed with FVI or GTL circuits on any one side of the die. Only a very limited buffer set is available. Table 6 Absolute Maximum Ratings (note1) Supply Voltage, Vdd -0.5 V to +6.0 V Input or Output Voltage -0.5 V to (Vdd + 0.5V) DC Forward Bias Current, Input or Output -24mA source, +24mA sink Storage Temperature Ceramic -65 to 150 degrees Centigrade Storage Temperature Plastic -40 to 125 degrees Centigrade Table 7 Recommended DC Operating Conditions Normal Operating Supply Voltage Vdd (note 1) 3.3 V +/- 10% (3.0 V to 3.6 V) Operating Ambient Temperature Commercial (note 3) Industrial (note 3) Military (note 4) 0 to 70 degrees Centigrade -40 to +85 degrees Centigrade -55 to +125 degrees Centigrade Table 8 Special Voltages (Vcc) Operating Conditions FVI (Five Volt Interface) Supply Voltage (notes 1,2) 5.0V +/- 10% (4.5 V to 5.5 V) GTL (Gunning Transistor Logic) Supply Voltage (notes 1, 3) 1.2V +/- 5% (1.14 V to 1.26 V) CTT (Center Tap Terminated) Supply Voltage (notes 1,4) 1.5V +/- 10% (1.35 V to 1.65 V)
Note 1. These are normal Voltage and extended temperature specifications Vdd from 3.0 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Note 2. Adherence to rules in Power Pin / Pad Specifications Required Note 3. Refer to the CB35000 Standard Cell Specification for full Testing Levels and Conditions Note 4. Buffers offered in 2, 4, 8, 12, 16, and 24 mA TTL options Note 1. These are extended voltage and temperature specifications Vdd from 2.7 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Note 2. Adherence to rules in Power Pin / Pad Specifications Required Note 3. Refer to the CB35000 Standard Cell Specification for full Testing Levels and Conditions Note 4. Buffers offered in 2, 4, and 8 mA CMOS options Note 5. Note only one CMOS buffer may sink or source DC current when parametric measurements are taken due to the reason that the power supply specifications for CMOS product are not written to support DC current. If more than one buffer is active voltage drops in the supply may cause false failure readings. Note 6. If no buffers are sinking or sourcing current and all internal pull up or pull down resistors in bidi buffers have been disabled by having the T2 Test Pin positive Vol (max) = 0.05 Volts and Voh (min)=Vdd-0.05 Volts Table 9 LVTTL Interface DC Electrical Characteristics (Note 1) Symbol Parameter Conditions Min Typ Max Unit Notes Vil Low Level Input Voltage 0.8 Volts 2,3 Vih High Level Input Voltage 2.0 Volts 2,3 Vol Low Level Output Voltage Iol = Rated Buffer Current 0.2 0.4 Volts 2,3,4 Voh High Level Output Voltage Ioh = Rated Buffer Current 2.4 3.0 Volts 2,3,4 Vt + Schmitt Trigger +Ve Threshold 1.7 1.9 Volts 2,3 Vt - Schmitt Trigger -Ve Threshold 0.9 1.1 Volts 2,3 Table 10 LVCMOS Interface DC Electrical Characteristics (Note 1) Symbol Parameter Conditions Min Typ Max Unit Notes Vil Low Level Input Voltage 0.2xVdd Volts 2,3,4 Vih High Level Input Voltage 0.8 x Vdd Volts 2,3,4 Vol Low Level Output Voltage Iol = Rated Buffer Current Voh High Level Output Voltage Ioh = Rated Buffer Current 0.85 x Vdd 0.9 x Vdd Volts 2,3,4,5,6 Vt + Schmitt Trigger +Ve Threshold 1.7 1.9 Volts 2,3 Vt - Schmitt Trigger -Ve Threshold 0.9 1.1 Volts 2,3
Note 1. These are extended voltage and temperature specifications Vdd from 2.7 V to 3.6 V Temperature Ambient from -55 to 125 degrees Centigrade Note 2. Adherence to rules in Power Pin / Pad Specifications Required Note 3. Excluding Package Note 4. At 0.0 Volts Note 5. Human Body Model Table 11 General Interface DC Electrical Characteristics (Note 1) Symbol Parameter Conditions Min Typ Max Unit Notes Iil Low Level Input Current Vi =Vss +/-10 uA 2 Iih High Level Input Current Vi = Vdd +/-10 uA 2 Ioz Tri-State Output Leakage Vo=0V or Vdd +/-10 uA 2 Cin Input Capacitance Freq=1MHz 2.0 4.0 pF 3,4 Co Output Capacitance Freq=1MHz 4.0 pF 3,4 Cio Bidi, I/O Capacitance Freq=1MHz 0.9 1.1 pF 3,4 Iklu I/O Latch Up Current V<Vss, V>Vdd 200 500 mA Vesd Electrostatic Protection HBM 2000 4000 V 5
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