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SN74AXC8T245-Q1 Automotive 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs REVISED OCTOBER 2021

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SN74AXC8T245-Q1 Automotive 8-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs

1 Features

AEC-Q100 qualified for automotive applications
Available in wettable flank QFN (WRGY) package
Qualified fully configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
Operating temperature from –40°C to +125°C
Multiple direction-control pins to allow simultaneous up and down translation
Up to 380 Mbps support when translating from 1.8 V to 3.3 V
VCC isolation feature to effectively Isolate both bses in a power-down scenario
Partial power-down mode to limit backflow current in a power-down scenario
Compatible with SN74AVC8T245-Q1 level shifter
Latch-up performance exceeds 100 mA per JESD 78, class II

2 Applications

Infotainment head unit
ADAS fusion
ADAS front camera
HEV battery management system

3 Description

The SN74AXC8T245-Q1 AEC-Q100 qualified device is an 8-bit non-inverting bus transceiver that resolves voltage level mismatch between devices operating at the latest voltage nodes (0.7 V, 0.8 V, and 0.9 V) and devices operating at industry standard voltage nodes (1.8 V, 2.5 V, and 3.3 V) and vice versa. The device operates by using two independent power- supply rails (V CCA and V CCB) that operate as low as 0.65 V. Data pins A1 through A8 are designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. Data pins B1 through B8 are designed to track V CCB, which accepts any supply voltage from 0.65 V to 3.6 V. The SN74AXC8T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIR1 and DIR2). The output-enable ( OE) input is used to disable the outputs so the buses are effectively isolated. The SN74AXC8T245-Q1 device is designed so the control pins (DIR and OE) are referenced to VCCA. This device is fully specified for partial-power-down applications using I off. The I off circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device. The V CC isolation feature ensures that if either V CC input supply is below 100 mV, all level shifter outputs are disabled and placed into a high-impedance state. To ensure the high-impedance state of the level shifter I/Os during power up or power down, OE should be tied to V CCA through a pullup resistor; the minimum value of the resistor is determined by the current- sinking capability of the driver. Device Information PART NUMBER(1) PACKAGE BODY SIZE (NOM) SN74AXC8T245PW-Q1 TSSOP (24) 4.40 mm × 7.80 mm SN74AXC8T245RHL-Q1 VQFN (24) 3.50 mm × 5.50 mm SN74AXC8T245WRGY-Q1 VQFN (24) 3.50 mm × 5.50 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Processor Interrupts Control Block SN74AXC8T245-Q1 Sensor Block Power Management Register Map 1.5 V DIR1 DIR2VCCA VCCB Data Block GND GND 3.3 V Typical Application Schematic SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..26

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May 2021) to Revision C (October 2021) Page Changes from Revision A (July 2019) to Revision B (May 2021) Page Changes from Revision * (November 2018) to Revision A (July 2019) Page SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. PW Package 24-Pin TSSOP Top View 2DIR1 DIR2 GND GND VCCA VCCB VCCB OE PAD PAD — may be grounded (recommended) or left floating. Figure 5-2. RHL and WRGY Package 24-Pin VQFN Top View Table 5-1. Pin Functions PIN I/O DESCRIPTION NAME PW, RHL, WRGY A1 3 I/O Input/output A1. Referenced to VCCA. A2 4 I/O Input/output A2. Referenced to VCCA. A3 5 I/O Input/output A3. Referenced to VCCA. A4 6 I/O Input/output A4. Referenced to VCCA. A5 7 I/O Input/output A5. Referenced to VCCA. A6 8 I/O Input/output A6. Referenced to VCCA. A7 9 I/O Input/output A7. Referenced to VCCA. A8 10 I/O Input/output A8. Referenced to VCCA. B1 21 I/O Input/output B1. Referenced to VCCB. B2 20 I/O Input/output B2. Referenced to VCCB. B3 19 I/O Input/output B3. Referenced to VCCB. B4 18 I/O Input/output B4. Referenced to VCCB. B5 17 I/O Input/output B5. Referenced to VCCB. B6 16 I/O Input/output B6. Referenced to VCCB. B7 15 I/O Input/output B7. Referenced to VCCB. B8 14 I/O Input/output B8. Referenced to VCCB. DIR1 2 I Direction-control signal 1. Referenced to VCCA. Refer to Table 8-1. DIR2 11 I Direction-control signal 2. Refer to Table 8-1. Referenced to VCCA. Tie to GND to maintain backward compatibility with SN74AVC8T245- Q1 device. GND 12 — Ground 13 — Ground OE 22 I Output Enable. Pull to GND to enable all outputs. Pull to VCCA to place all outputs in high-impedance mode. Referenced to VCCA. Refer to Table 8-1. VCCA 1 — A-port supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V VCCB 23 — B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V 24 — B-port supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74AXC8T245-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT Supply voltage, VCCA –0.5 4.2 V Supply voltage, VCCB –0.5 4.2 V Input voltage, VI (2) I/O ports (A port) –0.5 4.2 VI/O ports (B port) –0.5 4.2 Control inputs –0.5 4.2 Voltage applied to any output in the high-impedance or power-off state, VO (2) A port –0.5 4.2 V B port –0.5 4.2 Voltage applied to any output in the high or low state, VO (2) (3) A port –0.5 VCCA + 0.2 V B port –0.5 VCCB + 0.2 Input clamp current, IIK VI < 0 –50 mA Output clamp current, IOK VO < 0 –50 mA Continuous output current, IO –50 50 mA Continuous current through VCCA, VCCB, or GND –100 100 mA Junction Temperature, TJ 150 °C Storage temperature, Tstg –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Section 6.3. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±8000 V Charged-device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1) (2) (3) MIN MAX UNIT VCCA Supply voltage 0.65 3.6 V VCCB Supply voltage 0.65 3.6 V VIH High-level input voltage Data inputs VCCI = 0.65 V - 0.75 V VCCI × 0.70 V VCCI = 0.76 V - 1 V VCCI × 0.70 VCCI = 1.1 V - 1.95 V VCCI × 0.65 VCCI = 2.3 V - 2.7 V 1.6 VCCI = 3 V - 3.6 V 2 Control inputs (DIR, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA × 0.70 VCCA = 0.76 V - 1 V VCCA × 0.70 VCCA = 1.1 V - 1.95 V VCCA × 0.65 VCCA = 2.3 V - 2.7 V 1.6 VCCA = 3 V - 3.6 V 2 VIL Low-level input voltage Data inputs VCCI = 0.65 V - 0.75 V VCCI × 0.30 V VCCI = 0.76 V - 1 V VCCI × 0.30 VCCI = 1.1 V - 1.95 V VCCI × 0.35 VCCI = 2.3 V - 2.7 V 0.7 VCCI = 3 V - 3.6 V 0.8 Control inputs (DIR, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA × 0.30 VCCA = 0.76 V - 1 V VCCA × 0.30 VCCA = 1.1 V - 1.95 V VCCA × 0.35 VCCA = 2.3 V - 2.7 V 0.7 VCCA = 3 V - 3.6 V 0.8 VI Input voltage(3) 0 3.6 V VO Output voltage Active state 0 VCCO (2) V Tri-state 0 3.6 Δt/Δv Input transition rise or fall rate 10 ns/V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. See the Implications of Slow or Floating CMOS Inputs application report.

6.4 Thermal Information

THERMAL METRIC(1) SN74AXC8T245-Q1 UNITPW (TSSOP) RHL (VQFN) WRGY (VQFN)

24 PINS 24 PINS 24 PINS

RθJA Junction-to-ambient thermal resistance 92.0 35.0 48.1 °C/W RθJC(top) Junction-to-case (top) thermal resistance 29.3 39.9 43.2 °C/W RθJB Junction-to-board thermal resistance 46.7 13.8 26.1 °C/W ψJT Junction-to-top characterization parameter 1.5 0.3 2.9 °C/W ψJB Junction-to-board characterization parameter 46.2 13.8 26.0 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A 1.4 15.8 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74AXC8T245-Q1

6.5 Electrical Characteristics

Over recommended operating free-air temperature range (unless otherwise noted)(1) (2) PARAMETER TEST CONDITIONS VCCA VCCB –40°C to 85°C –40°C to 125°C UNIT MIN TYP(4) MAX MIN TYP(4) MAX VOH High-level output voltage VI = VIH V IOH = –50 µA 0.65 V 0.65 V 0.55 0.55 IOH = –200 µA 0.76 V 0.76 V 0.58 0.58 IOH = –500 µA 0.85 V 0.85 V 0.65 0.65 IOH = -3 mA 1.1 V 1.1 V 0.85 0.85 IOH = -6 mA 1.4 V 1.4 V 1.05 1.05 IOH = -8 mA 1.65 V 1.65 V 1.2 1.2 IOH = -9 mA 2.3 V 2.3 V 1.75 1.75 IOH = -12 mA 3 V 3 V 2.3 2.3 VOL Low-level output voltage VI = VIL V IOL = 50 µA 0.65 V 0.65 V 0.1 0.1 IOL = 200 µA 0.76 V 0.76 V 0.18 0.18 IOL = 500 µA 0.85 V 0.85 V 0.2 0.2 IOL = 3 mA 1.1 V 1.1 V 0.25 0.25 IOL = 6 mA 1.4 V 1.4 V 0.35 0.35 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 0.55 IOL = 12 mA 3 V 3 V 0.7 0.7 II Input leakage current Control Inputs (DIR, OE): Ioff Partial power down current A Port: VI or VO = 0 V - 3.6 V 0 V 0 V - 3.6 V -8 8 -12 12 µA B Port: VI or VO = 0 V - 3.6 V 0 V - 3.6 V 0 V -8 8 -12 12 IOZ (3) High- impedance state output current A Port: VO = VCCO or GND, VI = VCCI or GND, OE = VIH 3.6 V 3.6 V -8 8 -12 12 µA B Port: VO = VCCO or GND, VI = VCCI or GND, OE = VIH 3.6 V 3.6 V -8 8 -12 12 ICCA VCCA supply current VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 20 40 µA0 V 3.6 V -2 -12

3.6 V 0 V 12 25

current VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 20 40 µA0 V 3.6 V 12 25

3.6 V 0 V -2 -12

VI = VCCI or GND, IO = 0 mA 0.65 V - 3.6 V 0.65 V - 3.6 V 30 60 µA Ci Input capacitance Control Inputs (DIR, OE): Cio Data I/O capacitance Ports A and B: OE = VCCA, VO = 1.65V DC +

1 MHz -16 dBm sine wave

3.3 V 3.3 V 5.7 5.7 pF (1) VCCO is the VCC associated with the output port. (2) VCCI is the VCC associated with the input port. (3) For I/O ports, the parameter IOZ includes the input leakage current. (4) All typical values are for TA = 25°C SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.6 Switching Characteristics, VCCA = 0.7 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 172 0.5 114 0.5 82 0.5 49 ns –40°C to 125°C 0.5 172 0.5 114 0.5 82 0.5 49 From input B to output A –40°C to 85°C 0.5 172 0.5 153 0.5 126 0.5 88 –40°C to 125°C 0.5 172 0.5 153 0.5 126 0.5 88 tdis Disable time From input OE to output A –40°C to 85°C 0.5 192 0.5 192 0.5 192 0.5 192 ns –40°C to 125°C 0.5 195 0.5 195 0.5 195 0.5 195 From input OE to output B –40°C to 85°C 0.5 156 0.5 129 0.5 118 0.5 120 –40°C to 125°C 0.5 157 0.5 129 0.5 120 0.5 122 ten Enable time From input OE to output A –40°C to 85°C 0.5 237 0.5 237 0.5 237 0.5 237 ns –40°C to 125°C 0.5 237 0.5 237 0.5 237 0.5 237 From input OE to output B –40°C to 85°C 0.5 223 0.5 145 0.5 106 0.5 74 –40°C to 125°C 0.5 223 0.5 145 0.5 106 0.5 74 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 46 0.5 49 0.5 61 0.5 142 ns –40°C to 125°C 0.5 46 0.5 49 0.5 61 0.5 142 From input B to output A –40°C to 85°C 0.5 83 0.5 82 0.5 81 0.5 81 –40°C to 125°C 0.5 83 0.5 82 0.5 81 0.5 81 tdis Disable time From input OE to output A –40°C to 85°C 0.5 192 0.5 192 0.5 192 0.5 192 ns –40°C to 125°C 0.5 195 0.5 195 0.5 195 0.5 195 From input OE to output B –40°C to 85°C 0.5 69 0.5 66 0.5 67 0.5 150 –40°C to 125°C 0.5 70 0.5 67 0.5 67 0.5 150 ten Enable time From input OE to output A –40°C to 85°C 0.5 237 0.5 237 0.5 237 0.5 237 ns –40°C to 125°C 0.5 237 0.5 237 0.5 237 0.5 237 From input OE to output B –40°C to 85°C 0.5 68 0.5 69 0.5 84 0.5 552 –40°C to 125°C 0.5 68 0.5 69 0.5 84 0.5 552 www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74AXC8T245-Q1

6.7 Switching Characteristics, VCCA = 0.8 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 153 0.5 95 0.5 62 0.5 32 ns –40°C to 125°C 0.5 153 0.5 95 0.5 62 0.5 32 From input B to output A –40°C to 85°C 0.5 114 0.5 95 0.5 78 0.5 52 –40°C to 125°C 0.5 114 0.5 95 0.5 78 0.5 52 tdis Disable time From input OE to output A –40°C to 85°C 0.5 101 0.5 101 0.5 101 0.5 101 ns –40°C to 125°C 0.5 103 0.5 103 0.5 103 0.5 103 From input OE to output B –40°C to 85°C 0.5 141 0.5 114 0.5 104 0.5 106 –40°C to 125°C 0.5 142 0.5 115 0.5 106 0.5 109 ten Enable time From input OE to output A –40°C to 85°C 0.5 102 0.5 102 0.5 102 0.5 102 ns –40°C to 125°C 0.5 102 0.5 102 0.5 102 0.5 102 From input OE to output B –40°C to 85°C 0.5 202 0.5 124 0.5 86 0.5 52 –40°C to 125°C 0.5 202 0.5 124 0.5 86 0.5 52 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 26 0.5 25 0.5 25 0.5 35 ns –40°C to 125°C 0.5 26 0.5 25 0.5 25 0.5 35 From input B to output A –40°C to 85°C 0.5 42 0.5 41 0.5 40 0.5 40 –40°C to 125°C 0.5 42 0.5 41 0.5 40 0.5 40 tdis Disable time From input OE to output A –40°C to 85°C 0.5 101 0.5 101 0.5 101 0.5 101 ns –40°C to 125°C 0.5 103 0.5 103 0.5 103 0.5 103 From input OE to output B –40°C to 85°C 0.5 55 0.5 51 0.5 49 0.5 51 –40°C to 125°C 0.5 57 0.5 53 0.5 50 0.5 52 ten Enable time From input OE to output A –40°C to 85°C 0.5 102 0.5 102 0.5 102 0.5 102 ns –40°C to 125°C 0.5 102 0.5 102 0.5 102 0.5 102 From input OE to output B –40°C to 85°C 0.5 44 0.5 43 0.5 45 0.5 58 –40°C to 125°C 0.5 44 0.5 43 0.5 45 0.5 58 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.8 Switching Characteristics, VCCA = 0.9 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 127 0.5 78 0.5 52 0.5 23 ns –40°C to 125°C 0.5 127 0.5 78 0.5 52 0.5 23 From input B to output A –40°C to 85°C 0.5 82 0.5 63 0.5 52 0.5 39 –40°C to 125°C 0.5 82 0.5 63 0.5 52 0.5 39 tdis Disable time From input OE to output A –40°C to 85°C 0.5 125 0.5 125 0.5 125 0.5 125 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 From input OE to output B –40°C to 85°C 0.5 131 0.5 105 0.5 96 0.5 99 –40°C to 125°C 0.5 133 0.5 107 0.5 98 0.5 101 ten Enable time From input OE to output A –40°C to 85°C 0.5 124 0.5 124 0.5 124 0.5 124 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 From input OE to output B –40°C to 85°C 0.5 191 0.5 113 0.5 75 0.5 41 –40°C to 125°C 0.5 191 0.5 113 0.5 75 0.5 41 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 17 0.5 15 0.5 14 0.5 17 ns –40°C to 125°C 0.5 17 0.5 15 0.5 14 0.5 17 From input B to output A –40°C to 85°C 0.5 28 0.5 24 0.5 22 0.5 22 –40°C to 125°C 0.5 28 0.5 24 0.5 22 0.5 22 tdis Disable time From input OE to output A –40°C to 85°C 0.5 125 0.5 125 0.5 125 0.5 125 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 From input OE to output B –40°C to 85°C 0.5 47 0.5 44 0.5 40 0.5 73 –40°C to 125°C 0.5 50 0.5 46 0.5 42 0.5 73 ten Enable time From input OE to output A –40°C to 85°C 0.5 124 0.5 124 0.5 124 0.5 124 ns –40°C to 125°C 0.5 128 0.5 128 0.5 128 0.5 128 From input OE to output B –40°C to 85°C 0.5 34 0.5 32 0.5 31 0.5 35 –40°C to 125°C 0.5 34 0.5 32 0.5 31 0.5 35 www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74AXC8T245-Q1

6.9 Switching Characteristics, VCCA = 1.2 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 88 0.5 52 0.5 39 0.5 15 ns –40°C to 125°C 0.5 88 0.5 52 0.5 39 0.5 15 From input B to output A –40°C to 85°C 0.5 49 0.5 32 0.5 23 0.5 15 –40°C to 125°C 0.5 49 0.5 32 0.5 23 0.5 15 tdis Disable time From input OE to output A –40°C to 85°C 0.5 87 0.5 87 0.5 87 0.5 87 ns –40°C to 125°C 0.5 91 0.5 91 0.5 91 0.5 91 From input OE to output B –40°C to 85°C 0.5 119 0.5 94 0.5 85 0.5 89 –40°C to 125°C 0.5 121 0.5 96 0.5 88 0.5 93 ten Enable time From input OE to output A –40°C to 85°C 0.5 34 0.5 34 0.5 34 0.5 34 ns –40°C to 125°C 0.5 36 0.5 36 0.5 36 0.5 36 From input OE to output B –40°C to 85°C 0.5 168 0.5 98 0.5 61 0.5 29 –40°C to 125°C 0.5 168 0.5 98 0.5 61 0.5 30 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 10 0.5 9 0.5 7 0.5 7 ns –40°C to 125°C 0.5 10 0.5 9 0.5 7 0.5 8 From input B to output A –40°C to 85°C 0.5 13 0.5 11 0.5 8 0.5 7 –40°C to 125°C 0.5 13 0.5 11 0.5 8 0.5 7 tdis Disable time From input OE to output A –40°C to 85°C 0.5 87 0.5 87 0.5 87 0.5 87 ns –40°C to 125°C 0.5 91 0.5 91 0.5 91 0.5 91 From input OE to output B –40°C to 85°C 0.5 38 0.5 35 0.5 31 0.5 29 –40°C to 125°C 0.5 41 0.5 38 0.5 33 0.5 31 ten Enable time From input OE to output A –40°C to 85°C 0.5 34 0.5 34 0.5 34 0.5 34 ns –40°C to 125°C 0.5 36 0.5 36 0.5 36 0.5 36 From input OE to output B –40°C to 85°C 0.5 22 0.5 19 0.5 17 0.5 17 –40°C to 125°C 0.5 23 0.5 20 0.5 18 0.5 18 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.10 Switching Characteristics, VCCA = 1.5 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 84 0.5 42 0.5 28 0.5 13 ns –40°C to 125°C 0.5 84 0.5 42 0.5 28 0.5 13 From input B to output A –40°C to 85°C 0.5 46 0.5 26 0.5 17 0.5 10 –40°C to 125°C 0.5 46 0.5 26 0.5 17 0.5 10 tdis Disable time From input OE to output A –40°C to 85°C 0.5 34 0.5 34 0.5 34 0.5 34 ns –40°C to 125°C 0.5 37 0.5 37 0.5 37 0.5 37 From input OE to output B –40°C to 85°C 0.5 115 0.5 89 0.5 80 0.5 85 –40°C to 125°C 0.5 117 0.5 91 0.5 83 0.5 89 ten Enable time From input OE to output A –40°C to 85°C 0.5 21 0.5 21 0.5 21 0.5 21 ns –40°C to 125°C 0.5 23 0.5 23 0.5 23 0.5 23 From input OE to output B –40°C to 85°C 0.5 159 0.5 90 0.5 55 0.5 24 –40°C to 125°C 0.5 159 0.5 90 0.5 55 0.5 25 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 9 0.5 7 0.5 6 0.5 5 ns –40°C to 125°C 0.5 9 0.5 7 0.5 6 0.5 6 From input B to output A –40°C to 85°C 0.5 9 0.5 7 0.5 6 0.5 5 –40°C to 125°C 0.5 9 0.5 8 0.5 6 0.5 5 tdis Disable time From input OE to output A –40°C to 85°C 0.5 34 0.5 34 0.5 34 0.5 34 ns –40°C to 125°C 0.5 37 0.5 37 0.5 37 0.5 37 From input OE to output B –40°C to 85°C 0.5 35 0.5 31 0.5 28 0.5 25 –40°C to 125°C 0.5 38 0.5 34 0.5 31 0.5 27 ten Enable time From input OE to output A –40°C to 85°C 0.5 21 0.5 21 0.5 21 0.5 21 ns –40°C to 125°C 0.5 23 0.5 23 0.5 23 0.5 23 From input OE to output B –40°C to 85°C 0.5 17 0.5 15 0.5 12 0.5 11 –40°C to 125°C 0.5 18 0.5 15 0.5 13 0.5 12 www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74AXC8T245-Q1

6.11 Switching Characteristics, VCCA = 1.8 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 82 0.5 41 0.5 24 0.5 11 ns –40°C to 125°C 0.5 82 0.5 41 0.5 24 0.5 11 From input B to output A –40°C to 85°C 0.5 49 0.5 25 0.5 15 0.5 9 –40°C to 125°C 0.5 49 0.5 25 0.5 15 0.5 9 tdis Disable time From input OE to output A –40°C to 85°C 0.5 37 0.5 37 0.5 37 0.5 37 ns –40°C to 125°C 0.5 40 0.5 40 0.5 40 0.5 40 From input OE to output B –40°C to 85°C 0.5 113 0.5 87 0.5 78 0.5 83 –40°C to 125°C 0.5 115 0.5 89 0.5 81 0.5 87 ten Enable time From input OE to output A –40°C to 85°C 0.5 17 0.5 17 0.5 17 0.5 17 ns –40°C to 125°C 0.5 19 0.5 19 0.5 19 0.5 19 From input OE to output B –40°C to 85°C 0.5 157 0.5 88 0.5 54 0.5 23 –40°C to 125°C 0.5 157 0.5 88 0.5 54 0.5 23 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 8 0.5 6 0.5 5 0.5 5 ns –40°C to 125°C 0.5 8 0.5 7 0.5 6 0.5 5 From input B to output A –40°C to 85°C 0.5 7 0.5 6 0.5 5 0.5 4 –40°C to 125°C 0.5 7 0.5 7 0.5 5 0.5 4 tdis Disable time From input OE to output A –40°C to 85°C 0.5 37 0.5 37 0.5 37 0.5 37 ns –40°C to 125°C 0.5 40 0.5 40 0.5 40 0.5 40 From input OE to output B –40°C to 85°C 0.5 33 0.5 30 0.5 27 0.5 57 –40°C to 125°C 0.5 36 0.5 33 0.5 29 0.5 60 ten Enable time From input OE to output A –40°C to 85°C 0.5 17 0.5 17 0.5 17 0.5 17 ns –40°C to 125°C 0.5 19 0.5 19 0.5 19 0.5 19 From input OE to output B –40°C to 85°C 0.5 15 0.5 13 0.5 10 0.5 9 –40°C to 125°C 0.5 16 0.5 14 0.5 11 0.5 10 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.12 Switching Characteristics, VCCA = 2.5 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 81 0.5 40 0.5 22 0.5 8 ns –40°C to 125°C 0.5 81 0.5 40 0.5 22 0.5 8 From input B to output A –40°C to 85°C 0.5 61 0.5 25 0.5 14 0.5 7 –40°C to 125°C 0.5 61 0.5 25 0.5 14 0.5 7 tdis Disable time From input OE to output A –40°C to 85°C 0.5 25 0.5 25 0.5 25 0.5 25 ns –40°C to 125°C 0.5 28 0.5 28 0.5 28 0.5 28 From input OE to output B –40°C to 85°C 0.5 111 0.5 85 0.5 76 0.5 81 –40°C to 125°C 0.5 113 0.5 87 0.5 78 0.5 84 ten Enable time From input OE to output A –40°C to 85°C 0.5 11 0.5 11 0.5 11 0.5 11 ns –40°C to 125°C 0.5 12 0.5 12 0.5 12 0.5 12 From input OE to output B –40°C to 85°C 0.5 155 0.5 86 0.5 52 0.5 21 –40°C to 125°C 0.5 155 0.5 86 0.5 52 0.5 21 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 6 0.5 5 0.5 4 0.5 4 ns –40°C to 125°C 0.5 6 0.5 5 0.5 5 0.5 4 From input B to output A –40°C to 85°C 0.5 6 0.5 5 0.5 4 0.5 4 –40°C to 125°C 0.5 6 0.5 5 0.5 5 0.5 4 tdis Disable time From input OE to output A –40°C to 85°C 0.5 25 0.5 25 0.5 25 0.5 25 ns –40°C to 125°C 0.5 28 0.5 28 0.5 28 0.5 28 From input OE to output B –40°C to 85°C 0.5 31 0.5 28 0.5 25 0.5 23 –40°C to 125°C 0.5 34 0.5 31 0.5 28 0.5 25 ten Enable time From input OE to output A –40°C to 85°C 0.5 11 0.5 11 0.5 11 0.5 11 ns –40°C to 125°C 0.5 12 0.5 12 0.5 12 0.5 12 From input OE to output B –40°C to 85°C 0.5 14 0.5 11 0.5 9 0.5 7 –40°C to 125°C 0.5 14 0.5 12 0.5 9 0.5 8 www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74AXC8T245-Q1

6.13 Switching Characteristics, VCCA = 3.3 V See Figure 7-1 and Figure 7-2 for test circuit and loading conditions. See Figure 7-3 and Figure 7-4 for measurement waveforms. PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 81 0.5 40 0.5 22 0.5 7 ns –40°C to 125°C 0.5 81 0.5 40 0.5 22 0.5 7 From input B to output A –40°C to 85°C 0.5 142 0.5 35 0.5 17 0.5 7 –40°C to 125°C 0.5 142 0.5 35 0.5 17 0.5 8 tdis Disable time From input OE to output A –40°C to 85°C 0.5 22 0.5 22 0.5 22 0.5 22 ns –40°C to 125°C 0.5 24 0.5 24 0.5 24 0.5 24 From input OE to output B –40°C to 85°C 0.5 111 0.5 84 0.5 75 0.5 80 –40°C to 125°C 0.5 113 0.5 86 0.5 78 0.5 83 ten Enable time From input OE to output A –40°C to 85°C 0.5 9 0.5 9 0.5 9 0.5 9 ns –40°C to 125°C 0.5 10 0.5 10 0.5 10 0.5 10 From input OE to output B –40°C to 85°C 0.5 154 0.5 86 0.5 51 0.5 20 –40°C to 125°C 0.5 154 0.5 86 0.5 51 0.5 20 PARAMETER TEST CONDITIONS B-PORT SUPPLY VOLTAGE (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay From input A to output B –40°C to 85°C 0.5 5 0.5 4 0.5 4 0.5 4 ns –40°C to 125°C 0.5 5 0.5 4 0.5 4 0.5 4 From input B to output A –40°C to 85°C 0.5 5 0.5 5 0.5 4 0.5 4 –40°C to 125°C 0.5 6 0.5 5 0.5 4 0.5 4 tdis Disable time From input OE to output A –40°C to 85°C 0.5 22 0.5 22 0.5 22 0.5 22 ns –40°C to 125°C 0.5 24 0.5 24 0.5 24 0.5 24 From input OE to output B –40°C to 85°C 0.5 30 0.5 27 0.5 25 0.5 23 –40°C to 125°C 0.5 33 0.5 30 0.5 27 0.5 25 ten Enable time From input OE to output A –40°C to 85°C 0.5 9 0.5 9 0.5 9 0.5 9 ns –40°C to 125°C 0.5 10 0.5 10 0.5 10 0.5 10 From input OE to output B –40°C to 85°C 0.5 13 0.5 10 0.5 8 0.5 7 –40°C to 125°C 0.5 14 0.5 11 0.5 8 0.5 7 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.14 Operating Characteristics: TA = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CpdA Power dissipation capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.2 pF VCCA = VCCB = 0.8 V 1.8 VCCA = VCCB = 0.9 V 1.8 VCCA = VCCB = 1.2 V 1.7 VCCA = VCCB = 1.5 V 1.7 VCCA = VCCB = 1.8 V 1.7 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2.5 CpdA Power dissipation capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.1 pF VCCA = VCCB = 0.8 V 1.8 VCCA = VCCB = 0.9 V 1.8 VCCA = VCCB = 1.2 V 1.7 VCCA = VCCB = 1.5 V 1.7 VCCA = VCCB = 1.8 V 1.7 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2.1 CpdA Power dissipation capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 9.3 pF VCCA = VCCB = 0.8 V 11.8 VCCA = VCCB = 0.9 V 11.8 VCCA = VCCB = 1.2 V 12 VCCA = VCCB = 1.5 V 12.2 VCCA = VCCB = 1.8 V 13 VCCA = VCCB = 2.5 V 16.4 VCCA = VCCB = 3.3 V 18.1 CpdA Power dissipation capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 2.6 pF VCCA = VCCB = 0.8 V 1.2 VCCA = VCCB = 0.9 V 1.1 VCCA = VCCB = 1.2 V 1.2 VCCA = VCCB = 1.5 V 1.2 VCCA = VCCB = 1.8 V 1.3 VCCA = VCCB = 2.5 V 1.6 VCCA = VCCB = 3.3 V 3.9 www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74AXC8T245-Q1

6.14 Operating Characteristics: TA = 25°C (continued)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CpdB Power dissipation capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 9.3 pF VCCA = VCCB = 0.8 V 11.7 VCCA = VCCB = 0.9 V 11.8 VCCA = VCCB = 1.2 V 11.9 VCCA = VCCB = 1.5 V 12.2 VCCA = VCCB = 1.8 V 12.9 VCCA = VCCB = 2.5 V 16.3 VCCA = VCCB = 3.3 V 18 CpdB Power dissipation capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 2.6 VCCA = VCCB = 0.8 V 11.7 pF VCCA = VCCB = 0.9 V 11.8 VCCA = VCCB = 1.2 V 11.9 VCCA = VCCB = 1.5 V 12.2 VCCA = VCCB = 1.8 V 12.9 VCCA = VCCB = 2.5 V 16.3 VCCA = VCCB = 3.3 V 3.9 CpdB Power dissipation capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.2 pF VCCA = VCCB = 0.8 V 1.8 VCCA = VCCB = 0.9 V 1.8 VCCA = VCCB = 1.2 V 1.7 VCCA = VCCB = 1.5 V 1.7 VCCA = VCCB = 1.8 V 1.7 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2.5 CpdB Power dissipation capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns VCCA = VCCB = 0.7 V 1.1 VCCA = VCCB = 0.8 V 1.8 pF VCCA = VCCB = 0.9 V 1.8 VCCA = VCCB = 1.2 V 1.7 VCCA = VCCB = 1.5 V 1.7 VCCA = VCCB = 1.8 V 1.7 VCCA = VCCB = 2.5 V 2 VCCA = VCCB = 3.3 V 2.1 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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6.15 Typical Characteristics

IOH (mA) VOH (V) 0 2 4 6 8 10 12 14 16 18 20 1.4 1.6 1.8 2.2 2.4 2.6 2.8 3.2 3.4 D001 VCC = 1.8V VCC = 2.5V VCC = 3.3V Figure 6-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOH (mA) VOH (V) 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.05 1.1 1.15 1.2 1.25 D001 VCC = 0.7V VCC = 1.2V Figure 6-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOL (mA) VOL (mV) 0 2 4 6 8 10 12 14 16 18 20 -50 100 150 200 250 300 350 400 450 500 550 600 650 700 D001 VCC = 1.8V VCC = 2.5V VCC = 3.3V Figure 6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) IOL (mA) VOL (mV) 100 120 140 160 180 200 220 D001 VCC = 0.7V VCC = 1.2V Figure 6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74AXC8T245-Q1

7 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

f =1 MHz
Z0 = 50 Ω
dv / dt ≤ 1 ns/V Output Pin Under Test CL (1) RL RL GND Open

2 X VCCO

A. CL includes probe and jig capacitance. Figure 7-1. Load Circuit Parameter S1 1.1 V - 3.6 V 2 k 15 pF Open N/A 0.65 V - 0.95 V 20 k 15 pF Open N/A 3 V - 3.6 V 2 k 15 pF 0.3 V 1.65 V - 2.7 V 2 k 15 pF 0.15 V 1.1 V - 1.6 V 2 k 15 pF 0.1 V 0.65 V - 0.95 V 20 k 15 pF 0.1 V 3 V - 3.6 V 2 k 15 pF GND 0.3 V 1.65V - 2.7 V 2 k 15 pF GND 0.15 V 1.1 V - 1.6 V 2 k 15 pF GND 0.1 V 0.65 V - 0.95 V 20 k 15 pF GND 0.1 V (1), tdis (1) ten (2), tdis (2) A. Output waveform on the conditions that input is driven to a valid Logic Low. B. Output waveform on the condition that input is driven to a valid Logic High. Figure 7-2. Load Circuit Conditions An, Bn Input VCCI (1) VCCI / 2 Bn, An Output tpd GND VCCI / 2 VOH (2) VOL (2) VCCO / 2 tpd VCCO / 2 A. VCCI is the supply pin associated with the input port. B. VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 7-3. Propagation Delay SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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Output(1) tdis GND VCCA / 2 VCCO (3) VOL (4)VOL + VTP ten VCCO / 2 Output(2) VOH (4) GND VOH - VTP VCCO / 2 OE A. Output waveform on the condition that input is driven to a valid Logic Low. B. Output waveform on the condition that input is driven to a valid Logic High. C. VCCO is the supply pin associated with the output port. D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 7-4. Enable Time And Disable Time www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN74AXC8T245-Q1

8 Detailed Description

8.1 Overview

The SN74AXC8T245-Q1 device is an 8-bit, dual-supply non-inverting transceiver with bidirectional voltage level translation. The I/O pins labeled with A and the control pins (DIR1, DIR2, and OE) are supported by V CCA, and the I/O pins labeled with B are supported by V CCB. The A port and the B port are able to accept I/O voltages ranging from 0.65 V to 3.6 V.

8.2 Functional Block Diagram

Control Block To Enable or Disable Outputs (Note: Inputs on each buffer are always enabled) VCCA VCCB GND OE DIR1 DIR2 A8 B8 SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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8.3 Feature Description

8.3.1 Up-Translation and Down-Translation From 0.65 V to 3.6 V Both supply pins are configured from 0.65 V to 3.6 V, which makes the device suitable for translating between

8.3.2 Multiple Direction Control Pins

Two control pins are used to configure the 8 data I/Os. I/O channels 1 through 4 are grouped together and I/O channels 5 through 8 are banked together. The benefit of this is to permit simultaneous up-translation and down-translation within one device. This eliminates the need for multiple devices, where each device can only provide up-translation or down-translation sequentially. Simultaneous up and down translation is supported when both VCCA and VCCB are at least 1.40 V.

8.3.3 Ioff Supports Partial-Power-Down Mode Operation

This feature is to limit the leakage current of an I/O pin being driven to a voltage as large as 3.6 V while having its corresponding power supply rail powered down. This is represented by the I off parameter in the Electrical Characteristics table. www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN74AXC8T245-Q1

8.3.4 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. Package We able Flank Lead PCB Pad Standard Lead Package Solder Figure 8-1. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet as shown in Figure 8-1. Please see the mechanical drawing for additional details.

8.4 Device Functional Modes

All control inputs are referenced to V CCA and must be driven to a valid Logic High or Logic Low (that is, not floating) to assure proper device operation and to prevent excessive power consumption. Table 8-1 summarizes the possible modes of device operation based on the configuration of the control inputs. Table 8-1. Function Table CONTROL INPUTS(1) Signal Direction OE DIR1 DIR2 Bits 1:4 Bits 5:8 H X X Disabled (Hi-Z) L L L B to A L L H B to A A to B L H L A to B L H H A to B B to A (1) Input circuits of the data I/Os are always active and must be driven to a valid logic level. SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The AEC-Q100 qualified SN74AXC8T245-Q1 device can be used in level-translation applications for interfacing devices or systems operating at different voltage nodes. Figure 9-1 depicts an application in which the SN74AXC8T245-Q1 device is up-translating a 0.7 V input to a 3.3 V output to interface between a system controller and a peripheral device.

9.2 Typical Application

0.7 V Peripheral 3.3 V 0.1 µF 0.1 µF Figure 9-1. Typical Application Schematic www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: SN74AXC8T245-Q1

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUE Input voltage range 0.65 V to 3.6 V Output voltage range 0.65 V to 3.6 V

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

Input voltage range – Use the supply voltage of the device that is driving the SN74AXC8T245-Q1 device to determine the input voltage range. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value must be less than the VIL of the input port.
Output voltage range – Use the supply voltage of the device that the SN74AXC8T245-Q1 device is driving to determine the output voltage range.

9.2.3 Application Curve

Figure 9-2. Translation Up (0.7 V to 3.3 V) at 2.5 MHz SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. There are no additional requirements for power supply sequencing. This device was designed with various power supply sequencing methods in mind to help prevent unintended triggering of downstream devices. For more information regarding the power up glitch performance of the AXC family of level translators, see the Power Sequencing for AXC Family of Devices application report.

11 Layout

11.1 Layout Guidelines

To assure reliability of the device, follow common printed-circuit board layout guidelines.

Use bypass capacitors on power supplies.
Use short trace lengths to avoid excessive loading.
Place pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of signals depending on the system requirements.

11.2 Layout Example

(PW Package) VCCA DIR1 DIR2 GND GND OE VCCB VCCB1 LEGEND VIA to Power Plane (Inner Layer) VIA to GND Plane (Inner Layer) Polygonal Copper Pour To Destination To Destination To Destination To Destination To Destination To Destination To Destination To Destination From Source From Source From Source From Source From Source From Source From Source From Source Bypass Capacitor Bypass Capacitor VCCA Figure 11-1. SN74AXC8T245-Q1 Device Layout Example www.ti.com SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: SN74AXC8T245-Q1

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation, see the following:

Texas Instruments, SN74AXC8245-Q1 Evaluation Module user's guide
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74AXC8T245-Q1 SCES892C – NOVEMBER 2018 – REVISED OCTOBER 2021 www.ti.com

Product Folder Links: SN74AXC8T245-Q1

www.ti.com 8-Nov-2021 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CAXC8T245QRHLRQ1 ACTIVE VQFN RHL 24 1000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AX8T245Q CAXC8T245QWRGYRQ1 ACTIVE VQFN RGY 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 125 AX8T245Q SN74AXC8T245QPWRQ1 ACTIVE TSSOP PW 24 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 AX8T245Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

www.ti.com 8-Nov-2021 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AXC8T245-Q1 :

Catalog : SN74AXC8T245 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 21-Oct-2021 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CAXC8T245QRHLRQ1 VQFN RHL 24 1000 367.0 367.0 35.0 CAXC8T245QWRGYRQ1 VQFN RGY 24 3000 367.0 367.0 35.0 SN74AXC8T245QPWRQ1 TSSOP PW 24 2000 853.0 449.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 21-Oct-2021 Pack Materials-Page 2

Images above are just a representation of the package family, actual package may vary. Refer to the product data sheet for package details. RGY 24 5.5 x 3.5 mm, 0.5 mm pitch VQFN - 1 mm max height PLASTIC QUAD FLATPACK - NO LEAD 4203539-5/J

0.1 C A B

0.05 C B SYMM SYMM 3.6 3.4 5.6 5.4

1 MAX

0.05 0.00 (0.2) TYP PIN 1 INDEX AREA SECTION A-A TYPICAL (0.13)

0.1 MIN

C 2.1±0.1 4.1±0.1 2X 1.5 4.5 18X 0.5 PIN 1 ID (OPTIONAL) 24X 0.5 0.3 24X 0.3 0.2 A A 12 13 EXPOSED THERMAL PAD (0.16)

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225182/A 08/2019 www.ti.com VQFN - 1 mm max heightRGY0024E PLASTIC QUAD FLATPACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 15X SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED EXPOSED METAL SOLDER MASK OPENING METAL

0.07 MAX

0.07 MIN

2X (1.5) (2.1) (3.3) (4.1) 2X (4.5) 18X (0.5) 24X (0.25) 24X (0.6) (5.3) (1.12) (0.68) (0.8) (Ø0.2) VIA TYP (R0.05) TYP 12 13

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225182/A 08/2019 www.ti.com VQFN - 1 mm max heightRGY0024E PLASTIC QUAD FLATPACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 76% PRINTED COVERAGE BY AREA SCALE: 15X SYMM SYMM 2X (1.5) (3.3) (4.5) 18X (0.5) 24X (0.25) 24X (0.6) (5.3) (R0.05) TYP 12 13 (1.36) (0.57) 6X (0.94) 6X (1.16) METAL TYP

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4225250/A 09/2019 www.ti.com VQFN - 1 mm max height PLASTIC QUAD FLATPACK- NO LEAD RHL0024A AB PIN 1 INDEX AREA 3.6 3.4 5.6 5.4 0.08 C SEATING PLANE C1 MAX (0.1) TYP 0.05 0.00 0.05 C SYMM SYMM 1PIN 1 ID (OPTIONAL) 2.05±0.1 4.05±0.1 2X (0.55) 4.5 18X 0.5 12 13 2X 1.5 4X (0.2) 24X 0.30 0.18 24X 0.5 0.3

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4225250/A 09/2019 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 18X SYMM SYMM 2X (1.5) 6X (0.67) (0.775) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (4.05) (2.05) (R0.05) TYP 2X (1.105) 2X (0.4) SOLDER MASK OPENING METAL UNDER SOLDER MASK 4X (0.2) 2X (0.55) (Ø 0.2) VIA TYP 1 24 12 13 4.6 4.4 (PREFERRED) METAL SOLDER MASK OPENING EXPOSED METAL

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4225250/A 09/2019 www.ti.com VQFN - 1 mm max heightRHL0024A PLASTIC QUAD FLATPACK- NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 80% PRINTED COVERAGE BY AREA SCALE: 18X SYMM SYMM 2X (1.5) (1.34) 6X (0.56) (5.3) (3.3) 24X (0.6) 24X (0.24) 18X (0.5) (2.05) (R0.05) TYP 2X (0.84) METAL TYP 4X (0.2) 2X (0.55) 1 24 12 13 4.6 4.4 SOLDER MASK EDGE TYP

www.ti.com PACKAGE OUTLINE C 22X 0.65 7.15 24X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 7.9 7.7 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.000

www.ti.com EXAMPLE BOARD LAYOUT

0.05 MAX

0.05 MIN

24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 12 13 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 24X (1.5) 24X (0.45) 22X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0024A SMALL OUTLINE PACKAGE 4220208/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 12 13

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