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CAXC4T245QWBQBRQ1

Texas Instruments

SN74AXC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs REVISED DECEMBER 2021

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SN74AXC4T245-Q1 Automotive 4-Bit Dual-Supply Bus Transceiver With Configurable Voltage Translation and Tri-State Outputs

1 Features

AEC-Q100 qualified for automotive applications
Available in wettable flank QFN (WBQB) package
Fully-configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
Operating temperature from –40°C to +125°C
Multiple direction control pins to allow simultaneous up and down translation
Glitch-free power supply sequencing
Up to 380 Mbps support when translating from 1.8 V to 3.3 V
VCC isolation feature: – If either VCC input is below 100 mV, all I/O outputs are disabled and become high impedance
Ioff supports partial-power-down mode operation
Compatible with AVC-family level shifters
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD protection exceeds JEDEC JS-001 – 8000-V human-body model – 1000-V charged-device model

2 Applications

Infotainment head unit
ADAS fusion
ADAS front camera
Hybrid electric vehicles and electric vehicles battery management system
Telematics control unit

3 Description

The SN74AXC4T245-Q1 AEC-Q100 qualified device is a four-bit non-inverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both V CCA and V CCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXC4T245-Q1 is compatible with a single-supply system. The SN74AXC4T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (1DIR and 2DIR). The output-enable inputs (1 OE and 2 OE) are used to disable the outputs so the buses are effectively isolated. The SN74AXC4T245-Q1 device is designed so the control pins (xDIR and x OE) are referenced to VCCA. To ensure the high-impedance state of the level shifter I/Os during power up or power down, the x OE pins should be tied to VCCA through a pull-up resistor. This device is fully specified for partial-power-down applications using the I off current. The I off protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down. The VCC isolation feature ensures that if either V CCA or V CCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs. Glitch-Free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) SN74AXC4T245PW-Q1 TSSOP (16) 5.00 mm × 4.40 mm SN74AXC4T245BQB-Q1 WQFN (16) 2.50 mm × 3.50 mm SN74AXC4T245WBQB-Q1 WQFN (16) 2.50 mm × 3.50 mm SN74AXC4T245RSV-Q1 UQFN (16) 2.60 mm × 1.80 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. xA1 xB1 xDIR xOE xA2 xB2 One of Two Transceiver Pairs VCCA VCCB Functional Block Diagram SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

12.2 Receiving Notification of Documentation Updates..26

13 Mechanical, Packaging, and Orderable

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision D (September 2021) to Revision E (December 2021) Page Changes from Revision C (March 2021) to Revision D (September 2021) Page Changes from Revision B (July 2020) to Revision C (March 2021) Page Changes from Revision A (December 2019) to Revision B (July 2020) Page Changes from Revision * (July 2019) to Revision A (December 2019) Page SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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5 Pin Configuration and Functions

Figure 5-1. PW Package 16-Pin TSSOP Top View Thermal Pad 1DIR VCCA VCCB 1A1 1A2 2A1 GND 1OE 1B1 1B2 2B1 2DIR 2A2 GND 2B2 2OE Figure 5-2. BQB/WBQB Package 16-Pin WQFN Transparent Top View 131516 14 86 5 7 3VCCA 1DIR 2DIR 1A1 1A2 2A1 2A2 GND GNDVCCB 1OE 2OE 1B1 1B2 2B2 2B1 Figure 5-3. RSV Package 16-Pin UQFN Transparent Top View Table 5-1. Pin Functions PIN NO. TYPE DESCRIPTION NAME PW RSV BQB 1A1 4 6 4 I/O Input/output 1A1. Referenced to VCCA 1A2 5 7 5 I/O Input/output 1A2. Referenced to VCCA 1B1 13 15 13 I/O Input/output 1B1. Referenced to VCCB 1B2 12 14 12 I/O Input/output 1B2. Referenced to VCCB 1DIR 2 4 2 I Direction-control input for ‘1’ ports. Referenced to VCCA 1 OE 15 1 15 I Tri-state output-mode enable. Pull OE high to place ‘1’ outputs in tri-state mode. Referenced to VCCA 2A1 6 8 6 I/O Input/output 2A1. Referenced to VCCA 2A2 7 9 7 I/O Input/output 2A2. Referenced to VCCA 2B1 11 13 11 I/O Input/output 2B1. Referenced to VCCB 2B2 10 12 10 I/O Input/output 2B2. Referenced to VCCB 2DIR 3 5 3 I Direction-control input for ‘2’ ports. Referenced to VCCA 2 OE 14 16 14 I Tri-state output-mode enable. Pull OE high to place ‘2’ outputs in tri-state mode. Referenced to VCCA GND 8, 9 10, 11 8, 9 — Ground VCCA 1 3 1 — A-port power supply voltage. 0.65 V ≤ VCCA ≤ 3.6 V VCCB 16 2 16 — B-port power supply voltage. 0.65 V ≤ VCCB ≤ 3.6 V www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74AXC4T245-Q1

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA Supply voltage A –0.5 4.2 V VCCB Supply voltage B –0.5 4.2 V VI Input Voltage(2) I/O Ports (A Port) –0.5 4.2 VI/O Ports (B Port) –0.5 4.2 Control Inputs –0.5 4.2 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port –0.5 4.2 V B Port –0.5 4.2 VO Voltage applied to any output in the high or low state(2) (3) A Port –0.5 VCCA + 0.2 V B Port –0.5 VCCB + 0.2 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCC or GND –100 100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±8000 V Charged device model (CDM), per AEC Q100-011 ±1000 (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification. SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1) (2) MIN MAX UNIT VCCA Supply voltage A 0.65 3.6 V VCCB Supply voltage B 0.65 3.6 V VIH High-level input voltage Data Inputs VCCI = 0.65 V - 0.75 V VCCI x 0.70 V VCCI = 0.76 V - 1 V VCCI x 0.70 VCCI = 1.1 V - 1.95 V VCCI x 0.65 VCCI = 2.3 V - 2.7 V 1.6 VCCI = 3 V - 3.6 V 2 Control Inputs(xDIR, x OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA x 0.70 VCCA = 0.76 V - 1 V VCCA x 0.70 VCCA = 1.1 V - 1.95 V VCCA x 0.65 VCCA = 2.3 V - 2.7 V 1.6 VCCA = 3 V - 3.6 V 2 VIL Low-level input voltage Data Inputs VCCI = 0.65 V - 0.75 V VCCI x 0.30 V VCCI = 0.76 V - 1 V VCCI x 0.30 VCCI = 1.1 V - 1.95 V VCCI x 0.35 VCCI = 2.3 V - 2.7 V 0.7 VCCI = 3 V - 3.6 V 0.8 Control Inputs(xDIR, x OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA x 0.30 VCCA = 0.76 V - 1 V VCCA x 0.30 VCCA = 1.1 V - 1.95 V VCCA x 0.35 VCCA = 2.3 V - 2.7 V 0.7 VCCA = 3 V - 3.6 V 0.8 VI Input voltage (2) 0 3.6 V VO Output voltage Active State 0 VCCO V Tri-State 0 3.6 Δt/Δv(2) Input transition rate 10 ns/V TA Operating free-air temperature –40 125 °C (1) VCCI is the VCC associated with the input port. VCCO is the VCC associated with the output port. (2) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs.

6.4 Thermal Information

THERMAL METRIC(1) SN74AXC4T245-Q1 UNITPW (TSSOP) RSV (UQFN) BQB (WQFN) WBQB (WQFN)

16 PINS 16 PINS 16 PINS 16 PINS

RθJA Junction-to-ambient thermal resistance 126.9 130.1 73.0 72.9 °C/W RθJC(top) Junction-to-case (top) thermal resistance 49.3 70.3 35.1 69.6 °C/W RθJB Junction-to-board thermal resistance 74.3 57.4 42.8 41.9 °C/W ψJT Junction-to-top characterization parameter 8.1 4.6 4.6 4.6 °C/W ψJB Junction-to-board characterization parameter 73.4 55.8 42.8 41.9 °C/W RθJC(bottom) Junction-to-case (bottom) thermal resistance NA NA 10.2 19.9 °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report. www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74AXC4T245-Q1

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (1) (2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT–40°C to 85°C –40°C to 125°C MIN TYP(4) MAX MIN TYP(4) MAX VOH High-level output voltage VI = VIH IOH = –100 µA 0.7 V - 3.6 V 0.7 V - 3.6 V VCCO – 0.1 VCCO – 0.1 V IOH = –50 µA 0.65 V 0.65 V 0.55 0.55 IOH = –200 µA 0.76 V 0.76 V 0.58 0.58 IOH = –500 µA 0.85 V 0.85 V 0.65 0.65 IOH = –3 mA 1.1 V 1.1 V 0.85 0.85 IOH = –6 mA 1.4 V 1.4 V 1.05 1.05 IOH = –8 mA 1.65 V 1.65 V 1.2 1.2 IOH = –9 mA 2.3 V 2.3 V 1.75 1.75 IOH = –12 mA 3 V 3 V 2.3 2.3 VOL Low-level output voltage VI = VIL V IOL = 50 µA 0.65 V 0.65 V 0.1 0.1 IOL = 200 µA 0.76 V 0.76 V 0.18 0.18 IOL = 500 µA 0.85 V 0.85 V 0.2 0.2 IOL = 3 mA 1.1 V 1.1 V 0.25 0.25 IOL = 6 mA 1.4 V 1.4 V 0.35 0.35 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 0.55 IOL = 12 mA 3 V 3 V 0.7 0.7 II Input leakage current Control inputs (xDIR, x OE): VI Data Inputs (xAx, xBx) VI = VCCI or GND 0.65 V- 3.6 V 0.65 V- 3.6 V –4 4 –8 8 µA Ioff Partial power down current A or B Port VI or VO = 0 V - 3.6 V 0 V 0 V - 3.6 V –4 4 –8 8 µA 0 V - 3.6 V 0 V –4 4 –8 8 IOZ Tri-state output current (3) A or B Port VI = VCCI or GND, VO = VCCO or GND, OE = VIH 3.6 V 3.6 V –4 4 –8 8 µA ICCA VCCA supply current VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 13 26 µA0 V 3.6 V –2 –12

3.6 V 0 V 8 16

VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 13 26 µA0 V 3.6 V 8 16

3.6 V 0 V –2 –12

VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 20 40 µA Ci Control input Cio Data I/O capacitance OE = VCCA, VO = 1.65V DC +1 MHz -16 dBm sine wave 3.3 V 3.3 V 6.6 6.6 pF (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) For I/O ports, the parameter IOZ includes the input leakage current. (4) All typical data is taken at 25°C. SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.6 Switching Characteristics, VCCA = 0.7 V ± 0.05 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74AXC4T245-Q1

6.7 Switching Characteristics, VCCA = 0.8 V ± 0.04 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.8 Switching Characteristics, VCCA = 0.9 V ± 0.045 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74AXC4T245-Q1

6.9 Switching Characteristics, VCCA = 1.2 V ± 0.1 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.10 Switching Characteristics, VCCA = 1.5 V ± 0.1 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74AXC4T245-Q1

6.11 Switching Characteristics, VCCA = 1.8 V ± 0.15 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.12 Switching Characteristics, VCCA = 2.5 V ± 0.2 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74AXC4T245-Q1

6.13 Switching Characteristics, VCCA = 3.3 V ± 0.3 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.14 Operating Characteristics: TA = 25°C

PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT CpdA Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 2.2 pF 0.8 V 0.8 V 2.1 0.9 V 0.9 V 2.1 1.2 V 1.2 V 2.1 1.5 V 1.5 V 2.0 1.8 V 1.8 V 2.0 2.5 V 2.5 V 2.1 3.3 V 3.3 V 2.3 Power Dissipation Capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.5 pF 0.8 V 0.8 V 1.5 0.9 V 0.9 V 1.5 1.2 V 1.2 V 1.4 1.5 V 1.5 V 1.4 1.8 V 1.8 V 1.4 2.5 V 2.5 V 1.4 3.3 V 3.3 V 1.6 Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 12.1 pF 0.8 V 0.8 V 12.1 0.9 V 0.9 V 12.1 1.2 V 1.2 V 12.4 1.5 V 1.5 V 13.0 1.8 V 1.8 V 14.2 2.5 V 2.5 V 17.4 3.3 V 3.3 V 20.1 Power Dissipation Capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.1 pF 0.8 V 0.8 V 1.1 0.9 V 0.9 V 1.1 1.2 V 1.2 V 1.1 1.5 V 1.5 V 1.1 1.8 V 1.8 V 1.1 2.5 V 2.5 V 1.1 3.3 V 3.3 V 1.1 www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74AXC4T245-Q1

6.14 Operating Characteristics: TA = 25°C (continued)

PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT CpdB Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 12.1 pF 0.8 V 0.8 V 12.1 0.9 V 0.9 V 12.1 1.2 V 1.2 V 12.4 1.5 V 1.5 V 12.9 1.8 V 1.8 V 14.1 2.5 V 2.5 V 17.2 3.3 V 3.3 V 20.1 Power Dissipation Capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.1 pF 0.8 V 0.8 V 1.1 0.9 V 0.9 V 1.1 1.2 V 1.2 V 1.1 1.5 V 1.5 V 1.1 1.8 V 1.8 V 1.1 2.5 V 2.5 V 1.1 3.3 V 3.3 V 1.1 Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.2 pF 0.8 V 0.8 V 1.8 0.9 V 0.9 V 1.8 1.2 V 1.2 V 1.7 1.5 V 1.5 V 1.7 1.8 V 1.8 V 1.7 2.5 V 2.5 V 2 3.3 V 3.3 V 2.5 Power Dissipation Capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.1 pF 0.8 V 0.8 V 1.8 0.9 V 0.9 V 1.8 1.2 V 1.2 V 1.7 1.5 V 1.5 V 1.7 1.8 V 1.8 V 1.7 2.5 V 2.5 V 2 3.3 V 3.3 V 2.1 SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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6.15 Typical Characteristics

IOH (mA) VOH (V) 0 2 4 6 8 10 12 14 16 18 20 1.4 1.6 1.8 2.2 2.4 2.6 2.8 3.2 3.4 D001 VCC = 1.8V VCC = 2.5V VCC = 3.3V Figure 6-1. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOH (mA) VOH (V) 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.05 1.1 1.15 1.2 1.25 D001 VCC = 0.7V VCC = 1.2V Figure 6-2. Typical (TA=25°C) Output High Voltage (VOH) vs Source Current (IOH) IOL (mA) VOL (mV) 0 2 4 6 8 10 12 14 16 18 20 -50 100 150 200 250 300 350 400 450 500 550 600 650 700 D001 VCC = 1.8V VCC = 2.5V VCC = 3.3V Figure 6-3. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) IOL (mA) VOL (mV) 100 120 140 160 180 200 220 D001 VCC = 0.7V VCC = 1.2V Figure 6-4. Typical (TA=25°C) Output High Voltage (VOL) vs Sink Current (IOL) www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74AXC4T245-Q1

7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

Unless otherwise noted, all input pulses are supplied by generators having the following characteristics:

f = 1 MHz
ZO = 50 Ω
dv/dt ≤ 1 ns/V Output Pin Under Test CL (1) RL RL GND Open 2 x VCCO Measurement Point A. CL includes probe and jig capacitance. Figure 7-1. Load Circuit Table 7-1. Load Circuit Conditions Parameter VCCO RL CL S1 VTP Δt/Δv Input transition rise or fall rate 0.65 V – 3.6 V 1 MΩ 15 pF Open N/A tpd Propagation (delay) time 1.1 V – 3.6 V 2 kΩ 15 pF Open N/A 0.65 V – 0.95 V 20 kΩ 15 pF Open N/A ten, tdis Enable time, disable time 3 V – 3.6 V 2 kΩ 15 pF 2 × VCCO 0.3 V 1.65 V – 2.7 V 2 kΩ 15 pF 2 × VCCO 0.15 V 1.1 V – 1.6 V 2 kΩ 15 pF 2 × VCCO 0.1 V 0.65 V – 0.95 V 20 kΩ 15 pF 2 × VCCO 0.1 V ten, tdis Enable time, disable time 3 V – 3.6 V 2 kΩ 15 pF GND 0.3 V 1.65 V – 2.7 V 2 kΩ 15 pF GND 0.15 V 1.1 V – 1.6 V 2 kΩ 15 pF GND 0.1 V 0.65 V – 0.95 V 20 kΩ 15 pF GND 0.1 V Input A, B VCCI (1) VCCI / 2 0 V Output B, A VOH (2) VOL (2) tpd tpd VCCI / 2 VCCI / 2 V CCI / 2 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 7-2. Propagation Delay VCCI (1) 0 V 100 kHz 500 ps/V ± 100 ns/V VOH (2) VOL (2) Ensure Monotonic Rising and Falling Edge Output B, A Input A, B 1. VCCI is the supply pin associated with the input port. 2. VOH and VOL are typical output voltage levels that occur with specified RL, CL, and S1 Figure 7-3. Input Transition Rise or Fall Rate SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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Output(1) tdis GND VCCA / 2 VCCO (3) VOL (4)VOL + VTP ten VCCO / 2 Output(2) VOH (4) GND VOH - VTP VCCO / 2 OE A. Output waveform on the condition that input is driven to a valid Logic Low. B. Output waveform on the condition that input is driven to a valid Logic High. C. VCCO is the supply pin associated with the output port. D. VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 7-4. Enable Time And Disable Time www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN74AXC4T245-Q1

8 Detailed Description

8.1 Overview

The SN74AXC4T245-Q1 AEC-Q100 qualified device is a 4-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (1DIR, 2DIR,1 OE, and 2 OE) are referenced to V CCA logic levels, and Bx pins are referenced to V CCB logic levels. The A port is able to accept I/O voltages ranging from transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

8.2 Functional Block Diagram

One of Two Transceiver Pairs VCCA VCCB

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics, using ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.

8.3.3 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting current backflow into the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics.

8.3.4 VCC Isolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100 mV. SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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8.3.5 Over-Voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-Free Power Supply Sequencing

Either supply rail may be powered on or off in any order without producing a glitch on the I/Os (that is, where the output erroneously transitions to VCC when it should be held low). Glitches of this nature can be misinterpreted by a peripheral as a valid data bit, which could trigger a false device reset of the peripheral, a false device configuration of the peripheral, or even a false data initialization by the peripheral. For more information regarding the power up glitch performance of the AXC family of level translators, see Glitch Free Power Sequencing With AXC Level Translators.

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in Figure 8-1. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input negative-voltage and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed. GND LogicInput Output VCCDevice -IIK -IOK Figure 8-1. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

Both the VCCA and VCCB pins can be supplied at any voltage from 0.65 V to 3.6 V, making the device suitable for

8.3.9 Supports High-Speed Translation

The SN74AXC4T245-Q1 device can support high data-rate applications. The translated signal data rate can be up to 380 Mbps when the signal is translated from 1.8 V to 3.3 V. www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN74AXC4T245-Q1

8.3.10 Wettable Flanks

This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet for which packages include this feature. Package We able Flank Lead PCB Pad Standard Lead Package Solder Figure 8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet as shown in Figure 8-2. Please see the mechanical drawing for additional details.

8.4 Device Functional Modes

Table 8-1. Function Table (Each 2-Bit Section) CONTROL INPUTS(1) (2) PORT STATUS OPERATION OE DIR A PORT B PORT L L Output (Enabled) Input (Hi-Z) B data to A bus L H Input (Hi-Z) Output (Enabled) A data to B bus H X Input (Hi-Z) Input (Hi-Z) Isolation (1) Input circuits of the data I/Os are always active. (2) Pins configured as inputs should not be left floating. SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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9 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

9.1 Application Information

The AEC-Q100 qualified SN74AXC4T245-Q1 device can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. The SN74AXC4T245-Q1 device is ideal for use in applications where a push-pull driver is connected to the data I/Os. The maximum data rate can be up to 380 Mbps when device translates a signal from 1.8 V to 3.3 V. Figure 9-1 shows an example application where the SN74AXC4T245-Q1 device is used to translate a low voltage UART signal from an SoC to a higher voltage signal which properly drives the inputs of the Bluetooth® module, and vice versa.

9.2 Typical Application

0.7 V 3.3 V 0.1 µF 0.1 µF SN74AXC4T245-Q1 GND TX RX 2DIR 1OE 2OE 1B21A2 RTS CTS 2B12A1RX TX 2B22A2CTS RTS GPIO1 GPIO2 Pullup Resistors keep device disabled during power up. OE inputs may also be tied to GND to keep device enabled Figure 9-1. UART Interface Application

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 9-1. Table 9-1. Design Parameters DESIGN PARAMETERS EXAMPLE VALUES Input voltage range 0.65 V to 3.6 V Output voltage range 0.65 V to 3.6 V www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 23 Product Folder Links: SN74AXC4T245-Q1

9.2.2 Detailed Design Procedure

To begin the design process, determine the following:

Input voltage range: – Use the supply voltage of the device that is driving the SN74AXC4T245-Q1 device to determine the input voltage range. For a valid logic-high, the value must exceed the high-level input voltage (VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
Output voltage range: – Use the supply voltage of the device that the SN74AXC4T245-Q1 device is driving to determine the output voltage range.

9.2.3 Application Curve

Figure 9-2. Up Translation at 2.5 MHz (0.7 V to 3.3 V) SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

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10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. This device was designed with various power supply sequencing methods in mind to help prevent unintended triggering of downstream devices. For more information regarding the power up glitch performance of the AXC family of level translators, see Glitch Free Power Sequencing With AXC Level Translators.

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

Use bypass capacitors on the power supply pins and place them as close to the device as possible.
Use short trace lengths to avoid excessive loading.

11.2 Layout Example

B G Legend SN74AXC4T245-Q1PW G G G 0.1µF G G 0.1µFA B TX from SoC RTS from SoC RX to SoC CTS to SoC RX to Module CTS to Module TX from Module RTS from Module Figure 11-1. Layout Example www.ti.com SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 25 Product Folder Links: SN74AXC4T245-Q1

12 Device and Documentation Support

12.1 Documentation Support

12.1.1 Related Documentation

For related documentation see the following:

Texas Instruments, Glitch Free Power Sequencing With AXC Level Translators application report
Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
Texas Instruments, Low Voltage Translation For Standard Interfaces application report
Texas Instruments, Power Sequencing for AXC Family of Devices application report
Texas Instruments, SN74AXC4T245RSV EVM evaluation module user's guide
Texas Instruments, UART Interface Using SN74AXC4T245 video

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. Bluetooth® is a registered trademark of Bluetooth Special Interest Group (SIG). All trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74AXC4T245-Q1 SCES905E – JULY 2019 – REVISED DECEMBER 2021 www.ti.com

Product Folder Links: SN74AXC4T245-Q1

www.ti.com 16-Mar-2023 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CAXC4T245QBQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 4T245Q Samples CAXC4T245QRSVRQ1 ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1ZDR Samples CAXC4T245QWBQBRQ1 ACTIVE WQFN BQB 16 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 4T245Q Samples H14T245QRSVRQ1-NT ACTIVE UQFN RSV 16 3000 RoHS & Green NIPDAUAG Level-1-260C-UNLIM -40 to 125 1ZDR Samples SN74AXC4T245QPWRQ1 ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 4T245Q Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1

www.ti.com 16-Mar-2023 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AXC4T245-Q1 :

Catalog : SN74AXC4T245 NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 17-Mar-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 17-Mar-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CAXC4T245QBQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0 CAXC4T245QRSVRQ1 UQFN RSV 16 3000 189.0 185.0 36.0 CAXC4T245QWBQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0 H14T245QRSVRQ1-NT UQFN RSV 16 3000 189.0 185.0 36.0 SN74AXC4T245QPWRQ1 TSSOP PW 16 2000 356.0 356.0 35.0 Pack Materials-Page 2

www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQB 16 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3.5, 0.5 mm pitch 4226161/A

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4224640/A 11/2018 www.ti.com WQFN - 0.8 mm max height PLASTIC QUAD FLAT PACK-NO LEAD BQB0016A A 0.08 C

0.1 C A B

0.05 C B SYMM SYMM PIN 1 INDEX AREA 2.6 2.4 3.6 3.4 0.8 0.7 0.05 0.00 SEATING PLANE C 1.1 0.9 2.1 1.9 2X 0.5 16X 0.30 0.18 16X 0.5 0.3 2.5 10X 0.5 PIN 1 ID (OPTIONAL) (0.2) TYP 8 9

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4224640/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQB0016A PLASTIC QUAD FLAT PACK-NO LEAD SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (2) (3.3) 16X (0.24) 16X (0.6) (2.5) 10X (0.5) 2X (0.5) (2.3) (0.75) (Ø0.2) VIA TYP (R0.05) TYP 8 9

0.07 MAX

0.07 MIN

(PREFERRED) SOLDER MASK DEFINED

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4224640/A 11/2018 www.ti.com WQFN - 0.8 mm max heightBQB0016A PLASTIC QUAD FLAT PACK-NO LEAD SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 85% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.79) (3.3) 16X (0.24) 16X (0.6) (2.5) 10X (0.5) 2X (0.5) (2.3) (R0.05) TYP 8 9 EXPOSED METAL

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max height INDSTNAME BQB0016B A 0.08 C 0.05 C B SYMM SYMM 2.6 2.4 3.6 3.4

0.8 MAX

0.05 0.00 SEATING PLANE C (0.2) TYP 2X 0.5 2.5 10X 0.5 1.1 0.9 2.1 1.9 16X 0.5 0.3 16X 0.3 0.2 SYMM 8 9 PIN 1 ID (OPTIONAL) PIN 1 INDEX AREA (0.16)

0.1 MIN

(0.13) SECTION A-A TYPICAL

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max heightBQB0016B INDSTNAME SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (2) 16X (0.6) 16X (0.25) 2X (0.5) 10X (0.5) (2.3) (3.3) 2X (0.75) 1 16 8 9 (Ø 0.2) VIA TYP (R0.05) TYP

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max heightBQB0016B INDSTNAME SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 85% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.79) 16X (0.6) 16X (0.25) 2X (0.5) 10X (0.5) (2.3) (3.3) 2X (0.75) 1 16 8 9 (R0.05) TYP METAL TYP

www.ti.com PACKAGE OUTLINE C 1.85 1.75 2.65 2.55 0.55 0.45 0.05 0.00 2X 1.2 12X 0.4 2X 1.2 15X 0.45 0.35 16X 0.25 0.15 0.55 0.45 (0.13) TYP UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 0.05 C

0.07 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID (45 ° X 0.1) SYMM SYMM 5 8 1316 SCALE 5.000 AB

www.ti.com EXAMPLE BOARD LAYOUT 12X (0.4) (R0.05) TYP

0.05 MAX

0.05 MIN

15X (0.6) 16X (0.2) (1.6) (2.4) (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 3. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 25X SEE SOLDER MASK DETAIL 5 8 1316 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 15X (0.6) 16X (0.2) 12X (0.4) (1.6) (2.4) (R0.05) TYP (0.7) UQFN - 0.55 mm max heightRSV0016A ULTRA THIN QUAD FLATPACK - NO LEAD 4220314/C 02/2020 NOTES: (continued) 4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 25X SYMM SYMM 5 8 1316

www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.19 TYP6.6 6.2

1.2 MAX

0.15 0.05 0.25 GAGE PLANE -80 B NOTE 4 4.5 4.3 A NOTE 3 5.1 4.9 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500

www.ti.com EXAMPLE BOARD LAYOUT 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9

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