CAXC2T245QRSWRQ1

SN74AXC2T245-Q1 TI1 | Alldatasheet

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Technical content

ADVANCE□INFORMATION Ax Bx DIRx OE One of Two Transceivers VCCA VCCB Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for pre-production products; subject to change without notice. SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 SN74AXC2T245-Q1Automotive2-BitDual-SupplyBusTransceiverwithConfigurable VoltageTranslationandTri-StateOutputs

1 Features

1• AEC-Q100 automotive qualified

• Fully configurable dual-rail design allows each port to operate with a power supply range rrom 0.65 V to 3.6 V
• Operating temperature from –40°C to +125°C
• DIR control input for each channel
• Glitch-free power supply sequencing
• Up to 380 Mbps support when translating from 1.8 V to 3.3 V
• VCC isolation feature – If either VCC input is below 100 mV, all I/O outputs are disabled and become high- impedance
• Ioff supports partial-power-down mode operation
• Compatible with AVC-family level shifters
• Latch-up performance exceeds 100 mA per JESD 78, class II
• ESD protection exceeds JEDEC JS-001 – 8000-V Human-body model – 1000-V Charged-device model

2 Applications

• HEV/EV
• Infotainment head unit
• ADAS fusion
• ADAS front camera
• Enterprise and communications

3 Description

The SN74AXC2T245-Q1 is a two-bit noninverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both VCCA and VCCB supplies as low as 0.65 V. The A port is designed to track VCCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track VCCB, which also accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXC2T245-Q1 is compatible with a single- supply system. The SN74AXC2T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (DIRx). The SN74AXC2T245-Q1 device is designed so the control pin (DIR) is referenced to VCCA. This device is fully specified for partial-power-down applications using the Ioff current. The Ioff protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down. The VCC isolation feature ensures that if either VCCA or VCCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs. Glitch-free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) CAXC2T245QRSWRQ1 UQFN (10) 1.80 mm x 1.40 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Functional Block Diagram

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Table of Contents

12.2 Receiving Notification of Documentation Updates 24

13 Mechanical, Packaging, and Orderable

4 Revision History

February 2020 * Initial Advance Information Release.

ADVANCE□INFORMATION 8 7 6 5 21 3 DIR2 OE GND VCCB VCCA DIR1 SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

5 Pin Configuration and Functions

PIN NO.

DESCRIPTION

DIR2 1 Direction Pin for channel A2/B2, Connect to GND or to VCCA OE 2 Tri-state output-mode enable. Pull OE high to place all outputs in tri-state mode. Referenced to VCCA. GND 3 Ground B2 4 Output or input depending on state of DIR2. Output level depends on VCCB. B1 5 Output or input depending on state of DIR1. Output level depends on VCCB. VCCB 6 Supply Voltage B VCCA 7 Supply Voltage A A1 8 Output or input depending on state of DIR1. Output level depends on VCCA. A2 9 Output or input depending on state of DIR2. Output level depends on VCCA. DIR1 10 Direction Pin for channel A1/B1, Connect to GND or to VCCA

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed. (3) The output positive-voltage rating may be exceeded up to 4.2 V maximum if the output current rating is observed.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCCA Supply voltage A –0.5 4.2 V VCCB Supply voltage B –0.5 4.2 V VI Input Voltage(2) I/O Ports (A Port) –0.5 4.2 VI/O Ports (B Port) –0.5 4.2 Control Inputs –0.5 4.2 VO Voltage applied to any output in the high-impedance or power-off state(2) A Port –0.5 4.2 V B Port –0.5 4.2 VO Voltage applied to any output in the high or low state(2)(3) A Port –0.5 VCCA + 0.2 V B Port –0.5 VCCB + 0.2 IIK Input clamp current VI < 0 –50 mA IOK Output clamp current VO < 0 –50 mA IO Continuous output current –50 50 mA Continuous current through VCC or GND –100 100 mA Tj Junction Temperature 150 °C Tstg Storage temperature –65 150 °C (1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±8000 V Charged device model (CDM), per AEC Q100-011 ±1000

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)(2)(3) MIN MAX UNIT VCCA Supply voltage A 0.65 3.6 V VCCB Supply voltage B 0.65 3.6 V VIH High-level input voltage Data Inputs VCCI = 0.65 V - 0.75 V VCCI x 0.70 V VCCI = 0.76 V - 1 V VCCI x 0.70 VCCI = 1.1 V - 1.95 V VCCI x 0.65 VCCI = 2.3 V - 2.7 V 1.6 VCCI = 3 V - 3.6 V 2 Control Inputs(DIRx, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA x 0.70 VCCA = 0.76 V - 1 V VCCA x 0.70 VCCA = 1.1 V - 1.95 V VCCA x 0.65 VCCA = 2.3 V - 2.7 V 1.6 VCCA = 3 V - 3.6 V 2 VIL Low-level input voltage Data Inputs VCCI = 0.65 V - 0.75 V VCCI x 0.30 V VCCI = 0.76 V - 1 V VCCI x 0.30 VCCI = 1.1 V - 1.95 V VCCI x 0.35 VCCI = 2.3 V - 2.7 V 0.7 VCCI = 3 V - 3.6 V 0.8 Control Inputs(DIRx, OE) Referenced to VCCA VCCA = 0.65 V - 0.75 V VCCA x 0.30 VCCA = 0.76 V - 1 V VCCA x 0.30 VCCA = 1.1 V - 1.95 V VCCA x 0.35 VCCA = 2.3 V - 2.7 V 0.7 VCCA = 3 V - 3.6 V 0.8 VI Input voltage (3) 0 3.6 V VO Output voltage Active State 0 VCCO V Tri-State 0 3.6 Δt/Δv Input transition rate 10 ns/V TA Operating free-air temperature –40 125 °C (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.4 Thermal Information

THERMAL METRIC(1) SN74AXC2T245-Q1 UNITRSW (UQFN)

10 PINS

RθJA Junction-to-ambient thermal resistance 209.0 °C/W RθJC(top) Junction-to-case (top) thermal resistance 129.1 °C/W RθJB Junction-to-board thermal resistance 122.9 °C/W ψJT Junction-to-top characterization parameter 18.4 °C/W ψJB Junction-to-board characterization parameter 122.5 °C/W

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) VCCI is the VCC associated with the input port. (2) VCCO is the VCC associated with the output port. (3) All typical data is taken at 25°C. (4) For I/O ports, the parameter IOZ includes the input leakage current.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) (1)(2) PARAMETER TEST CONDITIONS VCCA VCCB Operating free-air temperature (TA) UNIT-40°C to 85°C -40°C to 125°C MIN TYP(3) MAX MIN TYP(3) MAX VOH High-level output voltage VI = VIH IOH = -100 µA 0.7 V - 3.6 V 0.7 V - 3.6 V VCCO – 0.1 VCCO – 0.1 V IOH = -50 µA 0.65 V 0.65 V 0.55 0.55 IOH = -200 µA 0.76 V 0.76 V 0.58 0.58 IOH = -500 µA 0.85 V 0.85 V 0.65 0.65 IOH = -3 mA 1.1 V 1.1 V 0.85 0.85 IOH = -6 mA 1.4 V 1.4 V 1.05 1.05 IOH = -8 mA 1.65 V 1.65 V 1.2 1.2 IOH = -9 mA 2.3 V 2.3 V 1.75 1.75 IOH = -12 mA 3 V 3 V 2.3 2.3 VOL Low-level output voltage VI = VIL V IOL = 50 µA 0.65 V 0.65 V 0.1 0.1 IOL = 200 µA 0.76 V 0.76 V 0.18 0.18 IOL = 500 µA 0.85 V 0.85 V 0.2 0.2 IOL = 3 mA 1.1 V 1.1 V 0.25 0.25 IOL = 6 mA 1.4 V 1.4 V 0.35 0.35 IOL = 8 mA 1.65 V 1.65 V 0.45 0.45 IOL = 9 mA 2.3 V 2.3 V 0.55 0.55 IOL = 12 mA 3 V 3 V 0.7 0.7 II Input leakage current Control inputs (DIRx, OE): Data Inputs (Ax, Bx) VI = VCCI or GND 0.65 V- 3.6 V 0.65 V- 3.6 V –4 4 –8 8 µA Ioff Partial power down current A or B Port VI or VO = 0 V - 3.6 V 0 V 0 V - 3.6 V –4 4 –8 8 µA 0 V - 3.6 V 0 V –4 4 –8 8 IOZ Tri-state output current (4) A or B Port VI = VCCI or GND, VO = VCCO or GND, OE = VIH 3.6 V 3.6 V –4 4 –8 8 µA ICCA VCCA supply current VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 10 14 µA0 V 3.6 V –2 –12

3.6 V 0 V 5 10

VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 10 14 µA0 V 3.6 V 5 10

3.6 V 0 V –2 –12

VI = VCCI or GND IO = 0 0.65 V- 3.6 V 0.65 V- 3.6 V 16 23 µA Ci Control input Cio Data I/O capacitance OE = VCCA, VO = 1.65V DC +1 MHz -16 dBm sine wave 3.3 V 3.3 V 5.1 5.1 pF

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated 6.6 Switching Characteristics, VCCA = 0.7 ± 0.05 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.7 Switching Characteristics, VCCA = 0.8 ± 0.04 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated 6.8 Switching Characteristics, VCCA = 0.9 ± 0.045 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.9 Switching Characteristics, VCCA = 1.2 ± 0.1 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated 6.10 Switching Characteristics, VCCA = 1.5 ± 0.1 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.11 Switching Characteristics, VCCA = 1.8 ± 0.15 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated 6.12 Switching Characteristics, VCCA = 2.5 ± 0.2 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated 6.13 Switching Characteristics, VCCA = 3.3 ± 0.3 V See Figure 1 and Table 1 for test circuit and loading. See Figure 2, Figure 3, and Figure 4 for measurement waveforms. PARAMETER FROM TO Test Conditions B-Port Supply Voltage (VCCB) MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tpd Propagation delay A B ns B A tdis Disable time OE A ns OE B ten Enable time OE A ns OE B

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

6.14 Operating Characteristics: TA = 25°C

PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT CpdA Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 2.1 pF 0.8 V 0.8 V 2.0 0.9 V 0.9 V 2.0 1.2 V 1.2 V 2.0 1.5 V 1.5 V 2.1 1.8 V 1.8 V 2.1 2.5 V 2.5 V 2.5 3.3 V 3.3 V 3.1 Power Dissipation Capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.6 pF 0.8 V 0.8 V 1.6 0.9 V 0.9 V 1.6 1.2 V 1.2 V 1.6 1.5 V 1.5 V 1.6 1.8 V 1.8 V 1.7 2.5 V 2.5 V 2.1 3.3 V 3.3 V 2.6 Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 10.5 pF 0.8 V 0.8 V 10.6 0.9 V 0.9 V 10.6 1.2 V 1.2 V 10.8 1.5 V 1.5 V 11.2 1.8 V 1.8 V 12.5 2.5 V 2.5 V 16.3 3.3 V 3.3 V 20.0 Power Dissipation Capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.0 pF 0.8 V 0.8 V 0.9 0.9 V 0.9 V 0.9 1.2 V 1.2 V 0.9 1.5 V 1.5 V 0.9 1.8 V 1.8 V 0.9 2.5 V 2.5 V 0.9 3.3 V 3.3 V 0.9

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated Operating Characteristics: TA = 25°C (continued) PARAMETER TEST CONDITIONS VCCA VCCB MIN TYP MAX UNIT CpdB Power Dissipation Capacitance per transceiver (A to B: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 10.9 pF 0.8 V 0.8 V 10.9 0.9 V 0.9 V 10.9 1.2 V 1.2 V 11.1 1.5 V 1.5 V 11.4 1.8 V 1.8 V 12.6 2.5 V 2.5 V 16.3 3.3 V 3.3 V 20.0 Power Dissipation Capacitance per transceiver (A to B: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.3 pF 0.8 V 0.8 V 1.2 0.9 V 0.9 V 1.2 1.2 V 1.2 V 1.1 1.5 V 1.5 V 1.1 1.8 V 1.8 V 1.1 2.5 V 2.5 V 1.1 3.3 V 3.3 V 1.2 Power Dissipation Capacitance per transceiver (B to A: outputs enabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 2.1 pF 0.8 V 0.8 V 2.1 0.9 V 0.9 V 2.0 1.2 V 1.2 V 2.0 1.5 V 1.5 V 2.1 1.8 V 1.8 V 2.2 2.5 V 2.5 V 2.5 3.3 V 3.3 V 3.1 Power Dissipation Capacitance per transceiver (B to A: outputs disabled) CL = 0, RL = Open f = 1 MHz, tr = tf = 1 ns 0.7 V 0.7 V 1.6 pF 0.8 V 0.8 V 1.6 0.9 V 0.9 V 1.6 1.2 V 1.2 V 1.6 1.5 V 1.5 V 1.6 1.8 V 1.8 V 1.7 2.5 V 2.5 V 2.1 3.3 V 3.3 V 2.6

7 Parameter Measurement Information

7.1 Load Circuit and Voltage Waveforms

• f = 1 MHz
• ZO = 50 Ω
• dv/dt ≤ 1 ns/V (1) CL includes probe and jig capacitance.

Figure 1. Load Circuit Table 1. Load Circuit Conditions

1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with

Figure 2. Propagation Delay

1. VCCI is the supply pin associated with the input port.
2. VOH and VOL are typical output voltage levels that occur with

Figure 3. Input Transition Rise or Fall Rate

(1) Output waveform on the condition that input is driven to a valid Logic Low. (2) Output waveform on the condition that input is driven to a valid Logic High. (3) VCCO is the supply pin associated with the output port. (4) VOH and VOL are typical output voltage levels with specified RL, CL, and S1. Figure 4. Enable Time And Disable Time

ADVANCE□INFORMATION Ax Bx DIRx OE One of Two Transceivers VCCA VCCB SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

8 Detailed Description

8.1 Overview

The SN74AXC2T245-Q1 is a 2-bit, dual-supply noninverting bidirectional voltage level translation device. Ax pins and control pins (DIRx and OE) are reference to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 0.65 V to 3.6 V, while the B port can accept I/O voltages from 0.65 V to 3.6 V. A high on DIR enables data transmission from A to B and a low on DIR enables data transmission from B to A. See Device Functional Modes for a summary of the operation of the control logic.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Standard CMOS Inputs

Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). Signals applied to the inputs need to have fast edge rates, as defined by Δt/Δv in Recommended Operating Conditions to avoid excessive current consumption and oscillations. If a slow or noisy input signal is required, a device with a Schmitt-trigger input should be used to condition the input signal prior to the standard CMOS input.

8.3.2 Balanced High-Drive CMOS Push-Pull Outputs

A balanced output allows the device to sink and source similar currents. The high drive capability of this device creates fast edges into light loads so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.

8.3.3 Partial Power Down (Ioff)

The inputs and outputs for this device enter a high-impedance state when the device is powered down, inhibiting current backflow into the device. The maximum leakage into or out of any input or output pin on the device is specified by Ioff in the Electrical Characteristics.

8.3.4 VCC Isolation

The inputs and outputs for this device enter a high-impedance state when either supply is <100mV.

8.3.5 Over-voltage Tolerant Inputs

Input signals to this device can be driven above the supply voltage so long as they remain below the maximum input voltage value specified in the Recommended Operating Conditions.

8.3.6 Glitch-free Power Supply Sequencing

8.3.7 Negative Clamping Diodes

The inputs and outputs to this device have negative clamping diodes as depicted in Figure 5. may be exceeded if the input and output clamp-current ratings are observed. Figure 5. Electrical Placement of Clamping Diodes for Each Input and Output

8.3.8 Fully Configurable Dual-Rail Design

8.3.9 Supports High-Speed Translation

up to 380 Mbps when the signal is translated from 1.8 V to 3.3 V.

8.4 Device Functional Modes

(1) Input circuits of the data I/Os are always active. (2) Pins configured as inputs should not be left floating. Table 2. Function Table

9 Application and Implementation

validate and test their design implementation to confirm system functionality.

9.1 Application Information

when device translates a signal from 1.8 V to 3.3 V. voltage UART signals from a CPU to a higher voltage signal to properly drive the inputs of a bluetooth module.

9.2 Typical Application

Figure 6. 2-Pin UART Application

9.2.1 Design Requirements

For this design example, use the parameters listed in Table 3. Table 3. Design Parameters

9.2.2 Detailed Design Procedure

• Input voltage range – Use the supply voltage of the device that is driving the SN74AXC2T245-Q1 device to determine the input voltage range. For a valid logic high, the value must exceed the high-level input voltage (VIH) of the input port. For a valid logic low the value must be less than the low-level input voltage (VIL) of the input port.
• Output voltage range – Use the supply voltage of the device being driven by the SN74AXC2T245-Q1 determine the output voltage range of the SN74AXC2T245-Q1.

9.2.3 Application Curve

Figure 7. Up Translation at 2.5 MHz (0.7 V to 3.3 V)

ADVANCE□INFORMATION Copper TracesVia to VCCB Via to VCCA Via to GNDA B G Legend SN74AXC2T245RSW 8 7 6 5 21 3 DIR2 GND VCCBVCCA DIR1 0.1µF 0201 0.1µF 0201 G BA OEG G 8 mil RX to SoC TX from Soc TX from Module RX to Module SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

10 Power Supply Recommendations

Always apply a ground reference to the GND pins first. This device is designed for glitch-free power sequencing without any supply sequencing requirements such as ramp order or ramp rate. This device is designed with various power supply sequencing methods in mind to help prevent unintended triggering of downstream devices. For more information regarding the power-up glitch performance of the AXC family of level translators, see the Glitch Free Power Sequencing With AXC Level Translators application report

11 Layout

11.1 Layout Guidelines

To ensure reliability of the device, following common printed-circuit board layout guidelines are recommended:

• Use bypass capacitors on the power supply pins and place them as close to the device as possible. A 0.1 µF capacitor is recommended, but transient performance can be improved by having both 1 µF and 0.1 µF capacitors in parallel as bypass capacitors.
• Use short trace lengths to avoid excessive loading.

11.2 Layout Example

ADVANCE□INFORMATION SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

12 Device and Documentation Support

12.1 Related Documentation

For related documentation see the following: Texas Instruments, Implications of Slow or Floating CMOS Inputs application report Texas Instruments, Power Sequencing for AXC Family of Devices application report

12.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

12.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

12.4 Trademarks

E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

12.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

12.6 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

ADVANCE□INFORMATION SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. space (4) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (5) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (6) Multiple Device markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

13.1 Package Option Addendum

13.1.1 Packaging Information

Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish(3) MSL Peak Temp (4) Op Temp (°C) Device Marking(5)(6) CAXC2T245QRSWRQ1 PREVIEW UQFN RSW 10 TBD TBD Call TI Call TI -40 to 125 TBD

ADVANCE□INFORMATION Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed SN74AXC2T245-Q1 SCES908 –FEBRUARY 2020 www.ti.com Product Folder Links: SN74AXC2T245-Q1 Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

13.1.2 Tape and Reel Information

(mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CAXC2T245QRSWRQ

1 UQFN RSW 10 TBD

ADVANCE□INFORMATION TAPE AND REEL BOX DIMENSIONS Width (mm) W L H SN74AXC2T245-Q1 www.ti.com SCES908 –FEBRUARY 2020 Product Folder Links: SN74AXC2T245-Q1 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CAXC2T245QRSWRQ1 UQFN RSW 10 TBD

www.ti.com PACKAGE OUTLINE C 1.45 1.35 1.85 1.75 0.55 0.45 NOTE 3 0.05 0.00 6X 0.4 2X 0.8 9X 0.45 0.35 10X 0.25 0.15 0.55 0.45 (0.13) TYP UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 0.05 C

0.07 C A B

0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM SYMM 3 5 810 SCALE 7.000 AB

www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP

0.05 MAX

0.05 MIN

9X (0.6) (0.7)10X (0.2) (1.2) (1.6) 6X (0.4) UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 30X SEE SOLDER MASK DETAIL 3 5 810 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 9X (0.6) 10X (0.2) 6X (0.4) (1.2) (1.6) (R0.05) TYP (0.7) UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 30X SYMM 3 5 810

www.ti.com 13-Mar-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CAXC2T245QRSWRQ1 PREVIEW UQFN RSW 10 3000 TBD Call TI Call TI -40 to 125 PCAXC2T245QRSWRQ1 ACTIVE UQFN RSW 10 3000 TBD Call TI Call TI -40 to 125 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com PACKAGE OUTLINE C 1.45 1.35 1.85 1.75 0.55 0.45 NOTE 3 0.05 0.00 6X 0.4 2X 0.8 9X 0.45 0.35 10X 0.25 0.15 0.55 0.45 (0.13) TYP UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 0.05 C 0.05 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM SYMM 3 5 810 SCALE 7.000 AB

www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP 9X (0.6) (0.7)10X (0.2) (1.2) (1.6) 6X (0.4) UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 30X SEE SOLDER MASK DETAIL 3 5 810 METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED SOLDER MASK DETAILS

www.ti.com EXAMPLE STENCIL DESIGN 9X (0.6) 10X (0.2) 6X (0.4) (1.2) (1.6) (R0.05) TYP (0.7) UQFN - 0.55 mm max heightRSW0010A PLASTIC QUAD FLATPACK - NO LEAD 4224897/A 03/2019 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SYMM SOLDER PASTE EXAMPLE BASED ON 0.125 MM THICK STENCIL SCALE: 30X SYMM 3 5 810

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