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  • PDF pages: 12

Technical content

Features

  • Automotive Temperature Grade 1 (−40°C to +125°C)
  • 10 MHz SPI Compatible
  • 2.5 V to 5.5 V Supply V oltage Range
  • SPI Modes (0,0) & (1,1)
  • 16−byte Page Write Buffer
  • Self−timed Write Cycle
  • Hardware and Software Protection
  • Block Write Protection − Protect 1/4, 1/2 or Entire EEPROM Array
  • Low Power CMOS Technology
  • 1,000,000 Program/Erase Cycles
  • 100 Year Data Retention
  • Industrial and Extended Temperature Range
  • SOIC and TSSOP 8−Lead Packages
  • These Devices are Pb−Free, Halogen Free/BFR Free, and RoHS Compliant SI SO CAV25010 CAV25020 CAV25040 SCK VSS VCC CS WP HOLD

Figure 1. Functional Symbol dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

SOIC−8 V SUFFIX CASE 751BD SCK SOIC (V), TSSOP (Y) TSSOP−8 Y SUFFIX CASE 948AL Chip SelectCS Serial Data OutputSO Write ProtectWP GroundVSS Serial Data InputSI Serial ClockSCK FunctionPin Name PIN FUNCTION Hold Transmission InputHOLD Power SupplyVCC For the location of Pin 1, please consult the corresponding package drawing.

Table 1. ABSOLUTE MAXIMUM RATINGS Table 2. RELIABILITY CHARACTERISTICS (Note 2) Table 4. PIN CAPACITANCE (Note 2) (TA = 25°C, f = 1.0 MHz, VCC = +5.0 V)

  1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.

  1. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

Table 5. A.C. CHARACTERISTICS (TA = −40°C to +125°C) (Note 4)

  1. This parameter is tested initially and after a design or process change that affects the parameter.
  2. t WC is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.

Table 6. POWER−UP TIMING (Notes 7, 8)

  1. This parameter is tested initially and after a design or process change that affects the parameter.
  2. t PUR and tPUW are the delays required from the time VCC is stable at the operating voltage until the specified operation can be initiated.

on the rising edge of the SCK clock input. on the falling edge of the SCK clock. between host and CA V25010/20/40. Mode (unless an internal write operation is in progress). tied low all write operations are inhibited. back high, with the SCK input low during both transitions. to VCC, either directly or through a resistor. instruction set and associated op−codes are listed in Table 7. a Status Register, as will be explained later. Table 7. INSTRUCTION SET (Note 9) Figure 2. Synchronous Data Timing number of status and control bits. to accept commands. For the host, this bit is read only. blocks then become read−only.

communication, HOLD must be taken high while SCK is low. failure following a temporary loss of power. must be issued prior to any writes to the device. remain in the high impedance state. Figure 11. HOLD Timing

CAV25010, CAV25020, CAV25040 http://onsemi.com PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80

1.27 BSC

1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35

CAV25010, CAV25020, CAV25040 http://onsemi.com PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O E1 E e b D cA TOP VIEW SIDE VIEW END VIEW /C01131 L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. SYMBOL θ MIN NOM MAX A b c D E e 0º 8º L 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30

0.65 BSC

1.00 REF

1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40

CAV25010, CAV25020, CAV25040 http://onsemi.com (Note 10) Package Type Temperature Range Lead Finish Shipping CAV25010VE−G 25010E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tube, 100 Units / Tube CAV25010VE−GT3 25010E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV25010YE−G S01E TSSOP−8 −40°C to +125°C NiPdAu Tube, 100 Units / Tube CAV25010YE−GT3 S01E TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV25020VE−GT3 25020E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV25020YE−GT3 S02E TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV25040VE−G 25040E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tube, 100 Units / Tube CAV25040VE−GT3 25040E SOIC−8, JEDEC −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel CAV25040YE−GT3 S04E TSSOP−8 −40°C to +125°C NiPdAu Tape & Reel, 3,000 Units / Reel 10.Specific Device Marking shows the first row top package marking. 11. All packages are RoHS−compliant (Lead−free, Halogen−free). 12.The standard lead finish is NiPdAu. 13.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Ree l Packaging Specifications Brochure, BRD8011/D. 15.For detailed information and a breakdown of device nomenclature and numbering systems, please see the ON Semiconductor Devic e Nomenclature document, TND310/D, available at www.onsemi.com ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. CAV25010/D PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative