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Document overview
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Technical content
Features
- High Speed Operation: 2 MHz
- 1.8 V to 5.5 V Supply V oltage Range
- Selectable x8 or x16 Memory Organization
- Sequential Read
- Software Write Protection
- Power−up Inadvertant Write Protection
- Low Power CMOS Technology
- 1,000,000 Program/Erase Cycles
- 100 Year Data Retention
- Industrial and Extended Temperature Ranges
- 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
- These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant SK DI ORG DOCAT93C57 GND CS VCC CAT93C56
Figure 1. Functional Symbol NOTE: When the ORG pin is connected to VCC, the x16 organization is selected. unconnected, then an internal pullup device will select the x16 organization. dimensions section on page 16 of this data sheet.
ORDERING INFORMATION
SOIC−8 V or W SUFFIX CASE 751BD TDFN−8 VP2 SUFFIX CASE 511AK ORG PDIP (L), SOIC (V, X), TSSOP (Y), TDFN (VP2, ZD4*) PDIP−8 L SUFFIX CASE 646AA TSSOP−8 Y SUFFIX CASE 948AL Chip SelectCS Clock InputSK Serial Data InputDI Serial Data OutputDO Power SupplyVCC GroundGND FunctionPin Name PIN FUNCTION Memory OrganizationORG No ConnectionNC DI DO GND ORG SK VCC NC CS SOIC (W*) (Top Views) SOIC−8 EIAJ X SUFFIX CASE 751BE TDFN−8 ZD4 SUFFIX CASE 511AL * TDFN 3x3 mm (ZD4) and SOIC (W) rotated pin−out packages are available for CAT93C57 and CAT93C56, Rev. E only (not recommen- ded for new designs of CAT93C56)
Table 1. ABSOLUTE MAXIMUM RATINGS
- The DC input voltage on any pin should not be lower than −0.5 V or higher than V
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2)
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
- Block Mode, V CC = 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS, CAT93C56, Die Rev. G – New Product
Table 5. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
Table 6. A.C. CHARACTERISTICS (Note 5), CAT93C56, Die Rev. G – New Product Table 7. A.C. CHARACTERISTICS (Note 5), CAT93C56/57, Die Rev. E – Mature Product Table 8. POWER−UP TIMING (Notes 6 and 7)
- Test conditions according to “A.C. Test Conditions” table.
- These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
- t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
Table 9. A.C. TEST CONDITIONS intended for use with industry standard microprocessors. follows the timing shown in Figure 2. Figure 2. Synchronous Data Timing
shown in Instruction Set table. Table 10. INSTRUCTION SET
- Address bit A8 for 256x8 organization and A7 for 128x16 organization are “Don’t Care” bits, but must be kept at either a “1” or “0” for READ,
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A D A L eb E eB c TOP VIEW SIDE VIEW END VIEW PIN # 1 IDENTIFICATION Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. SYMBOL MIN NOM MAX A b c D e L 0.38 2.92 0.36 6.10 1.14 0.20 9.02
2.54 BSC
3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eB 7.87 10.92 E 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80
1.27 BSC
1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O eb SIDE VIEW TOP VIEW E D PIN#1 IDENTIFICATION END VIEW A L c Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. /C0113 SYMBOL MIN NOM MAX θ A b c D E e 0º 8º 0.05 0.36 0.19 5.13 7.75 5.13 2.03 0.25 0.48 0.25 5.33 8.26 5.38 L 0.51 0.76
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O E1 E e b D cA TOP VIEW SIDE VIEW END VIEW /C01131 L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. SYMBOL θ MIN NOM MAX A b c D E e 0º 8º L 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30
0.65 BSC
1.00 REF
1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A PIN#1 IDENTIFICATION E2E ebD TOP VIEW SIDE VIEW BOTTOM VIEW PIN#1 INDEX AREA FRONT VIEW A LD2 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 E 3.00 E2 1.20 1.30 1.40 e 2.90
0.50 TYP
3.10 L 0.20 0.30 0.40 A2 0.45 0.55 0.65
CAT93C56, CAT93C57 http://onsemi.com PACKAGE DIMENSIONS TDFN8, 3x3 CASE 511AL−01 ISSUE A eb A SIDE VIEW BOTTOM VIEW E D TOP VIEW PIN#1 INDEX AREA PIN#1 ID FRONT VIEW A L Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 REF b 0.23 0.30 0.37 D 2.90 3.00 3.10 D2 2.20 −−− 2.50 E 3.00 E2 1.40 −−− 1.80 e 2.90
0.65 TYP
3.10 L 0.20 0.30 0.40
CAT93C56, CAT93C57 http://onsemi.com Example of Ordering Information CAT93C56, Die Rev. G, New Product Prefix Device # Suffix Company ID CAT 93C56 V Product Number 93C56 I − GT 3 Package I = Industrial (−40°C to +85°C) E = Extended (−40°C to +125°C) Temperature Range L: PDIP V: SOIC, JEDEC X: SOIC, EIAJ (Note 14) Y: TSSOP VP2: TDFN (2 x 3 mm) Lead Finish G: NiPdAu Blank: Matte−Tin T: Tape & Reel 2: 2,000 Units / Reel (Note 14) 3: 3,000 Units / Reel Tape & Reel (Note 16) 9. The device used in the above example is a CAT93C56VI −GT3 (SOIC, Industrial Temperature, NiPdAu, Tape & Reel). CAT93C56/57, Die Rev. E, Mature Product (CAT93C56, Rev. E − Not Recommended for New Designs) Prefix Device # Suffix Company ID CAT 93C56 V Product Number 93C56 I − G Package I = Industrial (−40°C to +85°C) A = Automotive (−40°C to +105°C) E = Extended (−40°C to +125°C) Temperature Range L: PDIP V: SOIC, JEDEC W: SOIC, JEDEC X: SOIC, EIAJ (Note 14) Y: TSSOP ZD4: TDFN (3 x 3 mm) Lead Finish G: NiPdAu Blank: Matte−Tin Die Revision 93C56: E 93C57: E 93C57 −1.8 Operating Voltage Blank: VCC = 2.5 V to 5.5 V 1.8: VCC = 1.8 V to 5.5 V T: Tape & Reel 2: 2,000 Units / Reel (Note 14) 3: 3,000 Units / Reel Rev E (Note 13) Tape & Reel (Note 16) 10.All packages are RoHS−compliant (Lead−free, Halogen−free). 11. The standard lead finish is NiPdAu. 12.The device used in the above example is a CAT93C56VI −1.8−GT3 (SOIC green package, Industrial Temperature, 1.8 Volt to 5.5 Volt Operating Voltage, NiPdAu finish, Tape & Reel). 13.Product die revision letter is marked on top of the package as a suffix to the production date code (e.g., AYWWE). For additional information, please contact your ON Semiconductor sales office. 15.For additional package and temperature options, please contact your nearest ON Semiconductor sales office. 16.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Ree l Packaging Specifications Brochure, BRD8011/D.
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