CAT93C46 ONSEMI | Alldatasheet

Document overview

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  • PDF pages: 13

Technical content

Features

  • High Speed Operation: 2 MHz
  • 1.8 V to 5.5 V Supply V oltage Range
  • Selectable x8 or x16 Memory Organization
  • Self−Timed Write Cycle with Auto−Clear
  • Software Write Protection
  • Power−up Inadvertant Write Protection
  • Low Power CMOS Technology
  • 1,000,000 Program/Erase Cycles
  • 100 Year Data Retention
  • Industrial Temperature Ranges
  • 8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
  • This Device is Pb−Free, Halogen Free/BFR Free and RoHS Compliant*

Figure 1. Functional Symbol Reference Manual, SOLDERRM/D. dimensions section on page 13 of this data sheet.

ORDERING INFORMATION

PDIP (L), SOIC (V, X), TSSOP (Y), TDFN (VP2) (Top View) Chip SelectCS Clock InputSK Serial Data InputDI Serial Data OutputDO Power SupplyVCC GroundGND FunctionPin Name PIN FUNCTION Memory OrganizationORG No ConnectionNC Note: When the ORG pin is connected to VCC, the x16 organization is selected. When it is connected to ground, the x8 organization is selected. If the ORG pin is left unconnected, then an internal pullup device will select the x16 organization. SOIC−8 V, W SUFFIX CASE 751BD PDIP−8 L SUFFIX CASE 646AA TDFN−8 VP2 SUFFIX CASE 511AK TSSOP−8 Y SUFFIX CASE 948AL SOIC−8 X SUFFIX CASE 751BE DI GND ORG SK CS VCC NC 1 DO SOIC (W) (Top View)

Table 1. ABSOLUTE MAXIMUM RATINGS

  1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V

undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns. Table 2. RELIABILITY CHARACTERISTICS (Note 2)

  1. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
  2. Block Mode, V CC = 5 V, 25°C

Table 4. PIN CAPACITANCE (TA = 25°C, f = 1 MHz, VCC = 5 V)

  1. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
  2. Test conditions according to “AC Test Conditions” table.
  3. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100

Table 6. POWER−UP TIMING (Notes 7 and 8)

  1. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
  2. t PUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.

Table 7. A.C. TEST CONDITIONS

intended for use with industry standard microprocessors. voltage required during any write operation. follows the timing shown in Figure 2. state; no change is allowed in Busy state. operations a 16−bit data field (8−bit for X8 organization). EWDS instructions timing is shown in Figure 4. Table 8. INSTRUCTION SET

location returns to a logical “1” state. bits return to a logical “1” state. clocking data write to all memory locations in the device. Figure 5. Write Instruction Timing

Figure 6. Erase Instruction Timing Figure 7. ERAL Instruction Timing Figure 8. WRAL Instruction Timing

00 DN D0

http://onsemi.com PACKAGE DIMENSIONS PDIP−8, 300 mils CASE 646AA−01 ISSUE A D A L eb E eB c TOP VIEW SIDE VIEW END VIEW PIN # 1 IDENTIFICATION Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MS-001. SYMBOL MIN NOM MAX A b c D e L 0.38 2.92 0.36 6.10 1.14 0.20 9.02

2.54 BSC

3.30 5.33 4.95 0.56 7.11 1.78 0.36 10.16 eB 7.87 10.92 E 7.62 8.25 2.92 3.80 3.30 0.46 6.35 1.52 0.25 9.27 7.87

http://onsemi.com PACKAGE DIMENSIONS SOIC 8, 150 mils CASE 751BD−01 ISSUE O E1 E A h θ L c e b D PIN # 1 IDENTIFICATION TOP VIEW SIDE VIEW END VIEW Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MS-012. SYMBOL MIN NOM MAX θ A b c D E e h 0º 8º 0.10 0.33 0.19 0.25 4.80 5.80 3.80

1.27 BSC

1.75 0.25 0.51 0.25 0.50 5.00 6.20 4.00 L 0.40 1.27 1.35

http://onsemi.com PACKAGE DIMENSIONS SOIC−8, 208 mils CASE 751BE−01 ISSUE O eb SIDE VIEW TOP VIEW E D PIN#1 IDENTIFICATION END VIEW A L c Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with EIAJ EDR-7320. /C0113 SYMBOL MIN NOM MAX θ A b c D E e 0º 8º 0.05 0.36 0.19 5.13 7.75 5.13 2.03 0.25 0.48 0.25 5.33 8.26 5.38 L 0.51 0.76

http://onsemi.com PACKAGE DIMENSIONS TSSOP8, 4.4x3 CASE 948AL−01 ISSUE O E1 E e b D cA TOP VIEW SIDE VIEW END VIEW /C01131 L Notes: (1) All dimensions are in millimeters. Angles in degrees. (2) Complies with JEDEC MO-153. SYMBOL θ MIN NOM MAX A b c D E e 0º 8º L 0.05 0.80 0.19 0.09 0.50 2.90 6.30 4.30

0.65 BSC

1.00 REF

1.20 0.15 1.05 0.30 0.20 0.75 3.10 6.50 4.50 0.90 0.60 3.00 6.40 4.40

http://onsemi.com PACKAGE DIMENSIONS TDFN8, 2x3 CASE 511AK−01 ISSUE A PIN#1 IDENTIFICATION E2E ebD TOP VIEW SIDE VIEW BOTTOM VIEW PIN#1 INDEX AREA FRONT VIEW A LD2 Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC MO-229. SYMBOL MIN NOM MAX A 0.70 0.75 0.80 A1 0.00 0.02 0.05 A3 0.20 REF b 0.20 0.25 0.30 D 1.90 2.00 2.10 D2 1.30 1.40 1.50 E 3.00 E2 1.20 1.30 1.40 e 2.90

0.50 TYP

3.10 L 0.20 0.30 0.40 A2 0.45 0.55 0.65

http://onsemi.com Example of Ordering Information Prefix Device # Suffix Company ID CAT 93C46 V Product Number 93C46 I − GT 3 Package I = Industrial (−40°C to +85°C) Temperature Range L: PDIP V: SOIC, JEDEC W: SOIC, JEDEC X: SOIC, EIAJ Y: TSSOP VP2: TDFN (2 x 3 mm) Lead Finish G: NiPdAu Blank: Matte−Tin T: Tape & Reel 2: 2,000 Units / Reel (Note 12) 3: 3,000 Units / Reel Tape & Reel (Note 14) 9. All packages are RoHS −compliant (Lead−free, Halogen−free). 10.The standard lead finish for the SOIC, EIAJ (X) package is Matte−Tin; the standard lead finish for all other packages is NiPdAu. 11. The device used in the above example is a CAT93C46VI−GT3 (SOIC, JEDEC, Industrial Temperature, NiPdAu, Tape & Reel). 12.The SOIC, EIAJ (X) package is available in reels of 2,000 pcs/reel (i.e. CAT93C46XI−T2). All other packages are offered in reels of 3,000 pcs/reel. 13.For additional package and temperature options, please contact your nearest ON Semiconductor Sales office. 14.For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. CAT93C46/D PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative