CAT6095

CAT6095 ONSEMI | Alldatasheet

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Technical content

Characteristics subject to change without notice Digital Output Temperature Sensor

FEATURES

„ JEDEC JC42.4 Compliant Temperature Sensor „ Temperature Range: - 40°C to 125°C „ Supply Range: 3.3 V ± 10% „ I2C /SMBus Interface „ Schmitt Triggers and Noise Suppression Filters on SCL and SDA Inputs „ Low Power CMOS Technology „ RoHS-compliant 2 x 3 x 0.75 mm TDFN package For Ordering Information details, see page 17. PIN CONFIGURATION TDFN (VP2) Note: For the location of Pin 1, please consult the corresponding package drawing. PIN FUNCTIONS Name Description A0, A1, A2 Device Address Input SDA Serial Data Input/Output SCL Serial Clock Input EVENT¯¯¯¯¯¯ Open-drain Event Output VCC Power Supply VSS Ground DAP Backside exposed DAP at VSS

DESCRIPTION

The CAT6095 is a JEDEC JC42.4 compliant Temperature Sensor designed for general purpose temperature measurements requiring a digital output. The CAT6095 measures temperature at least 10 times every second. Temperature readings can be retrieved by the host via the serial interface, and are compared to high, low and crit ical trigger limits stored into internal registers. Over or under limit conditions can be signaled on the open-drain EVENT¯¯¯¯¯¯ pin. The CAT6095 is packaged in space saving TDFN package with exposed backside die attach pads (DAP). The exposed DAP reduces overall thermal resistance, thus providing faster response to thermal changes when compared to SOIC, TSSOP or SOT packages. FUNCTIONAL SYMBOL EVENTCAT6095 SCL SDA A2, A1, A0 VSS VCC8 EVENT SCL SDA VSS VCCA0

Characteristics subject to change without notice ABSOLUTE MAXIMUM RATINGS(1) Parameter Rating Unit Operating Temperature -45 to +130 °C Storage Temperature -65 to +150 °C Voltage on any pin with respect to Ground(2) -0.5 to +6.5 V TEMPERATURE CHARACTERISTICS VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified Parameter Test Conditions/Comments Max Unit 75°C ≤ TA ≤ 95°C, active range ± 1.0 °C 40°C ≤ TA ≤ 125°C, monitor range ± 2.0 °C Temperature Reading Error Class B, JC42.4 compliant -20°C ≤ TA ≤ 125°C, sensing range ± 3.0 °C ADC Resolution 12 Bits Temperature Resolution 0.0625 °C Temperature Conversion Time 100 ms Thermal Resistance(3) θJA Junction-to-Ambient (Still Air) 92 ºC/W D.C. OPERATING CHARACTERISTICS VCC = 3.3 V ± 10%, TA = −40°C to +125°C, unless otherwise specified Symbol Parameter Test Conditions/Comments Min Max Unit ICC TS active 200 μA ISHDN Supply Current TS shut-down; no bus activity 5 μA IL I/O Pin Leakage Current Pin at GND or V CC 5 μA VIL Input Low Voltage -0.5 0.3 x V CC V VIH Input High Voltage 0.7 x V CC V CC + 0.5 V VOL Output Low Voltage I OL = 3 mA, VCC > 2.5 V 0.4 V Notes: (1) Stresses above those listed under “Absolut e Maximum Ratings” may cause permanent dam age to the device. These are stress rat ings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sectio ns of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability. (2) The DC input voltage on any pin should not be lower than -0.5 V or higher than V CC + 0.5 V. The A 0 pin can be raised to a HV level compatible with the use of a DDR3 SPD device sharing the bus with the TS. SCL and SDA inputs can be raised to the maximum limit , irrespective of VCC. (3) Power Dissipation is defined as P J = (T J − TA)/θJA, where T J is the junction temperature and T A is the ambient temperature. The thermal resistance value refers to the case of a package being used on a standard 2-layer PCB.

Characteristics subject to change without notice A.C. CHARACTERISTICS(1) VCC = 3.3 V ± 10%, TA = −40°C to +125°C Symbol Parameter Min Max Units FSCL (2) Clock Frequency 10 400 kHz tHIGH High Period of SCL Clock 600 ns tLOW Low Period of SCL Clock 1300 ns tTIMEOUT (2) SMBus SCL Clock Low Timeout 25 35 ms tR (3) SDA and SCL Rise Time 300 ns tF (3) SDA and SCL Fall Time 300 ns tSU:DAT (4) Data Setup Time 100 ns Data Hold Time (for Input Data) 0 ns tHD:DAT (3) Data Hold Time (for Output Data) 300 900 ns tSU:STA START Condition Setup Time 600 ns tHD:STA START Condition Hold Time 600 ns tSU:STO STOP Condition Setup Time 600 ns tBUF Bus Free Time Between STOP and START 1300 ns Ti Noise Pulse Filtered at SCL and SDA Inputs 100 ns tPU (5) Power-up Delay to Valid Temperature Recording 100 ms PIN CAPACITANCE VCC = 3.3 V, TA = 25°C, f = 1 MHz Symbol Parameter Test Conditions/Comments Min Max Unit SDA, EVENT¯¯¯¯¯¯ Pin Capacitance VIN = 0 8 pF CIN Input Capacitance (other pins) V IN = 0 6 pF Notes: (1) Timing reference points are set at 30%, respectively 70% of VCC, as illustrated in Figure 4. Bus loading must be such as to allow meeting the VIL, VOL as well as the various timing limits. (2) The TS interface will reset itself and will release the SDA line if the SCL line stays low beyond the t TIMEOUT limit. The time-out count is started (and then re-started) on every negative transition of SCL in the time interval between START and STOP. (3) In a “Wired-OR” system (such as I C or SMBus), SDA rise time is determined by bus loading. Since each bus pull-down device must be able to sink the (external) bus pull-up current (in order to meet the V IL and/or VOL limits), it follows that SDA fall time is inherently faster than SDA rise time. SDA rise time can exceed the standard recommended t R limit, as long as it does not exceed t LOW - tHD:DAT - tSU:DAT, where tLOW and t HD:DAT are actual values (rather than spec limits). A shorter t HD:DAT leaves more room for a longer SDA t R, allowing for a more capacitive bus or a larger bus pull-up resistor. At the minimum t LOW spec limit of 1300 ns, the maximum t HD:DAT of 900 ns demands a maximum SDA tR of 300 ns. The CAT6095’s maximum tHD:DAT is < 700 ns, thus allowing for an SDA tR of up to 500 ns at minimum tLOW. (4) The minimum t SU:DAT of 100 ns is a limit recommended by standards. The TS will accept a tSU:DAT of 0 ns. (5) The first valid temperature recording can be expected after t PU at nominal supply voltage.

Characteristics subject to change without notice TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified. TS Active Current (I²C-bus idle) 100 150 200 250 300 -25 0 25 50 75 100 125 TAMB (ºC) ICC (µA) Standby Current (I²C-bus idle, TS shut-down) -25 0 25 50 75 100 125 TAMB (ºC) ISHDN (µA) SDA Output Current 0.0 20.0 40.0 60.0 80.0 100.0 -25 0 25 50 75 100 125 TAMB (ºC) IOL_SDA_TS (mA) VOL = 0.6 V 0.0 10.0 20.0 30.0 40.0 50.0 60.0 -25 0 25 50 75 100 125 TAMB (ºC) IOL_EVENT (mA) VOL = 0.4 V Temperature Read-Out Error -25 0 25 50 75 100 125 TAMB (ºC) ΔT (ºC) Part # 1 Part # 2 A/D Conversion Time -25 0 25 50 75 100 125 TAMB (ºC) TCONV (ms)

Characteristics subject to change without notice TYPICAL PERFORMANCE CHARACTERISTICS VCC = 3.3 V, TA = −25°C to +125°C, unless otherwise specified. TS POR Threshold Voltage 1.50 1.70 1.90 2.10 2.30 2.50 -25 0 25 50 75 100 125 T AMB (ºC) VTH (V) SMBus SCL Clock Low Timeout -25 0 25 50 75 100 125 TAMB (ºC) tTIMEOUT (ms)

Characteristics subject to change without notice PIN DESCRIPTION SCL: The Serial Clock input pin accepts the Serial Clock generated by the Master (Host). SDA: The Serial Data I/O pin receives input data and transmits data stored in t he internal registers. In transmit mode, this pin is open drain. Data is acquired on the positive edge, and is delivered on the negative edge of SCL. A0, A1 and A2: The Address pins set the device address. These pins have on-chip pull-down resistors. programmed to signal over/under temperature limit conditions. POWER-ON RESET (POR) The CAT6095 incorporates Power-On Reset (POR) circuitry which monitors the supply voltage, and then resets (initializes) the internal state machine below (above) a POR trigger level of approximately 2.0 V, i.e. well below the minimum recommended V CC value. The TS powers-up into conversion mode. The internal state machine will operate properly above the POR trigger level, but valid temperature readings can be expected only after the first conversion cycle started and completed at nominal supply voltage. DEVICE INTERFACE The CAT6095 supports I 2C and SMBus data transmission protocols. T hese protocols describe serial communication between transmitters and receivers sharing a 2-wire data bus. Data flow is controlled by a Master device, which generates the serial clock and the START and STOP conditions. The CAT6095 acts as a Slave device. Master and Slave alternate as transmitter and receiver. Up to 8 CAT6095 devices may be present on the bus simultaneously, and can be individually addressed by matching the logic state of the address inputs A0, A1, and A2. I2C/SMBUS PROTOCOL The I2C/SMBus uses two ‘wires’, one for clock (SCL) and one for data (SDA). The two wires are connected to the V CC supply via pull-up resistors. Master and Slave devices connect to the bus via their respective SCL and SDA pins. The transmitting device pulls down the SDA line to ‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’. Data transfer may be initiated only when the bus is not busy (see A.C. Characteristics). During data transfer, the SDA line must remain stable while the SCL line is HIGH. An SDA transition while SCL is HIGH will be interpreted as a START or STOP condition (Figure 1). START The START condition precedes all commands. It consists of a HIGH to LOW transition on SDA while SCL is HIGH. The START acts as a ‘wake-up’ call to all Slaves. Absent a START, a Slave will not respond to commands. STOP The STOP condition completes all commands. It consists of a LOW to HIGH transition on SDA while SCL is HIGH. The STOP tells the Slave that no more data will be written to or read from the Slave. DEVICE ADDRESSING The Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8-bit serial Slave address. The first 4 bits of the Slave address (the preamble) select the Temperature Sensor (TS preamble = 0011) as shown in Figure 2. The next 3 bits, A2, A1 and A0, select one of 8 possible TS Slave devices. The last bit, R/W¯¯, specifies whether a Read (1) or Write (0) operation is being performed ACKNOWLEDGE A matching Slave address is acknowledged (ACK) by the Slave by pulling down the SDA line during the th clock cycle (Figure 3). After that, the Slave will acknowledge all data bytes sent to the bus by the Master. When t he Slave is the transmitter, the Master will in turn acknowledge data bytes in the 9 th clock cycle. The Slave will stop transmitting after the Master does not respond with acknowledge (NoACK) and then issues a STOP. Bus timing is illustrated in Figure 4.

Characteristics subject to change without notice WRITE OPERATIONS Temperature Sensor Register Write To write data to a TS register the Master creates a START condition on the bus, and then sends out the appropriate Slave address (with the R/W¯¯ bit set to ‘0’), followed by an address byte and two data bytes. The matching Slave will acknowledge the Slave address, TS register addr ess and the TS register data (Figure 5). The Master then ends the session by creating a STOP condition on the bus. The STOP completes the TS register update. Note that all registers in the TS are ‘volatile’ meaning any data contained in them is lost when power is removed from the chip. READ OPERATIONS Immediate Read Upon power-up, the Temperature Sensor (TS) address counter is initialized to 00h. The TS address counter will thus point to the Capability Register. This address counter may be updated by subsequent operations. A CAT6095 presented with a Slave address containing a ‘1’ in the R/W¯¯ position will acknowledge the Slave address and will then start transmitting data being pointed at by the current TS register address counter. The Master stops this transmission by responding with NoACK, followed by a STOP (Figure 6). Selective Read The Read operation can be started at an address different from the one stor ed in the address counter, by preceeding the Immediate Read sequence with a ‘data less’ Write operation. The Master sends out a START, Slave address and address byte, but rather than following up with data (as in a Write operation), the Master then issues another START and continuous with an Immediate Read sequence (Figure 7).

Characteristics subject to change without notice TEMPERATURE SENSOR OPERATION The CAT6095 temperature sensor (TS) combines a Proportional to Absolute Temperature (PTAT) sensor with a ∑-Δ modulator, yielding a 12 bit plus sign digital temperature representation. The TS runs on an internal clock, and starts a new conversion cycle at least every 100 ms. The result of the most recent conversion is stored in the Temperature Data Register (TDR) , and remains there following a TS Shut-Down. Reading from the TDR does not interfere with the conversion cycle. The value stored in the TDR is compared against limits stored in the High Limit Register (HLR), the Low Limit Register (LLR) and/or Critical Temperature Register (CTR) . If the measured value is outside the alarm limits or above the critical limit, output function is programmable, via the Configuration Register for interrupt mode, comparator mode and polarity. The temperature limit registers can be Read or Written by the host, via the serial interface. At power- on, all the (writable) internal registers default to 0x0000, and should therefore be initialized by the host to the desired values.The EVENT¯¯¯¯¯¯ output starts out disabled (corresponding to polarity active low); thus preventing irrelevant event bus activity before the limit registers are initialize d. While the TS is enabled (not shut-down), event conditions are normally generated by a change in measured temperature as recorded in the TDR, but limit changes can also trigger events as soon as the new limit creates an event condition, i.e. as ynchronously with the temperature sampling activity. In order to minimize the thermal resistance between sensor and PCB, it is recommended that the exposed backside die attach pad (DAP) be soldered to the PCB ground plane. REGISTERS The CAT6095 contains eight 16-bit wide registers allocated to TS functions, as shown in Table 1. Upon power-up, the internal address counter points to the capability register. Capability Register (User Read Only) This register lists the capabilities of the TS, as detailed in the corresponding bit map. Configuration Register (Read/Write) This register controls the various operating modes of the TS, as detailed in the corresponding bit map. Temperature Trip Point Registers (Read/Write) The CAT6095 features 3 tem perature limit registers, the HLR, LLR and CLR mentioned earlier. The temperature value recorded in the TDR is compared to the various limit values, and the result is used to activate the EVENT¯¯¯¯¯¯ pin. To avoid undesirable EVENT¯¯¯¯¯¯ pin activity, this pin is automatically disabled at power- up to allow the host to initialize the limit registers and the converter to complete the first conversion cycle under nominal supply conditions. Data format is two’s complement with the LSB representing 0.25°C, as detailed in the corresponding bit maps . Temperature Data Register (User Read Only) This register stores the measured temperature, as well as trip status information. B15, B14 and B13 are the trip status bits, representing the relationship between measured temperature and the 3 limit values; these bits are not affected by EVENT st atus or by Configuration register settings. Measured temperature is represented by bits B12 to B0. Data format is two’s complement, where B12 represents the sign, B11 represents 128°C, etc. and B0 represents 0.0625°C. Manufacturer ID Register (Read Only) The manufacturer ID assigned by the PCI-SIG trade organization to the CAT6095 device is 0x1B09. Device ID and Revision Register (Read Only) This register contains manufacturer specific device ID and device revision information.

Table 1. Temperature Sensor Registers

Characteristics subject to change without notice CONFIGURATION REGISTER B15 B14 B13 B12 B11 B10 B9 B8 RFU RFU RFU RFU RFU HYST [1:0] SHDN B7 B6 B5 B4 B3 B2 B1 B0 TCRIT_LOCK EVENT_LOCK CLEAR EVENT_STS EVENT_CTRL TCRIT_ONLY EVENT_POL EVENT_MODE Bit Description B15:B11 Reserved for future use ; can not be written ; should be ignored; will typically read as 0 B10:B9(1) 00: Disable hysteresis 01: Set hysteresis at 1.5°C 10: Set hysteresis at 3°C 11: Set hysteresis at 6°C B8 (5) 0: Thermal Sensor is enabled; temperature readings are updated at sampling rate 1: Thermal Sensor is shut down; temperature reading is frozen to value recorded before SHDN B7 (4) 0: Critical trip register can be updated 1: Critical trip register cannot be modified; this bit can be cleared only at POR B6 (4) 0: Alarm trip registers can be updated 1: Alarm trip registers cannot be modified; this bit can be cleared only at POR B5 (3) 0: Always reads as 0 (self-clearing) 1: Writing a 1 to this position clears an event recording in interrupt mode only B4 (2) 0: EVENT output pin is not being asserted 1: EVENT output pin is being asserted B3 (1) 0: EVENT output disabled; polarity dependent: open-drain for bit B1 = 0 and grounded for B1 = 1 1: EVENT output enabled B2 (7) 0: event condition triggered by alarm or critical temperature limit crossing 1: event condition triggered by critical temperature limit crossing only B1 (1), (6) 0: EVENT output active low 1: EVENT output active high B0 (1) 0: Comparator mode 1: Interrupt mode Notes: (1) Can not be altered (set or cleared) as long as ei ther one of the two lock bits, B6 or B7 is set. (2) This bit is a polarity independent ‘software’ copy of the EVENT¯¯¯¯¯¯ pin, i.e. it is under the control of B3. (3) Writing a ‘1’ to this bit clears an event condition in Interrupt mode, but has no effect in comparator mode. When read, thi s bit always returns 0. Once the measured temperature exceeds the critical limit, setting this bit has no effect (see Figure 5). (4) Cleared at power-on reset (POR). Once set, th is bit can only be cleared by a POR condition. (5) The TS powers up into active mode, i.e. this bit is cleared at power-on reset (POR). When the TS is shut down the ADC is di sabled and the temperature reading is frozen to the most recently recorded value. The TS can not be shut down (B8 can not be set) as long as either one of the two lock bits, B6 or B7 is set. However, the bit can be cleared at any time. (6) The EVENT¯¯¯¯¯¯ output is “open-drain” and requires an exter nal pull-up resistor for either polarity. The “natural” polarity is “active low”, as it allows “wired-or” operation on the EVENT bus. (7) Can not be set as long as lock bit B6 is set.

Characteristics subject to change without notice HIGH LIMIT REGISTER B15 B14 B13 B12 B11 B10 B9 B8 0 0 0 Sign 128°C 64°C 32°C 16°C B7 B6 B5 B4 B3 B2 B1 B0 8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0 LOW LIMIT REGISTER B15 B14 B13 B12 B11 B10 B9 B8 0 0 0 Sign 128°C 64°C 32°C 16°C B7 B6 B5 B4 B3 B2 B1 B0 8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0 TCRIT LIMIT REGISTER B15 B14 B13 B12 B11 B10 B9 B8 0 0 0 Sign 128°C 64°C 32°C 16°C B7 B6 B5 B4 B3 B2 B1 B0 8°C 4°C 2°C 1°C 0.5°C 0.25°C 0 0 TEMPERATURE DATA REGISTER B15 B14 B13 B12 B11 B10 B9 B8 TCRIT HIGH LOW Sign 128°C 64°C 32°C 16°C B7 B6 B5 B4 B3 B2 B1 B0 * When applicable (as defined by Capability bit TRES), unsupported bits will read as 0 Bit Description B15 0: Temperature is below the TCRIT limit 1: Temperature is equal to or above the TCRIT limit B14 0: Temperature is equal to or below the High limit 1: Temperature is above the High limit B13 0: Temperature is equal to or above the Low limit 1: Temperature is below the Low limit

Characteristics subject to change without notice REGISTER DATA FORMAT The values used in the temperature data register and the 3 temperature trip point registers are expressed in two’s complement format. The measured temperature value is expressed with 12-bit resolution, while the 3 trip temperature limits are set with 10-bit resolution. The total temperature range is arbitrarily defined as 256°C, thus yielding an LSB of 0.0625°C for the measured temperature and 0.25°C for the 3 limit values. Bit B12 in all temperature registers represents the sign, with a ‘0’ indicating a positive, and a ‘1’ a negative value. In two’s complement format, negative values are obtained by complementing their positive counterpart and adding a ‘1’, so that the sum of opposite signed numbers, but of equal absolute value, adds up to zero. Note that trailing ‘0’ bits, are ‘0’ irrespective of polarity. Therefore the don’t care bits (B1 and B0) in the 10-bit resolution temperature limit registers, are always ‘0’. 12-Bit Temperature Data Format Binary (B12 to B0) Hex Temperature 1 1100 1001 0000 1C90 −55°C 1 1100 1110 0000 1CE0 −50°C 1 1110 0111 0000 1E70 −25°C 1 1111 1111 1111 1FFF −0.0625°C 0 0000 0000 0000 000 0°C 0 0000 0000 0001 001 +0.0625°C 0 0001 1001 0000 190 +25°C 0 0011 0010 0000 320 +50°C 0 0111 1101 0000 7D0 +125°C EVENT PIN FUNCTIONALITY The EVENT¯¯¯¯¯¯ output reacts to temperature changes as illustrated in Figure 8, and according to the operating mode defined by the Configuration register. In Interrupt Mode, the enabled EVENT¯¯¯¯¯¯ output will be asserted every time the temperature crosses one of the alarm window limits, and can be de-asserted by writing a ‘1’ to the clear event bit (B5) in the configuration register. When the temperature exceeds the critical limit, the event remains asserted as long as the temperature stays above the critical limit and can not be cleared. In Comparator Mode, the EVENT¯¯¯¯¯¯ output is asserted outside the alarm window limits, while in Critical Temperature Mode , EVENT¯¯¯¯¯¯ is asserted only above the critical limit. The exact trip limits are determined by the 3 temperature limit se ttings and the hystersis offsets, as illustrated in Figure 9. Following a TS shut-down request, the converter is stopped and the most recent ly recorded temperature value present in the TDR is frozen; the EVENT¯¯¯¯¯¯ output will continue to reflect the state immediatelly preceding the shut-down command. Therefore, if the state of the EVENT¯¯¯¯¯¯ output creates an undesirable bus condition, appropriate action must be taken either before or after shutting down the TS. This may require clearing the event, disabling the EVENT¯¯¯¯¯¯ output or perhaps changing the EVENT¯¯¯¯¯¯ output polarity. In normal use, events are triggered by a change in recorded temperature, but the CAT6095 will also respond to limit register changes. Whereas recorded temperature values are updated at sampling rate frequency, limits can be modified at any time. The enabled EVENT¯¯¯¯¯¯ output will react to limit changes as soon as the respective registers are updated.This feature may be useful during testing.

Characteristics subject to change without notice PACKAGE OUTLINE DRAWING TDFN 8-Pad 2 x 3 x 0.75 mm (VP2) (1)(2) Notes: (1) All dimensions are in millimeters. (2) Complies with JEDEC standard MO-229. For current Tape and Reel information, download the PDF file from: http://www.catsemi.com/documents/tapeandreel.pdf. PIN#1 IDENTIFICATION E2E ebD TOP VIEW SIDE VIEW BOTTOM VIEW PIN#1 INDEX AREA FRONT VIEW A LD2

Characteristics subject to change without notice EXAMPLE OF ORDERING INFORMATION (1) - (4) TOP MARKING Notes: (1) All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu. (3) The device used in the above example is a CAT6095VP2-GT4 (i.e. TDFN, NiPdAu lead finish, Tape & Reel, 4,000/Reel). (4) For additional package and temperatur e options, please contact your nearest ON Semiconductor Sales office. Prefix Device # Suffix CAT 6095 VP2 – G T4 Product Number 6095 Lead Finish G: NiPdAu Optional Group ID Package VP2: TDFN Tape & Reel T: Tape & Reel 4: 4 ,000/Reel TDFN 8-Pad 2 x 3 x 0.75 mm 321 MH 654 Top Mark Legend (Position) Production Year: A 1 digit mark. Production Month: A 1 digit mark (1 - 9, A, B, C).8 Mark “HM”21 Mark for traceability.64 53

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REVISION HISTORY

16-Sep-08 A Initial Release 3-Nov-08 B Change logo and fine print to ON Semiconductor 01-May-09 C Update Features, Description, Parametric Tables, TS functionality description, Add Top Marking, Ordering Information, Align to JC42.4 TS3000 Standard terminology 05-Oct-09 D Update Parametric Tables, Add Typical Performance Characteristics, Update Package Outline Drawing, Update Example of Ordering Information