CALVC164245IDGGREP

SN74ALVC164245-EP TI1 | Alldatasheet

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(TOP VIEW) 1DIR 1B1 1B2 GND 1B3 1B4 (3.3 V, 5 V) V CCB 1B5 1B6 GND 1B7 1B8 2B1 2B2 GND 2B3 2B4 (3.3 V, 5 V) V CCB 2B5 2B6 GND 2B7 2B8 2DIR 1OE 1A1 1A2 GND 1A3 1A4 V CCA (2.5 V, 3.3 V) 1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V CCA (2.5 V, 3.3 V) 2A5 2A6 GND 2A7 2A8 2OE DESCRIPTION/ORDERING INFORMATION SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 Controlled Baseline One Assembly/Test Site, One Fabrication Site Enhanced Diminishing Manufacturing Sources (DMS) Support Enhanced Product-Change Notification Qualification Pedigree (1) Member of the Texas Instruments Widebus Family Max t pd of 5.8 ns at 3.3 V 24-mA Output Drive at 3.3 V Control Inputs V IH IL Levels Are Referenced to V CCA Voltage Latch-Up Performance Exceeds 250 mA Per JESD (1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails. B port has V CCB which is set to operate at 3.3 V and A port has V CCA which is set to operate at 2.5 V and 3.3 This allows for translation from a 2.5-V to a 3.3-V environment, and vice versa, or from a 3.3-V to a 5-V environment, and vice versa. The SN74ALVC164245 is designed for asynchronous communication between data buses. The control circuitry (1DIR, 2DIR, OE and OE is powered by V CCA To ensure the high-impedance state during power up or power down, the output-enable OE input should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION T A PACKAGE (1) ORDERABLE PART NUMBER TOP-SIDE MARKING SSOP DL Reel of 1000 CALVC164245IDLREP ALVC164245 TSSOP DGG Reel of 2000 CALVC164245IDGGREP ALVC164245 C to C VFBGA GQL CALVC164245IGQLREP Reel of 1000 VC4245EP VFBGA ZQL (Pb-free) CALVC164245IZQLREP C to 125 C TSSOP DGG Reel of 2000 CALVC164245MDGGREP C164245MEP (1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/sc/package. Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2004 2005, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com GQL OR ZQL PACKAGE (TOP VIEW) J H G F E D C B A 21 3 4 65 K SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 TERMINAL ASSIGNMENTS (1) A 1DIR NC NC NC NC OE B 1B2 1B1 GND GND 1A1 1A2 C 1B4 1B3 V CCB V CCA 1A3 1A4 D 1B6 1B5 GND GND 1A5 1A6 E 1B8 1B7 1A7 1A8 F 2B1 2B2 2A2 2A1 G 2B3 2B4 GND GND 2A4 2A3 H 2B5 2B6 V CCB V CCA 2A6 2A5 J 2B7 2B8 GND GND 2A8 2A7 K 2DIR NC NC NC NC OE (1) NC No internal connection FUNCTION TABLE (EACH 8-BIT SECTION) INPUTS OPERATION OE DIR L L B data to A bus L H A data to B bus H X Isolation

www.ti.com To Seven Other Channels 1DIR 1A1 1B1 1OE To Seven Other Channels 2DIR 2A1 2B1 2OE Pin numbers shown are for the DGG and DL packages. Absolute Maximum Ratings (1) SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range for V CCB at V and V CCA at 3.3 V (unless otherwise noted) MIN MAX UNIT V CCA 0.5 4.6 Supply voltage range V V CCB 0.5 Except I/O ports (2) 0.5 V I Input voltage range I/O port A (3) 0.5 V CCA 0.5 V I/O port B (2) 0.5 V CCB 0.5 I IK Input clamp current V I mA I OK Output clamp current V O mA I O Continuous output current mA Continuous current through each V CC or GND 100 mA DGG package θ JA Package thermal impedance (4) DL package C/W GQL/ZQL package T stg Storage temperature range 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) This value is limited to V maximum. (3) This value is limited to 4.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7.

www.ti.com Recommended Operating Conditions (1) Recommended Operating Conditions (1) SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 for V CCB at 3.3 V and V MIN MAX UNIT V CCB Supply voltage 5.5 V V IH High-level input voltage V V CCB V to 3.6 V 0.7 V IL Low-level input voltage V V CCB 4.5 V to 5.5 V 0.8 V IB Input voltage V CCB V V OB Output voltage V CCB V I OH High-level output current mA I OL Low-level output current mA Δ Δ v Input transition rise or fall rate ns/V CALVC16245I T A Operating free-air temperature C CALVC16245M 125 (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. for V CCA at 2.5 V and 3.3 V MIN MAX UNIT V CCA Supply voltage 2.3 3.6 V V CCA 2.3 V to 2.7 V 1.7 V IH High-level input voltage V V CCA V to 3.6 V V CCA 2.3 V to 2.7 V 0.7 V IL Low-level input voltage V V CCA V to 3.6 V 0.8 V IA Input voltage V CCA V V OA Output voltage V CCA V V CCA 2.3 V I OH High-level output current mA V CCA V V CCA 2.3 V I OL Low-level output current mA V CCA V Δ Δ v Input transition rise or fall rate ns/V CALVC16245I T A Operating free-air temperature C CALVC16245M 125 (1) All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004.

www.ti.com Electrical Characteristics SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 over recommended operating free-air temperature range for V CCA 2.7 V to 3.6 V and V CCB 4.5 V to 5.5 V (unless otherwise noted) CALVC164245I CALVC164245M PARAMETER TEST CONDITIONS V CCA V CCB UNIT MIN TYP (1) MAX MIN TYP (1) MAX 2.7 V to I OH 100 µ A V CC 0.2 V CC 0.2 3.6 V 2.7 V 2.2 2.2 B to A I OH mA V 2.4 2.4 I OH mA V V OH V 4.5 V 4.3 4.3 I OL 100 µ A 5.5 V 5.3 5.3 A to B 4.5 V 3.7 3.7 I OL mA 5.5 V 4.7 4.7 2.7 V to I OL 100 µ A 0.2 0.2 3.6 V B to A I OL mA 2.7 V 0.4 0.4 I OL mA V 0.55 0.55 V OL V 4.5 V to I OL 100 µ A 0.2 0.2 5.5 V A to B 4.5 V to I OL mA 0.55 0.55 5.5 V Control I I V I V CCA CCB or GND 3.6 V 5.5 V µ A inputs A or B I OZ (2) V O V CCA CCB or GND 3.6 V 5.5 V µ A port V I V CCA CCB or GND, I CC 5.5 V 5.5 V µ A I O One input at V CCA CCB 0.6 V to 4.5 V to Δ I CC (3) 750 750 µ A Other inputs at V CCA CCB or GND 3.6 V 5.5 V Control C i V I V CCA CCB or GND 3.3 V V 6.5 6.5 pF inputs A or B C io V O V CCA CCB or GND 3.3 V 3.3 V 8.5 8.5 pF port (1) All typical values are at V CCA 3.3 V and V CCB T A (2) For I/O ports, the parameter I OZ includes the input leakage current. (3) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at or the associated V CC

www.ti.com Electrical Characteristics SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 over recommended operating free-air temperature range for V CCA 2.3 V to 2.7 V and V CCB V to 3.6 V (unless otherwise noted) CALVC164245I CALVC164245M PARAMETER TEST CONDITIONS V CCA V CCB UNIT MIN MAX MIN MAX I OH 100 µ A 2.3 V to 2.7 V V to 3.6 V V CCA 0.2 V CCA 0.2 B to A I OH mA 2.3 V V to 3.6 V 1.7 1.7 V OH I OH mA 2.7 V V to 3.6 V 1.8 1.8 V I OL 100 µ A 2.3 V to 2.7 V V to 3.6 V V CCB 0.2 V CCB 0.2 A to B I OL mA 2.3 V to 2.7 V V 2.2 2.2 I OL 100 µ A 2.3 V to 2.7 V V to 3.6 V 0.2 0.2 B to A I OL mA 2.3 V V to 3.6 V 0.6 0.6 V OL V I OL 100 µ A 2.3 V to 2.7 V V to 3.6 V 0.2 0.2 A to B I OL mA 2.3 V V 0.55 0.55 I I Control V I V CCA CCB or GND 2.3 V to 2.7 V V to 3.6 V µ A inputs I OZ (1) A or B V O V CCA CCB or GND 2.3 V to 2.7 V V to 3.6 V µ A port V I V CCA CCB or GND, I CC 2.3 V to 2.7 V V to 3.6 V µ A I O One input at V CCA CCB 0.6 Δ I CC (2) 2.3 V to 2.7 V V to 3.6 V 750 750 µ A Other inputs at V CCA CCB or GND (1) For I/O ports, the parameter I OZ includes the input leakage current. (2) This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than at or the associated V CC

www.ti.com Switching Characteristics Switching Characteristics Operating Characteristics SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure CALVC16245I V CCB 3.3 V V CCB V 0.5 V 0.3 V FROM TO PARAMETER UNIT (INPUT) (OUTPUT) V CCA 2.5 V V CCA 3.3 V V CCA 2.7 V 0.2 V 0.3 V MIN MAX MIN MAX MIN MAX A B 7.6 5.9 5.8 t pd ns B A 7.6 6.7 1.2 5.8 t en OE B 11.5 9.3 8.9 ns t dis OE B 10.5 9.2 2.1 9.5 ns t en OE A 12.3 10.2 9.1 ns t dis OE A 9.3 2.9 8.6 ns over recommended operating free-air temperature range (unless otherwise noted) (see Figure through Figure CALVC16245M V CCB 3.3 V V CCB V 0.5 V 0.3 V FROM TO PARAMETER UNIT (INPUT) (OUTPUT) V CCA 2.5 V V CCA 3.3 V V CCA 2.7 V 0.2 V 0.3 V MIN MAX MIN MAX MIN MAX A B 8.6 6.9 6.8 t pd ns B A 8.6 7.7 1.2 6.8 t en OE B 12.5 10.3 9.9 ns t dis OE B 11.5 10.2 2.1 10.5 ns t en OE A 14.5 11.2 10.1 ns t dis OE A 11.3 2.9 10.6 ns T A C V CCB 3.3 V V CCB V PARAMETER TEST CONDITIONS V CCA 2.5 V V CCA 3.3 V UNIT TYP TYP Outputs enabled (B) C L pF, f MHz Outputs disabled (B) C pd Power dissipation capacitance pF Outputs enabled (A) 118 C L pF, f MHz Outputs disabled (A)

www.ti.com Power-Up Considerations (1) SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 TI level-translation devices offer an opportunity for successful mixed-voltage signal design. A proper power-up sequence always should be followed to avoid excessive supply current, bus contention, oscillations, or other anomalies caused by improperly biased device pins. To guard against such power-up problems, take these precautions: Connect ground before any supply voltage is applied. Power up the control side of the device CCA for all four of these devices). Tie OE to V CCA with a pullup resistor so that it ramps with V CCA Depending on the direction of the data path, DIR can be high or low. If DIR high is needed data to B bus), ramp it with V CCA Otherwise, keep DIR low. (1) Refer to the TI application report, Texas Instruments Voltage-Level-Translation Devices literature number SCEA021.

www.ti.com PARAMETER MEASUREMENT INFORMATION VOHB VOLB From Output CL = 30 pF (see Note A) LOAD CIRCUIT VCCB = 6 V Open GND 500 Ω 500 Ω tPLH tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ VCCA/2VCCA/2 VCCA/2 VCCA/2 VCCA 0 V 1.5 V 1.5 V VOHB VOLB 0 V 1.5 V VOL + 0.3 V 1.5 V VOH − 0.3 V 0 V Input VCCA VCCB VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output tpd tPLZ/tPZL tPHZ/tPZH Open VCCB = 6 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω , tr≤ 2 ns, tf≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 V CCA 2.5 V 0.2 V to V CCB 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION VCCA/2 VCCA/2 1.5 V1.5 V VOHA VOLA From Output Under Test CL = 30 pF (see Note A) LOAD CIRCUIT S1 Open GND 500 Ω 500 Ω Output Control (low-level enabling) Output Waveform 1 S1 at 2 × VCCA (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 0 V VOL + 0.15 V VOH − 0.15 V 0 V 2.7 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES tpd tPLZ/tPZL tPHZ/tPZH Open 2 × VCCA GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR≤ 10 MHz, ZO = 50 Ω , tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. tPHL 1.5 V 1.5 V 2.7 V 0 V VOHA VOLA Input Output VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VCCA/2 VCCA/2 tPLH 2 × VCCA VCCA SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 V CCB 3.3 V 0.3 V to V CCA 2.5 V 0.2 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION tPLH VOH VOL From Output CL = 50 pF (see Note A) LOAD CIRCUIT

2 VCCB

500 Ω 500 Ω tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 2 VCCB (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 1.5 V1.5 V 1.5 V 1.5 V 2.7 V 0 V 50% VCCB 50% VCCB VOH VOL 0 V 20% VCCB 50% VCCB 80% VCCB 0 V Input 2.7 V ≈ VCCB VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output tpd tPLZ/tPZL tPHZ/tPZH Open 50% VCCB NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 V CCA 3.3 V 0.3 V to V CCB V 0.5 V Figure Load Circuit and Voltage Waveforms

www.ti.com PARAMETER MEASUREMENT INFORMATION VOHA VOLA From Output CL = 50 pF (see Note A) LOAD CIRCUIT VCCA = 6 V Open GND 500 Ω 500 Ω tPLH tPHL Output Control (low-level enabling) Output Waveform 1 S1 at 6 V (see Note B) Output Waveform 2 S1 at GND (see Note B) tPZL tPZH tPLZ tPHZ 1.5 V1.5 V 1.5 V 1.5 V 3 V 0 V 1.5 V 1.5 V VOHA VOLA 0 V 1.5 V VOL + 0.3 V 1.5 V VOH − 0.3 V 0 V Input 3 V ≈ 3 V VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES Output tpd tPLZ/tPZL tPHZ/tPZH Open VCCA = 6 V GND TEST S1 NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤/char????????10 MHz, ZO = 50 Ω , tr ≤/char????????2.5 ns, tf ≤/char????????2.5 ns. D. The outputs are measured one at a time, with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as ten. G. tPLH and tPHL are the same as tpd. SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 V CCB V 0.5 V to V CCA 2.7 V and 3.3 V 0.3 V Figure Load Circuit and Voltage Waveforms

www.ti.com Tj − Continuous – ° C 120 125 130 135 140 145 150 155 160 Electromigration Fail Mode Years Estimated LIfe Wirebond Voiding Fail Mode SN74ALVC164245-EP 16-BIT 2.5-V TO 3.3-V/3.3-V TO 5-V LEVEL-SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS SCAS774A JUNE 2004 REVISED SEPTEMBER 2005 74ALVC164245MDGG*EP Estimated Device Life at Elevated Temperatures Electromigration and Wirebond Voiding Fail Modes Silicon operating life design goal is years at 105 C junction temperature.

Orderable Device Status(1) Package Type Package Drawing Pins Package Qty Eco Plan(2) Lead/Ball FinishMSL Peak Temp (3) CALVC164245IDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CALVC164245IDLREP ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM CALVC164245MDGGREP ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/05612-01XE ACTIVE SSOP DL 48 1000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/05612-01YE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM V62/05612-02YE ACTIVE TSSOP DGG 48 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1)The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2)Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontentfor the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS):TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br):TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74ALVC164245-EP :

• Catalog:SN74ALVC164245 NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product PACKAGE OPTION ADDENDUM www.ti.com 18-Sep-2008 Addendum-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CALVC164245IDGGREP TSSOP DGG 48 2000 346.0 346.0 41.0 CALVC164245IDLREP SSOP DL 48 1000 346.0 346.0 49.0 CALVC164245MDGGREP TSSOP DGG 48 2000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 5-Aug-2008 Pack Materials-Page 2

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040048/E 12/01

48 PINS SHOWN

0.730 (18,54) 0.720 (18,29) 4828 0.370 (9,40) (9,65) 0.380 Gage Plane DIM 0.420 (10,67) 0.395 (10,03) A MIN A MAX 0.010 (0,25) PINS ** 0.630 (16,00) (15,75) 0.620 0.010 (0,25) Seating Plane 0.020 (0,51) 0.040 (1,02) 0.008 (0,203) 0.0135 (0,343) 0.008 (0,20) MIN A 0.110 (2,79) MAX 0.299 (7,59) 0.291 (7,39) 0.004 (0,10) M0.005 (0,13) 0.025 (0,635) 0°–/C02578° 0.005 (0,13) NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). D. Falls within JEDEC MO-118

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 4040078/F 12/97 0,25 0,15 NOM Gage Plane 6,00 6,20 8,30 7,90 0,75 0,50 Seating Plane 0,27 0,17 A 1,20 MAX M0,08 0,10 0,50 0°–8° 14,10 13,90 48DIM A MAX A MIN PINS ** 12,40 12,60 17,10 16,90 0,15 0,05 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

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