SN74AHCT1G14-Q1 TI | Alldatasheet

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SN74AHCT1G14-Q1 Automotive Single Schmitt-Trigger Inverter Gate

1 Features

  • AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B
  • Operating range of 4.5 V to 5.5 V
  • Low power consumption, 10-µA maximum ICC
  • ±8-mA output drive at 5 V
  • Inputs are TTL-voltage compatible
  • Latch-up performance exceeds 250 mA per JESD 17

2 Applications

  • Synchronize inverted clock inputs
  • Debounce a switch
  • Invert a digital signal

3 Description

The SN74AHCT1G14-Q1 is a single inverter gate. The device performs the Boolean function Y = A. The device functions as an independent inverter gate, but because of the Schmitt action, gates may have different input threshold levels for positive-going (V T+) and negative-going (VT−) signals.

Package Information

PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) SN74AHCT1G14-Q1 DCK (SC-70, 5) 2 mm × 2.1 mm 2 mm × 1.25 mm DBV (SOT-23, 5) 2.9 mm x 2.8 mm 2.9 mm x 1.6 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable (3) The body size (length × width) is a nominal value and does not include pins. Simplified Logic Diagram (Positive Logic) SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

11 Mechanical, Packaging, and Orderable

SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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4 Pin Configuration and Functions

5 VCC

Figure 4-1. SN74AHCT1G14-Q1 DBV Package, 5-Pin SOT-23; DCK Package, 5-Pin SC-70 (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. NC 1 I No Connect A 2 I Data Input GND 3 G Ground Y 4 O Data Output VCC 5 P Power (1) I = input, O = output, I/O = input or output, G = ground, P = power. www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74AHCT1G14-Q1

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage –0.5 7 V VI Input voltage range -0.5 7 V VO Output voltage range -0.5 VCC + 0.5 V VO Voltage range applied to any output in the high-impedance or power-off state -0.5 4.6 V IIK Input clamp current(2) VI < 0 –20 mA IOK Output clamp current(2) VO < 0 or VO > VCC –20 20 mA IO Continuous output current VO = 0 to VCC –25 25 mA IO Continuous output current through VCC or GND –50 50 mA TJ Junction temperature 150 °C Tstg Storage temperature –65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

5.2 ESD Ratings

V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) HBM ESD Classification Level 2 ±200 V Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B ±100 (1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN MAX UNIT VCC Supply Voltage 3 5.5 V VIH high-level input voltage VCC= 3V 1.4 V VCC= 4.5 V to 5.5 V 2 V VIL low-level input voltage VCC= 3 V 0.53 V VCC= 4.5 V to 5.5 V 0.8 V VI input voltage 0 5.5 V VO output voltage 0 VCC V IOH high-level output current VCC= 5 V ± 0.5 V -8 mA IOL low-level output current VCC= 5 V ± 0.5 V 8 mA Δt/Δv input transition rise or fall rate VCC= 5 V ± 0.5 V 20 nS/V TA Operating free-air temperature -40 125 °C SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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5.4 Thermal Information

THERMAL METRIC(1) SN74AHCT1G14-Q1 UNITDBV (SOT-23) DCK (SC70)

5 PINS 5 PINS

RθJA Junction-to-ambient thermal resistance 278.0 293.4 °C/W RθJC(top) Junction-to-case (top) thermal resistance 180.5 208.8 °C/W RθJB Junction-to-board thermal resistance 184.4 180.6 °C/W ΨJT Junction-to-top characterization parameter 115.4 120.6 °C/W ΨJB Junction-to-board characterization parameter 183.4 179.5 °C/W RθJC(bot) Junction-to-case (bottom) thermal resistance N/A N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

5.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C -40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX VT+ Positive-going input threshold voltage 5.5 V 1.1 2 1.1 2 V VT- Negative-going input threshold voltage ΔVT Hysteresis (V T+ − VT−) VOH IOH = -8 mA 4.5 V 3.94 3.8 V VOL IOL = 50 µA 4.5 V 0.1 0.1 V IOL = 8 mA 4.5 V 0.36 0.44 V II VI = 5.5 V or GND 0 V to 5.5 V -0.1 0.1 -1 1 µA ICC VI = VCC or GND 5.5 V 1 10 µA ΔICC One input at 3.4 V, other inputs at VCC or GND 5.5 V 1.35 1.5 mA Ci VI = VCC or GND 5 V 4 10 pF CO VO = VCC or GND 5 V 15 pF CPD No load, f 10 MHz 5 V 14 pF

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE VCC TA = 25°C -40°C to 85°C -40°C to 125°C UNIT MIN TYP MAX MIN TYP MAX MIN TYP MAX TPHL A Y CL = 15 pF 5 V ± 0.5 V 4 7 1 8 1 9 ns TPLH A Y CL = 15 pF 5 V ± 0.5 V 4 7 1 8 1 9 ns TPHL A Y CL = 50 pF 5 V ± 0.5 V 5.5 8 1 9 1 10 ns TPLH A Y CL = 50 pF 5 V ± 0.5 V 5.5 8 1 9 1 10 ns www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74AHCT1G14-Q1

5.7 Typical Characteristics

TA = 25°C (unless otherwise noted) IOH (mA) VOH (V) 4.3 4.35 4.4 4.45 4.5 4.55 4.6 4.65 4.7 4.75 4.8 4.85 4.9 4.95 -40°C 25°C 125°C Figure 5-1. Output Voltage vs Current in HIGH State; 5-V Supply IOL (mA) VOL (V) 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 -40°C 25°C 125°C Figure 5-2. Output Voltage vs Current in LOW State; 5-V Supply SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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6 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 3 ns. For clock inputs, fmax is measured when the input duty cycle is 50%. The outputs are measured one at a time with one input transition per measurement. CL (1) From Output Under Test Test Point (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs 50%Input 50% VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Output 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms Propagation Delays VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% (1) The greater between tr and tf is the same as tt. Figure 6-3. Voltage Waveforms, Input and Output Transition Times www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74AHCT1G14-Q1

7 Detailed Description

7.1 Overview

The SN74AHCT1G14-Q1 is a single inverter gate. The device performs the Boolean function Y = A. The device functions as an independent inverter gate, but because of the Schmitt action, gates may have different input threshold levels for positive-going (VT+) and negative-going (VT−) signals.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Balanced CMOS Push-Pull Outputs

This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important for the output power of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs should be left disconnected.

7.3.2 TTL-Compatible CMOS Inputs

This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL logic devices by having a reduced input voltage threshold. TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics . The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will result in excessive power consumption and could cause oscillations. More details can be found in the Implications of Slow or Floating CMOS Inputs application report. Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be terminated at V CC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ resistor is recommended and will typically meet all requirements.

7.3.3 CMOS Schmitt-Trigger Inputs

This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics table, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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7.3.4 Clamp Diode Structure

The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have negative clamping diodes only as shown in Figure 7-1. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND LogicInput Output VCCDevice -IIK +IOK -IOK Figure 7-1. Electrical Placement of Clamping Diodes for Each Input and Output

7.4 Device Functional Modes

Table 7-1 lists the device function modes. Table 7-1. Function Table INPUT(1) A OUTPUT(1) Y H L L H (1) H = High Voltage Level, L = Low Voltage Level www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74AHCT1G14-Q1

8 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.

8.1 Application Information

The SN74AHCT1G14-Q1can be used to add an additional stage to a counter with an external flip-flop. Because counters use a negative edge trigger, the flip-flop's clock input must be inverted to provide this function. Having Schmitt-trigger inputs is important in this application to eliminate any noise issues that could impact the counting function which could lead to incorrect frequency division. The SN74AHCT1G14-Q1 is a high drive CMOS device that can be used for implementing inversion logic with a high output drive.

8.2 Typical Application

Figure 8-1. Typical Application Block Diagram

8.2.1 Design Requirements

8.2.1.1 Power Considerations

Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions . The supply voltage sets the electrical characteristics of the device as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74AHCT1G14-Q1 plus the maximum static supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Be sure to not exceed the maximum total current through VCC listed in the Absolute Maximum Ratings. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74AHCT1G14-Q1 plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum Ratings. The SN74AHCT1G14-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50 pF. SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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The SN74AHCT1G14-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in the CMOS Power Consumption and Cpd Calculation application note. Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application note. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device.

8.2.1.2 Input Considerations

Input signals must cross VIL(max) Vt-(min) to be considered a logic LOW, and VIH(min) Vt+(max) to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74AHCT1G14-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-k Ω resistor value is often used due to these factors. The SN74AHCT1G14-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power consumption, and reduction in device reliability. The SN74AHCT1G14-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs. Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical Characteristics. This hysteresis value will provide the peak-to-peak limit. Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without causing huge increases in power consumption. The typical additional current caused by holding an input at a value other than VCC or ground is plotted in the Typical Characteristics. Refer to the Feature Description section for additional information regarding the inputs for this device.

8.2.1.3 Output Considerations

The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74AHCT1G14-Q1

8.2.2 Detailed Design Procedure

  1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit; by design, however, it will optimize performance. This can be accomplished by providing short, appropriately sized traces from the SN74AHCT1G14-Q1 to one or more of the receiving devices. 3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. Doing this will not violate the maximum output current from the Absolute Maximum Ratings. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd Calculation.

8.2.3 Application Curves

Input ± 32 kHz 24 ± 1 kHz Figure 8-2. Application Timing Diagram

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1- μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example.

8.4 Layout

8.4.1 Layout Guidelines

When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient. SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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8.4.2 Layout Example

0.1 F Bypass capacitor placed close to the device Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation NC A GND VCC Y Avoid 90° corners for signal lines Figure 8-3. Example Layout for the SN74AHCT1G14-Q1 www.ti.com SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74AHCT1G14-Q1

9 Device and Documentation Support

TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device, generate code, and develop solutions are listed below.

9.1 Documentation Support

9.1.1 Related Documentation

For related documentation, see the following:

  • Texas Instruments, CMOS Power Consumption and Cpd Calculation application note
  • Texas Instruments, Designing With Logic application note
  • Texas Instruments, Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application note
  • Texas Instruments, Implications of Slow or Floating CMOS Inputs application note

9.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

9.3 Support Resources

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.

9.4 Trademarks

TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.

9.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

9.6 Glossary

TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from Revision * (August 2023) to Revision A (January 2024) Page

  • Added thermal values for DBV package: RθJA = 278.0, RθJC(top) = 180.5, RθJB = 184.4, ΨJT = 115.4, ΨJB

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74AHCT1G14-Q1 SCLS953A – AUGUST 2023 – REVISED JANUARY 2024 www.ti.com

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www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CAHCT1G14QDBVRQ1 Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 36EH CAHCT1G14QDBVRQ1.A Active Production SOT-23 (DBV) | 5 3000 | LARGE T&R Yes SN Level-1-260C-UNLIM -40 to 125 36EH CAHCT1G14QDCKRQ1 Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1O5 CAHCT1G14QDCKRQ1.A Active Production SC70 (DCK) | 5 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM -40 to 125 1O5 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AHCT1G14-Q1 : Addendum-Page 1

www.ti.com 23-May-2025

  • Catalog : SN74AHCT1G14 NOTE: Qualified Version Definitions:
  • Catalog - TI's standard catalog product Addendum-Page 2

PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 4-Feb-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CAHCT1G14QDBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0 CAHCT1G14QDCKRQ1 SC70 DCK 5 3000 190.0 190.0 30.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 0.22

0.08 TYP

0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15

0.00 TYP

5X 0.5 0.3 0.6

0.3 TYP

0 TYP

1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.

0.2 C A B

0.1 C SCALE 4.000

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MAX

0.07 MIN

5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4

www.ti.com PACKAGE OUTLINE C 0.22 0.15 2.4 1.8 2X 0.65 1.3

1.1 MAX

0.1

0.0 TYP

5X 0.33 0.15 NOTE 5

0.1 C A B

0.46

0.26 TYP

1.3 4X 0 -12 4X 4 -15 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600

www.ti.com EXAMPLE BOARD LAYOUT 5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/G 11/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL

www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/G 11/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4

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