SN74AHCT1G125-Q1_V04 TI | Alldatasheet
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Technical content
SN74AHCT1G125-Q1 Automotive Single Bus Buffer Gate with 3-State Output
1 Features
- Qualified for automotive applications
- Operating range of 3V to 5.5V
- Max tpd of 6ns at 5V
- Low power consumption, 10µA max ICC
- ±8-mA output drive at 5V
- Inputs are TTL-voltage compatible
2 Applications
- Enable or disable a digital signal
- Controlling an indicator LED
- Translation between communication modules and system controllers
3 Description
The SN74AHCT1G125-Q1 is a single bus buffer gate/ line driver with 3-state output. The output is disabled when the output-enable ( OE) input is high. When OE is low, true data is passed from the A input to the Y output.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) SN74AHCT1G125- DBV (SOT-23, 5) 2.9mm × 2.8mm 2.9mm × 1.6mm DCK (SC70, 5) 2.0mm × 2.1mm 2mm × 1.25mm DTX (X2SON, 5) 1.1mm x 0.85mm 1.1mm x 0.85mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable. (3) The body size (length × width) is a nominal value and does not include pins. SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
11 Mechanical, Packaging, and Orderable
SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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4 Pin Configuration and Functions
Figure 4-1. DBV Package, 5-Pin SOT-23; DCK Package (Top View) 1OE GND 4 Y
5 VCC
Figure 4-2. DTX Package, 5-Pin X2SON (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NO. NAME
1 OE I Output Enable
2 A I Input A
3 GND — Ground Pin
4 Y O Output Y
5 VCC — Power Pin
(1) Signal Types: I = Input, O = Output, I/O = Input or Output www.ti.com SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74AHCT1G125-Q1
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) MIN MAX UNIT VCC Supply voltage range –0.5 7 V VI (2) Input voltage range –0.5 7 V VO (2) Output voltage range –0.5 VCC + 0.5 V IIK Input clamp current (VI < 0) –20 mA IOK Output clamp current (VO < 0 or VO > VCC) ±20 mA IO Continuous output current (VO = 0 to VCC) ±25 mA Continuous current through VCC or GND ±50 mA Tstg Storage temperature range –65 150 °C (1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002(1) ±2000 V (1) AEC Q100-002 indicates that HBM stressing must be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage 3 5.5 V VIH High-level input voltage VCC = 3.0 V 1.4 V VCC = 4.5 V to 5.5 V 2 VIL Low-level input voltage VCC = 3.0 V 0.53 V VCC = 4.5 V to 5.5 V 0.8 VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current –8 mA IOL Low-level output current 8 mA Δt/Δv Input transition rise or fall rate 20 ns/V TA Operating free-air temperature –40 125 °C (1) All unused inputs of the device must be held at VCC or GND for specified device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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5.4 Thermal Information
THERMAL METRIC(1) SN74AHCT1G125-Q1 UNITDBV (SOT-23) DCK (SC-70) DTX (X2SON) 5 5 5 RθJA Junction-to-ambient thermal resistance 278.0 293.4 184.7 °C/W (1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report (SPRA953).
5.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC TA = 25°C MIN MAX UNIT MIN TYP MAX VOH IOH = –50 µA 3 V 2.9 3 2.9 V 4.5 V 4.4 4.5 4.4 IOH = –4 mA 3 V 2.58 2.34 IOH = –8 mA 4.5 V 3.94 3.66 VOL IOL = 50 µA 3 V and 4.5 V 0.1 0.1 VIOL = 4 mA 3 V 0.36 0.52 IOL = 8 mA 4.5 V 0.36 0.52 II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 µA IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 µA ICC VI = VCC or GND, IO = 0, OE high or low
3 V and
5.5 V 1 10 µA
ΔICC (1) One input at 3.4 Other input at VCC or GND 5.5 V 1.35 1.5 mA Ci VI = VCC or GND 5 V 4 10 10 pF Co VO = VCC or GND 5 V 10 pF (1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC. www.ti.com SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74AHCT1G125-Q1
5.6 Switching Characteristics, VCC = 3 V ± 0.3 V over recommended operating free-air temperature range, VCC = 3 V ± 0.3 V (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH A Y CL = 15 pF 5.6 8 12 ns tPHL 5.6 8 12 tPZH OE Y CL = 15 pF 5.4 8 11.5 ns tPZL 5.4 8 11.5 tPHZ OE Y CL = 15 pF 6.5 9.7 14.5 ns tPLZ 6.5 9.7 14.5 tPLH A Y CL = 50 pF 8.1 11.5 16 ns tPHL 8.1 11.5 16 tPZH OE Y CL = 50 pF 7.9 11.5 15 ns tPZL 7.9 11.5 15 tPHZ OE Y CL = 50 pF 8 13.2 18 ns tPLZ 8 13.2 18 5.7 Switching Characteristics, VCC = 5 V ± 0.5 V over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Load Circuit and Voltage Waveforms) PARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE TA = 25°C MIN MAX UNIT MIN TYP MAX tPLH A Y CL = 15 pF 3.8 5.5 8.5 ns tPHL 3.8 5.5 8.5 tPZH OE Y CL = 15 pF 3.6 5.1 7.5 ns tPZL 3.6 5.1 7.5 tPHZ OE Y CL = 15 pF 4.8 6.8 10 ns tPLZ 4.8 6.8 10 tPLH A Y CL = 50 pF 5.3 7.5 10.5 ns tPHL 5.3 7.5 10.5 tPZH OE Y CL = 50 pF 5.1 7.1 9.5 ns tPZL 5.1 7.1 9.5 tPHZ OE Y CL = 50 pF 7 8.8 12 ns tPLZ 7 8.8 12
5.8 Operating Characteristics
VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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6 Parameter Measurement Information
A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 6-1. Load Circuit and Voltage Waveforms TEST S1 tPLH/tPHL Open tPLZ/tPZL VCC tPHZ/tPZH GND Open Drain VCC www.ti.com SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74AHCT1G125-Q1
7 Detailed Description
7.1 Overview
For specified high-impedance state during power up or power down, OE should be tied to V CC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
7.2 Functional Block Diagram
Figure 7-1. Logic Diagram (Positive Logic)
7.3 Device Functional Modes
Table 7-1. Function Table INPUTS OUTPUT OE A Y L H H L L L H X Z SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
In this application, three 2-input AND gates are combined to produce a 4-input AND gate function as shown in Figure 8-1. The fourth gate can be used for another application in the system, or the inputs can be grounded and the channel left unused. The SN74AHCT1G125-Q1 is used to directly control the RESET pin of a motor controller. The controller requires four input signals to all be HIGH before being enabled, and should be disabled in the event that any one signal goes LOW. The 4-input AND gate function combines the four individual reset signals into a single active-low reset signal.
8.2 Typical Application
Figure 8-1. Typical Application Block Diagram
8.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions . Each V CC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1- μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the following layout example.
8.4 Layout
8.4.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases, functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a triple-input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left unconnected because the undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular unused input depends on the function of the device. Generally, the inputs are tied to GND or V CC, whichever makes more sense for the logic function or is more convenient. www.ti.com SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74AHCT1G125-Q1
8.4.2 Layout Example
0.1 μ F Bypass capacitor placed close to the device Recommend GND flood fill for improved signal isolation, noise reduction, and thermal dissipation OE A GND VCC Y Avoid 90° corners for signal lines Figure 8-2. Example Layout for the SN74AHCT1G125-Q1 SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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9 Device and Documentation Support
9.1 Documentation Support (Analog)
9.1.1 Related Documentation
The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 9-1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY SN74AHCT1G125-Q1 Click here Click here Click here Click here Click here
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. Changes from Revision D (October 2023) to Revision E (October 2024) Page Changes from Revision C (July 2023) to Revision D (October 2023) Page www.ti.com SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74AHCT1G125-Q1
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74AHCT1G125-Q1 SCLS504E – MAY 2003 – REVISED OCTOBER 2024 www.ti.com
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www.ti.com 31-Oct-2024 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead finish/ Ball material (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CAHCT1G125QDBVRQ1 ACTIVE SOT-23 DBV 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 37PH Samples CAHCT1G125QDCKRG4Q ACTIVE SC70 DCK 5 3000 RoHS & Green Call TI | NIPDAU Level-1-260C-UNLIM -40 to 125 BMS Samples CAHCT1G125QDCKRQ1 ACTIVE SC70 DCK 5 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM -40 to 125 BMS Samples CAHCT1G125WDTXRQ1 ACTIVE X2SON DTX 5 3000 RoHS & Green SN Level-1-260C-UNLIM -40 to 125 7 Samples PCAHCT1G125QDTXRQ1 ACTIVE X2SON DTX 5 3000 TBD Call TI Call TI -40 to 125 Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 1
www.ti.com 31-Oct-2024 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AHCT1G125-Q1 :
- Catalog : SN74AHCT1G125 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2024 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 1-Nov-2024 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CAHCT1G125QDBVRQ1 SOT-23 DBV 5 3000 210.0 185.0 35.0 CAHCT1G125QDCKRQ1 SC70 DCK 5 3000 190.0 190.0 30.0 CAHCT1G125WDTXRQ1 X2SON DTX 5 3000 210.0 185.0 35.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 0.22
0.08 TYP
0.15 2.4 1.8 2X 0.65 1.3
1.1 MAX
0.1
0.0 TYP
5X 0.33 0.15 NOTE 5
0.1 C A B
0.46
0.26 TYP
0 TYP
1.3 4X 0 -12 4X 4 -14 A 2.15 1.85 B1.4 1.1 (0.9) (0.15) (0.1) SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/F 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-203. 4. Support pin may differ or may not be present. 5. Lead width does not comply with JEDEC. 6. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25mm per side 0.1 C SCALE 5.600
www.ti.com EXAMPLE BOARD LAYOUT
0.07 MAX
0.07 MIN
5X (0.95) 5X (0.4) (2.2) (1.3) 2X (0.65) (R0.05) TYP 4214834/F 08/2024 SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 7. Publication IPC-7351 may have alternate designs. 8. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:18X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.2) (1.3) 2X(0.65) 5X (0.95) 5X (0.4) (R0.05) TYP SOT - 1.1 max heightDCK0005A SMALL OUTLINE TRANSISTOR 4214834/F 08/2024 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 10. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 THICK STENCIL SCALE:18X SYMM PKG 3 4
www.ti.com PACKAGE OUTLINE C 0.22 0.25 3.0 2.6 2X 0.95 1.9 1.45 0.90 0.15
0.00 TYP
5X 0.5 0.3 0.6
0.3 TYP
1.9 (0.1) (0.15) 4X 0 -15 4X 4 -15 A 3.05 2.75 B1.75 1.45 (1.1) SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Refernce JEDEC MO-178. 4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.25 mm per side. 5. Support pin may differ or may not be present.
0.2 C A B
0.1 C SCALE 4.000
www.ti.com EXAMPLE BOARD LAYOUT 5X (1.1) 5X (0.6) (2.6) (1.9) 2X (0.95) (R0.05) TYP 4214839/K 08/2024 SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X PKG 3 4 SOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK DEFINED EXPOSED METAL METALSOLDER MASK OPENING NON SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (2.6) (1.9) 2X(0.95) 5X (1.1) 5X (0.6) (R0.05) TYP SOT-23 - 1.45 mm max heightDBV0005A SMALL OUTLINE TRANSISTOR 4214839/K 08/2024 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:15X SYMM PKG 3 4
www.ti.com PACKAGE OUTLINE C 0.9 0.8 1.15 1.05
0.4 MAX
0.05 0.00 2X 0.78 4X 0.295 0.195 4X 0.27 0.17 0.35 0.05 0.605
0.51 MIN
0.1 MIN
(0.127) TYP(0.06) TYP (0.01) TYP 4X (0.225) X2SON - 0.4 mm max heightDTX0005A PLASTIC SMALL OUTLINE - NO LEAD 4229388/C 10/2024 0.08 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. PIN 1 INDEX AREA SEATING PLANE PIN 1 ID SYMM SYMM 0.05 C 4X (45 X 0.106) SCALE 11.000 SCALE 55.000 SIDE WALL PIN DETAIL TYPICAL AB
www.ti.com EXAMPLE BOARD LAYOUT (R0.05) TYP
0.05 MAX
0.05 MIN
4X (0.445) 4X (0.22) (0.805) 2X (0.78) (0.35) 4X (0.225) X2SON - 0.4 mm max heightDTX0005A PLASTIC SMALL OUTLINE - NO LEAD 4229388/C 10/2024 NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 40X SEE SOLDER MASK DETAIL 4X (45 X 0.106) METAL EDGE SOLDER MASK OPENING EXPOSED METAL METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METAL NON SOLDER MASK DEFINED SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DETAILS
www.ti.com EXAMPLE STENCIL DESIGN 4X (0.445) 4X (0.22) (0.805) (R0.05) TYP 2X (0.78) (0.335) 4X (0.233) X2SON - 0.4 mm max heightDTX0005A PLASTIC SMALL OUTLINE - NO LEAD 4229388/C 10/2024 NOTES: (continued) 5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.1 mm THICK STENCIL SCALE: 40X PRINTED SOLDER PASTE COVERAGE BY AREA UNDER PACKAGE PAD 5: 92% SYMM SYMM 4X (45 X 0.106)
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