SN74AHCT125-Q1 TI1 | Alldatasheet
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SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008 1POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 /C0068Qualified for Automotive Applications /C0068ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) /C0068Inputs Are TTL-Voltage Compatible description/ordering information The SN74AHCT125 is a quadruple bus buffer gate featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE ) input is high. When OE is low, the respective gate passes the data from the A input to its Y output. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION† TA PACKAGE‡ ORDERABLE PART NUMBER TOP-SIDE MARKING 40°C to 125°C SOIC − D Tape and reel SN74AHCT125QDRQ1 AHCT125Q −40°C to 125°C TSSOP − PW Tape and reel SN74AHCT125QPWRQ1 HB125Q † For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at http://www.ti.com. ‡ Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging. FUNCTION TABLE (each buffer) INPUTS OUTPUT OE A OUTPUT Y L H H L LL H X Z 1OE 2OE GND V CC 4OE 3OE D OR PW PACKAGE (TOP VIEW) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008, Texas Instruments Incorporated Please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008
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logic diagram (positive logic) 2A 2Y 2OE 1A 1Y 1OE 3A 3Y 3OE 4A 4Y 4OE Pin numbers shown are for the D and PW packages. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditi ons” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS508A − JUNE 2003 − REVISED FEBRUARY 2008 3POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 recommended operating conditions (see Note 3) MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VIH High-level input voltage 2 V VIL Low-level input voltage 0.8 V VI Input voltage 0 5.5 V VO Output voltage 0 VCC V IOH High-level output current −8 mA IOL Low-level output current 8 mA Δt/Δv Input transition rise or fall rate 20 ns/V TA Operating free-air temperature −40 125 °C NOTE 3: All unused inputs of the device must be held at V CC or GND to ensure proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004. electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V TA = 25°C MIN MAX UNITPARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX UNIT V IOH = −50 /C0109A 45V 4.4 4.5 4.4 VVOH IOH = −8 mA 4.5 V 3.94 3.8 V V IOL = 50 /C0109A 45V 0.1 0.1 VVOL IOL = 8 mA 4.5 V 0.36 0.44 V II VI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1 /C0109A IOZ VO = VCC or GND 5.5 V ±0.25 ±2.5 /C0109A ICC VI = VCC or GND, IO = 0 5.5 V 2 20 /C0109A ΔICC† One input at 3.4 V, Other inputs at VCC or GND 5.5 V 1.35 1.5 mA Ci VI = VCC or GND 5 V 4 10 10 pF Co VO = VCC or GND 5 V 15 pF † This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or VCC.
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switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1) PARAMETER FROM TO LOAD TA = 25°C MIN MAX UNITPARAMETER FROM (INPUT) TO (OUTPUT) LOAD CAPACITANCE MIN TYP MAX MIN MAX UNIT tPLH A Y C 15 pF 3.8 5.5 1 6.5 nstPHL A Y CL = 15 pF 3.8 5.5 1 6.5 ns tPZH OE Y C 15 pF 3.6 5.1 1 6 nstPZL OE Y CL = 15 pF 3.6 5.1 1 6 ns tPHZ OE Y C =1 5p F 4.6 6.8 1 8 ns tPLZ OE Y CL = 15 pF 4.6 6.8 1 8 ns tPLH A Y C 50 pF 5.3 7.5 1 8.5 nstPHL A Y CL = 50 pF 5.3 7.5 1 8.5 ns tPZH OE Y C 50 pF 5.1 7.1 1 8 nstPZL OE Y CL = 50 pF 5.1 7.1 1 8 ns tPHZ OE Y C =5 0p F 6.1 8.8 1 10 ns tPLZ OE Y CL = 50 pF 6.1 8.8 1 10 ns tsk(o) CL = 50 pF 1 1 ns noise characteristics, VCC = 5 V, CL = 50 pF, TA = 25°C (see Note 4) PARAMETER MIN MAX UNIT VOL(P) Quiet output, maximum dynamic VOL 0.8 V VOL(V) Quiet output, minimum dynamic VOL −0.8 V VOH(V) Quiet output, minimum dynamic VOH 4.4 V VIH(D) High-level dynamic input voltage 2 V VIL(D) Low-level dynamic input voltage 0.8 V NOTE 4: Characteristics are for surface-mount packages only. operating characteristics, VCC = 5 V, TA = 25°C PARAMETER TEST CONDITIONS TYP UNIT Cpd Power dissipation capacitance No load, f = 1 MHz 14 pF
NOTES: A. C L includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns. D. The outputs are measured one at a time with one input transition per measurement. E. All parameters and waveforms are not applicable to all devices. Figure 1. Load Circuit and Voltage Waveforms
www.ti.com 17-Aug-2011 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) CAHCT125QPWRG4Q1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT125QDRG4Q1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT125QDRQ1 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SN74AHCT125QPWRQ1 ACTIVE TSSOP PW 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74AHCT125-Q1 :
www.ti.com 17-Aug-2011 Addendum-Page 2
- Catalog: SN74AHCT125
- Enhanced Product: SN74AHCT125-EP
- Military: SN54AHCT125 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product
- Enhanced Product - Supports Defense, Aerospace and Medical Applications
- Military - QML certified for Military and Defense Applications
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