SN74ACT2G100-Q1_V01 TI | Alldatasheet
Document overview
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Technical content
SN74ACT2G100-Q1 Automotive Dual Configurable Data Flip-Flops with Clear and TTL-Compatible Inputs
1 Features
- AEC-Q100 qualified for automotive applications: – Device temperature grade 1: -40°C to +125°C – Device HBM ESD classification level 2 – Device CDM ESD classification level C4B
- Available in wettable flank QFN package
- Operating voltage range of 4.5V to 5.5V
- TTL-compatible Schmitt-trigger inputs support slow and noisy input signals
- Continuous ±24mA output drive at 5V
- Supports up to ±75mA output drive at 5V in short bursts
- Drives 50Ω transmission lines
- Fast operation with delay of 10.4ns max
2 Applications
- Hold a signal during controller reset
- Input slow edge-rate signals
- Operate in noisy environments
3 Description
The SN74ACT2G100-Q1 contains two independent D-type flip-flops with rising edge triggered clock, active low clear, and configurable logic data inputs. The data inputs can be configured for many 1- and 2-input logic functions, including buffer, inverter, AND, OR, NAND, NOR, XOR, XNOR. All inputs have Schmitt-trigger architecture to support slow or noisy input signals.
Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3) SN74ACT2G100- BQB (WQFN, 16) 3.6mm × 2.6mm 3.6mm × 2.6mm PW (TSSOP, 16) 6.4mm × 5mm 5mm × 4.4mm (1) For more information, see Mechanical, Packaging, and Orderable Information. (2) The package size (length × width) is a nominal value and includes pins, where applicable (3) The body size (length × width) is a nominal value and does not include pins. Y A B C D CLK CLR D CLR Q CLK Q Logic Diagram (Positive Logic) SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
11 Mechanical, Packaging, and Orderable
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4 Pin Configuration and Functions
8 GND
9 CLK2
11 DD2
12 DC2
13 DB2
14 DA2
15 CLR2
Figure 4-1. BQB Package, 16-Pin WQFN (Top View) 1CLR1 16 VCC 2DA1 15 CLR2 3DB1 14 DA2 4DC1 13 DB2 5DD1 12 DC2 6Q1 11 DD2 7CLK1 10 Q2 8GND 9 CLK2 Not to scale Figure 4-2. PW Package, 16-Pin TSSOP (Preview) (Top View) Table 4-1. Pin Functions PIN TYPE(1) DESCRIPTION NAME NO. CLR1 1 I Clear for Channel 1, active low DA1 2 I Channel 1, Data input A DB1 3 I Channel 1, Data input B DC1 4 I Channel 1, Data input C DD1 5 I Channel 1, Data input D Q1 6 O Channel 1, Output Q CLK1 7 I Clock for Channel 1, rising edge triggered GND 8 G Ground CLK2 9 I Clock for Channel 2, rising edge triggered Q2 10 O Channel 2, Output Q DD2 11 I Channel 2, Data input D DC2 12 I Channel 2, Data input C DB2 13 I Channel 2, Data input B DA2 14 I Channel 2, Data input A CLR2 15 I Clear for Channel 2, active low VCC 16 P Positive Supply Thermal Pad(2) — The thermal pad can be connected to GND or left floating. Do not connect to any other signal or supply. (1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power. (2) BQB package only www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: SN74ACT2G100-Q1
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) MIN MAX UNIT VCC Supply voltage range -0.5 7 V VI Input voltage range(2) -0.5 VCC + 0.5 V VO Output voltage range(2) -0.5 VCC + 0.5 V IIK Input clamp current VI < -0.5V or VI > VCC + 0.5V ±20 mA IOK Output clamp current VO < -0.5V or VO > VCC + 0.5V ±50 mA IO Continuous output current VO = 0 to VCC ±50 mA Continuous output current through VCC or GND ±200 mA TJ Junction temperature 150 °C Tstg Storage temperature -65 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality, performance, and shorten the device lifetime. (2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
5.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1) ±2000 VCharged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B ±1000 (1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCC Supply voltage 4.5 5.5 V VI Input Voltage 0 VCC V VO Output Voltage 0 VCC V IOH High-level output current –24 mA IOL Low-level output current 24 mA TA Operating free-air temperature –40 125 °C
5.4 Thermal Information
THERMAL METRIC(1) UNIT RθJA RθJC(top) RθJB ΨJT ΨJB RθJC(bot) PW (TSSOP) 16 140 80 90 30 90 N/A °C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note. SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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5.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VT+ Positive-going input threshold voltage 4.5V 1.28 1.54 1.83 V 5.5V 1.46 1.72 2.02 V VT- Negative-going input threshold voltage 4.5V 0.65 0.91 1.2 V 5.5V 0.71 0.99 1.29 V ΔVT Hysteresis (VT+ - VT-) 4.5V 0.51 0.75 V 5.5V 0.59 0.88 V VOH IOH = -50µA 4.5V 4.4 4.49 V 5.5V 5.4 5.49 IOH = -24mA 4.5V 3.7 IOH = -24mA 5.5V 4.7 IOH = -75mA(1) 5.5V 3.85 VOL IOL = 50µA 4.5V 0.01 0.1 V 5.5V 0.01 0.1 IOL = 24mA 4.5V 0.5 IOL = 24mA 5.5V 0.5 IOL = 75mA(1) 5.5V 1.65 II VI = 5.5V or GND 0V to 5.5V ±1 µA ICC VI = VCC or GND, IO = 0 5.5V 0.1 2 µA ΔICC VI = VCC – 2.1V; Any Input 4.5V to 5.5V 1.5 mA CI VI = VCC or GND 5V 2 pF (1) Not more than one output should be tested at a time, and the duration of the test should not exceed 2ms
5.6 Timing Characteristics
over recommended operating free-air temperature range (unless otherwise noted) PARAMETE R DESCRIPTION CONDITION VCC -40°C to 125°C UNIT MIN MAX fclock 5V ± 0.5V 150 tW Pulse duration CLR low 5V ± 0.5V 5 ns CLK 5V ± 0.5V 5 tSU Set up time, data before CLK↑ DAx, DBx and DCx 5V ± 0.5V 8 nsDDx 5V ± 0.5V 6 CLR inactive 5V ± 0.5V 1 tH Hold time, data after CLK↑ DAx, DBx and DCx 5V ± 0.5V 0 ns DDx 5V ± 0.5V 0
5.7 Switching Characteristics
over operating free-air temperature range; CL = 50pF typical values measured at TA = 25°C (unless otherwise noted). See #i#Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) VCC -40°C to 125°C UNIT MIN TYP MAX tpd CLK Q 5V ± 0.5V 8.9 ns CLR Q 5V ± 0.5V 10.4 ns tsk(o) Q 5V ± 0.5V 1 ns www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: SN74ACT2G100-Q1
over operating free-air temperature range; CL = 50pF typical values measured at TA = 25°C (unless otherwise noted). See #i#Parameter Measurement Information PARAMETER FROM (INPUT) TO (OUTPUT) VCC -40°C to 125°C UNIT MIN TYP MAX CPD (1) CLK or CLK INH QH 5V 15 pF (1) Power dissipation capacitance measured with CL = 50pF, F = 1MHz SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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5.8 Typical Characteristics
TA = 25°C (unless otherwise noted) V C C ( V ) ICC(nA) 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 2 5 ° C 1 2 5 ° C - 4 0 ° C Figure 5-1. Supply Current Across Supply Voltage I O H ( m A ) VOH(V) - 5 0 - 4 5 - 4 0 - 3 5 - 3 0 - 2 5 - 2 0 - 1 5 - 1 0 - 5 0 4 . 2 4 4 . 3 2 4 . 4 4 . 4 8 4 . 5 6 4 . 6 4 4 . 7 2 4 . 8 4 . 8 8 4 . 9 6 5 . 0 4 2 5 ° C 1 2 5 ° C - 4 0 ° C Figure 5-2. Output Voltage vs Current in HIGH State; 5V Supply I O L ( m A ) VOL(V) 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 5 0 0 . 0 4 0 . 0 8 0 . 1 2 0 . 1 6 0 . 2 0 . 2 4 0 . 2 8 0 . 3 2 0 . 3 6 0 . 4 2 5 ° C 1 2 5 ° C - 4 0 ° C Figure 5-3. Output Voltage vs Current in LOW State; 5V Supply www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: SN74ACT2G100-Q1
6 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily for the examples listed in the following table. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1MHz, ZO = 50Ω, tt < 2.5ns, Vt = 1.5V. For push-pull outputs, RL = 500Ω. The outputs are measured individually with one input transition per measurement. CL (1) From Output Under Test Test Point RL (1) CL includes probe and test-fixture capacitance. Figure 6-1. Load Circuit for Push-Pull Outputs VtInput Vt VCC 0 V 50% 50% VOH VOL tPLH (1) tPHL (1) VOH VOL tPHL (1) tPLH (1) Output Waveform 1 Output Waveform 2 50% 50% (1) The greater between tPLH and tPHL is the same as tpd. Figure 6-2. Voltage Waveforms Propagation Delays VOH VOL Output VCC 0 V Input tf (1)tr (1) 90% 10% 90% 10% tr (1) 90% 10% tf (1) 90% 10% (1) The greater between tr and tf is the same as tt. Figure 6-3. Voltage Waveforms, Input and Output Transition Times SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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7 Detailed Description
7.1 Overview
The SN74ACT2G100-Q1 is a dual, sequential, configurable multiple function device with Schmitt-trigger inputs . A 4-input combinational logic block provides a wide range of configurable data input logic. The output of the configurable logic block is the data input to a D-Flip Flop, which is transferred to the Q output on the positive going CLK edge. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and buffer.
7.2 Functional Block Diagram
Y A B C D CLK CLR D CLR Q CLK Q www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: SN74ACT2G100-Q1
7.3 Feature Description
7.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink and source similar currents. The drive capability of this device may create fast edges into light loads, so routing and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without being damaged. It is important to limit the output power of the device to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times. Unused push-pull CMOS outputs must be left disconnected.
7.3.2 TTL-Compatible Schmitt-Trigger CMOS Inputs
This device includes TTL-compatible CMOS inputs with Schmitt-trigger architecture. These inputs are specifically designed to interface with TTL logic devices by having reduced input voltage thresholds. TTL-compatible Schmitt-trigger CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings , and the maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I). The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers. Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be terminated at V CC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors, however a 10kΩ resistor is recommended and will typically meet all requirements. SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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7.3.3 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the data sheet where packages include this feature. Package We able Flank Lead PCB Pad Standard Lead Package Solder Figure 7-1. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After Soldering Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with automatic optical inspection (AOI). As shown in Figure 7-1 , a wettable flank can be dimpled or step-cut to provide additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical drawing for additional details. www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: SN74ACT2G100-Q1
7.3.4 Clamp Diode Structure
As shown in Figure 7-2, the inputs and outputs to this device have both positive and negative clamping diodes. CAUTION Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to the device. The input and output voltage ratings may be exceeded if the input and output clamp- current ratings are observed. GND LogicInput Output VCCDevice -IIK +IIK +IOK -IOK Figure 7-2. Electrical Placement of Clamping Diodes for Each Input and Output SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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7.4 Device Functional Modes
Table 7-1. Function Table INPUTS OUTPUT A B C D Y L L L L L L L L H H L L H L L L L H H H L H L L L L H L H H L H H L H L H H H L H L L L H H L L H L H L H L L H L H H H H H L L H H H L H L H H H L H H H H H L Table 7-2. Function Table INPUTS(1) (2) OUTPUT CLR CLK D Q L X X L H ↑ H H H ↑ L L H L X Q0 (1) H = high voltage level, L = low voltage level, X = don't care (2) This configuration is nonstable; that is, it does not persist when CLR returns to its inactive (high) level. www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: SN74ACT2G100-Q1
7.5 Combinatorial Logic Configurations
A B C D Y 2-Input AND Gate A B C D Y VCC 2-Input NAND Gate A B C D Y VCC 2-Input OR Gate A B C D VCC Y 2-Input NOR Gate A B C D Y VCC 2-Input XOR Gate A B C D Y VCC 2-Input XNOR Gate Figure 7-3. Logic Configurations SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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8 Application and Implementation
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes, as well as validating and testing their design implementation to confirm system functionality.
8.1 Application Information
The SN74ACT2G100-Q1 device offers flexible configuration for many design applications. The following example shows one way to hold the power supply operating mode while the system controller is put into a low power or disabled state. It is often beneficial to reduce the power consumption of a system controller when it is not required. The SN74ACT2G100-Q1 provides a highly configurable D-type flip-flop to maintain a valid logic state to control a variety of system components when the controller is disabled.
8.2 Typical Application
D CLR Q CLK Y Q Equivalent logic with A = GND, D = GND CLR EN2 SET LATCHED MODE A D EN1 Figure 8-1. Typical Application Schematic www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 15 Product Folder Links: SN74ACT2G100-Q1
8.2.1 Design Requirements
8.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Electrical Characteristics . The supply voltage sets the device's electrical characteristics of the device as described in the Electrical Characteristics section. The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the SN74ACT2G100-Q1 plus the maximum static supply current, I CC, listed in the Electrical Characteristics, and any transient current required for switching. The logic device can only source as much current that is provided by the positive supply source. Ensure the maximum total current through V CC listed in the Absolute Maximum Ratings is not exceeded. The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the SN74ACT2G100-Q1 plus the maximum supply current, I CC, listed in the Electrical Characteristics , and any transient current required for switching. The logic device can only sink as much current that can be sunk into its ground connection. Ensure the maximum total current through GND listed in the Absolute Maximum Ratings is not exceeded. The SN74ACT2G100-Q1 can drive a load with a total capacitance less than or equal to 50pF while still meeting all of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to exceed 50pF. The SN74ACT2G100-Q1 can drive a load with total resistance described by R L ≥ VO / IO, with the output voltage and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state, the output voltage in the equation is defined as the difference between the measured output voltage and the supply voltage at the VCC pin. Total power consumption can be calculated using the information provided in the CMOS Power Consumption and Cpd Calculation application note. Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard Linear and Logic (SLL) Packages and Devices application note. CAUTION The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum Ratings. These limits are provided to prevent damage to the device. SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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8.2.1.2 Input Considerations
Input signals must cross to be considered a logic LOW, and to be considered a logic HIGH. Do not exceed the maximum input voltage range found in the Absolute Maximum Ratings. Unused inputs must be terminated to either V CC or ground. The unused inputs can be directly terminated if the input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used for a default state of LOW. The drive current of the controller, leakage current into the SN74ACT2G100-Q1 (as specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10k Ω resistor value is often used due to these factors. Refer to the Feature Description section for additional information regarding the inputs for this device.
8.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will decrease the output voltage as specified by the V OH specification in the Electrical Characteristics. The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output voltage as specified by the VOL specification in the Electrical Characteristics. Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected directly together. This can cause excessive current and damage to the device. Two channels within the same device with the same input signals can be connected in parallel for additional output drive strength. Unused outputs can be left floating. Do not connect outputs directly to VCC or ground. Refer to the Feature Description section for additional information regarding the outputs for this device. www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 17 Product Folder Links: SN74ACT2G100-Q1
8.2.2 Detailed Design Procedure
- Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout section. 2. Verify that the capacitive load at the output is ≤ 50pF. This is not a hard limit; by design, however, it will optimize performance. This can be accomplished by providing short, appropriately sized traces from the SN74ACT2G100-Q1 to one or more of the receiving devices. 3. Verify that the resistive load at the output is larger than (VCC / IO(max))Ω. Doing this prevents the maximum output current from the Absolute Maximum Ratings from being violated. Most CMOS inputs have a resistive load measured in MΩ; much larger than the minimum calculated previously. 4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however, can be calculated using the steps provided in the CMOS Power Consumption and Cpd Calculation application note.
8.3 Application Curves
Y = EN1 AND EN2 Figure 8-2. Typical Application Timing Diagram SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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8.4 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power disturbance. A 0.1 μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass capacitors to reject different frequencies of noise. The 0.1 μF and 1μF capacitors are commonly used in parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results.
8.5 Layout
8.5.1 Layout Guidelines
- Bypass capacitor placement – Place near the positive supply terminal of the device – Provide an electrically short ground return path – Use wide traces to minimize impedance – Keep the device, capacitors, and traces on the same side of the board whenever possible
- Signal trace geometry – 8mil to 12mil trace width – Lengths less than 12cm to minimize transmission line effects – Avoid 90° corners for signal traces – Use an unbroken ground plane below signal traces – Flood fill areas around signal traces with ground – Parallel traces must be separated by at least 3x dielectric thickness – For traces longer than 12cm
- Use impedance controlled traces
- Source-terminate using a series damping resistor near the output
- Avoid branches; buffer each signal that must branch separately
8.5.2 Layout Example
≥ W W W ≥ 5W WORST BETTER BEST Figure 8-3. Example Trace Corners for Improved Signal Integrity www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: SN74ACT2G100-Q1
0.1 F Figure 8-4. Example Bypass Capacitor Placement for TSSOP and Similar Packages 0.1 F VCC GND 1 20 10 11 9 12 GNDVCC GND Figure 8-5. Example Bypass Capacitor Placement for WQFN and Similar Packages GND GND VCC 0.1 F VCC Figure 8-6. Example Bypass Capacitor Placement for SOT, SC70 and Similar Packages Long controlled-impedance trace Receiving PortTransmitting Port Figure 8-7. Example Damping Resistor Placement for Improved Signal Integrity SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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9 Device and Documentation Support
9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Notifications to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments. All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. DATE REVISION NOTES September 2025 * Initial Release www.ti.com SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 21 Product Folder Links: SN74ACT2G100-Q1
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. SN74ACT2G100-Q1 SLVSJW6 – SEPTEMBER 2025 www.ti.com
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www.ti.com 6-Nov-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CACT2G100WBQBRQ1 Active Production WQFN (BQB) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - AD100Q SN74ACT2G100PWRQ1 Active Production TSSOP (PW) | 16 3000 | LARGE T&R Yes NIPDAU Level-1-260C-UNLIM - ACT100Q (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. OTHER QUALIFIED VERSIONS OF SN74ACT2G100-Q1 :
- Catalog : SN74ACT2G100 Addendum-Page 1
www.ti.com 6-Nov-2025 NOTE: Qualified Version Definitions:
- Catalog - TI's standard catalog product Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 29-Sep-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CACT2G100WBQBRQ1 WQFN BQB 16 3000 210.0 185.0 35.0 SN74ACT2G100PWRQ1 TSSOP PW 16 3000 353.0 353.0 32.0 Pack Materials-Page 2
www.ti.com GENERIC PACKAGE VIEW This image is a representation of the package family, actual package may vary. Refer to the product data sheet for package details. WQFN - 0.8 mm max heightBQB 16 PLASTIC QUAD FLATPACK - NO LEAD2.5 x 3.5, 0.5 mm pitch 4226161/A
NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance. PACKAGE OUTLINE 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max height INDSTNAME BQB0016B A 0.08 C
0.1 C A B
0.05 C B SYMM SYMM 2.6 2.4 3.6 3.4
0.8 MAX
0.05 0.00 SEATING PLANE C (0.2) TYP 2X 0.5 2.5 10X 0.5 1.1 0.9 2.1 1.9 16X 0.5 0.3 16X 0.3 0.2 SYMM 8 9 PIN 1 ID (OPTIONAL) PIN 1 INDEX AREA (0.16)
0.1 MIN
(0.13) SECTION A-A TYPICAL
NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271) . 5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented. EXAMPLE BOARD LAYOUT 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max heightBQB0016B INDSTNAME SYMM SYMM LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 20X (1) (2) 16X (0.6) 16X (0.25) 2X (0.5) 10X (0.5) (2.3) (3.3) 2X (0.75) 1 16 8 9 (Ø 0.2) VIA TYP (R0.05) TYP
NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. EXAMPLE STENCIL DESIGN 4226135/A 08/2020 www.ti.com WQFN - 0.8 mm max heightBQB0016B INDSTNAME SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 85% PRINTED COVERAGE BY AREA SCALE: 20X SYMM SYMM (0.95) (1.79) 16X (0.6) 16X (0.25) 2X (0.5) 10X (0.5) (2.3) (3.3) 2X (0.75) 1 16 8 9 (R0.05) TYP METAL TYP
www.ti.com PACKAGE OUTLINE C 14X 0.65 4.55 16X 0.30 0.17 6.6
6.2 TYP
1.2 MAX
0.15 0.05 0.25 GAGE PLANE 0 -8 4X (0 -12 ) B 4.5 4.3 NOTE 4 A 5.1 4.9 NOTE 3 0.75 0.50 (0.15) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 0.1 C NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. SEATING PLANE A 20 DETAIL A TYPICAL SCALE 2.500
www.ti.com EXAMPLE BOARD LAYOUT
0.05 MAX
0.05 MIN
16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SYMM SYMM 8 9 15.000 METALSOLDER MASK OPENING METAL UNDER SOLDER MASK SOLDER MASK OPENING EXPOSED METALEXPOSED METAL SOLDER MASK DETAILS NON-SOLDER MASK DEFINED (PREFERRED) SOLDER MASK DEFINED
www.ti.com EXAMPLE STENCIL DESIGN 16X (1.5) 16X (0.45) 14X (0.65) (5.8) (R0.05) TYP TSSOP - 1.2 mm max heightPW0016A SMALL OUTLINE PACKAGE 4220204/B 12/2023 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X SYMM SYMM 8 9
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