CAB4A TI1 | Alldatasheet

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Technical content

  • 32 Bits 1-to-2 Register Outputs VDD mode.
  • 1-to-4 Differential Clock Buffer All inputs are pseudo-differential using external or
  • 1.2V Operation internal voltage reference. All outputs are full swing CMOS drivers optimized to drive 15 to 50 Ω effective• PLL with Internal Feedback terminated traces in DDR4 RDIMM, LRDIMM and 3D-• Configurable Driver Strength Stacked DIMM applications. The clock outputs,
  • Scalable Weak Driver command/address outputs, control outputs, data buffer control outputs can be enabled in groups, and• Programmable Latency independently driven with different strengths to• Output Driver Calibration compensate for different DIMM net topologies. The
  • Address Mirroring and Inversion DDR4 Register operates from a differential clock (CK_t and CK_c). Inputs are registered at the• DDR4 Full-Parity Operation crossing of CK_t going HIGH, and CK_c going LOW.• On-Chip Programmable VREF Generation The input signals could be either re-driven to the• CA Bus Training Mode outputs if one of the input signals DCS[n:0]_n is driven LOW or it could be used to access device• I2C™ Interface Support internal control registers when certain input conditions• Up to 16-Logical Ranks Support for 3DS are met.RDIMMs and LRDIMMs The device is characterized in the operating• Up to 4 Physical Ranks Support for RDIMMs temperature range from -40°C to 95°C.and LRDIMMs

Figure 1. DDR4 - RDIMM Memory Subsystem Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2I2C is a trademark of NXP Semiconductors. 3All other trademarks are the property of their respective owners. necessarily include testing of all parameters.

x DA[13:0], DBA[1:0], Control Word State Machine and Control Logic DCS[1:0]_n, DCKE0, DODT0, DCKE1 DODT1 PLL R D Q CE R D Q R D Q R D Q Output-Enable Y0..Y3, BCK- Enable VrefCA QAA[13:0], QABA[1:0] QACS[1:0]_n, Y1_t Y1_c Y0_t Y0_c Y2_t Y2_c Y3_t Y3_c CK_t CK_c DRST_n 10k : 100k : CS Logic DA[13:0], DBA[1:0], DBG[1:0], QABG[1:0], QxACT_n QBA13, QBA11, QBBA[1;0] QBBG[1:0], QBCS[1:0]_n, QACKE[1:0] QBCKE[1:0] QAODT[1:0] QBODT[1:0] DACT_n DBG[1:0], DACT_n,DPAR Feedback QAC2 QBC2 QRST_n DCS2_n/DC0, DC2 DCS3_n/DC1, QACS2_n/C0, QACS3_n/C1, QBCS2_n/C0, QBCS3_n/C1, DA17, DRAS_n/A16, DCAS_n/A15, DWE_n/A14, DA17,DRAS_n/A16, DCAS_n/A15, DWE_n/A14 QxRAS_n/QxA16, QxCAS_n/QxA15, QxWE_n/QxA14, QBA17, QBA[9,3], QBA12, QBA10,QAA17 QBA[2:0], QAPAR I 2C VDDSPD SCL SDA SA[2:0] BFUNC ZQCal ZQCal BCK_t BCK_c DQB Interface Command Decoder BCOM[3:0] BCKE BODT DPAR QBPAR (cond.) ERROR_IN_n Parity Logic ALERT_n Vref Generation and Control and Decoder QVREFCA BVREFCA Vref for Input Receivers CW Table 120k : CAB4A SNAS630B –JULY 2013–REVISED OCTOBER 2013 www.ti.com FUNCTIONAL BLOCK DIAGRAM

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Table 1. TERMINAL FUNCTIONS n which should be re-driven.

  • DCS3_n ↔ DC1 DC2 DRAM corresponding register Chip ID 2 signal. DRAM corresponding register inputs. In case of an ACT command some of these terminals have an alternative function:DA0..DA13, DRAM corresponding register command signalsDA17 DBA0..DBA1, • DA14 ↔ DWE_n DBG0..DBG1
  • DA15 ↔ DCAS_nCMOS(1) VREF basedInput Address and
  • DA16 ↔ DRAS_nCommand bus DA14..DA16 or DWE_n, DCAS_n, DRAS_n DACT_n DRAM corresponding register DACT_n signal. Differential master clock input pair to the PLL with a 10 kΩ ~Clock inputs CK_t, CK_c CMOS differential 100 kΩ pull-down resistor. Active LOW asynchronous reset input. When LOW, it causes a Reset input DRST_n CMOS input reset of the internal latches and disables the outputs, thereby forcing the outputs to float. Input parity is received on pin DPAR and should maintain even Parity input DPAR CMOS(2) VREF based parity across the address and command inputs (see above), at the rising edge of the input clock. DRAM address parity and CRC Alert is connected to this input Error Input ERROR_IN_n CMOS input pin, which in turn is buffered and re-driven to the ALERT_n output of the register. Requires external pull-up resistor.(3) BODT Data buffer on-die termination signal. BCKE Data buffer clock enable signal for PLL power management.CMOS(3) Data buffer control Register communication bus for data buffer programming andand communication BCOM[3:0] control access.outputs BCK_t, BCK_c CMOS differential Differential clock output pair to the data buffer BVREFCA VDD/2Reference Voltage Output reference voltage for data buffer control bus receivers. (1) These receivers use VREFCA as the switching point reference. (2) These receivers use VREFCA as the switching point reference. (3) CMOS: These outputs with rail to rail signal swing and programmable impedance are optimized for memory applications to drive DRAM inputs over a terminated transmission line. Error_In_n: Internal Pull-up resistor can be turned on. Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CAB4A

Table 1. TERMINAL FUNCTIONS (continued)

  • QxCS2_n ↔ QxC0 QAC2, QBC2 Register output Chip ID2 signals. CMOSQAA0..QAA13, QAA17, QBA0..QBA13, QBA17, Outputs of the register, valid after the specified clock count and QABA0..QABA1, immediately following a rising edge of the clock. QBBA0..QBBA1, QAG0..QAG1, QBG0..QBG1 Outputs of the register, valid after the specified clock count andOutput Address and QAA14..QAA16, immediately following a rising edge of the clock.Command bus QBA14..QBA16 In case of an ACT command some of these terminals have anor QAWE_n, alternative function:QACAS_n, QARAS_n, • QxA14 ↔ QxWE_n QBWE_n,
  • QxA15 ↔ QxCAS_nQBCAS_n, QBRAS_n • QxA16 ↔ QxRAS_n QAACT-n, Outputs of the register, valid after the specified clock count and QBACT_n immediately following a rising edge of the clock. Vref output QVREFCA VDD/2 Reference voltage Output reference voltage for DRAM receivers Y0_t..Y3_t,Clock outputs CMOS differential Re-driven clocksY0_c..Y3_c Reset output QRST_n Re-driven reset. This is not an asynchronous output. CMOS Parity outputs QAPAR, QBPAR Re-driven parity(4) When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs Error out ALERT_n Open drain when parity checking is enabled or that the ERROR_IN_n input was asserted, regardless of whether parity checking is enabled or not. Open drainSDA I2C DataI/OSCL I2C ClockCMOS inputI2C pins SA[2:0] I2C Address signalsCMOS inputBFUNC Reserved(5) CMOS inputVDDSPD I2C power inputPower input (4) I2C inputs: These inputs are 2.5V inputs, except BFUNC which is a 1.2V input. (5) BFUNC has an internal pull-down resistor of 120 kΩ to V.

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VREFCA VCC/2Reference voltage Input reference voltage for the CMOS inputs. Miscellaneous pins PVDD Clock power Clock logic and clock output driver power supply. PVSS Clock ground Clock logic and clock output driver ground. ZQCAL Reference Needs a calibration resistor of 240Ω ±1% to VSS. NU Mechanical ball Do not connect on PCB. RFU[3:0] I/O Reserved; must be left floating on DIMM and in DDR4 register.

SNAS630B –JULY 2013–REVISED OCTOBER 2013 www.ti.com

REVISION HISTORY

Change document to production data.

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www.ti.com 19-Oct-2013 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CAB4AZNRR ACTIVE NFBGA ZNR 253 2000 Green (RoHS & no Sb/Br) SNAGCU Level-3-260C-168 HR -40 to 95 CAB4A6 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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