CA5470 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • High Speed CMOS Input Stage Provides
  • ESD Protection to 2000V
  • 3V to 16V Power Supply Operation
  • Fully Guaranteed Specifications Over Full Military Range
  • Wide BW (14MHz); High SR (5V/µs) at 5V Supply
  • Wide V lCR Range From -0.5V to 3.7V (Typ) at 5V Supply
  • Ideally Suited for CMOS and HCMOS Applications

Applications

  • Bar Code Readers
  • Photodiode Amplifiers (IR)
  • Microprocessor Buffering
  • Ground Reference Single Supply Amplifiers
  • Fast Sample and Hold
  • Timers
  • Voltage Controlled Oscillators
  • Voltage Followers
  • V to l Converters
  • Peak Detectors
  • Precision Rectifiers
  • 5V Logic Systems
  • 3V Logic Systems

Description

The CA5470 is an operational amplifier that combines the advantages of both high speed CMOS and bipolar transistors on a single monolithic chip. It is constructed in the BiMOS-E process which adds drain-extension implants to 3µm polygate CMOS, enhancing both the voltage capability and providing vertical bipolar transistors for broadband analog/digital func- tions. This process lends itself easily to high speed operational amplifiers, comparators, analog switches and interface periph- erals, resulting in twice the speed of the conventional CMOS transistors having similar feature size. BiMOS-E are broadbased bipolar transistors that have high transconductance, gains more constant with current level, sta- ble “precision” base-emitter offset voltages and superior drive capability. Excellent interface with environmental potentials enable use in 5V logic systems and future 3.3V logic systems. Refer to Application Note AN8811. ESD capability exceeds the standard 2000V level. The CA5470 series can operate with single supply voltages from 3V to 16V or±1.5V to±8V. They have guaranteed specifica- tions at both 5V and±7.5V at room temperature as well as over the full -55 oC to 125oC military range. Pinout CA5470 (PDIP, SOIC) TOP VIEW

Ordering Information

(BRAND) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA5470E -55 to 125 14 Ld PDIP E14.3 CA5470M (5470) -55 to 125 14 Ld SOIC M14.15 CA5470M96 (5470) -55 to 125 14 Ld SOIC Tape and Reel M14.15 OUTPUT 1 NEG. INPUT 1 POS. INPUT 1 POS. INPUT 2 NEG. INPUT 2 OUTPUT 2 OUTPUT 4 NEG. INPUT 4 POS. INPUT 4 POS. INPUT 3 NEG. INPUT 3 OUTPUT 3 - ++ - - ++ - File Number 1946.3CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1) θJA (oC/W) (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical SpecificationsTypical Values Intended Only for Design Guidance at V+ = 5V, V- = 0V, TA = 25oC, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITS Input Resistance R I 5T Ω Input Capacitance C I f = 1MHz 3.1 pF Unity Gain Crossover Frequency f T 14 MHz Slew Rate SR V OUT = 3.65VP-P 5V / µs Transient Response: C L = 25pF, RL= 2kΩ (Voltage Follower)Rise Time/Fall Time t r 27/25 ns Overshoot OS 20 % Settling Time (To <0.1%, VIN = 4VP-P)t S C L = 25pF, RL= 2kΩ (Voltage Follower) 1 µs Full Power BW, SR = 5V/µs FPBW A V = 1, VOUT = 3.65VP-P 436 kHz Electrical SpecificationsTA = 25oC, V+ = 5V, V- = GND PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |V IO|- 6 2 2 m V Input Offset Current |I IO| - 0.5 50 (Note 3) pA Input Current I I - 0.5 50 (Note 3) pA Common Mode Input Range V ICR 3.5 -0.5 to 3.7 0 V Common Mode Rejection Ratio CMRR V ICR = 0V to 3.5V 55 70 - dB Power Supply Rejection Ratio PSRR ∆V = 2V 60 75 - dB Positive Output Voltage Swing V OM +R L = 2kΩ to GND 4 4.4 - V Negative Output Voltage Swing V OM -R L = 2kΩ to GND - 0.06 0.10 V Total Supply Current I SUPPL Y VOUT = 2.5V, RL =∞ -67 m A Unity Gain Bandwidth Product f T 10 14 - MHz Slew Rate SR 4 5 - V/ µs Output Current Source to opposite supply I SOURCE 4 5.5 - mA Sink to opposite supply I SlNK 1.0 1.2 - mA Open Loop Gain A OL 0.5V to 3.5V, RL = 10kΩ 80 90 - dB NOTE: 3. This is the lowest value that can be tested reliably. Almost all devices will be <10pA. CA5470

Electrical SpecificationsTA = -55oC to 125oC, V+ = 5V, V- = GND PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |V IO|- 6 2 5 m V Input Offset Current |I IO| - 550 5500 pA Input Current I I - 550 11000 pA Common Mode Input Range V ICR 3.5 -0.5 to 3.7 0 V Common Mode Rejection Ratio CMRR V ICR = 0V to 3.5V 50 65 - dB Power Supply Rejection Ratio PSRR ∆V = 2V 58 75 - dB Positive Output Voltage Swing V OM +R L = 2kΩ to GND 3.8 4.2 - V Negative Output Voltage Swing V OM -R L = 2kΩ to GND - 0.08 0.11 V Total Supply Current I SUPPL Y VOUT = 2.5V - 9 11 mA Unity Gain Bandwidth Product f T 8 12 - MHz Slew Rate SR 3 5 - V/ µs Output Current Source to opposite supply I SOURCE 4 5.5 - mA Sink to opposite supply I SlNK 0.8 1.2 - mA Open Loop Gain A OL 0.5V to 3.5V, RL = 10kΩ 80 90 - dB Electrical SpecificationsTA = 25oC, VSUPPL Y =±7.5V PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |V IO|- 5 2 5 m V Input Offset Current |I IO| - 0.5 50 (Note 4) pA Input Current I I - 1 50 (Note 4) pA Common Mode Input Range V ICR 5.8 -7.8 to 6.0 -7.5 V Common Mode Rejection Ratio CMRR V ICR = 0V to 13.3V 60 70 - dB Power Supply Rejection Ratio PSRR ∆V = 1V 60 76 - dB Positive Output Voltage Swing V OM + R L = 2kΩ to GND 6.3 6.5 - V R L = 10kΩ to GND 6.4 6.6 - V Negative Output Voltage Swing V OM - R L = 2kΩ to GND - -2.6 -2 V R L = 10kΩ to GND - -7.3 -7.1 V Total Supply Current I SUPPL Y VOUT = GND, RL =∞ -1 0 1 2 m A Unity Gain Bandwidth Product f T 12 16 - MHz Slew Rate SR 4 7 - V/ µs Output Current Source to opposite supply I SOURCE 6.2 6.8 - mA Sink to opposite supply I SlNK 1 1.4 - mA Open Loop Gain A OL -5V to +5V, RL = 10kΩ 80 90 - dB NOTE: 4. This is the lowest value that can be tested reliably. Almost all devices will be <10pA. CA5470

Block Diagram(1/4 of CA5470) Electrical SpecificationsTA = -55oC to 125oC, VSUPPL Y =±7.5V PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS Input Offset Voltage |V IO|- 5 3 0 m V Input Offset Current |I IO| - 550 5500 pA Input Current I I - 1100 11000 pA Common Mode Input Range V ICR 5.8 -7.8 to 6.0 -7.5 V Common Mode Rejection Ratio CMRR V ICR = 0V to 3.5V 58 70 - dB Power Supply Rejection Ratio PSRR ∆V = 1V 60 76 - dB Positive Output Voltage Swing V OM + R L = 2kΩ to GND 4.75 5.5 - V R L = 10kΩ to GND 6.1 6.4 - V Negative Output Voltage Swing V OM - R L = 2kΩ to GND - -2.6 -2 V R L = 10kΩ to GND - -7.3 -7.1 V Total Supply Current I SUPPL Y VOUT = GND, RL =∞ -1 2 1 8 m A Unity Gain Bandwidth Product f T 10 15 - MHz Slew Rate SR 3 7 - V/ µs Output Current Source to opposite supply I SOURCE 6.2 6.8 - mA Sink to opposite supply I SlNK 1 1.4 - mA Open Loop Gain A OL -5V to +5V, RL = 10kΩ 80 90 - dB AV ≈ 30dB AV ≈ 54dB AV ≈ 6dB+INPUT -INPUT 4 1.8mA/AMPV+ 150µA100µA 320 µA5 0 µA5 0 µA 1.2mA OUTPUT 2kΩ TO BIAS CIRCUIT GND OR - SUPPLY OUTPUT STAGECOMPOSITE MILLER GAIN STAGE GROUNDED GATE LEVEL SHIFTER PMOS DIFFERENTIAL INPUT STAGE 2kΩ CA5470

FIGURE 1. MAXIMUM OUTPUT VOLTAGE SWING vs FREQUENCY derived from the basic inch dimensions as indicated. mils (0.17mm) larger in both dimensions.