CA5420A RENESAS | Alldatasheet

Document overview

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  • PDF pages: 9

Technical content

Features

  • CA5420A at 5V supply voltage with full military temperature range guaranteed specifications
  • CA5420A guaranteed to operate from ±1V to ±10V supplies
  • 2V supply at 350µA supply current
  • 1pA (Typ) input current (essentially constant to +85°C)
  • Rail-to-rail output swing (Drive ±2mA into 1k Ω load)
  • Pin compatible with 741 op amp
  • Pb-free (RoHS compliant)

Applications

  • pH probe amplifiers
  • Picoammeters
  • Electrometer (High Z) instruments
  • Portable equipment
  • Inaccessible field equipment
  • Battery dependent equipment (medical and military)
  • 5V logic systems
  • Microprocessor interface BiMOS TA BUFER (X2) HIGH GAIN (50k) BUFFER AMPS; BOOTSTRAPPED INPUT PROTECTION NETWORK

FIGURE 1. FUNCTIONAL DIAGRAM

FN1925 Rev 9.00 Page 2 of 9 February 11, 2015 Pin Configuration CA5420A (8 LD SOIC) TOP VIEW

Ordering Information

(Notes 1, 2, 3) PART MARKING TEMP. RANGE (°C) PACKAGE (RoHS Compliant) PKG. DWG. # CA5420AMZ 5420 AMZ -55 to +125 8 Ld SOIC M8.15 NOTES: 1. Add “96” suffix for Tape and Reel. Please refer to TB347 for details on reel specifications. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. 3. For Moisture Sensitivity Level (MSL), please see product information page for CA5420A. For more information on MSL please see techbrief TB363. OFFSET INV. INPUT NON-INV. INPUT STROBE OUTPUT OFFSET NULL NULL Pin is connected to Case.

FN1925 Rev 9.00 Page 3 of 9 February 11, 2015 Absolute Maximun Ratings Thermal Information Output Short Circuit Duration (Note 4 Thermal Resistance (Typical, Note 5) JA (°C/W) JC (°C/W) CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. Short circuit may be applied to ground or to either supply. 5.  JA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. Electrical Specifications Typical Values Intended Only for Design Guidance. V+ = +5V; V- = GND, TA = +25°C PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS Input Resistance R I 150 T Ω Input Capacitance C I 4.9 pF Output Resistance R O 300 Ω Equivalent Input Noise Voltage eN f = 1kHz R S = 100Ω 62 nV/ Hz f = 10kHz 38 nV/ Hz Short-Circuit Current To Opposite Supply Source I OM+2 . 6 m A Sink I OM-2 . 4 m A Gain Bandwidth Product f T 0.5 MHz Slew Rate SR 0.5 V/µs Transient Response Rise Time t r RL = 2kΩ, CL = 100pF 0.7 µs Overshoot OS 15 % Current from Terminal 8 To V- I 8+2 0 µ A Current from Terminal 8 To V+ I 8-2 m A Settling Time 0.01% A V = 1 2V P-P Input 8 µs 0.10% A V = 1 2V P-P Input 4.5 µs Electrical Specifications TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS MIN (Note 6)T Y P MAX (Note 6) Input Offset Voltage V IO VO = 2.5V 1 5 mV Input Offset Current I IO VO = 2.5V 0.02 4 pA Input Current I I VO = 2.5V 0.02 5 pA Common Mode Rejection Ratio CMRR V CM = 0 to 3.7V, VO = 2.5V 75 83 dB Common Mode Input Voltage Range V lCR+V O = 2.5V 3.7 4 V VlCR- -0.3 0 V Power Supply Rejection Ratio PSRR V+ = 1V; V- = 1V 70 83 dB Large Signal Voltage Gain A OL VO = 0.5 to 4V R L =  85 87 dB VO = 0.5 to 4V R L = 10kΩ 85 87 dB VO = 0.7 to 3V R L = 2kΩ 70 85 dB Source Current I SOURCE VO = 0V 1.2 2.7 mA

FN1925 Rev 9.00 Page 4 of 9 February 11, 2015 Sink Current I SINK VO = 5V 1.2 2.1 mA Output Voltage V OM+R L =  4.85 4.94 V VOM- 0.13 0.15 V VOM+R L = 10kΩ 4.7 4.9 V VOM-0 . 1 2 0 . 1 5 V VOM+R L = 2kΩ 3.5 4.6 V VOM- 0.1 0.15 V Supply Current I SUPPLY VO = 0V 400 550 µA VO = 2.5V 430 600 µA Electrical Specifications TA = +25°C, V+ = 5V, V- = 0, Unless Otherwise Specified. (Continued) PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS MIN (Note 6)T Y P MAX (Note 6) Electrical Specifications TA = -55°C to +125°C, V+ = 5V, V- = 0, Unless Otherwise Specified. Boldface limits apply across the operating temperature range, -55°C to +125°C. PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS MIN (Note 6)T Y P MAX (Note 6) Input Offset Voltage V IO VO = 2.5V 2 10 mV Input Offset Current I IO VO = 2.5V 1.5 3 nA Up to TA = +85°C 21 0 p A Input Current II VO = 2.5V 2 5 nA Up to TA = +85°C 10 15 pA Common Mode Rejection Ratio CMRR V CM = 0 to 3.7V, VO = 2.5V 70 80 dB Common Mode Input Voltage Range V lCR+V O = 2.5V 3.7 4V VlCR- -0.3 0 V Power Supply Rejection Ratio PSRR V+ = 1V; V- = 1V 70 83 dB Large Signal Voltage Gain A OL VO = 0.5 to 4V R L =  65 75 dB VO = 0.7 to 4V R L = 10kΩ 80 87 dB VO = 0.7 to 2.5V R L = 2kΩ 70 80 dB Source Current I SOURCE VO = 0V 1 2.7 mA Sink Current I SINK VO = 5V 1 2.1 mA Output Voltage V OM+R L =  4.8 4.9 V VOM-0 . 1 6 0.2 V VOM+R L = 10kΩ 4.7 4.9 V VOM-0 . 1 5 0.2 V VOM+R L = 2kΩ 3 4V VOM-0 . 1 4 0.2 V Supply Current I SUPPLY VO = 0V 430 600 µA VO = 2.5V 480 650 µA

FN1925 Rev 9.00 Page 5 of 9 February 11, 2015 Electrical Specifications For Equipment Design at VSUPPLY = ±1V, TA = +25°C, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS MIN (Note 6)T Y P MAX (Note 6) Input Offset Voltage V IO 25 m V Input Offset Current IIO 0.01 4 pA Input Current II 0.02 5 pA Large Signal Voltage Gain A OL RL = 10kΩ 10 100 kV/V 80 100 dB Common Mode Rejection Ratio CMRR 560 µV/V 50 65 dB Common Mode Input Voltage Range V lCR+0 . 2 0 . 5 V VlCR-- 1 - 1 . 3 V Power Supply Rejection Ratio PSRR 32 425 µV/V 70 90 dB Maximum Output Voltage V OM+R L =  0.9 0.95 V VOM- -0.85 -0.91 V Supply Current I SUPPLY 350 650 µA Device Dissipation P D 0.7 1.1 mW Input Offset Voltage Temperature Drift VIO/T 4 µV/°C Electrical Specifications For Equipment Design at VSUPPLY = ±10V, TA = +25°C, Unless Otherwise Specified. PARAMETER SYMBOL TEST CONDITIONS CA5420A UNITS MIN (Note 6)T Y P MAX (Note 6) Input Offset Voltage V IO 25 m V Input Offset Current IIO 0.03 4 pA Input Current II 0.05 5 pA Large Signal Voltage Gain A OL RL = 10kΩ 20 100 kV/V 80 100 dB Common Mode Rejection Ratio CMRR 100 320 µV/V 70 80 dB Common Mode Input Voltage Range V lCR+9 9 . 3 V VlCR-- 1 0 - 1 0 . 3 V Power Supply Rejection Ratio PSRR 32 320 µV/V 70 90 dB Maximum Output Voltage V OM+R L =  9.7 9.9 V VOM- -9.7 -9.85 V Supply Current I SUPPLY 450 1000 µA Device Dissipation P D 91 4 m W Input Offset Voltage Temperature Drift VIO/T 4 µV/°C NOTE: 6. Compliance to datasheet limits is assu red by one or more methods: production test, characterization and/or design.

FN1925 Rev 9.00 Page 8 of 9 February 11, 2015 CA5420A Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com For additional products, see www.intersil.com/en/products.html © Copyright Intersil Americas LLC 2002-2015. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. About Intersil Intersil Corporation is a leading provider of innovative power management and precision analog solutions. The company's products address some of the largest markets within the industrial and infrastructure, mobile computing and high-end consumer markets. For the most updated datasheet, application notes, related documentation and related parts, please see the respective product information page found at www.intersil.com. You may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask. Reliability reports are also available from our website at www.intersil.com/support

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest revision. DATE REVISION CHANGE February 11, 2015 FN1925.9 Electrical Specifications Table: On page 3, Large signal voltage gain Vo = 0.7 to 3V Min limit changed from 80 to 70, and page 4 Large signal voltage gain Vo = 0.7 to 2.5V Min limit changed from 75 to 70. September 25, 2013 FN1925.8 Page 5 - Changed CMRR limits for ±1V spec table from 60dB to 50dB Page 9 - Updated POD to rev 4. Changes from rev 3: Changed Note 1 "1982" to "1994". page 3 Updated Thermal Resistance note for package. page 3 Electrical Spec Table, V+ = 5V, V- = 0V (lower table): change PSRR min from 75dB to 70dB. page 4 Electrical Spec Table, V+ = 5V, V- = 0V (upper table) Change Supply Current Vo =0V Max from 500µA to 550µA, and V0 = 2.5V change max from 550µA to 600µA. page 4 Electrical Spec Table, TA = -55 to +125 V+ = 5V, V- = 0V (lower table) change Supply Current VO=0V Max from 550µA to 600µA, change Vo=2.5V max from 600uA to 650uA. page 5 Electrical Spec Table Vsupply =+/-1V (upper table) Common Mode Rejection Ratio, delete 1000uV/V MAX spec and leave only a typ spec. PSRR change 320uV/V max to 425µV/V max. page 9 POD M8.15 Updated to new POD format by removing table and moving dimensions onto drawing and adding land pattern. Changed in Typical Recommended Land Pattern the following: 0.200 to 5.20(0.205) December 08, 2009 FN1925.6 Electrical Specificat ions Table; TA = 25°C, V+ = 5V, V- = 0V; Change Input Offset Current Max from 0.5pA to 4pA P3, same table as above; Input Current Max from 1pA to 5pA. P4: same table as above; Output Voltage VOM+: Minimum spec for RL = Infinity from 4.9V to 4.85V P5: In Vsupply = +/-1V, Large Signal Voltage Gain spec : Min from 20kV/V to 10kV/V and from 86dB to 80dB P4; Large Signal Voltage Gain RL = inf; change min to 65dB and typ to75dB (was 85dB Min and 87dB Typ) Updated Pb-free bullet in Features and Pb-free note in Ordering Information based on lead finish. Added TB347 link to ordering information for reel specifications. Added MSL link to Order Info Updated Caution statement in Abs Max per legal's new verbiage. Added Pb-Free Reflow link to Thermal Info Added POD to last page Added standard Over Temp note to applicable elec spec tables Corrected Input Offset Current Max from 0.4pA to 4pA December 21, 2005 FN1925.5 Added redline rele ase FGs to ordering information table. September 1998 FN1925.4 Initial Release

FN1925 Rev 9.00 Page 9 of 9 February 11, 2015 Package Outline Drawing M8.15

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 4, 1/12 DETAIL "A" TOP VIEW INDEX AREA 12 3 -C- SEATING PLANE x 45° NOTES: 1. Dimensioning and tolerancing per ANSI Y14.5M-1994. 2. Package length does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm ( 0.006 inch) per side. 3. Package width does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 4. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 5. Terminal numbers are shown for reference only. 6. The lead width as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 7. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. 8. This outline conforms to JEDEC publication MS-012-AA ISSUE C. SIDE VIEW “A SIDE VIEW “B” 1.27 (0.050) 6.20 (0.244) 5.80 (0.228) 4.00 (0.157) 3.80 (0.150) 0.50 (0.20) 0.25 (0.01) 5.00 (0.197) 4.80 (0.189) 1.75 (0.069) 0.10(0.004) 0.51(0.020) 0.33(0.013) 0.25 (0.010) 0.19 (0.008) 1.27 (0.050) 0.40 (0.016) 1.27 (0.050) 5.20(0.205) 4 5 TYPICAL RECOMMENDED LAND PATTERN 2.20 (0.087) 0.60 (0.023)