CA5260_05 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • MOSFET Input Stage provides 2pA (Typ) at 5V Operation
  • Ideal for Single Supply Applications
  • Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail
  • CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails
  • CA5260A, CA5260 Have Full Military Temperature Range Guaranteed Specifications for V+ = 5V
  • CA5260A, CA5260 are Guaranteed to Operate Down to 4.5V for A OL
  • Fully Guaranteed to Operat e from -55°C to 125°C at V+ = 5V, V- = GND
  • Pb-Free Plus Anneal Available (RoHS Compliant)

Applications

  • Ground Referenced Single Supply Amplifiers
  • Fast Sample-Hold Amplifiers
  • Long Duration Timers/Monostables
  • Ideal Interface with Digital CMOS
  • High Input Impedance Wideband Amplifiers
  • Voltage Followers (e.g., Follower for Single Supply D/A Converter)
  • Voltage Regulators (Permits Control of Output Voltage Down to 0V)
  • Wien Bridge Oscillators
  • Voltage Controlled Oscillators
  • Photo Diode Sensor Amplifiers
  • 5V Logic Systems
  • Microprocessor Interface NON INV. INPUT (A) OUTPUT (B) INV. INPUT (B) NON INV. INPUT (B) OUTPUT (A) A B + - +-INV. INPUT (A)

Ordering Information

PART NUMBER PART MARKING TEMP. RANGE (°C) PACKAGE PKG. DWG. # CA5260AM96 5260A -55 to 125 8 Ld SOIC Tape and Reel M8.15 CA5260M 5260 -55 to 125 8 Ld SOIC M8.15 CA5260MZ (Note) CA5260MZ -55 to 125 8 Ld SOIC (Pb-free) M8.15 CA5260MZ96 (Note) CA5260MZ -55 to 125 8 Ld SOIC (Pb-free) M8.15 NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. FN1929.6 CA5260, CA5260A Data Sheet December 23, 2005 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or1-888-468-37743 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2003-2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.

2 FN1929.6 December 23, 2005 Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2) θJA (°C/W) (Lead Tips Only) CAUTION: Stresses above those listed in “Abs olute Maximum Ratings” may cause permanent dam age to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θJA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Typical Values Intended Only for Design Guidance, V+ = 5V, V- = 0V, TA = 25°C, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITSCA5260 CA5260A Input Resistance R I 1.5 1.5 T Ω Input Capacitance C I f = 1MHz 4.3 4.3 pF Unity Gain Crossover Frequency f T 33 M H z Slew Rate SR V OUT = 2.5VP-P 55 V / µs Transient Response C L = 25pF, RL = 2kΩ (Voltage Follower) Rise Time tr 0.09 0.09 µs Overshoot OS 10 10 % Settling Time (To <0.1%, VIN = 4VP-P)t S CL = 25pF, RL = 2kΩ (Voltage Follower) 1.8 1.8 µs Electrical Specifications TA = 25°C, V+ = 5V, V- = 0V PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 2 15 - 1.5 4 mV Input Offset Current I IO VO = 2.5V - 1 10 - 1 10 pA Input Current I I VO = 2.5V - 2 15 - 2 15 pA Common Mode Rejection Ratio CMRR V CM = 0 to 1V 70 85 - 80 85 - dB VCM = 0 to 2.5V 50 55 - 50 55 - dB Common Mode Input Voltage Range VlCR+2 . 5 3 - 2 . 5 3 - V Power Supply Rejection Ratio PSRR ∆V+ = 1V; ∆V- = 1V 70 84 - 75 84 - dB Large Signal Voltage Gain (Note 3) AOL RL = ∞, VO = 0.5 to 4V 105 111 - 107 113 - dB RL = 10kΩ, VO = 0.5 to 3.6V 80 86 - 83 86 - dB Source Current I SOURCE VO = 0V 1.75 2.2 - 1.75 2.2 - mA Sink Current I SINK VO = 5V 1.70 2 - 1.70 2 - mA CA5260, CA5260ACA5260, CA5260A

3 FN1929.6 December 23, 2005 Output Voltage V OM+R L = ∞ 4.99 5 - 4.99 5 - V VOM- - 0 0.01 - 0 0.01 V VOM+R L = 10kΩ 4.4 4.7 - 4.4 4.7 - V VOM- - 0 0.01 - 0 0.01 V VOM+R L = 2kΩ 33 . 4- 33 . 4- V VOM- - 0 0.01 - 0 0.01 V Supply Current I SUPPLY VO = 0V - 1.60 2.0 - 1.60 2.0 mA NOTE: Electrical Specifications TA = 25°C, V+ = 5V, V- = 0V (Continued) PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A UNITSMIN TYP MAX MIN TYP MAX Electrical Specifications TA = -55°C to 125°C, V+ = 5V, V- = 0V PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 3 20 - 2 15 mV Input Offset Current I IO VO = 2.5V - 1 10 - 1 10 nA Input Current I I VO = 2.5V - 2 15 - 2 15 nA Common Mode Rejection Ratio CMRR V CM = 0 to 1V 60 78 - 65 78 - dB VCM = 0 to 2.5V 50 60 - 50 60 - dB Common Mode Input Voltage Range VlCR+2 . 5 3 - 2 . 5 3 - V Power Supply Rejection Ratio PSRR ∆V+ = 1V; ∆V- = 1V 60 65 - 62 65 - dB Large Signal Voltage Gain (Note 4) A OL RL = ∞, VO = 0.5 to 4V 70 78 - 70 78 - dB RL = 10kΩ, VO = 0.5 to 3.6V 60 65 - 60 65 - dB Source Current I SOURCE VO = 0V 1.3 1.6 - 1.3 1.6 - mA Sink Current I SINK VO = 5V 1.2 1.4 - 1.2 1.4 - mA Output Voltage V OM+R L = ∞ 4.99 5 - 4.99 5 - V VOM- - 00 . 0 1- 00 . 0 1V VOM+R L = 10kΩ 4.2 4.4 - 4.2 4.4 - V VOM- - 00 . 0 1- 00 . 0 1V VOM+R L = 2kΩ 2.5 2.7 - 2.5 2.7 - V VOM- - 00 . 0 1- 00 . 0 1V Supply Current I SUPPLY VO = 0V - 1.65 2.2 - 1.65 2.2 mA NOTE: CA5260, CA5260ACA5260, CA5260A

4 FN1929.6 December 23, 2005 Electrical Specifications Each Amplifier at TA = 25°C, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5260 CA5260A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VS = ±7.5 - 6 15 - 2 5 mV Input Offset Current I IO VS = ±7.5 - 0.5 30 - 0.5 20 pA Input Current I I VS = ±7 . 5 - 55 0- 53 0 p A Large Signal Voltage Gain A OL VO = 10VP-P, RL = 10kΩ 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB Common Mode Rejection Ratio CMRR 70 90 - 80 95 - dB Common Mode Input Voltage Range VlCR 10 -0.5 to 01 0 - 0 . 5 t o Power Supply Rejection Ratio, ∆VIO/ ∆V± PSRR V S = ±7.5 - 32 320 - 32 150 µV/V Maximum Output Voltage V OM+R L = 10kΩ 11 13.3 - 11 13.3 - V VOM- - 0.002 0.01 - 0.002 0.01 V VOM+R L = ∞ 14.99 15 - 14.99 15 - V VOM-- 0 0 . 0 1 - 0 0 . 0 1 V Maximum Output Current I OM+ (Source) VO = 7.5V 12 22 45 12 22 45 mA IOM- (Sink) 12 20 45 12 20 45 mA Total Supply Current, RL = ∞ I+ V O (Amp A) = 7.5V VO (Amp B) = 7.5V - 9 16.5 - 9 16.5 mA VO (Amp A) = 0V VO (Amp B) = 0V -1 . 24 -1 . 24 m A VO (Amp A) = 0V VO (Amp B) = 7.5V -5 9 . 5 -5 9 . 5 m A Input Offset Voltage Temperature Drift ∆VIO/∆T- 8 - - 6 - µV/°C Crosstalk f = 1kHz - 120 - - 120 - dB CA5260, CA5260ACA5260, CA5260A

5 FN1929.6 December 23, 2005 Schematic Diagram 200K R7 300K Q12 Q11 Q10 D2 D3 D4D1 Q1 Q2 Q13Q14 Q3 Q4 30pF 3 2 1 AMPLIFIER A R13 200K R14 300Ω Q26 Q25 Q24D7D6 D5 D8 Q15 Q16 Q20 R11 R10 Q27 Q28 Q17Q18 30pF R12 Q21 Q23 567 Q19 Q22 AMPLIFIER B OUT -IN +IN V-+IN -IN CA5260, CA5260A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN1929.6 December 23, 2005 CA5260, CA5260ACA5260, CA5260A Small Outline Plastic Packages (SOIC) INDEX AREA E D N 123 -B- 0.25(0.010) C AM BS e -A- L B M -C- A SEATING PLANE 0.10(0.004) h x 45° C H 0.25(0.010) BM M α NOTES: 1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M -1982. 3. Dimension “D” does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension “E” does not include interlead flash or protrusions. Inter- lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. “L” is the length of terminal for soldering to a substrate. 7. “N” is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETE R. Converted inch dimensions are not necessarily exact. M8.15 (JEDEC MS-012-AA ISSUE C)

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

A 0.0532 0.0688 1.35 1.75 - A1 0.0040 0.0098 0.10 0.25 - B 0.013 0.020 0.33 0.51 9 C 0.0075 0.0098 0.19 0.25 - D 0.1890 0.1968 4.80 5.00 3 E 0.1497 0.1574 3.80 4.00 4 e 0.050 BSC 1.27 BSC - H 0.2284 0.2440 5.80 6.20 - h 0.0099 0.0196 0.25 0.50 5 L 0.016 0.050 0.40 1.27 6 N8 8 7 α 0° 8° 0° 8° - Rev. 1 6/05