CA5160 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- MOSFET Input Stage - Very High ZI; 1.5TΩ (1.5 x 1012Ω ) (Typ) - Very Low II; 5pA (Typ) at 15V Operation 2pA (Typ) at 5V Operation
- Common-Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can be Swung 0.5V Below Negative Supply Rail
- CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails
- CA5160 Has Full Military Temperature Range Guaranteed Specifications for V+ = 5V
- CA5160 is Guaranteed to Operate Down to 4.5V for A OL
- CA5160 is Guaranteed Up to±7.5V
Applications
- Ground Referenced Single Supply Amplifiers
- Fast Sample-Hold Amplifiers
- Long Duration Timers/Monostables
- Ideal Interface With Digital CMOS
- High Input Impedance Wideband Amplifiers
- Voltage Followers (e.g., Follower for Single Supply D/A Converter)
- Wien-Bridge Oscillators
- Voltage Controlled Oscillators
- Photo Diode Sensor Amplifiers
- 5V Logic Systems
- Microprocessor Interface
Description
CA5160 is an integrated circuit operational amplifier that com- bines the advantage of both CMOS and bipolar transistors on a monolithic chip. The CA5160 is a frequency compensated version of the popular CA5130 series. It is designed and guar- anteed to operate in microprocessor or logic systems that use +5V supplies. Gate-protected P-Channel MOSFET (PMOS) transistors are used in the input circuit to provide very high input impedance, very low input current, and exceptional speed performance. The use of PMOS field effect transistors in the input stage results in common-mode input voltage capability down to 0.5V below the negative supply terminal, an important attribute in single supply applications. A complementary symmetry MOS (CMOS) transistor pair, capable of swinging the output voltage to within 10mV of either supply voltage terminal (at very high values of load impedance), is employed as the output circuit. The CA5160 operates at supply voltages ranging from +5V to +16V, or±2.5V to±8V when using split supplies, and have ter- minals for adjustment of offset voltage for applications requir- ing offset-null capability. Terminal provisions are also made to permit strobing of the output stage. It has guaranteed specifi- cations for 5V operation over the full military temperature range of -55 oC to 125oC. Pinout
Ordering Information
(BRAND) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA5160E -55 to 125 8 Ld PDIP E8.3 CA5160M96 (5160) -55 to 125 8 Ld SOIC Tape and Reel M8.15 CA5160 (PDIP, SOIC) TOP VIEW NOTE: CA5160 devices have an on-chip frequency compensation network. Supplementary phase-compensation or frequency roll-off (if desired) can be connected externally between terminals 1 and 8. NON INV. INPUT STROBE OUTPUT OFFSET NULL OFFSET NULL INV. INPUT File Number 1924.4 NOT RECOMMENDED FOR NEW DESIGNS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 1)θJA (oC/W) θJC (oC/W) oC (SOIC - Lead Tips Only) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. θJA is measured with the component mounted on an evaluation PC board in free air. 2. Short circuit may be applied to ground or to either supply. Electrical SpecificationsTA = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5160 UNITSMIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 2 10 mV Input Offset Current I IO VO = 2.5V - 0.1 10 pA Input Current I I VO = 2.5V - 2 15 pA Common Mode Rejection Ratio CMRR V CM = 0 to 1V 70 80 - dB VCM = 0 to 2.5V 60 69 - dB Common Mode Input Voltage Range V lCR+ 2.5 2.8 - V VlCR- - -0.5 0 V Power Supply Rejection Ratio PSRR ∆V+ = 1V;∆V- = 1V 55 67 - dB Large Signal Voltage Gain (Note 3) VO = 0.1 to 4.1V A OL R L= ∞ 95 117 - dB VO = 0.1 to 3.6V R L=10kΩ 85 102 - dB Source Current I SOURCE VO = 0V 1.0 3.4 4.0 mA Sink Current I SINK VO = 5V 1.0 2.2 4.0 mA Maximum Output Voltage VOM +V OUT R L =∞ 4.99 5 - V VOM - - 0 0.01 V VOM +R L = 10kΩ 4.4 4.7 - V VOM - - 0 0.01 V VOM +R L = 2kΩ 2.5 3.3 - V VOM - - 0 0.01 V Supply Current I SUPPL Y VO = 0V - 50 100 µA ISUPPL Y VO = 2.5V - 320 400 µA NOTE: Electrical SpecificationsTA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5160 UNITSMIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 3 15 mV Input Offset Current I IO VO = 2.5 V - 0.1 10 nA CA5160
Input Current I I VO = 2.5V - 2 15 nA Common Mode Rejection Ratio CMRR V CM = 0 to 1V 60 80 - dB VCM = 0 to 2.5V 50 75 - dB Common Mode Input Voltage Range V lCR+ 2.5 2.8 - V VlCR- - -0.5 0 V Power Supply Rejection Ratio PSRR ∆V+ = 2V 40 60 - dB Large Signal Voltage Gain (Note 4) VO = 0.1 to 4.1V A OL R L= ∞ 90 110 - dB VO = 0.1 to 3.6V R L=10kΩ 75 100 - dB Source Current I SOURCE VO = 0V 0.6 - 5.0 mA Sink Current I SINK VO = 5V 0.6 - 5.0 mA Maximum Output Voltage V OM +V OUT R L= ∞ 4.99 5 - V VOM - - 0 0.01 V VOM +R L = 10kΩ 4.0 4.3 - V VOM - - 0 0.01 V VOM +R L = 2kΩ 2.0 2.5 - V VOM - - 0 0.01 V Supply Current V O = 0V I SUPPL Y - 170 220 µA VO = 2.5V I SUPPL Y - 410 500 µA NOTE: Electrical SpecificationsTA = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS CA5160 UNITSMIN TYP MAX Electrical SpecificationsTA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5160 UNITSMIN TYP MAX Input Offset Voltage V IO VS = ±7.5V - 6 15 mV Input Offset Current I IO VS = ±7.5V - 0.5 30 pA Input Current I I VS = ±7.5V - 5 50 pA Large Signal Voltage Gain A OL VO = 10VP-P R L = 2kΩ 50 320 - kV/V 94 110 - dB Common Mode Rejection Ratio CMRR 70 90 - dB Common Mode Input Voltage Range V lCR 10 -0.5 to 12 0 V Power Supply Rejection Ratio PSRR ∆V+ = 1V;∆V- = 1V VS =±7.5V - 32 320 µV/V Maximum Output Voltage VOM +V OUT R L = 2kΩ 12 13.3 - V VOM - - 0.002 0.01 V VOM +R L =∞ 14.99 15 - V VOM - - 0 0.1 V CA5160
IOM + (Source) I O VO = 0V 12 22 45 mA IOM - (Sink) V O = 15V 12 20 45 mA Supply Current I+ R L =∞ , VO = 7.5V - 10 15 mA R L =∞ , VO = 0V - 2 3 mA Input Offset Voltage Temperature Drift ∆VIO/∆T- 8 - µV/oC Electrical SpecificationsTA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS CA5160 UNITSMIN TYP MAX Electrical SpecificationsFor Design Guidance, At TA = 25oC, VSUPPL Y =±7.5V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS TYPICAL VALUES UNITSCA5160 Input Offset Voltage Adjustment Range 10k Ω Across Terminals 4 and 5 or 4 and 1 ±22 mV Input Resistance R I 1.5 T Ω Input Capacitance C I f = 1MHz 4.3 pF Equivalent Input Noise Voltage e N BW = 0.2MHz, RS = 1MΩ 40 µV BW = 0.2MHz, RS = 10MΩ 50 µV Equivalent Input Noise Voltage e N R S = 100Ω , 1kHz 72 nV/ √Hz R S = 100Ω , 10kHz 30 nV/ √Hz Unity Gain Crossover Frequency f T 4 MHz Slew Rate SR 10 V/ µs Transient Response Rise Time t R C C = 25pF, RL = 2kΩ (Voltage Follower) 0.09 µs Overshoot OS 10 % Settling Time (To <0.1%, VIN = 4VP-P)t S C C = 25pF, RL = 2kΩ , (Voltage Follower) 1.8 µs BIAS CKT. 200µA 1.35mA 200 µA 8mA (NOTE 5) OUTPUT AV ≈ 30XAV ≈ 6000X STROBE OFFSET NULL COMPENSATION (WHEN DESIRED) INPUT AV ≈ 5X C C NOTE: 5. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 6. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail. 5 1 0mA (NOTE 6) CA5160
Application Information
Refer to the block diagram of the CA5160 CMOS Operational Amplifier. The input terminals may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Conse- quently, the CA5160 circuit is ideal for single supply operation. Three class A amplifier stages, having the individual gain capability and current consumption shown in the block dia- gram, provide the total gain of the CA5160. A biasing circuit provides two potentials for common use in the first and sec- ond stages. Terminals 8 and 1 can be used to supplement the internal phase compensation network if additional phase com- pensation or frequency roll-off is desired. Terminals 8 and 4 can also be used to strobe the output stage into a low quies- cent current state. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resis- tance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in com- parator applications). Input Stages The circuit of the CA5160 is shown in the schematic diagram. It consists of a differential input stage using PMOS field effect transistors (Q 6, Q7) working into a mirror pair of bipolar tran- sistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also func- tion as a differential-to-single-ended converter to provide base drive to the second-stage bipolar transistor (Q 11). Offset null- ing, when desired, can be effected by connecting a 100,000Ω potentiometer across Terminals 1 and 5 and the potentiome- ter slider arm to Terminal 4. Cascode-connected PMOS transistors Q 2, Q4, are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D 5 through D7 provide gate- oxide protection against high voltage transients, including static electricity during handling for Q 6 and Q7. Second Stage Most of the voltage gain in the CA5160 is provided by the second amplifier stage, consisting of bipolar transistor Q11 and its cascode-connected load resistance provided by 4815 BIAS CIRCUIT “CURRENT SOURCE LOAD” FOR Q 11 Q 2 D 1 D 2 D 3 D 4 8.3V Q 1 R 1 40kΩ Q 4 R 2 5kΩ INPUT STAGE D 5 NON-INV. INPUT INV. INPUT Q 6 R 3 1kΩ Q 9 Q 10 R 5 1kΩ R 6 1kΩ R 4 1kΩ Q 7 D 6 D 7 Q 3 OFFSET NULL Q 11 SUPPLEMENTARY COMP IF DESIRED STROBING SECOND OUTPUT Q 8 Q 12 STAGE STAGE Q 5 2kΩ pF OUTPUT CURRENT SOURCE FOR Q 6 AND Q 7 NOTE: Diodes D5 through D7 provide gate oxide protection for MOSFET Input Stage. CA5160
if desired, may be used between Terminals 1 and 8. both the first and second amplifier stages, respectively. 4.5V results in seriously degraded performance. fier using CMOS transistors operating in the Class A mode. including the negative supply rail. tioned in the mid point of the potentiometer’s total range.
- Figure 1 contains data showing the variation of input
“guarded” from spurious leakage currents. FIGURE 1. CA5160 INPUT CURRENT vs COMMON MODE
9 Bit CMOS DAC
10V logic levels are used in the circuit of Figure 8. tems tailored to particular needs. when the regulated output voltage is required to approach 0V. of zero with only one DC power supply input. condition typical of many operational-amplifier regulator circuits. to have influence on the regulator performance. CD4007A CMOS IC”, Application Note AN6080. Center Trace: Difference Signal 5mV/Div. FIGURE 6. SPLIT SUPPLY VOLTAGE FOLLOWER WITH
thereby adjusting the multivibrator interval, T3. FIGURE 7. SINGLE SUPPLY VOLTAGE FOLLOWER WITH
1 Standard
FIGURE 8. 9 BIT DAC USING CMOS DIGITAL SWITCHES AND CA5160
FIGURE 11. CA5160A HIGH INPUT RESISTANCE DC VOLTMETER
3 POSITION
All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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FIGURE 26. OUTPUT CURRENT vs TEMPERATURE FIGURE 27. VOLTAGE ACROSS PMOS OUTPUT TRANSISTOR FIGURE 28. VOLTAGE ACROSS NMOS OUTPUT TRANSISTOR FIGURE 29. EQUIVALENT NOISE VOLTAGE vs FREQUENCY