CA5130

CA5130 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

• MOSFET Input Stage 2pA (Typ) at 5V Operation
• Ideal for Single Supply Applications
• Common Mode Input Voltage Range Includes Negative Supply Rail; Input Terminals Can Be Swung 0.5V Below Negative Supply Rail
• CMOS Output Stage Permits Signal Swing to Either (or Both) Supply Rails
• CA5130A, CA5130 Have Full Military Temperature Range Guaranteed Specifications for V+ = 5V
• CA5130A, CA5130 Are Guaranteed to Operate Down to V+ = 4.5V for A OL
• CA5130A, CA5130 Are Guaranteed to Operate at±7.5V CA3130A, CA3130 Specifications

Applications

• Ground Referenced Single Supply Amplifiers
• Fast Sample-Hold Amplifiers
• Long Duration Timers/Monostables
• High Input lmpedance Comparators (Ideal Interface with Digital CMOS)
• High lnput Impedance Wideband Amplifiers
• Voltage Followers (e.g., Follower for Single-Supply D/A Converter)
• Voltage Regulators (Permits Control of Output Voltage Down to 0V)
• Peak Detectors
• Single Supply Full Wave Precision Rectifiers
• Photo Diode Sensor Amplifiers
• 5V Logic Systems
• Microprocessor Interface OFFSET NULL INV. INPUT NON-INV. INPUT STROBE OUTPUT OFFSET NULL Part Number Information PART NUMBER (BRAND) TEMP. RANGE ( oC) PACKAGE PKG. NO. CA5130AE -55 to 125 8 Ld PDIP E8.3 CA5130E -55 to 125 8 Ld PDIP E8.3 Data Sheet March 2000 [ /Title /Sub- ject () /Autho r () /Key- words /Cre- ator () /DOCI NFO pdf- mark /Page- Mode /Use- Out- lines /DOC- VIEW pdf- mark OBSOLETE PR ODUCT POSSIBLE SUBSTITUTE PR ODUCT CA3130

Absolute Maximum Ratings Thermal Information Operating Conditions Thermal Resistance (Typical, Note 2)θJA (oC/W) θJC (oC/W) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTES: 1. Short circuit may be applied to ground or to either supply. 2. θ JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications T A = 25oC, V+ = 5V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5130 CA5130A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 2 10 - 1.5 4 mV Input Offset Current I IO VO = 2.5V - 0.1 10 - 0.1 5 pA Input Current I I VO = 2.5V - 2 15 - 2 10 pA Common Mode Rejection Ratio CMRR V CM = 0V to 1V 70 85 - 75 87 - dB VCM = 0V to 2.5V 60 69 - 60 69 - dB Input Common Mode Voltage Range Power Supply Rejection Ratio PSRR ∆+ = 1V;∆- = 1V 55 73 - 60 75 - dB Large Signal Voltage Gain (Note 3) AOL VO = 0.1V to 4.1V R L =∞ 95 105 - 100 105 - dB VO = 0.1V to 3.6V R L = 10kΩ 85 95 - 90 97 - dB Output Voltage V OUT VOM +R L =∞ 4.99 5 - 4.99 5 - V VOM - - 0 0.01 - 0 0.01 V VOM +R L = 10kΩ 4.4 4.7 - 4.4 4.7 - V VOM - - 0 0.01 - 0 0.01 V VOM +R L = 2kΩ 2.5 3.5 - 2.5 3.5 - V VOM - - 0 0.01 - 0 0.01 V Supply Current I SUPPL Y VO = 0V - 50 100 - 50 100 µA VO = 2.5V - 260 400 - 260 400 µA NOTE: CA5130, CA5130A

Electrical Specifications T A = -55oC to 125oC, V+ = 5V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5130 CA5130A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO VO = 2.5V - 3 15 - 2 10 mV Input Offset Current I IO VO = 2.5V - 0.1 10 - 0.1 5 nA Input Current I I VO = 2.5V - 2 15 - 2 10 nA Common Mode Rejection Ratio CMRR V CM = 0V to 1V 60 80 - 60 80 - dB VCM = 0V to 2.5V 50 80 - 55 80 - dB Input Common Mode Voltage Range Power Supply Rejection Ratio PSRR ∆+ = 1V;∆- = 1V 40 66 - 45 70 - dB Large Signal Voltage Gain (Note 4) AOL VO = 0.1V to 4.1V R L =∞ 90 98 - 94 98 - dB VO = 0.1V to 3.6V R L = 10kΩ 75 85 - 80 88 - dB Output Voltage V OUT VOM +R L =∞ 4.99 5 - 4.99 5 - V VOM - - 0 0.01 - 0 0.01 V VOM +R L = 10kΩ 4.0 4.6 - 4.0 4.6 - V VOM - - 0 0.01 - 0 0.01 V VOM +R L = 2kΩ 2.0 3.0 - 2.0 3.0 - V VOM - - 0 0.01 - 0 0.01 V Supply Current I SUPPL Y VO = 0V - 80 220 - 80 220 µA VO = 2.5V - 300 500 - 300 500 µA NOTE: Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5130 CA5130A UNITSMIN TYP MAX MIN TYP MAX Input Offset Voltage V IO V± =±7.5V - 8 15 - 2 5 mV Input Offset Current I IO V± =±7.5V - 0.5 30 - 0.5 20 pA Input Current I I V± =±7.5V - 5 50 - 5 30 pA Common Mode Rejection Ratio CMRR 70 90 - 80 90 - dB Input Common Mode Voltage Range V ICR 10 -0.5 to 0 10 -0.5 to Power Supply Rejection Ratio PSRR ∆VIO/∆V± V± =±7.5V - 32 320 - 32 150 µV/V Large Signal Voltage Gain A OL VO = 10VP-P R L = 2kΩ 50 320 - 50 320 - kV/V 94 110 - 94 110 - dB CA5130, CA5130A

Source I OM +V O = 0V 12 22 45 12 22 45 mA Sink I OM -V O = 15V 12 20 45 12 20 45 mA Supply Current I SUPPL Y VO = 7.5V, RL =∞ - 10 15 - 10 15 mA VO = 0V, RL =∞ -23-23 m A Maximum Output Voltage V OUT VOM +R L =∞ 14.99 15 - 14.99 15 - V VOM - - 0 0.01 - 0 0.01 V VOM +R L = 2kΩ 12 13.3 - 12 13.3 - V VOM - - 0.002 0.01 - 0.002 0.01 V Input Offset Voltage Temperature Drift ∆VIO/∆T - 10 - - 10 - µV/oC Electrical Specifications TA = 25oC, V+ = 15V, V- = 0V, Unless Otherwise Specified (Continued) PARAMETER SYMBOL TEST CONDITIONS CA5130 CA5130A UNITSMIN TYP MAX MIN TYP MAX Electrical Specifications Typical Values Intended Only for Design Guidance, At TA = 25oC, VSUPPL Y = ±7.5V Unless Otherwise Specified PARAMETER SYMBOL TEST CONDITIONS CA5130 CA5130A UNITSTYP TYP Input Offset Voltage Adjustment Range 10k Ω Across Terminals 4 and 5 or 4 and 1±22 ±22 mV Input Resistance R I 1.5 1.5 T Ω Input Capacitance C I f = 1MHz 4.3 4.3 pF Equivalent Input Noise Voltage e N BW = 0.2MHz, RS = 1MΩ (Note 5) 23 23 µV Open Loop Crossover Frequency For Unity Gain Stability≥47pF Required fT C C = 0 15 15 MHz C C = 47pF 4 4 MHz Slew Rate SR Open Loop C C = 0 30 30 V/ µs Closed Loop C C = 56pF 10 10 V/ µs Transient Response C C = 56pF, CL = 25pF, RL = 2kΩ (Voltage Follower)Rise Time t r 0.09 0.09 µs Overshoot OS 10 10 % Settling Time (To <0.1%, VIN = 4VP-P)t S C C = 56pF, CL = 25pF, RL = 2kΩ (Voltage Follower) 1.2 1.2 µs NOTE: 5. Although a 1MΩ source is used for this test, the equivalent input noise remains constant for values of RS up to 10MΩ . CA5130, CA5130A

8.3V INPUT R 3 1kΩ R 4 1kΩ R 6 1kΩ R 5 1kΩ NON-INV. INPUT INV. INPUT R 1 40kΩ 5kΩ R 2 BIAS CIRCUIT CURRENT SOURCE FOR “CURRENT SOURCE LOAD” FOR Q 11Q 6 AND Q 7 OUTPUT OUTPUT STAGE Q 8 Q 12 Q 11 SECOND STAGE OFFSET NULL COMPENSATION STROBING STAGE NOTE: 6. Diodes D5 through D8 provide gate oxide protection for MOSFET Input Stage. (NOTE 6) 815 BIAS CKT. COMPENSATION (WHEN REQUIRED) AV ≈ 5X AV ≈ AV ≈ 6000X 30XINPUT 200µA 200 µA1.35mA 8mA (NOTE 7) 0mA (NOTE 8) OUTPUT STROBE C C OFFSET NULL CA5130 NOTES: 7. Total supply voltage (for indicated voltage gains) = 15V with input terminals biased so that Terminal 6 potential is +7.5V above Terminal 4. 8. Total supply voltage (for indicated voltage gains) = 15V with output terminal driven to either supply rail. CA5130, CA5130A

Application Information

The input terminals shown in the block diagram of the CA5130 Series CMOS Operational Amplifiers may be operated down to 0.5V below the negative supply rail, and the output can be swung very close to either supply rail in many applications. Consequently, the CA5130 Series circuits are ideal for single supply operation. Three Class A amplifier stages, having the individual gain capability and current consumption shown in the Block Diagram, provide the total gain of the CA5130. A biasing circuit provides two potentials for common use in the first and second stages. Terminal 8 can be used both for phase compensation and to strobe the output stage into quiescence. When Terminal 8 is tied to the negative supply rail (Terminal 4) by mechanical or electrical means, the output potential at Terminal 6 essentially rises to the positive supply rail potential at Terminal 7. This condition of essentially zero current drain in the output stage under the strobed “OFF” condition can only be achieved when the ohmic load resistance presented to the amplifier is very high (e.g., when the amplifier output is used to drive CMOS digital circuits in comparator applications). Input Stages The circuit of the CA5130 is shown in the Schematic Diagram. It consists of a differential input stage using PMOS field-effect transistors (Q 6, Q7) working into a mirror pair of bipolar transistors (Q9, Q10) functioning as load resistors together with resistors R3 through R6. The mirror pair transistors also function as a differential-to-single-ended converter to provide base drive to the second stage bipolar transistor (Q 11). Offset nulling, when desired, can be effected by connecting a 100,000Ω potentiometer across Terminals 1 and 5 and the potentiometer slider arm to Terminal 4. Cascode connected PMOS transistors Q 2, Q4 are the constant current source for the input stage. The biasing circuit for the constant current source is subsequently described. The small diodes D through D8 provide gate oxide protection against high voltage transients, e.g., including static electricity during handling for Q 6 and Q7. Second Stage Most of the voltage gain in the CA5130 is provided by the second amplifier stage, consisting of bipolar transistor Q and its cascode connected load resistance provided by PMOS transistors Q 3 and Q5. The source of bias potentials for these PMOS transistors is subsequently described. Miller-Effect compensation (roll-off) is accomplished by simply connecting a small capacitor between Terminals 1 and 8. A 47pF capacitor provides sufficient compensation for stable unity gain operation in most applications. Bias Source Circuit At total supply voltages, somewhat above 8.3V, resistor R2 and zener diode Z1 serve to establish a voltage of 8.3V across the series connected circuit, consisting of resistor R1, diodes D1 through D4, and PMOS transistor Q1. A tap at the junction of resistor R1 and diode D4 provides a gate bias potential of about 4.5V for PMOS transistors Q4 and Q5 with respect to Terminal 7. A potential of about 2.2V is developed across diode connected PMOS transistor Q 1 with respect to Terminal 7 to provide gate bias for PMOS transistors Q2 and Q 3. It should be noted that Q1 is “mirror connected” to both Q 2 and Q3. Since transistors Q1,Q 2,Q 3 are designed to be identical, the approximately 200µA current in Q1 establishes a similar current in Q2 and Q3 as constant current sources for both the first and second amplifier stages, respectively. At total supply voltages somewhat less than 8.3V, zener diode Z1 becomes nonconductive and the potential, developed across series connected R1,D1-D4, and Q1, varies directly with variations in supply voltage. Consequently, the gate bias for Q4, Q 5 and Q2, Q3 varies in accordance with supply voltage variations. This variation results in deterioration of the power supply rejection ratio (PSRR) at total supply voltages below 8.3V. Operation at total supply voltages below about 4.5V results in seriously degraded performance. Output Stage The output stage consists of a drain loaded inverting amplifier using CMOS transistors operating in the Class A mode. When operating into very high resistance load, the output can be swung within mV of either supply rail. Because the output stage is a drain loaded amplifier, its gain is dependent upon the load impedance. The transfer characteristics of the output stage for a load returned to the negative supply rail are shown in Figure 15. Typical op amp loads are readily driven by the output stage. Because large signal excursions are nonlinear, requiring feedback for good waveform reproduction, transient delays may be encountered. As a voltage follower, the amplifier can achieve 0.01% accuracy levels, including the negative supply rail. Input Current Variation with Common Mode Input Voltage As shown in the Table of Electrical Specifications, the input current for the CA5130 Series Op Amps is typically 5pA at T A =2 5oC when Terminals 2 and 3 are at a common mode potential of +7.5V with respect to negative supply Terminal 4. Figure 24 contains data showing the variation of input current as a function of common mode input voltage at T A =2 5oC. This data shows that circuit designers can advantageously exploit these characteristics to design circuits which typically require an input current of less than 1pA, provided the common mode input voltage does not exceed 2V. As previously noted, the input current is essentially the result of the leakage current through the gate protection diodes in the input circuit and, therefore, a function of the applied voltage. Although the finite resistance of the glass terminal-to-case insulator of the metal can package also contributes an increment of leakage current, there are useful compensating factors. Because the gate protection network functions as if it is connected to Terminal 4 potential, and the metal can case of the CA5130 is also internally tied to Terminal 4, input Terminal 3 is essentially “guarded” from spurious leakage currents. CA5130, CA5130A

FIGURE 7. PEAK-DETECTOR CIRCUITS FIGURE 8. VOLTAGE REGULATOR CIRCUIT (0V TO 13V AT 40mA)

0.3 VP-P INPUT;

0 TO 13V

1. Regulation (no load to full load): <0.01%.
2. Input Regulation: 0.02%/V.
3. Hum and noise output: <25µV up to 100kHz.

FIGURE 9. VOLTAGE REGULATOR CIRCUIT (0.1V TO 50V AT 1A) FIGURE 10. PULSE GENERATOR (ASTABLE MULTIVIBRATOR) WITH PROVISIONS FOR INDEPENDENT CONTROL OF “ON” AND “OFF”

0.1 TO 50V

1. Regulation (no load to full load): <0.005%.
2. Input Regulation: 0.01%/V.
3. Hum and noise output: <250µV

FIGURE 25. INPUT CURRENT vs TEMPERATURE FIGURE 26. TYPICAL INCREMENTAL OFFSET VOLTAGE

All Intersil semiconductor products are manufactured, assembled and tested underISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with- out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web sitewww.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (321) 724-7000 FAX: (321) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee

1130 Brussels, Belgium

TEL: (32) 2.724.2111 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029 CA5130, CA5130A Dual-In-Line Plastic Packages (PDIP) CL E eA C eB eC -B- INDEX 1 2 3 N/2 N AREA SEATING BASE PLANE PLANE -C- B e D AA2 L A 1 -A- 0.010 (0.25) C AM BS NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protru- sions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and are measured with the leads constrained to be per- pendicular to datum . 7. e B and eC are measured at the lead tips with the leads uncon- strained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm). eA -C- E8.3(JEDEC MS-001-BA ISSUE D)

8 LEAD DUAL-IN-LINE PLASTIC PACKAGE

A - 0.210 - 5.33 4 A1 0.015 - 0.39 - 4 A2 0.115 0.195 2.93 4.95 - B 0.014 0.022 0.356 0.558 - B1 0.045 0.070 1.15 1.77 8, 10 C 0.008 0.014 0.204 0.355 - D 0.355 0.400 9.01 10.16 5 D1 0.005 - 0.13 - 5 E 0.300 0.325 7.62 8.25 6 E1 0.240 0.280 6.10 7.11 5 e 0.100 BSC 2.54 BSC - e A 0.300 BSC 7.62 BSC 6 eB - 0.430 - 10.92 7 L 0.115 0.150 2.93 3.81 4 N8 8 9 Rev. 0 12/93