CA1524 INTERSIL | Alldatasheet

Document overview

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  • PDF pages: 16

Technical content

Features

  • Complete PWM Power Control Circuitry
  • Separate Outputs for Single-Ended or Push-Pull Operation
  • Internal Reference Supply with 1% (Max) Oscillator and Reference Voltage Variation Over Full Temperature Range
  • Standby Current of Less Than 10mA
  • Frequency of Operation Beyond 100kHz
  • Variable-Output Dead Time of 0.5µs to 5µs
  • L o w V CE(sat) Over the Temperature Range

Applications

  • Positive and Negative Regulated Supplies
  • Dual-Output Regulators
  • Flyback Converters
  • DC-DC Transformer-Coupled Regulating Converters
  • Single-Ended DC-DC Converters
  • Variable Power Supplies File Number 1239.4 Pinout CA1524, CA3524 (PDIP, CERDIP) TOP VIEW C T R T VREF EMITTER B COLLECTOR B COLLECTOR A EMITTER A SHUTDOWN INV. INPUT OSC OUT GND (-) C.L. SENSE (+) C.L. SENSE COMPENSATION AND COMPARATOR NON- INV. INPUT October 2000 CA2524 IS AN OBSOLETEPR ODUCT

CA1524, CA2524, CA3524 Functional Block Diagram Test Circuit REFERENCE REGULATOR FLIP OSCILLATOR COMPARATOR INV. INPUT NON-INV. INPUT ERROR AMP SHUTDOWN GND FLOP +5V +5V TO ALL INTERNAL CIRCUITS +5V +5V +5V C.L. +5V 10kΩ 1kΩ COMPENSATION AND COMPARATOR - SENSE + SENSE SA EA C A SB EB C B C T R T OSC OUT VREF 5410912768 ls CA1524 8 - 40V 0.1µF R T C T 2kΩ 10kΩ 1kΩ kΩ 2kΩ 2kΩ 2kΩ 2kΩ OUT A OUT B

Specifications CA1524,CA2524, CA3524 Absolute Maximum Ratings Thermal Information Output Current Each Output: Thermal Resistance θ JA Device Dissipation Lead Temperature (During Soldering) At distance 1/16± in. (1.59mm±0.79mm) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. f = 20kHz, Unless Otherwise Stated. PARAMETER TEST CONDITIONS CA1524, CA2524 CA3524 UNITSMIN TYP MAX MIN TYP MAX REFERENCE SECTION Output Voltage 4.8 5 5.2 4.6 5 5.4 V Line Regulation V+ = 8 to 40V - 10 20 - 10 30 mV Load Regulation I L = 0 to 20mA - 20 50 - 20 50 mV Ripple Rejection f = 120Hz, T A = 25oC - 66 - - 66 - db Short Circuit Current Limit V REF = 0, TA = 25oC - 100 - - 100 - mA Temperature Stability Over Operating Temperature Range - 0.3 1 - 0.3 1 % Long Term Stability T A = 25oC - 20 - - 20 - mV/khr OSCILLATOR SECTION Maximum Frequency C T = 0.001µF, RT = 2KΩ - 300 - - 300 - kHz Initial Accuracy R T and CT Constant - 5 - - 5 - % Voltage Stability V+ = 8 to 40V, T A = 25oC- - 1 - - 1 % Temperature Stability Over Operating Temperature Range --2--2 % Output Amplitude Terminal 3, T A = 25oC - 3.5 - - 3.5 - V Output Pulse Width (Pin 3) C T = 0.01µF, TA = 25oC - 0.5 - - 0.5 - µs Ramp Voltage Low (Note 1) Pin 7 - 0.6 - - 0.6 - V Ramp Voltage High (Note 1) Pin 7 - 3.5 - - 3.5 - V Capacitor Charging Current Range Pin 7 (5-2 V BE )/RT 0.03 - 2 0.03 - 2 mA Timing Resistance Range Pin 6 1.8 - 120 1.8 - 120 k Ω Charging Capacitor Range Pin 7 0.001 - 0.1 0.001 - 0.1 µF Dead Time Expansion Capacitor on Pin 3 (when a small osc. cap is used) Pin 3 100 - 1000 100 - 1000 pF ERROR AMPLIFIER SECTION Input Offset Voltage V CM = 2.5V - 0.5 5 - 2 10 mV Input Bias Current V CM = 2.5V - 1 10 - 1 10 µA Open Loop Voltage Gain 72 80 - 60 80 - dB Common Mode Voltage T A = 25oC 1.8 - 3.4 1.8 - 3.4 V Common Mode Rejection Ratio T A = 25oC - 70 - - 70 - dB Small Signal Bandwidth A V = 0dB, TA = 25oC - 3 - - 3 - MHz

Specifications CA1524,CA2524, CA3524 Output Voltage T A = 25oC 0.5 - 3.8 0.5 - 3.8 V Amplifier Pole - 250 - - 250 - Hz Pin 9 Shutdown Current External Sink - 200 - - 200 - µA COMPARATOR SECTION Duty Cycle % Each Output On 0 - 45 0 - 45 % Input Threshold Zero Duty Cycle - 1 - - 1 - V Input Threshold Max. Duty Cycle - 3.5 - - 3.5 - V Input Bias Current - 1 - - 1 - µA CURRENT LIMITING SECTION Sense Voltage for 25% Output Duty Cycle Terminal 9 = 2V with Error Amplifier Set for Max Out, T A = 25oC 190 200 210 180 200 220 mV Sense Voltage T.C. - 0.2 - - 0.2 - mV/ oC Common Mode Voltage -1 - +1 -1 - +1 V Rolloff Pole of R51 C3 + Q64 - 300 - - 300 - Hz OUTPUT SECTION (EACH OUTUT) Collector-Emitter Voltage 40 - - 40 - - V Collector Leakage Current V CE = 40V - 0.1 50 - 0.1 50 µA Saturation Voltage V+ = 40V, I C = 50mA - 0.8 2 - 0.8 2 V Emitter Output Voltage V+ = 20V 17 18 - 17 18 - V Rise Time R C = 2KΩ , TA = 25oC - 0.2 - - 0.2 - µs Fall Time R C = 2KΩ , TA = 25oC - 0.1 - - 0.1 - µs Total Standby Current: (Note 2) IS V+ = 40V - 4 10 - 4 10 mA NOTES: 1. Ramp voltage at Pin 7 where t = OSC period in microseconds t≅ RTC T with CT in microfarads and RT in ohms. Output frequency at each output transistor is half OSC frequency when each output is used separately and is equal to the OSC frequency when each output is connected in parallel. 2. Excluding oscillator charging current, error and current limit dividers, and with outputs open. f = 20kHz, Unless Otherwise Stated. (Continued) PARAMETER TEST CONDITIONS CA1524, CA2524 CA3524 UNITSMIN TYP MAX MIN TYP MAX High Low t

CA1524, CA2524, CA3524 Schematic Diagram 500 Q2 Q7 Q13 Q3 Q4 2.7K RC 10K 6.3K Q10 Q11 D2D1 Q9 C1 20pF 500 500 Q5 Q12 RB 4.8K RA 5.3K QA OSC SECTION Q42 Q43 Q44 Q47 Q48 Q49 Q50 Q45 Q46 R39 R41 24K R40 560 R42 19.8K Q51 Q52 R45 25K R44 1.8K R43 7.4K Q53 Q54 Q55 R46 3.3K OSC. OUT Q59 Q60 Q61 Q56 Q57 INV. IN ERROR AMP NON-INV. INPUT Q58 Q62 R47 R48 J K L F G H I C D E Q24Q22 Q20 R15 25K 20pF N + P 10K 1.9K RD Q19 R14 450 Q14 Q15 8.4K

500 R10

15 VIN

B A R16 16.2K R19 18.7 K R17 18.7 K R18 18.7 K R18 18.7 K Q21 Q23 VREF +5V GND R T C T

CA1524, CA2524, CA3524 Schematic Diagram(Continued) COLL. A EMIT A 13 COLL. B

14 EMIT B

A B OUTPUT A Q34 Q36 Q35 R33 200 R32 R34 500 CA 1pF R31 4.7Ω RE 500 Q33 OUTPUT B Q40 Q37 Q38 D3 D4 Q39 RF 500 R38 4.7Ω Q41 R35 500 R37 R36 200 CB 1pF C D E R21 43.3K R25 R24 Q26 Q27 R23 8.7K F G H I R26 Q29 R27 Q30 Q31 R30 43.3K R28 8.7K NORNOR R52 1.96K R54 1.96K Q65 Q67 J COMP R49 R50 10K Q63 Q64 Q66 CURRENT LIMIT SECTION R51 10K R53 1.8K 45pF (-) C.L. SENSE Q68 Q71 Q70Q68 Q73Q72 K L COMPARATOR (+) C.L. SENSE

FIGURE 26. SCHEMATIC DIAGRAM OF DIGITAL READOUT SCALE isolated chip is actually 7 mils (0.17mm) larger in both dimensions.

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